1 /*
2 * Copyright (c) 2019 Vestas Wind Systems A/S
3 * Copyright (c) 2020 Innoseis BV
4 * Copyright (c) 2023 Cruise LLC
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8 #include <zephyr/device.h>
9 #include <zephyr/devicetree.h>
10 #include <zephyr/drivers/adc.h>
11 #include <zephyr/drivers/i2c.h>
12 #include <zephyr/kernel.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/sys/byteorder.h>
15 #include <zephyr/sys/util.h>
16
17 #define ADC_CONTEXT_USES_KERNEL_TIMER 1
18 #include "adc_context.h"
19
20 #define DT_DRV_COMPAT ti_ads1112
21
22 LOG_MODULE_REGISTER(ADS1112, CONFIG_ADC_LOG_LEVEL);
23
24 #define ADS1112_CONFIG_GAIN(x) ((x)&BIT_MASK(2))
25 #define ADS1112_CONFIG_DR(x) (((x)&BIT_MASK(2)) << 2)
26 #define ADS1112_CONFIG_CM(x) (((x)&BIT_MASK(1)) << 4)
27 #define ADS1112_CONFIG_MUX(x) (((x)&BIT_MASK(2)) << 5)
28
29 #define ADS1112_CONFIG_MASK_READY BIT(7)
30
31 #define ADS1112_DEFAULT_CONFIG 0x8C
32 #define ADS1112_REF_INTERNAL 2048
33
34 enum ads1112_reg {
35 ADS1112_REG_OUTPUT = 0,
36 ADS1112_REG_CONFIG = 1,
37 };
38
39 enum {
40 ADS1112_CONFIG_MUX_DIFF_0_1 = 0,
41 ADS1112_CONFIG_MUX_BOTH_2_3 = 1,
42 ADS1112_CONFIG_MUX_SINGLE_0_3 = 2,
43 ADS1112_CONFIG_MUX_SINGLE_1_3 = 3,
44 };
45
46 enum {
47 ADS1112_CONFIG_DR_RATE_240_RES_12 = 0,
48 ADS1112_CONFIG_DR_RATE_60_RES_14 = 1,
49 ADS1112_CONFIG_DR_RATE_30_RES_15 = 2,
50 ADS1112_CONFIG_DR_RATE_15_RES_16 = 3,
51 ADS1112_CONFIG_DR_DEFAULT = ADS1112_CONFIG_DR_RATE_15_RES_16,
52 };
53
54 enum {
55 ADS1112_CONFIG_GAIN_1 = 0,
56 ADS1112_CONFIG_GAIN_2 = 1,
57 ADS1112_CONFIG_GAIN_4 = 2,
58 ADS1112_CONFIG_GAIN_8 = 3,
59 };
60
61 enum {
62 ADS1112_CONFIG_CM_SINGLE = 0,
63 ADS1112_CONFIG_CM_CONTINUOUS = 1,
64 };
65
66 struct ads1112_config {
67 const struct i2c_dt_spec bus;
68 };
69
70 struct ads1112_data {
71 struct adc_context ctx;
72 k_timeout_t ready_time;
73 struct k_sem acq_sem;
74 int16_t *buffer;
75 int16_t *buffer_ptr;
76 bool differential;
77 };
78
ads1112_read_reg(const struct device * dev,enum ads1112_reg reg_addr,uint8_t * reg_val)79 static int ads1112_read_reg(const struct device *dev, enum ads1112_reg reg_addr, uint8_t *reg_val)
80 {
81 const struct ads1112_config *config = dev->config;
82 uint8_t buf[3] = {0};
83 int rc = i2c_read_dt(&config->bus, buf, sizeof(buf));
84
85 if (reg_addr == ADS1112_REG_OUTPUT) {
86 reg_val[0] = buf[0];
87 reg_val[1] = buf[1];
88 } else {
89 reg_val[0] = buf[2];
90 }
91
92 return rc;
93 }
94
ads1112_write_reg(const struct device * dev,uint8_t reg)95 static int ads1112_write_reg(const struct device *dev, uint8_t reg)
96 {
97 uint8_t msg[1] = {reg};
98 const struct ads1112_config *config = dev->config;
99
100 /* It's only possible to write the config register, so the ADS1112
101 * assumes all writes are going to that register and omits the register
102 * parameter from write transactions
103 */
104 return i2c_write_dt(&config->bus, msg, sizeof(msg));
105 }
106
ads1112_acq_time_to_dr(const struct device * dev,uint16_t acq_time)107 static inline int ads1112_acq_time_to_dr(const struct device *dev, uint16_t acq_time)
108 {
109 struct ads1112_data *data = dev->data;
110 int odr = -EINVAL;
111 uint16_t acq_value = ADC_ACQ_TIME_VALUE(acq_time);
112 uint32_t ready_time_us = 0;
113
114 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
115 acq_value = ADS1112_CONFIG_DR_DEFAULT;
116 } else if (ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
117 return -EINVAL;
118 }
119
120 switch (acq_value) {
121 case ADS1112_CONFIG_DR_RATE_15_RES_16:
122 odr = ADS1112_CONFIG_DR_RATE_15_RES_16;
123 ready_time_us = (1000 * 1000) / 15;
124 break;
125 case ADS1112_CONFIG_DR_RATE_30_RES_15:
126 odr = ADS1112_CONFIG_DR_RATE_30_RES_15;
127 ready_time_us = (1000 * 1000) / 30;
128 break;
129 case ADS1112_CONFIG_DR_RATE_60_RES_14:
130 odr = ADS1112_CONFIG_DR_RATE_60_RES_14;
131 ready_time_us = (1000 * 1000) / 60;
132 break;
133 case ADS1112_CONFIG_DR_RATE_240_RES_12:
134 odr = ADS1112_CONFIG_DR_RATE_240_RES_12;
135 ready_time_us = (1000 * 1000) / 240;
136 break;
137 default:
138 break;
139 }
140
141 /* Add some additional time to ensure that the data is truly ready,
142 * as chips in this family often require some additional time beyond
143 * the listed times
144 */
145 data->ready_time = K_USEC(ready_time_us + 10);
146
147 return odr;
148 }
149
ads1112_wait_data_ready(const struct device * dev)150 static int ads1112_wait_data_ready(const struct device *dev)
151 {
152 int rc;
153 struct ads1112_data *data = dev->data;
154
155 k_sleep(data->ready_time);
156 uint8_t status = 0;
157
158 rc = ads1112_read_reg(dev, ADS1112_REG_CONFIG, &status);
159 if (rc != 0) {
160 return rc;
161 }
162
163 while ((status & ADS1112_CONFIG_MASK_READY) == 0) {
164
165 k_sleep(K_USEC(100));
166 rc = ads1112_read_reg(dev, ADS1112_REG_CONFIG, &status);
167 if (rc != 0) {
168 return rc;
169 }
170 }
171
172 return 0;
173 }
174
ads1112_read_sample(const struct device * dev,uint16_t * buff)175 static int ads1112_read_sample(const struct device *dev, uint16_t *buff)
176 {
177 int res;
178 uint8_t sample[2] = {0};
179 const struct ads1112_config *config = dev->config;
180
181 res = ads1112_read_reg(dev, ADS1112_REG_OUTPUT, sample);
182 buff[0] = sys_get_be16(sample);
183 return res;
184 }
185
ads1112_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)186 static int ads1112_channel_setup(const struct device *dev,
187 const struct adc_channel_cfg *channel_cfg)
188 {
189 struct ads1112_data *data = dev->data;
190 uint8_t config = 0;
191 int dr = 0;
192
193 if (channel_cfg->channel_id != 0) {
194 return -EINVAL;
195 }
196
197 if (channel_cfg->differential) {
198 if (channel_cfg->input_positive == 0 && channel_cfg->input_negative == 1) {
199 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_DIFF_0_1);
200 } else if (channel_cfg->input_positive == 2 && channel_cfg->input_negative == 3) {
201 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_BOTH_2_3);
202 } else {
203 return -EINVAL;
204 }
205 } else {
206 if (channel_cfg->input_positive == 0) {
207 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_SINGLE_0_3);
208 } else if (channel_cfg->input_positive == 1) {
209 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_SINGLE_1_3);
210 } else if (channel_cfg->input_positive == 2) {
211 config |= ADS1112_CONFIG_MUX(ADS1112_CONFIG_MUX_BOTH_2_3);
212 } else {
213 return -EINVAL;
214 }
215 }
216
217 data->differential = channel_cfg->differential;
218
219 dr = ads1112_acq_time_to_dr(dev, channel_cfg->acquisition_time);
220 if (dr < 0) {
221 return dr;
222 }
223
224 config |= ADS1112_CONFIG_DR(dr);
225
226 switch (channel_cfg->gain) {
227 case ADC_GAIN_1:
228 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_1);
229 break;
230 case ADC_GAIN_2:
231 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_2);
232 break;
233 case ADC_GAIN_3:
234 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_4);
235 break;
236 case ADC_GAIN_4:
237 config |= ADS1112_CONFIG_GAIN(ADS1112_CONFIG_GAIN_8);
238 break;
239 default:
240 return -EINVAL;
241 }
242
243 config |= ADS1112_CONFIG_CM(ADS1112_CONFIG_CM_SINGLE); /* Only single shot supported */
244
245 return ads1112_write_reg(dev, config);
246 }
247
ads1112_validate_buffer_size(const struct adc_sequence * sequence)248 static int ads1112_validate_buffer_size(const struct adc_sequence *sequence)
249 {
250 size_t needed = sizeof(int16_t);
251
252 if (sequence->options) {
253 needed *= (1 + sequence->options->extra_samplings);
254 }
255
256 if (sequence->buffer_size < needed) {
257 LOG_ERR("Insufficient buffer %i < %i", sequence->buffer_size, needed);
258 return -ENOMEM;
259 }
260
261 return 0;
262 }
263
ads1112_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)264 static int ads1112_validate_sequence(const struct device *dev, const struct adc_sequence *sequence)
265 {
266 const struct ads1112_data *data = dev->data;
267
268 if (sequence->channels != BIT(0)) {
269 LOG_ERR("Invalid Channel 0x%x", sequence->channels);
270 return -EINVAL;
271 }
272
273 if (sequence->oversampling) {
274 LOG_ERR("Oversampling not supported");
275 return -EINVAL;
276 }
277
278 return ads1112_validate_buffer_size(sequence);
279 }
280
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)281 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
282 {
283 struct ads1112_data *data = CONTAINER_OF(ctx, struct ads1112_data, ctx);
284
285 if (repeat_sampling) {
286 data->buffer = data->buffer_ptr;
287 }
288 }
289
adc_context_start_sampling(struct adc_context * ctx)290 static void adc_context_start_sampling(struct adc_context *ctx)
291 {
292 struct ads1112_data *data = CONTAINER_OF(ctx, struct ads1112_data, ctx);
293
294 data->buffer_ptr = data->buffer;
295 k_sem_give(&data->acq_sem);
296 }
297
ads1112_adc_start_read(const struct device * dev,const struct adc_sequence * sequence,bool wait)298 static int ads1112_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
299 bool wait)
300 {
301 int rc = 0;
302 struct ads1112_data *data = dev->data;
303
304 rc = ads1112_validate_sequence(dev, sequence);
305 if (rc != 0) {
306 return rc;
307 }
308
309 data->buffer = sequence->buffer;
310
311 adc_context_start_read(&data->ctx, sequence);
312
313 if (wait) {
314 rc = adc_context_wait_for_completion(&data->ctx);
315 }
316 return rc;
317 }
318
ads1112_adc_perform_read(const struct device * dev)319 static int ads1112_adc_perform_read(const struct device *dev)
320 {
321 int rc;
322 struct ads1112_data *data = dev->data;
323
324 k_sem_take(&data->acq_sem, K_FOREVER);
325
326 rc = ads1112_wait_data_ready(dev);
327 if (rc != 0) {
328 adc_context_complete(&data->ctx, rc);
329 return rc;
330 }
331
332 rc = ads1112_read_sample(dev, data->buffer);
333 if (rc != 0) {
334 adc_context_complete(&data->ctx, rc);
335 return rc;
336 }
337 data->buffer++;
338
339 adc_context_on_sampling_done(&data->ctx, dev);
340
341 return rc;
342 }
343
ads1112_read(const struct device * dev,const struct adc_sequence * sequence)344 static int ads1112_read(const struct device *dev, const struct adc_sequence *sequence)
345 {
346 int rc;
347 struct ads1112_data *data = dev->data;
348
349 adc_context_lock(&data->ctx, false, NULL);
350 rc = ads1112_adc_start_read(dev, sequence, false);
351
352 while (rc == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
353 rc = ads1112_adc_perform_read(dev);
354 }
355
356 adc_context_release(&data->ctx, rc);
357 return rc;
358 }
359
ads1112_init(const struct device * dev)360 static int ads1112_init(const struct device *dev)
361 {
362 int rc = 0;
363 uint8_t status;
364 const struct ads1112_config *config = dev->config;
365 struct ads1112_data *data = dev->data;
366
367 adc_context_init(&data->ctx);
368
369 k_sem_init(&data->acq_sem, 0, 1);
370
371 if (!device_is_ready(config->bus.bus)) {
372 return -ENODEV;
373 }
374
375 rc = ads1112_write_reg(dev, ADS1112_DEFAULT_CONFIG);
376 if (rc) {
377 LOG_ERR("Could not set default config 0x%x", ADS1112_DEFAULT_CONFIG);
378 return rc;
379 }
380
381 adc_context_unlock_unconditionally(&data->ctx);
382
383 return rc;
384 }
385
386 static const struct adc_driver_api api = {
387 .channel_setup = ads1112_channel_setup,
388 .read = ads1112_read,
389 .ref_internal = ADS1112_REF_INTERNAL,
390 };
391 #define ADC_ADS1112_INST_DEFINE(n) \
392 static const struct ads1112_config config_##n = {.bus = I2C_DT_SPEC_INST_GET(n)}; \
393 static struct ads1112_data data_##n; \
394 DEVICE_DT_INST_DEFINE(n, ads1112_init, NULL, &data_##n, &config_##n, POST_KERNEL, \
395 CONFIG_ADC_INIT_PRIORITY, &api);
396
397 DT_INST_FOREACH_STATUS_OKAY(ADC_ADS1112_INST_DEFINE);
398
