1 /** 2 * @file adc9_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the ADC9 Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_ADC9_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_ADC9_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup adc9 66 * @defgroup adc9_registers ADC9_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the ADC9 Peripheral Module. 68 * @details Magnetic Strip Reader - 9 bit ADC 69 */ 70 71 /** 72 * @ingroup adc9_registers 73 * Structure type to access the ADC9 Registers. 74 */ 75 typedef struct { 76 __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> ADC9 CFG Register */ 77 __IO uint32_t cmd; /**< <tt>\b 0x0004:</tt> ADC9 CMD Register */ 78 __IO uint32_t fifo; /**< <tt>\b 0x0008:</tt> ADC9 FIFO Register */ 79 __IO uint32_t intr; /**< <tt>\b 0x000C:</tt> ADC9 INTR Register */ 80 __IO uint32_t stat; /**< <tt>\b 0x0010:</tt> ADC9 STAT Register */ 81 } mxc_adc9_regs_t; 82 83 /* Register offsets for module ADC9 */ 84 /** 85 * @ingroup adc9_registers 86 * @defgroup ADC9_Register_Offsets Register Offsets 87 * @brief ADC9 Peripheral Register Offsets from the ADC9 Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_ADC9_CFG ((uint32_t)0x00000000UL) /**< Offset from ADC9 Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_ADC9_CMD ((uint32_t)0x00000004UL) /**< Offset from ADC9 Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_ADC9_FIFO ((uint32_t)0x00000008UL) /**< Offset from ADC9 Base Address: <tt> 0x0008</tt> */ 93 #define MXC_R_ADC9_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC9 Base Address: <tt> 0x000C</tt> */ 94 #define MXC_R_ADC9_STAT ((uint32_t)0x00000010UL) /**< Offset from ADC9 Base Address: <tt> 0x0010</tt> */ 95 /**@} end of group adc9_registers */ 96 97 /** 98 * @ingroup adc9_registers 99 * @defgroup ADC9_CFG ADC9_CFG 100 * @brief ADC Control 101 * @{ 102 */ 103 #define MXC_F_ADC9_CFG_CLKDIV_POS 0 /**< CFG_CLKDIV Position */ 104 #define MXC_F_ADC9_CFG_CLKDIV ((uint32_t)(0xFFUL << MXC_F_ADC9_CFG_CLKDIV_POS)) /**< CFG_CLKDIV Mask */ 105 106 #define MXC_F_ADC9_CFG_ACHSEL_POS 8 /**< CFG_ACHSEL Position */ 107 #define MXC_F_ADC9_CFG_ACHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_ACHSEL_POS)) /**< CFG_ACHSEL Mask */ 108 #define MXC_V_ADC9_CFG_ACHSEL_INVALID_000 ((uint32_t)0x0UL) /**< CFG_ACHSEL_INVALID_000 Value */ 109 #define MXC_S_ADC9_CFG_ACHSEL_INVALID_000 (MXC_V_ADC9_CFG_ACHSEL_INVALID_000 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_INVALID_000 Setting */ 110 #define MXC_V_ADC9_CFG_ACHSEL_IN0 ((uint32_t)0x1UL) /**< CFG_ACHSEL_IN0 Value */ 111 #define MXC_S_ADC9_CFG_ACHSEL_IN0 (MXC_V_ADC9_CFG_ACHSEL_IN0 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_IN0 Setting */ 112 #define MXC_V_ADC9_CFG_ACHSEL_IN1 ((uint32_t)0x2UL) /**< CFG_ACHSEL_IN1 Value */ 113 #define MXC_S_ADC9_CFG_ACHSEL_IN1 (MXC_V_ADC9_CFG_ACHSEL_IN1 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_IN1 Setting */ 114 #define MXC_V_ADC9_CFG_ACHSEL_IN2 ((uint32_t)0x3UL) /**< CFG_ACHSEL_IN2 Value */ 115 #define MXC_S_ADC9_CFG_ACHSEL_IN2 (MXC_V_ADC9_CFG_ACHSEL_IN2 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_IN2 Setting */ 116 #define MXC_V_ADC9_CFG_ACHSEL_IN3 ((uint32_t)0x4UL) /**< CFG_ACHSEL_IN3 Value */ 117 #define MXC_S_ADC9_CFG_ACHSEL_IN3 (MXC_V_ADC9_CFG_ACHSEL_IN3 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_IN3 Setting */ 118 #define MXC_V_ADC9_CFG_ACHSEL_IN4 ((uint32_t)0x5UL) /**< CFG_ACHSEL_IN4 Value */ 119 #define MXC_S_ADC9_CFG_ACHSEL_IN4 (MXC_V_ADC9_CFG_ACHSEL_IN4 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_IN4 Setting */ 120 #define MXC_V_ADC9_CFG_ACHSEL_IN5 ((uint32_t)0x6UL) /**< CFG_ACHSEL_IN5 Value */ 121 #define MXC_S_ADC9_CFG_ACHSEL_IN5 (MXC_V_ADC9_CFG_ACHSEL_IN5 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_IN5 Setting */ 122 #define MXC_V_ADC9_CFG_ACHSEL_INVALID_111 ((uint32_t)0x7UL) /**< CFG_ACHSEL_INVALID_111 Value */ 123 #define MXC_S_ADC9_CFG_ACHSEL_INVALID_111 (MXC_V_ADC9_CFG_ACHSEL_INVALID_111 << MXC_F_ADC9_CFG_ACHSEL_POS) /**< CFG_ACHSEL_INVALID_111 Setting */ 124 125 #define MXC_F_ADC9_CFG_BCHSEL_POS 11 /**< CFG_BCHSEL Position */ 126 #define MXC_F_ADC9_CFG_BCHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_BCHSEL_POS)) /**< CFG_BCHSEL Mask */ 127 128 #define MXC_F_ADC9_CFG_CCHSEL_POS 14 /**< CFG_CCHSEL Position */ 129 #define MXC_F_ADC9_CFG_CCHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_CCHSEL_POS)) /**< CFG_CCHSEL Mask */ 130 131 #define MXC_F_ADC9_CFG_DCHSEL_POS 17 /**< CFG_DCHSEL Position */ 132 #define MXC_F_ADC9_CFG_DCHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_DCHSEL_POS)) /**< CFG_DCHSEL Mask */ 133 134 #define MXC_F_ADC9_CFG_ECHSEL_POS 20 /**< CFG_ECHSEL Position */ 135 #define MXC_F_ADC9_CFG_ECHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_ECHSEL_POS)) /**< CFG_ECHSEL Mask */ 136 137 #define MXC_F_ADC9_CFG_FCHSEL_POS 23 /**< CFG_FCHSEL Position */ 138 #define MXC_F_ADC9_CFG_FCHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_FCHSEL_POS)) /**< CFG_FCHSEL Mask */ 139 140 #define MXC_F_ADC9_CFG_GCHSEL_POS 26 /**< CFG_GCHSEL Position */ 141 #define MXC_F_ADC9_CFG_GCHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_GCHSEL_POS)) /**< CFG_GCHSEL Mask */ 142 143 #define MXC_F_ADC9_CFG_HCHSEL_POS 29 /**< CFG_HCHSEL Position */ 144 #define MXC_F_ADC9_CFG_HCHSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CFG_HCHSEL_POS)) /**< CFG_HCHSEL Mask */ 145 146 /**@} end of group ADC9_CFG_Register */ 147 148 /** 149 * @ingroup adc9_registers 150 * @defgroup ADC9_CMD ADC9_CMD 151 * @brief MSRADC Command 152 * @{ 153 */ 154 #define MXC_F_ADC9_CMD_RST_POS 0 /**< CMD_RST Position */ 155 #define MXC_F_ADC9_CMD_RST ((uint32_t)(0x1UL << MXC_F_ADC9_CMD_RST_POS)) /**< CMD_RST Mask */ 156 157 #define MXC_F_ADC9_CMD_SNGLSMPL_POS 1 /**< CMD_SNGLSMPL Position */ 158 #define MXC_F_ADC9_CMD_SNGLSMPL ((uint32_t)(0x1UL << MXC_F_ADC9_CMD_SNGLSMPL_POS)) /**< CMD_SNGLSMPL Mask */ 159 160 #define MXC_F_ADC9_CMD_CONTSMPL_POS 2 /**< CMD_CONTSMPL Position */ 161 #define MXC_F_ADC9_CMD_CONTSMPL ((uint32_t)(0x1UL << MXC_F_ADC9_CMD_CONTSMPL_POS)) /**< CMD_CONTSMPL Mask */ 162 163 #define MXC_F_ADC9_CMD_ROTLIMIT_POS 4 /**< CMD_ROTLIMIT Position */ 164 #define MXC_F_ADC9_CMD_ROTLIMIT ((uint32_t)(0x7UL << MXC_F_ADC9_CMD_ROTLIMIT_POS)) /**< CMD_ROTLIMIT Mask */ 165 #define MXC_V_ADC9_CMD_ROTLIMIT_1_CHANNEL ((uint32_t)0x0UL) /**< CMD_ROTLIMIT_1_CHANNEL Value */ 166 #define MXC_S_ADC9_CMD_ROTLIMIT_1_CHANNEL (MXC_V_ADC9_CMD_ROTLIMIT_1_CHANNEL << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_1_CHANNEL Setting */ 167 #define MXC_V_ADC9_CMD_ROTLIMIT_2_CHANNELS ((uint32_t)0x1UL) /**< CMD_ROTLIMIT_2_CHANNELS Value */ 168 #define MXC_S_ADC9_CMD_ROTLIMIT_2_CHANNELS (MXC_V_ADC9_CMD_ROTLIMIT_2_CHANNELS << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_2_CHANNELS Setting */ 169 #define MXC_V_ADC9_CMD_ROTLIMIT_3_CHANNELS ((uint32_t)0x2UL) /**< CMD_ROTLIMIT_3_CHANNELS Value */ 170 #define MXC_S_ADC9_CMD_ROTLIMIT_3_CHANNELS (MXC_V_ADC9_CMD_ROTLIMIT_3_CHANNELS << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_3_CHANNELS Setting */ 171 #define MXC_V_ADC9_CMD_ROTLIMIT_4_CHANNELS ((uint32_t)0x3UL) /**< CMD_ROTLIMIT_4_CHANNELS Value */ 172 #define MXC_S_ADC9_CMD_ROTLIMIT_4_CHANNELS (MXC_V_ADC9_CMD_ROTLIMIT_4_CHANNELS << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_4_CHANNELS Setting */ 173 #define MXC_V_ADC9_CMD_ROTLIMIT_5_CHANNELS ((uint32_t)0x4UL) /**< CMD_ROTLIMIT_5_CHANNELS Value */ 174 #define MXC_S_ADC9_CMD_ROTLIMIT_5_CHANNELS (MXC_V_ADC9_CMD_ROTLIMIT_5_CHANNELS << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_5_CHANNELS Setting */ 175 #define MXC_V_ADC9_CMD_ROTLIMIT_6_CHANNELS ((uint32_t)0x5UL) /**< CMD_ROTLIMIT_6_CHANNELS Value */ 176 #define MXC_S_ADC9_CMD_ROTLIMIT_6_CHANNELS (MXC_V_ADC9_CMD_ROTLIMIT_6_CHANNELS << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_6_CHANNELS Setting */ 177 #define MXC_V_ADC9_CMD_ROTLIMIT_7_CHANNELS ((uint32_t)0x6UL) /**< CMD_ROTLIMIT_7_CHANNELS Value */ 178 #define MXC_S_ADC9_CMD_ROTLIMIT_7_CHANNELS (MXC_V_ADC9_CMD_ROTLIMIT_7_CHANNELS << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_7_CHANNELS Setting */ 179 #define MXC_V_ADC9_CMD_ROTLIMIT_8_CHANNELS ((uint32_t)0x7UL) /**< CMD_ROTLIMIT_8_CHANNELS Value */ 180 #define MXC_S_ADC9_CMD_ROTLIMIT_8_CHANNELS (MXC_V_ADC9_CMD_ROTLIMIT_8_CHANNELS << MXC_F_ADC9_CMD_ROTLIMIT_POS) /**< CMD_ROTLIMIT_8_CHANNELS Setting */ 181 182 #define MXC_F_ADC9_CMD_CLKSEL_POS 8 /**< CMD_CLKSEL Position */ 183 #define MXC_F_ADC9_CMD_CLKSEL ((uint32_t)(0x7UL << MXC_F_ADC9_CMD_CLKSEL_POS)) /**< CMD_CLKSEL Mask */ 184 #define MXC_V_ADC9_CMD_CLKSEL_3_SAMPLES ((uint32_t)0x0UL) /**< CMD_CLKSEL_3_SAMPLES Value */ 185 #define MXC_S_ADC9_CMD_CLKSEL_3_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_3_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_3_SAMPLES Setting */ 186 #define MXC_V_ADC9_CMD_CLKSEL_5_SAMPLES ((uint32_t)0x1UL) /**< CMD_CLKSEL_5_SAMPLES Value */ 187 #define MXC_S_ADC9_CMD_CLKSEL_5_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_5_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_5_SAMPLES Setting */ 188 #define MXC_V_ADC9_CMD_CLKSEL_4_SAMPLES ((uint32_t)0x2UL) /**< CMD_CLKSEL_4_SAMPLES Value */ 189 #define MXC_S_ADC9_CMD_CLKSEL_4_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_4_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_4_SAMPLES Setting */ 190 #define MXC_V_ADC9_CMD_CLKSEL_8_SAMPLES ((uint32_t)0x3UL) /**< CMD_CLKSEL_8_SAMPLES Value */ 191 #define MXC_S_ADC9_CMD_CLKSEL_8_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_8_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_8_SAMPLES Setting */ 192 #define MXC_V_ADC9_CMD_CLKSEL_16_SAMPLES ((uint32_t)0x4UL) /**< CMD_CLKSEL_16_SAMPLES Value */ 193 #define MXC_S_ADC9_CMD_CLKSEL_16_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_16_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_16_SAMPLES Setting */ 194 #define MXC_V_ADC9_CMD_CLKSEL_32_SAMPLES ((uint32_t)0x5UL) /**< CMD_CLKSEL_32_SAMPLES Value */ 195 #define MXC_S_ADC9_CMD_CLKSEL_32_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_32_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_32_SAMPLES Setting */ 196 #define MXC_V_ADC9_CMD_CLKSEL_64_SAMPLES ((uint32_t)0x6UL) /**< CMD_CLKSEL_64_SAMPLES Value */ 197 #define MXC_S_ADC9_CMD_CLKSEL_64_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_64_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_64_SAMPLES Setting */ 198 #define MXC_V_ADC9_CMD_CLKSEL_128_SAMPLES ((uint32_t)0x7UL) /**< CMD_CLKSEL_128_SAMPLES Value */ 199 #define MXC_S_ADC9_CMD_CLKSEL_128_SAMPLES (MXC_V_ADC9_CMD_CLKSEL_128_SAMPLES << MXC_F_ADC9_CMD_CLKSEL_POS) /**< CMD_CLKSEL_128_SAMPLES Setting */ 200 201 /**@} end of group ADC9_CMD_Register */ 202 203 /** 204 * @ingroup adc9_registers 205 * @defgroup ADC9_FIFO ADC9_FIFO 206 * @brief ADC FIFO 207 * @{ 208 */ 209 #define MXC_F_ADC9_FIFO_SAMPLE_POS 0 /**< FIFO_SAMPLE Position */ 210 #define MXC_F_ADC9_FIFO_SAMPLE ((uint32_t)(0x1FFUL << MXC_F_ADC9_FIFO_SAMPLE_POS)) /**< FIFO_SAMPLE Mask */ 211 212 #define MXC_F_ADC9_FIFO_SMPLIN_POS 9 /**< FIFO_SMPLIN Position */ 213 #define MXC_F_ADC9_FIFO_SMPLIN ((uint32_t)(0x7UL << MXC_F_ADC9_FIFO_SMPLIN_POS)) /**< FIFO_SMPLIN Mask */ 214 #define MXC_V_ADC9_FIFO_SMPLIN_INVALID_000 ((uint32_t)0x0UL) /**< FIFO_SMPLIN_INVALID_000 Value */ 215 #define MXC_S_ADC9_FIFO_SMPLIN_INVALID_000 (MXC_V_ADC9_FIFO_SMPLIN_INVALID_000 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_INVALID_000 Setting */ 216 #define MXC_V_ADC9_FIFO_SMPLIN_IN0 ((uint32_t)0x1UL) /**< FIFO_SMPLIN_IN0 Value */ 217 #define MXC_S_ADC9_FIFO_SMPLIN_IN0 (MXC_V_ADC9_FIFO_SMPLIN_IN0 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_IN0 Setting */ 218 #define MXC_V_ADC9_FIFO_SMPLIN_IN1 ((uint32_t)0x2UL) /**< FIFO_SMPLIN_IN1 Value */ 219 #define MXC_S_ADC9_FIFO_SMPLIN_IN1 (MXC_V_ADC9_FIFO_SMPLIN_IN1 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_IN1 Setting */ 220 #define MXC_V_ADC9_FIFO_SMPLIN_IN2 ((uint32_t)0x3UL) /**< FIFO_SMPLIN_IN2 Value */ 221 #define MXC_S_ADC9_FIFO_SMPLIN_IN2 (MXC_V_ADC9_FIFO_SMPLIN_IN2 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_IN2 Setting */ 222 #define MXC_V_ADC9_FIFO_SMPLIN_IN3 ((uint32_t)0x4UL) /**< FIFO_SMPLIN_IN3 Value */ 223 #define MXC_S_ADC9_FIFO_SMPLIN_IN3 (MXC_V_ADC9_FIFO_SMPLIN_IN3 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_IN3 Setting */ 224 #define MXC_V_ADC9_FIFO_SMPLIN_IN4 ((uint32_t)0x5UL) /**< FIFO_SMPLIN_IN4 Value */ 225 #define MXC_S_ADC9_FIFO_SMPLIN_IN4 (MXC_V_ADC9_FIFO_SMPLIN_IN4 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_IN4 Setting */ 226 #define MXC_V_ADC9_FIFO_SMPLIN_IN5 ((uint32_t)0x6UL) /**< FIFO_SMPLIN_IN5 Value */ 227 #define MXC_S_ADC9_FIFO_SMPLIN_IN5 (MXC_V_ADC9_FIFO_SMPLIN_IN5 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_IN5 Setting */ 228 #define MXC_V_ADC9_FIFO_SMPLIN_INVALID_111 ((uint32_t)0x7UL) /**< FIFO_SMPLIN_INVALID_111 Value */ 229 #define MXC_S_ADC9_FIFO_SMPLIN_INVALID_111 (MXC_V_ADC9_FIFO_SMPLIN_INVALID_111 << MXC_F_ADC9_FIFO_SMPLIN_POS) /**< FIFO_SMPLIN_INVALID_111 Setting */ 230 231 /**@} end of group ADC9_FIFO_Register */ 232 233 /** 234 * @ingroup adc9_registers 235 * @defgroup ADC9_INTR ADC9_INTR 236 * @brief ADC Interrupt Enable Register 237 * @{ 238 */ 239 #define MXC_F_ADC9_INTR_FIFOLVL_POS 0 /**< INTR_FIFOLVL Position */ 240 #define MXC_F_ADC9_INTR_FIFOLVL ((uint32_t)(0x7UL << MXC_F_ADC9_INTR_FIFOLVL_POS)) /**< INTR_FIFOLVL Mask */ 241 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_1 ((uint32_t)0x0UL) /**< INTR_FIFOLVL_AT_LEAST_1 Value */ 242 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_1 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_1 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_1 Setting */ 243 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_2 ((uint32_t)0x1UL) /**< INTR_FIFOLVL_AT_LEAST_2 Value */ 244 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_2 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_2 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_2 Setting */ 245 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_3 ((uint32_t)0x2UL) /**< INTR_FIFOLVL_AT_LEAST_3 Value */ 246 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_3 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_3 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_3 Setting */ 247 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_4 ((uint32_t)0x3UL) /**< INTR_FIFOLVL_AT_LEAST_4 Value */ 248 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_4 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_4 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_4 Setting */ 249 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_5 ((uint32_t)0x4UL) /**< INTR_FIFOLVL_AT_LEAST_5 Value */ 250 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_5 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_5 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_5 Setting */ 251 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_6 ((uint32_t)0x5UL) /**< INTR_FIFOLVL_AT_LEAST_6 Value */ 252 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_6 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_6 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_6 Setting */ 253 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_7 ((uint32_t)0x6UL) /**< INTR_FIFOLVL_AT_LEAST_7 Value */ 254 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_7 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_7 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_7 Setting */ 255 #define MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_8 ((uint32_t)0x7UL) /**< INTR_FIFOLVL_AT_LEAST_8 Value */ 256 #define MXC_S_ADC9_INTR_FIFOLVL_AT_LEAST_8 (MXC_V_ADC9_INTR_FIFOLVL_AT_LEAST_8 << MXC_F_ADC9_INTR_FIFOLVL_POS) /**< INTR_FIFOLVL_AT_LEAST_8 Setting */ 257 258 #define MXC_F_ADC9_INTR_DMAREQEN_POS 3 /**< INTR_DMAREQEN Position */ 259 #define MXC_F_ADC9_INTR_DMAREQEN ((uint32_t)(0x1UL << MXC_F_ADC9_INTR_DMAREQEN_POS)) /**< INTR_DMAREQEN Mask */ 260 261 #define MXC_F_ADC9_INTR_OVERFIE_POS 6 /**< INTR_OVERFIE Position */ 262 #define MXC_F_ADC9_INTR_OVERFIE ((uint32_t)(0x1UL << MXC_F_ADC9_INTR_OVERFIE_POS)) /**< INTR_OVERFIE Mask */ 263 264 #define MXC_F_ADC9_INTR_UNDRFIE_POS 7 /**< INTR_UNDRFIE Position */ 265 #define MXC_F_ADC9_INTR_UNDRFIE ((uint32_t)(0x1UL << MXC_F_ADC9_INTR_UNDRFIE_POS)) /**< INTR_UNDRFIE Mask */ 266 267 #define MXC_F_ADC9_INTR_FIFOLVLIE_POS 8 /**< INTR_FIFOLVLIE Position */ 268 #define MXC_F_ADC9_INTR_FIFOLVLIE ((uint32_t)(0x1UL << MXC_F_ADC9_INTR_FIFOLVLIE_POS)) /**< INTR_FIFOLVLIE Mask */ 269 270 #define MXC_F_ADC9_INTR_GLOBIE_POS 9 /**< INTR_GLOBIE Position */ 271 #define MXC_F_ADC9_INTR_GLOBIE ((uint32_t)(0x1UL << MXC_F_ADC9_INTR_GLOBIE_POS)) /**< INTR_GLOBIE Mask */ 272 273 /**@} end of group ADC9_INTR_Register */ 274 275 /** 276 * @ingroup adc9_registers 277 * @defgroup ADC9_STAT ADC9_STAT 278 * @brief ADC Interrupt Flag Register. 279 * @{ 280 */ 281 #define MXC_F_ADC9_STAT_FIFOCNT_POS 0 /**< STAT_FIFOCNT Position */ 282 #define MXC_F_ADC9_STAT_FIFOCNT ((uint32_t)(0xFUL << MXC_F_ADC9_STAT_FIFOCNT_POS)) /**< STAT_FIFOCNT Mask */ 283 #define MXC_V_ADC9_STAT_FIFOCNT_FIFO_EMPTY ((uint32_t)0x0UL) /**< STAT_FIFOCNT_FIFO_EMPTY Value */ 284 #define MXC_S_ADC9_STAT_FIFOCNT_FIFO_EMPTY (MXC_V_ADC9_STAT_FIFOCNT_FIFO_EMPTY << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_FIFO_EMPTY Setting */ 285 #define MXC_V_ADC9_STAT_FIFOCNT_ONE_SAMPLE ((uint32_t)0x1UL) /**< STAT_FIFOCNT_ONE_SAMPLE Value */ 286 #define MXC_S_ADC9_STAT_FIFOCNT_ONE_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_ONE_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_ONE_SAMPLE Setting */ 287 #define MXC_V_ADC9_STAT_FIFOCNT_TWO_SAMPLE ((uint32_t)0x2UL) /**< STAT_FIFOCNT_TWO_SAMPLE Value */ 288 #define MXC_S_ADC9_STAT_FIFOCNT_TWO_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_TWO_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_TWO_SAMPLE Setting */ 289 #define MXC_V_ADC9_STAT_FIFOCNT_THREE_SAMPLE ((uint32_t)0x3UL) /**< STAT_FIFOCNT_THREE_SAMPLE Value */ 290 #define MXC_S_ADC9_STAT_FIFOCNT_THREE_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_THREE_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_THREE_SAMPLE Setting */ 291 #define MXC_V_ADC9_STAT_FIFOCNT_FOUR_SAMPLE ((uint32_t)0x4UL) /**< STAT_FIFOCNT_FOUR_SAMPLE Value */ 292 #define MXC_S_ADC9_STAT_FIFOCNT_FOUR_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_FOUR_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_FOUR_SAMPLE Setting */ 293 #define MXC_V_ADC9_STAT_FIFOCNT_FIVE_SAMPLE ((uint32_t)0x5UL) /**< STAT_FIFOCNT_FIVE_SAMPLE Value */ 294 #define MXC_S_ADC9_STAT_FIFOCNT_FIVE_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_FIVE_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_FIVE_SAMPLE Setting */ 295 #define MXC_V_ADC9_STAT_FIFOCNT_SIX_SAMPLE ((uint32_t)0x6UL) /**< STAT_FIFOCNT_SIX_SAMPLE Value */ 296 #define MXC_S_ADC9_STAT_FIFOCNT_SIX_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_SIX_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_SIX_SAMPLE Setting */ 297 #define MXC_V_ADC9_STAT_FIFOCNT_SEVEN_SAMPLE ((uint32_t)0x7UL) /**< STAT_FIFOCNT_SEVEN_SAMPLE Value */ 298 #define MXC_S_ADC9_STAT_FIFOCNT_SEVEN_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_SEVEN_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_SEVEN_SAMPLE Setting */ 299 #define MXC_V_ADC9_STAT_FIFOCNT_EIGHT_SAMPLE ((uint32_t)0x8UL) /**< STAT_FIFOCNT_EIGHT_SAMPLE Value */ 300 #define MXC_S_ADC9_STAT_FIFOCNT_EIGHT_SAMPLE (MXC_V_ADC9_STAT_FIFOCNT_EIGHT_SAMPLE << MXC_F_ADC9_STAT_FIFOCNT_POS) /**< STAT_FIFOCNT_EIGHT_SAMPLE Setting */ 301 302 #define MXC_F_ADC9_STAT_FULL_POS 4 /**< STAT_FULL Position */ 303 #define MXC_F_ADC9_STAT_FULL ((uint32_t)(0x1UL << MXC_F_ADC9_STAT_FULL_POS)) /**< STAT_FULL Mask */ 304 305 #define MXC_F_ADC9_STAT_EMPTY_POS 5 /**< STAT_EMPTY Position */ 306 #define MXC_F_ADC9_STAT_EMPTY ((uint32_t)(0x1UL << MXC_F_ADC9_STAT_EMPTY_POS)) /**< STAT_EMPTY Mask */ 307 308 #define MXC_F_ADC9_STAT_OVERFINT_POS 6 /**< STAT_OVERFINT Position */ 309 #define MXC_F_ADC9_STAT_OVERFINT ((uint32_t)(0x1UL << MXC_F_ADC9_STAT_OVERFINT_POS)) /**< STAT_OVERFINT Mask */ 310 311 #define MXC_F_ADC9_STAT_UNDRFINT_POS 7 /**< STAT_UNDRFINT Position */ 312 #define MXC_F_ADC9_STAT_UNDRFINT ((uint32_t)(0x1UL << MXC_F_ADC9_STAT_UNDRFINT_POS)) /**< STAT_UNDRFINT Mask */ 313 314 #define MXC_F_ADC9_STAT_FIFOLVLST_POS 8 /**< STAT_FIFOLVLST Position */ 315 #define MXC_F_ADC9_STAT_FIFOLVLST ((uint32_t)(0x1UL << MXC_F_ADC9_STAT_FIFOLVLST_POS)) /**< STAT_FIFOLVLST Mask */ 316 317 #define MXC_F_ADC9_STAT_GLOBINT_POS 9 /**< STAT_GLOBINT Position */ 318 #define MXC_F_ADC9_STAT_GLOBINT ((uint32_t)(0x1UL << MXC_F_ADC9_STAT_GLOBINT_POS)) /**< STAT_GLOBINT Mask */ 319 320 /**@} end of group ADC9_STAT_Register */ 321 322 #ifdef __cplusplus 323 } 324 #endif 325 326 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_ADC9_REGS_H_ 327
