1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 25)>,
10				<NRF_PSEL(UART_RX, 0, 24)>;
11		};
12	};
13
14	uart0_sleep: uart0_sleep {
15		group1 {
16			psels = <NRF_PSEL(UART_TX, 0, 25)>,
17				<NRF_PSEL(UART_RX, 0, 24)>;
18			low-power-enable;
19		};
20	};
21
22	i2c0_default: i2c0_default {
23		group1 {
24			psels = <NRF_PSEL(TWIM_SDA, 0, 12)>,
25				<NRF_PSEL(TWIM_SCL, 0, 11)>;
26		};
27	};
28
29	i2c0_sleep: i2c0_sleep {
30		group1 {
31			psels = <NRF_PSEL(TWIM_SDA, 0, 12)>,
32				<NRF_PSEL(TWIM_SCL, 0, 11)>;
33			low-power-enable;
34		};
35	};
36
37	spi1_default: spi1_default {
38		group1 {
39			psels = <NRF_PSEL(SPIM_SCK, 0, 14)>,
40				<NRF_PSEL(SPIM_MOSI, 0, 13)>,
41				<NRF_PSEL(SPIM_MISO, 0, 15)>;
42		};
43	};
44
45	spi1_sleep: spi1_sleep {
46		group1 {
47			psels = <NRF_PSEL(SPIM_SCK, 0, 14)>,
48				<NRF_PSEL(SPIM_MOSI, 0, 13)>,
49				<NRF_PSEL(SPIM_MISO, 0, 15)>;
50			low-power-enable;
51		};
52	};
53
54	qspi_default: qspi_default {
55		group1 {
56			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
57				<NRF_PSEL(QSPI_IO0, 0, 17)>,
58				<NRF_PSEL(QSPI_IO1, 0, 22)>,
59				<NRF_PSEL(QSPI_IO2, 0, 23)>,
60				<NRF_PSEL(QSPI_IO3, 0, 21)>,
61				<NRF_PSEL(QSPI_CSN, 0, 20)>;
62		};
63	};
64
65	qspi_sleep: qspi_sleep {
66		group1 {
67			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
68				<NRF_PSEL(QSPI_IO0, 0, 17)>,
69				<NRF_PSEL(QSPI_IO1, 0, 22)>,
70				<NRF_PSEL(QSPI_IO2, 0, 23)>,
71				<NRF_PSEL(QSPI_IO3, 0, 21)>,
72				<NRF_PSEL(QSPI_CSN, 0, 20)>;
73			low-power-enable;
74		};
75	};
76
77};
78