1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart1_default: uart1_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 24)>,
10				<NRF_PSEL(UART_RX, 0, 23)>;
11		};
12	};
13
14	uart1_sleep: uart1_sleep {
15		group1 {
16			psels = <NRF_PSEL(UART_TX, 0, 24)>,
17				<NRF_PSEL(UART_RX, 0, 23)>;
18			low-power-enable;
19		};
20	};
21
22	uart2_default: uart2_default {
23		group1 {
24			psels = <NRF_PSEL(UART_TX, 0, 4)>,
25				<NRF_PSEL(UART_RX, 0, 5)>;
26		};
27	};
28
29	uart2_sleep: uart2_sleep {
30		group1 {
31			psels = <NRF_PSEL(UART_TX, 0, 4)>,
32				<NRF_PSEL(UART_RX, 0, 5)>;
33			low-power-enable;
34		};
35	};
36
37	i2c2_default: i2c2_default {
38		group1 {
39			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
40				<NRF_PSEL(TWIM_SCL, 0, 27)>;
41		};
42	};
43
44	i2c2_sleep: i2c2_sleep {
45		group1 {
46			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
47				<NRF_PSEL(TWIM_SCL, 0, 27)>;
48			low-power-enable;
49		};
50	};
51
52	spi3_default: spi3_default {
53		group1 {
54			psels = <NRF_PSEL(SPIM_SCK, 0, 20)>,
55				<NRF_PSEL(SPIM_MOSI, 0, 21)>,
56				<NRF_PSEL(SPIM_MISO, 0, 22)>;
57		};
58	};
59
60	spi3_sleep: spi3_sleep {
61		group1 {
62			psels = <NRF_PSEL(SPIM_SCK, 0, 20)>,
63				<NRF_PSEL(SPIM_MOSI, 0, 21)>,
64				<NRF_PSEL(SPIM_MISO, 0, 22)>;
65			low-power-enable;
66		};
67	};
68
69	pwm0_default: pwm0_default {
70		group1 {
71			psels = <NRF_PSEL(PWM_OUT0, 0, 10)>,
72				<NRF_PSEL(PWM_OUT1, 0, 11)>,
73				<NRF_PSEL(PWM_OUT2, 0, 12)>;
74			nordic,invert;
75		};
76	};
77
78	pwm0_sleep: pwm0_sleep {
79		group1 {
80			psels = <NRF_PSEL(PWM_OUT0, 0, 10)>,
81				<NRF_PSEL(PWM_OUT1, 0, 11)>,
82				<NRF_PSEL(PWM_OUT2, 0, 12)>;
83			low-power-enable;
84		};
85	};
86
87};
88