1 /* 2 * Copyright (c) 2024 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ 7 #define __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ 8 9 /* DMIC Link Synchronization */ 10 #define DMICSYNC_OFFSET 0x1C 11 12 /* Sync Period */ 13 #define DMICSYNC_SYNCPRD GENMASK(19, 0) 14 15 /* Sync Period Update */ 16 #define DMICSYNC_SYNCPU BIT(20) 17 18 /* Sync Go */ 19 #define DMICSYNC_SYNCGO BIT(23) 20 21 /* Command Sync */ 22 #define DMICSYNC_CMDSYNC BIT(24) 23 24 25 /* DMIC Link Control */ 26 #define DMICLCTL_OFFSET 0x04 27 28 /* Set Clock Frequency */ 29 #define DMICLCTL_SCF GENMASK(3, 0) 30 31 /* Offload Enable */ 32 #define DMICLCTL_OFLEN BIT(4) 33 34 /* Interrupt Enable */ 35 #define DMICLCTL_INTEN BIT(5) 36 37 /* Set Power Active */ 38 #define DMICLCTL_SPA BIT(16) 39 40 /* Current Power Active */ 41 #define DMICLCTL_CPA BIT(23) 42 43 /* Interrupt Status */ 44 #define DMICLCTL_INTSTS BIT(31) 45 46 47 /* Digital Microphone x Link Vendor Specific Control */ 48 #define DMICLVSCTL_OFFSET 0x04 49 50 /* Force Clock Gating */ 51 #define DMICLVSCTL_FCG BIT(26) 52 53 /* Host Link Clock Select */ 54 #define DMICLVSCTL_MLCS GENMASK(29, 27) 55 56 /* Dynamic Clock Gating Disable */ 57 #define DMICLVSCTL_DCGD BIT(30) 58 59 /* Idle Clock Gating Disable */ 60 #define DMICLVSCTL_ICGD BIT(31) 61 62 63 /* Digital Microphone PCM Stream y Channel Map 64 * 65 * Offset: 12h + 02h * y 66 */ 67 #define DMICXPCMSyCM_OFFSET 0x16 68 #define DMICXPCMSyCM_SIZE 0x02 69 70 #endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ */ 71
