1 /* 2 * Copyright (c) 2024 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ 7 #define __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ 8 9 /* DMIC Link Synchronization */ 10 #define DMICSYNC_OFFSET 0x1C 11 12 /* Sync Period */ 13 #define DMICSYNC_SYNCPRD GENMASK(19, 0) 14 15 /* Sync Period Update */ 16 #define DMICSYNC_SYNCPU BIT(20) 17 18 /* Sync Go */ 19 #define DMICSYNC_SYNCGO BIT(23) 20 21 /* Command Sync */ 22 #define DMICSYNC_CMDSYNC BIT(24) 23 24 /* DMIC Link Control */ 25 #define DMICLCTL_OFFSET 0x04 26 27 /* Set Clock Frequency */ 28 #define DMICLCTL_SCF GENMASK(3, 0) 29 30 /* Offload Enable */ 31 #define DMICLCTL_OFLEN BIT(4) 32 33 /* Interrupt Enable */ 34 #define DMICLCTL_INTEN BIT(5) 35 36 /* Set Power Active */ 37 #define DMICLCTL_SPA BIT(16) 38 39 /* Current Power Active */ 40 #define DMICLCTL_CPA BIT(23) 41 42 /* Interrupt Status */ 43 #define DMICLCTL_INTSTS BIT(31) 44 45 /* Digital Microphone x Link Vendor Specific Control */ 46 #define DMICLVSCTL_OFFSET 0x04 47 48 /* Force Clock Gating */ 49 #define DMICLVSCTL_FCG BIT(26) 50 51 /* Host Link Clock Select */ 52 #define DMICLVSCTL_MLCS GENMASK(29, 27) 53 54 /* Dynamic Clock Gating Disable */ 55 #define DMICLVSCTL_DCGD BIT(30) 56 57 /* Idle Clock Gating Disable */ 58 #define DMICLVSCTL_ICGD BIT(31) 59 60 /* Digital Microphone PCM Stream y Channel Map 61 * 62 * Offset: 12h + 02h * y 63 */ 64 #define DMICXPCMSyCM_OFFSET 0x16 65 #define DMICXPCMSyCM_SIZE 0x02 66 67 #endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__ */ 68
