1 /* SPDX-License-Identifier: Apache-2.0 */ 2 /* 3 * Copyright (c) 2023 Intel Corporation 4 * 5 * Author: Adrian Warecki <adrian.warecki@intel.com> 6 */ 7 8 #ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__ 9 #define __INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__ 10 11 /* DMIC Link Synchronization */ 12 #define DMICSYNC_OFFSET 0x1C 13 14 /* Sync Period */ 15 #define DMICSYNC_SYNCPRD GENMASK(19, 0) 16 17 /* Sync Period Update */ 18 #define DMICSYNC_SYNCPU BIT(20) 19 20 /* Sync Go */ 21 #define DMICSYNC_SYNCGO BIT(23) 22 23 /* Command Sync */ 24 #define DMICSYNC_CMDSYNC BIT(24) 25 26 27 /* DMIC Link Control */ 28 #define DMICLCTL_OFFSET 0x04 29 30 /* Set Clock Frequency */ 31 #define DMICLCTL_SCF GENMASK(3, 0) 32 33 /* Offload Enable */ 34 #define DMICLCTL_OFLEN BIT(4) 35 36 /* Interrupt Enable */ 37 #define DMICLCTL_INTEN BIT(5) 38 39 /* Set Power Active */ 40 #define DMICLCTL_SPA BIT(16) 41 42 /* Current Power Active */ 43 #define DMICLCTL_CPA BIT(23) 44 45 /* Interrupt Status */ 46 #define DMICLCTL_INTSTS BIT(31) 47 48 49 /* Digital Microphone x Link Vendor Specific Control */ 50 #define DMICLVSCTL_OFFSET 0x04 51 52 /* Force Clock Gating */ 53 #define DMICLVSCTL_FCG BIT(26) 54 55 /* Host Link Clock Select */ 56 #define DMICLVSCTL_MLCS GENMASK(29, 27) 57 58 /* Dynamic Clock Gating Disable */ 59 #define DMICLVSCTL_DCGD BIT(30) 60 61 /* Idle Clock Gating Disable */ 62 #define DMICLVSCTL_ICGD BIT(31) 63 64 65 /* Digital Microphone PCM Stream y Channel Map 66 * 67 * Offset: 12h + 02h * y 68 */ 69 #define DMICXPCMSyCM_OFFSET 0x16 70 #define DMICXPCMSyCM_SIZE 0x02 71 72 #endif /* !__INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__ */ 73
