1/* 2 * Copyright (c) 2022 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/** 8 * @file 9 * @brief Linker command/script file 10 * 11 * Linker script for the intel_apl_adsp platform 12 */ 13 14OUTPUT_ARCH(xtensa) 15 16#include <zephyr/devicetree.h> 17#include <xtensa/config/core-isa.h> 18#include <zephyr/linker/sections.h> 19#include <adsp-vectors.h> 20#include <adsp_memory.h> 21 22#include <zephyr/linker/linker-defs.h> 23#include <zephyr/linker/linker-tool.h> 24 25ENTRY(rom_entry); 26 27/* DSP RAM regions (all of them) are mapped twice on the DSP. One 28 * mapping is set up to bypass the L1 cache, so it must be used when 29 * multiprocessor coherence is desired, where the latter mapping is 30 * best used for processor-local data (e.g. stacks) or shared data 31 * that is managed with explicit cache flush/invalidate operations. 32 * 33 * These macros will set up a segment start address correctly, 34 * including alignment to a cache line. Be sure to also emit the 35 * section to ">ram" or ">ucram" as appropriate, to prevent the linker 36 * from filling in 512MB of sparse zeros. 37 */ 38#ifdef CONFIG_KERNEL_COHERENCE 39#define RPO_SET(addr, reg) ((addr & 0x1fffffff) | (reg << 29)) 40#ifdef CONFIG_MMU 41#define SEGSTART_CACHED RPO_SET(ALIGN(CONFIG_MMU_PAGE_SIZE), CONFIG_XTENSA_CACHED_REGION) 42#define SEGSTART_UNCACHED RPO_SET(ALIGN(CONFIG_MMU_PAGE_SIZE), CONFIG_XTENSA_UNCACHED_REGION) 43#else 44#define SEGSTART_CACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_CACHED_REGION) 45#define SEGSTART_UNCACHED RPO_SET(ALIGN(64), CONFIG_XTENSA_UNCACHED_REGION) 46#endif 47#else 48#ifdef CONFIG_MMU 49#define SEGSTART_CACHED ALIGN(CONFIG_MMU_PAGE_SIZE) 50#define SEGSTART_UNCACHED ALIGN(CONFIG_MMU_PAGE_SIZE) 51#else 52#define SEGSTART_CACHED . 53#define SEGSTART_UNCACHED . 54#endif 55#define ucram ram 56#endif 57 58/* intlist.ld needs an IDT_LIST memory region */ 59#define IDT_BASE 0xe0000000 60#define IDT_SIZE 0x2000 61 62/* rimage module sections are C struct data, and thus flagged ALLOC. 63 * The xcc linker demands they be in a declared memory region even if 64 * the enclosing output section is (NOLOAD). Put them here. 65 */ 66#define NOLOAD_BASE 0x20000 67#define NOLOAD_SIZE 0x100000 68 69#ifdef CONFIG_MMU 70#define MMU_PAGE_ALIGN . = ALIGN(CONFIG_MMU_PAGE_SIZE); 71#define HDR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE) 72#define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(CONFIG_MMU_PAGE_SIZE) 73#else 74#define MMU_PAGE_ALIGN 75#define HDR_MMU_PAGE_ALIGN 76#define HDR_4K_OR_MMU_PAGE_ALIGN ALIGN(4096) 77#endif 78 79#define SMEM_PARTITION_ALIGN(size) MMU_PAGE_ALIGN 80 81MEMORY { 82 vector_base_text : 83 org = VECBASE_RESET_PADDR_SRAM, 84 len = MEM_VECBASE_LIT_SIZE 85 vector_int2_lit : 86 org = INTLEVEL2_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 87 len = MEM_VECT_LIT_SIZE 88 vector_int2_text : 89 org = INTLEVEL2_VECTOR_PADDR_SRAM, 90 len = MEM_VECT_TEXT_SIZE 91 vector_int3_lit : 92 org = INTLEVEL3_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 93 len = MEM_VECT_LIT_SIZE 94 vector_int3_text : 95 org = INTLEVEL3_VECTOR_PADDR_SRAM, 96 len = MEM_VECT_TEXT_SIZE 97 vector_int4_lit : 98 org = INTLEVEL4_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 99 len = MEM_VECT_LIT_SIZE 100 vector_int4_text : 101 org = INTLEVEL4_VECTOR_PADDR_SRAM, 102 len = MEM_VECT_TEXT_SIZE 103 vector_int7_lit : 104 org = INTLEVEL7_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 105 len = MEM_VECT_LIT_SIZE 106 vector_int7_text : 107 org = INTLEVEL7_VECTOR_PADDR_SRAM, 108 len = MEM_VECT_TEXT_SIZE 109 vector_kernel_lit : 110 org = KERNEL_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 111 len = MEM_VECT_LIT_SIZE 112 vector_kernel_text : 113 org = KERNEL_VECTOR_PADDR_SRAM, 114 len = MEM_VECT_TEXT_SIZE 115 vector_user_lit : 116 org = USER_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 117 len = MEM_VECT_LIT_SIZE 118 vector_user_text : 119 org = USER_VECTOR_PADDR_SRAM, 120 len = MEM_VECT_TEXT_SIZE 121 vector_double_lit : 122 org = DOUBLEEXC_VECTOR_PADDR_SRAM - MEM_VECT_LIT_SIZE, 123 len = MEM_VECT_LIT_SIZE 124 vector_double_text : 125 org = DOUBLEEXC_VECTOR_PADDR_SRAM, 126 len = MEM_VECT_TEXT_SIZE 127#ifdef CONFIG_XTENSA_MMU 128 xtensa_vector_code : 129 org = DOUBLEEXC_VECTOR_PADDR_SRAM + MEM_VECT_TEXT_SIZE, 130 len = RAM_BASE - (DOUBLEEXC_VECTOR_PADDR_SRAM + MEM_VECT_TEXT_SIZE) 131#endif 132 imr : 133 org = IMR_BOOT_LDR_TEXT_ENTRY_BASE, 134 len = 0x100000 135 ram : 136 org = RAM_BASE, 137 len = RAM_SIZE 138#ifdef CONFIG_KERNEL_COHERENCE 139 ucram : 140 org = RPO_SET(RAM_BASE, CONFIG_XTENSA_UNCACHED_REGION), 141 len = RAM_SIZE 142#endif 143#ifdef CONFIG_GEN_ISR_TABLES 144 IDT_LIST : 145 org = IDT_BASE, 146 len = IDT_SIZE 147#endif 148 lpram : 149 org = LP_SRAM_BASE, 150 len = LP_SRAM_SIZE 151 noload : 152 org = NOLOAD_BASE, 153 len = NOLOAD_SIZE 154} 155 156SECTIONS { 157 158 /* Boot loader code in IMR memory */ 159 .imr : { 160 _imr_start = .; 161 /* Entry point MUST be here per external configuration */ 162 KEEP (*(.boot_entry.text)) 163 *(.imr .imr.*) 164 } >imr 165 166 /* Boot loader data. Note that rimage seems to want this 167 * page-aligned or it will throw an error, not sure why since all 168 * the ROM cares about is a contiguous region. And it's 169 * particularly infuriating as it precludes linker .rodata next to 170 * .text. 171 */ 172 .imrdata : ALIGN(4096) { 173 *(.imrdata .imrdata.*) 174 } >imr 175 176 /* Cold code in IMR memory */ 177 .cold : ALIGN(4096) { 178 *(.cold .cold.* ) 179 } >imr 180 181 /* Cold data. */ 182 .coldrodata : ALIGN(4096) { 183 *(.coldrodata .coldrodata.*) 184 _imr_end = .; 185 } >imr 186 187 .WindowVectors.text : { 188 _WindowVectors_text_start = .; 189 KEEP (*(.WindowVectors.text)) 190 _WindowVectors_text_end = .; 191 } >vector_base_text 192 .Level2InterruptVector.literal : { 193 _Level2InterruptVector_literal_start = .; 194 *(.Level2InterruptVector.literal) 195 _Level2InterruptVector_literal_end = .; 196 } >vector_int2_lit 197 .Level2InterruptVector.text : { 198 _Level2InterruptVector_text_start = .; 199 KEEP (*(.Level2InterruptVector.text)) 200 _Level2InterruptVector_text_end = .; 201 } >vector_int2_text 202 .Level3InterruptVector.literal : { 203 _Level3InterruptVector_literal_start = .; 204 *(.Level3InterruptVector.literal) 205 _Level3InterruptVector_literal_end = .; 206 } >vector_int3_lit 207 .Level3InterruptVector.text : { 208 _Level3InterruptVector_text_start = .; 209 KEEP (*(.Level3InterruptVector.text)) 210 _Level3InterruptVector_text_end = .; 211 } >vector_int3_text 212 .Level4InterruptVector.literal : { 213 _Level4InterruptVector_literal_start = .; 214 *(.Level4InterruptVector.literal) 215 _Level4InterruptVector_literal_end = .; 216 } >vector_int4_lit 217 .Level4InterruptVector.text : { 218 _Level4InterruptVector_text_start = .; 219 KEEP (*(.Level4InterruptVector.text)) 220 _Level4InterruptVector_text_end = .; 221 } >vector_int4_text 222 .DebugExceptionVector.literal : { 223 _DebugExceptionVector_literal_start = .; 224 *(.DebugExceptionVector.literal) 225 _DebugExceptionVector_literal_end = .; 226 } >vector_int4_lit 227 .DebugExceptionVector.text : { 228 _DebugExceptionVector_text_start = .; 229 KEEP (*(.DebugExceptionVector.text)) 230 _DebugExceptionVector_text_end = .; 231 } >vector_int4_text 232 .NMIExceptionVector.literal : { 233 _NMIExceptionVector_literal_start = .; 234 *(.NMIExceptionVector.literal) 235 _NMIExceptionVector_literal_end = .; 236 } >vector_int7_lit 237 .NMIExceptionVector.text : { 238 _NMIExceptionVector_text_start = .; 239 KEEP (*(.NMIExceptionVector.text)) 240 _NMIExceptionVector_text_end = .; 241 } >vector_int7_text 242 .KernelExceptionVector.literal : { 243 _KernelExceptionVector_literal_start = .; 244 *(.KernelExceptionVector.literal) 245 _KernelExceptionVector_literal_end = .; 246 } >vector_kernel_lit 247 .KernelExceptionVector.text : { 248 _KernelExceptionVector_text_start = .; 249 KEEP (*(.KernelExceptionVector.text)) 250 _KernelExceptionVector_text_end = .; 251 } >vector_kernel_text 252 .UserExceptionVector.literal : { 253 _UserExceptionVector_literal_start = .; 254 *(.UserExceptionVector.literal) 255 _UserExceptionVector_literal_end = .; 256 } >vector_user_lit 257 .UserExceptionVector.text : { 258 _UserExceptionVector_text_start = .; 259 KEEP (*(.UserExceptionVector.text)) 260 _UserExceptionVector_text_end = .; 261 } >vector_user_text 262 .DoubleExceptionVector.literal : { 263 _DoubleExceptionVector_literal_start = .; 264 *(.DoubleExceptionVector.literal) 265 _DoubleExceptionVector_literal_end = .; 266 } >vector_double_lit 267 .DoubleExceptionVector.text : { 268 _DoubleExceptionVector_text_start = .; 269 KEEP (*(.DoubleExceptionVector.text)) 270 _DoubleExceptionVector_text_end = .; 271 } >vector_double_text 272 273#ifdef CONFIG_XTENSA_MMU 274 .xtensa_vector_code : { 275 /* There is not much space between .DoubleExceptionVector 276 * and the beginning of .text. So need to be careful on 277 * what to put in this section. It would mostly be things 278 * that are required to handle exceptions and interrupts. 279 * Also things we want to avoid TLB misses during exception 280 * handling. 281 */ 282 283 *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.literal) 284 *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.iram.text) 285 *libarch__xtensa__core.a:xtensa_asm2_util.S.obj(.text) 286 287 *libarch__xtensa__core.a:window_vectors.S.obj(.iram.text) 288 289 /* For _Level1Vector */ 290 *libarch__xtensa__core.a:vector_handlers_util.S.obj(.iram0.text) 291 292 *libarch__xtensa__core.a:vector_handlers.c.obj(.literal.xtensa_int?_c) 293 *libarch__xtensa__core.a:vector_handlers.c.obj(.text.xtensa_int?_c) 294 295 *libarch__xtensa__core.a:userspace.S.obj(.literal.xtensa_do_syscall) 296 *libarch__xtensa__core.a:userspace.S.obj(.text.xtensa_do_syscall) 297 298#ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER 299 *libarch__xtensa__core.a:syscall_helper.c.obj(.text.xtensa_syscall_helper*) 300#endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ 301 302 } > xtensa_vector_code 303#endif /* CONFIG_XTENSA_MMU */ 304 305 .text : HDR_MMU_PAGE_ALIGN 306 { 307 __text_region_start = .; 308 _image_ram_start = .; 309 z_mapped_start = .; 310 *(.iram1 .iram1.*) 311 *(.entry.text) 312 *(.init.literal) 313 *(.iram0.text) 314 315#ifdef CONFIG_XTENSA_MMU 316 /* 317 * The C handle blows up in size significantly when logging is enabled. 318 * So we can't keep this in .xtensa_vector_code above. Though we try to 319 * leep these close enough that, hopefully, we can avoid TLB misses. 320 */ 321 *libarch__xtensa__core.a:vector_handlers.c.obj(.literal.xtensa_excint1_c) 322 *libarch__xtensa__core.a:vector_handlers.c.obj(.text.xtensa_excint1_c) 323 324 /* 325 * Experiment shows that system would not boot if this is away from 326 * VECBASE more than a few pages. So workaround the issue by putting 327 * xtensa_mmu_init() here. 328 */ 329 *libarch__xtensa__core.a:ptables.c.obj(.literal.xtensa_mmu_init) 330 *libarch__xtensa__core.a:ptables.c.obj(.text.xtensa_mmu_init) 331#endif 332 333 KEEP(*(.init)) 334 KEEP(*(.lps_vector)) 335 *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) 336 MMU_PAGE_ALIGN 337 *(.literal .text) 338 *(.literal.* .text.*) 339 *(.fini.literal) 340 KEEP(*(.fini)) 341 *(.gnu.version) 342#include <zephyr/linker/kobject-text.ld> 343 MMU_PAGE_ALIGN 344 __text_region_end = .; 345 } >ram 346 347 .rodata : HDR_4K_OR_MMU_PAGE_ALIGN 348 { 349 __rodata_region_start = .; 350 *(.rodata) 351 *(.rodata.*) 352 *(.gnu.linkonce.r.*) 353 *(.rodata1) 354 355 . = ALIGN(4); 356 #include <snippets-rodata.ld> 357 #include <zephyr/linker/kobject-rom.ld> 358 359 __XT_EXCEPTION_TABLE__ = .; 360 KEEP (*(.xt_except_table)) 361 KEEP (*(.gcc_except_table .gcc_except_table.*)) 362 *(.gnu.linkonce.e.*) 363 *(.gnu.version_r) 364 KEEP (*(.eh_frame)) 365 KEEP (*crtbegin.o(.ctors)) 366 KEEP (*crtbegin.o(.dtors)) 367 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 368 KEEP (*(SORT(.dtors.*))) 369 KEEP (*(.dtors)) 370 __XT_EXCEPTION_DESCS__ = .; 371 *(.xt_except_desc) 372 *(.gnu.linkonce.h.*) 373 __XT_EXCEPTION_DESCS_END__ = .; 374 *(.xt_except_desc_end) 375 *(.dynamic) 376 *(.gnu.version_d) 377 _bss_table_start = .; 378 LONG(_bss_start) 379 LONG(_bss_end) 380 _bss_table_end = .; 381 MMU_PAGE_ALIGN 382 } >ram 383 384 .module_init : HDR_MMU_PAGE_ALIGN { 385 _module_init_start = .; 386 *(*.initcall) 387 _module_init_end = .; 388 } >ram 389 390#define RAMABLE_REGION ram 391#define ROMABLE_REGION ram 392 393 __common_rom_region_start = SEGSTART_CACHED; 394#include <zephyr/linker/common-rom.ld> 395/* Located in generated directory. This file is populated by calling 396 * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs. 397 */ 398#include <snippets-rom-sections.ld> 399 __rodata_region_end = .; 400 __common_rom_region_end = .; 401 __rodata_region_end = .; 402 403 .noinit SEGSTART_UNCACHED : HDR_MMU_PAGE_ALIGN { 404 __data_start = .; 405 *(.noinit) 406 *(.noinit.*) 407 } >ucram 408 409#include <zephyr/linker/kobject-priv-stacks.ld> 410 . = SEGSTART_UNCACHED; 411 412 .data SEGSTART_UNCACHED : HDR_MMU_PAGE_ALIGN { 413 *(.data) 414 *(.data.*) 415 *(.gnu.linkonce.d.*) 416 KEEP(*(.gnu.linkonce.d.*personality*)) 417 *(.data1) 418 *(.sdata) 419 *(.sdata.*) 420 *(.gnu.linkonce.s.*) 421 *(.sdata2) 422 *(.sdata2.*) 423 *(.gnu.linkonce.s2.*) 424 KEEP(*(.jcr)) 425 _trace_ctx_start = ABSOLUTE(.); 426 *(.trace_ctx) 427 _trace_ctx_end = ABSOLUTE(.); 428 *(.gna_model) 429 __data_end = .; 430 MMU_PAGE_ALIGN 431 } >ucram 432 433 .lit4 SEGSTART_CACHED : { 434 _lit4_start = .; 435 *(*.lit4) 436 *(.lit4.*) 437 *(.gnu.linkonce.lit4.*) 438 _lit4_end = .; 439 } >ram 440 441/* These values need to change in our scheme, where the common-ram 442 * sections need to be linked in safe/uncached memory but common-rom 443 * wants to use the cache 444 */ 445. = SEGSTART_UNCACHED; 446#undef RAMABLE_REGION 447#undef ROMABLE_REGION 448#define RAMABLE_REGION ucram 449#define ROMABLE_REGION ucram 450 451 .fw_ready SEGSTART_UNCACHED : { 452 KEEP(*(".fw_ready")); 453 KEEP (*(.fw_ready_metadata)) 454 } > ucram 455 456 __common_ram_region_start = .; 457 458#ifdef CONFIG_USERSPACE 459 460#define APP_SHARED_ALIGN MMU_PAGE_ALIGN 461#define EMPTY_APP_SHARED_ALIGN APP_SHARED_ALIGN 462 463 /* APP SHARED MEMORY REGION */ 464#include <app_smem.ld> 465 _app_smem_size = _app_smem_end - _app_smem_start; 466 _app_smem_num_words = _app_smem_size >> 2; 467 _app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME); 468#endif /* CONFIG_USERSPACE */ 469 470#include <zephyr/linker/common-ram.ld> 471#include <zephyr/linker/kobject-data.ld> 472 __common_ram_region_end = .; 473 474 .tm_clone_table : { 475 *(.tm_clone_table) 476 } >ram 477 478 /* This section is cached. By default it contains only declared 479 * thread stacks, but applications can put symbols here too. 480 */ 481 .cached SEGSTART_CACHED : { 482 _cached_start = .; 483 *(.cached .cached.*) 484#ifdef CONFIG_USERSPACE 485 z_user_stacks_start = .; 486 *(.user_stacks*) 487 z_user_stacks_end = .; 488#endif 489 _cached_end = .; 490 } >ram 491 492 /* Rimage requires 4k alignment between "DATA" and "BSS", can't do 493 * this in the section declaration below because we're also changing 494 * cacheability and that leaves a gap in the image large enough for 495 * binutils to decide to warn about (no way to turn that off, it 496 * seems, --warn-section-align is on by default) 497 */ 498 . = ALIGN(4096); 499 500 .bss SEGSTART_UNCACHED (NOLOAD) : 501 { 502 _bss_start = .; 503 *(.dynsbss) 504 *(.sbss) 505 *(.sbss.*) 506 *(.gnu.linkonce.sb.*) 507 *(.scommon) 508 *(.sbss2) 509 *(.sbss2.*) 510 *(.gnu.linkonce.sb2.*) 511 *(.dynbss) 512 *(.bss) 513 *(.bss.*) 514 *(.gnu.linkonce.b.*) 515 *(COMMON) 516 . = ALIGN(8); 517 MMU_PAGE_ALIGN 518 _bss_end = .; 519 } >ucram 520 521 . = SEGSTART_UNCACHED; 522 _end = ALIGN(8); 523 524 /* Heap start and end markers. Used to reserve system heap memory. */ 525 .heap_mem SEGSTART_UNCACHED (NOLOAD) : 526 { 527 _heap_start = .; 528 *(.heap_mem) 529 } >ucram 530 531 .unused_ram_start_marker SEGSTART_CACHED (NOLOAD) : 532 { 533 . = ALIGN(4096); 534 _unused_ram_start_marker = .; 535 *(.unused_ram_start_marker) 536 *(.unused_ram_start_marker.*) 537 z_mapped_end = .; 538 } >ram 539 540 /* Heap start and end markers. Used with libc malloc code. */ 541 . = SEGSTART_UNCACHED; 542 _end = ALIGN(8); 543 . = SEGSTART_CACHED; 544 z_mapped_end = .; 545 . = L2_SRAM_BASE + L2_SRAM_SIZE; 546 . = SEGSTART_UNCACHED; 547 _heap_end = .; 548 _heap_sentry = .; 549 . = SEGSTART_CACHED; 550 _image_ram_end = .; 551 552 /* dma buffers */ 553 .lpbuf (NOLOAD): { 554 _dma_buf_start = .; 555 *(.dma_buffers) 556 _dma_buf_end = .; 557 } >lpram 558 559 /* Non-loadable sections below. Back to cached memory so 560 * the cache remap script doesn't try to move them around needlessly. 561 */ 562 . = SEGSTART_CACHED; 563 564 /* rimage module manifest headers */ 565 .module.boot : { KEEP(*(.module.boot)) } >noload 566 .module.cold : { KEEP(*(.module.cold)) } >noload 567 .module.main : { KEEP(*(.module.main)) } >noload 568 569 .static_uuid_entries : { 570 *(*.static_uuids) 571 } >noload 572 573 .static_log_entries : { 574 *(*.static_log*) 575 } >noload 576 577 /* This is the "extended manifest" data (mostly versioning stuff) 578 * emitted by SOF and inspected by the kernel driver. It doesn't 579 * appear directly in the image, but rimage will parse and repack 580 * this into the output file header, so requires this be present 581 * even if empty. Alignment and padding to 16 bytes is required, 582 * otherwise rimage will complain about the size being wrong (which 583 * sounds like a struct should be declared packed somewhere...) 584 */ 585 .fw_metadata : ALIGN(16) { 586 KEEP (*(.fw_metadata)) 587 . = ALIGN(16); 588 } >noload 589 590#include <snippets-sections.ld> 591 592#include <zephyr/linker/debug-sections.ld> 593 594 /DISCARD/ : { *(.note.GNU-stack) } 595 596 .xtensa.info 0 : { *(.xtensa.info) } 597 .xt.insn 0 : { 598 KEEP (*(.xt.insn)) 599 KEEP (*(.gnu.linkonce.x.*)) 600 } 601 .xt.prop 0 : { 602 KEEP (*(.xt.prop)) 603 KEEP (*(.xt.prop.*)) 604 KEEP (*(.gnu.linkonce.prop.*)) 605 } 606 .xt.lit 0 : { 607 KEEP (*(.xt.lit)) 608 KEEP (*(.xt.lit.*)) 609 KEEP (*(.gnu.linkonce.p.*)) 610 } 611 .xt.profile_range 0 : { 612 KEEP (*(.xt.profile_range)) 613 KEEP (*(.gnu.linkonce.profile_range.*)) 614 } 615 .xt.profile_ranges 0 : { 616 KEEP (*(.xt.profile_ranges)) 617 KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) 618 } 619 .xt.profile_files 0 : { 620 KEEP (*(.xt.profile_files)) 621 KEEP (*(.gnu.linkonce.xt.profile_files.*)) 622 } 623 624#ifdef CONFIG_GEN_ISR_TABLES 625#include <zephyr/linker/intlist.ld> 626#endif 627 628#ifdef CONFIG_LLEXT 629#include <zephyr/linker/llext-sections.ld> 630#endif 631} 632
