1 /* 2 * Copyright (c) 2013-2014 Wind River Systems, Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file 9 * @brief Stack helpers for Cortex-M CPUs 10 * 11 * Stack helper functions. 12 */ 13 14 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ 15 #define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ 16 17 #ifdef _ASMLANGUAGE 18 19 /* nothing */ 20 21 #else 22 23 #include <arch/arm/aarch32/cortex_m/cmsis.h> 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 K_KERNEL_STACK_ARRAY_EXTERN(z_interrupt_stacks, CONFIG_MP_NUM_CPUS, 30 CONFIG_ISR_STACK_SIZE); 31 32 /** 33 * 34 * @brief Setup interrupt stack 35 * 36 * On Cortex-M, the interrupt stack is registered in the MSP (main stack 37 * pointer) register, and switched to automatically when taking an exception. 38 * 39 * @return N/A 40 */ z_arm_interrupt_stack_setup(void)41static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void) 42 { 43 uint32_t msp = 44 (uint32_t)(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) + 45 K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]); 46 47 __set_MSP(msp); 48 #if defined(CONFIG_BUILTIN_STACK_GUARD) 49 #if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM) 50 __set_MSPLIM((uint32_t)z_interrupt_stacks[0]); 51 #else 52 #error "Built-in MSP limit checks not supported by HW" 53 #endif 54 #endif /* CONFIG_BUILTIN_STACK_GUARD */ 55 56 #if defined(CONFIG_STACK_ALIGN_DOUBLE_WORD) 57 /* Enforce double-word stack alignment on exception entry 58 * for Cortex-M3 and Cortex-M4 (ARMv7-M) MCUs. For the rest 59 * of ARM Cortex-M processors this setting is enforced by 60 * default and it is not configurable. 61 */ 62 #if defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4) 63 SCB->CCR |= SCB_CCR_STKALIGN_Msk; 64 #endif 65 #endif /* CONFIG_STACK_ALIGN_DOUBLE_WORD */ 66 } 67 68 #ifdef __cplusplus 69 } 70 #endif 71 72 #endif /* _ASMLANGUAGE */ 73 74 #endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_STACK_H_ */ 75
