1 /** 2 ****************************************************************************** 3 * @file a3g4250d_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * a3g4250d_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef A3G4250D_REGS_H 23 #define A3G4250D_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup A3G4250D 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * 41 */ 42 43 #ifndef __BYTE_ORDER__ 44 45 #define DRV_LITTLE_ENDIAN 1234 46 #define DRV_BIG_ENDIAN 4321 47 48 /** if DRV_BYTE_ORDER is not defined, choose the endianness of your architecture 49 * by uncommenting the define which fits your platform endianness 50 */ 51 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 52 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 53 54 #else /* defined __BYTE_ORDER__ */ 55 56 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 57 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 58 #define DRV_BYTE_ORDER __BYTE_ORDER__ 59 60 #endif /* DRV_BYTE_ORDER */ 61 62 /** 63 * @} 64 * 65 */ 66 67 /** @defgroup STMicroelectronics sensors common types 68 * @{ 69 * 70 */ 71 72 #ifndef MEMS_SHARED_TYPES 73 #define MEMS_SHARED_TYPES 74 75 typedef struct 76 { 77 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 78 uint8_t bit0 : 1; 79 uint8_t bit1 : 1; 80 uint8_t bit2 : 1; 81 uint8_t bit3 : 1; 82 uint8_t bit4 : 1; 83 uint8_t bit5 : 1; 84 uint8_t bit6 : 1; 85 uint8_t bit7 : 1; 86 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 87 uint8_t bit7 : 1; 88 uint8_t bit6 : 1; 89 uint8_t bit5 : 1; 90 uint8_t bit4 : 1; 91 uint8_t bit3 : 1; 92 uint8_t bit2 : 1; 93 uint8_t bit1 : 1; 94 uint8_t bit0 : 1; 95 #endif /* DRV_BYTE_ORDER */ 96 } bitwise_t; 97 98 #define PROPERTY_DISABLE (0U) 99 #define PROPERTY_ENABLE (1U) 100 101 /** @addtogroup Interfaces_Functions 102 * @brief This section provide a set of functions used to read and 103 * write a generic register of the device. 104 * MANDATORY: return 0 -> no Error. 105 * @{ 106 * 107 */ 108 109 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 110 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 111 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 112 113 typedef struct 114 { 115 /** Component mandatory fields **/ 116 stmdev_write_ptr write_reg; 117 stmdev_read_ptr read_reg; 118 /** Component optional fields **/ 119 stmdev_mdelay_ptr mdelay; 120 /** Customizable optional pointer **/ 121 void *handle; 122 } stmdev_ctx_t; 123 124 /** 125 * @} 126 * 127 */ 128 129 #endif /* MEMS_SHARED_TYPES */ 130 131 #ifndef MEMS_UCF_SHARED_TYPES 132 #define MEMS_UCF_SHARED_TYPES 133 134 /** @defgroup Generic address-data structure definition 135 * @brief This structure is useful to load a predefined configuration 136 * of a sensor. 137 * You can create a sensor configuration by your own or using 138 * Unico / Unicleo tools available on STMicroelectronics 139 * web site. 140 * 141 * @{ 142 * 143 */ 144 145 typedef struct 146 { 147 uint8_t address; 148 uint8_t data; 149 } ucf_line_t; 150 151 /** 152 * @} 153 * 154 */ 155 156 #endif /* MEMS_UCF_SHARED_TYPES */ 157 158 /** 159 * @} 160 * 161 */ 162 163 /** 164 * @defgroup a3g4250d_Infos 165 * @{ 166 * 167 */ 168 169 /** I2C Device Address 8 bit format if SA0=0 -> 0xD1 if SA0=1 -> 0xD3 **/ 170 #define A3G4250D_I2C_ADD_L 0xD1U 171 #define A3G4250D_I2C_ADD_H 0xD3U 172 173 /** Device Identification (Who am I) **/ 174 #define A3G4250D_ID 0xD3U 175 176 /** 177 * @} 178 * 179 */ 180 181 #define A3G4250D_WHO_AM_I 0x0FU 182 #define A3G4250D_CTRL_REG1 0x20U 183 typedef struct 184 { 185 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 186 uint8_t pd : 4; /* xen yen zen pd */ 187 uint8_t bw : 2; 188 uint8_t dr : 2; 189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 190 uint8_t dr : 2; 191 uint8_t bw : 2; 192 uint8_t pd : 4; /* xen yen zen pd */ 193 #endif /* DRV_BYTE_ORDER */ 194 } a3g4250d_ctrl_reg1_t; 195 196 #define A3G4250D_CTRL_REG2 0x21U 197 typedef struct 198 { 199 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 200 uint8_t hpcf : 4; 201 uint8_t hpm : 2; 202 uint8_t not_used_01 : 2; 203 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 204 uint8_t not_used_01 : 2; 205 uint8_t hpm : 2; 206 uint8_t hpcf : 4; 207 #endif /* DRV_BYTE_ORDER */ 208 } a3g4250d_ctrl_reg2_t; 209 210 #define A3G4250D_CTRL_REG3 0x22U 211 typedef struct 212 { 213 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 214 uint8_t i2_empty : 1; 215 uint8_t i2_orun : 1; 216 uint8_t i2_wtm : 1; 217 uint8_t i2_drdy : 1; 218 uint8_t pp_od : 1; 219 uint8_t h_lactive : 1; 220 uint8_t i1_boot : 1; 221 uint8_t i1_int1 : 1; 222 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 223 uint8_t i1_int1 : 1; 224 uint8_t i1_boot : 1; 225 uint8_t h_lactive : 1; 226 uint8_t pp_od : 1; 227 uint8_t i2_drdy : 1; 228 uint8_t i2_wtm : 1; 229 uint8_t i2_orun : 1; 230 uint8_t i2_empty : 1; 231 #endif /* DRV_BYTE_ORDER */ 232 } a3g4250d_ctrl_reg3_t; 233 234 #define A3G4250D_CTRL_REG4 0x23U 235 typedef struct 236 { 237 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 238 uint8_t sim : 1; 239 uint8_t st : 2; 240 uint8_t not_used_01 : 3; 241 uint8_t ble : 1; 242 uint8_t not_used_02 : 1; 243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 244 uint8_t not_used_02 : 1; 245 uint8_t ble : 1; 246 uint8_t not_used_01 : 3; 247 uint8_t st : 2; 248 uint8_t sim : 1; 249 #endif /* DRV_BYTE_ORDER */ 250 } a3g4250d_ctrl_reg4_t; 251 252 #define A3G4250D_CTRL_REG5 0x24U 253 typedef struct 254 { 255 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 256 uint8_t out_sel : 2; 257 uint8_t int1_sel : 2; 258 uint8_t hpen : 1; 259 uint8_t not_used_01 : 1; 260 uint8_t fifo_en : 1; 261 uint8_t boot : 1; 262 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 263 uint8_t boot : 1; 264 uint8_t fifo_en : 1; 265 uint8_t not_used_01 : 1; 266 uint8_t hpen : 1; 267 uint8_t int1_sel : 2; 268 uint8_t out_sel : 2; 269 #endif /* DRV_BYTE_ORDER */ 270 } a3g4250d_ctrl_reg5_t; 271 272 #define A3G4250D_REFERENCE 0x25U 273 typedef struct 274 { 275 uint8_t ref : 8; 276 } a3g4250d_reference_t; 277 278 #define A3G4250D_OUT_TEMP 0x26U 279 #define A3G4250D_STATUS_REG 0x27U 280 typedef struct 281 { 282 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 283 uint8_t xda : 1; 284 uint8_t yda : 1; 285 uint8_t zda : 1; 286 uint8_t zyxda : 1; 287 uint8_t _xor : 1; 288 uint8_t yor : 1; 289 uint8_t zor : 1; 290 uint8_t zyxor : 1; 291 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 292 uint8_t zyxor : 1; 293 uint8_t zor : 1; 294 uint8_t yor : 1; 295 uint8_t _xor : 1; 296 uint8_t zyxda : 1; 297 uint8_t zda : 1; 298 uint8_t yda : 1; 299 uint8_t xda : 1; 300 #endif /* DRV_BYTE_ORDER */ 301 } a3g4250d_status_reg_t; 302 303 #define A3G4250D_OUT_X_L 0x28U 304 #define A3G4250D_OUT_X_H 0x29U 305 #define A3G4250D_OUT_Y_L 0x2AU 306 #define A3G4250D_OUT_Y_H 0x2BU 307 #define A3G4250D_OUT_Z_L 0x2CU 308 #define A3G4250D_OUT_Z_H 0x2DU 309 #define A3G4250D_FIFO_CTRL_REG 0x2EU 310 typedef struct 311 { 312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 313 uint8_t wtm : 5; 314 uint8_t fm : 3; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t fm : 3; 317 uint8_t wtm : 5; 318 #endif /* DRV_BYTE_ORDER */ 319 } a3g4250d_fifo_ctrl_reg_t; 320 321 #define A3G4250D_FIFO_SRC_REG 0x2FU 322 typedef struct 323 { 324 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 325 uint8_t fss : 5; 326 uint8_t empty : 1; 327 uint8_t ovrn : 1; 328 uint8_t wtm : 1; 329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 330 uint8_t wtm : 1; 331 uint8_t ovrn : 1; 332 uint8_t empty : 1; 333 uint8_t fss : 5; 334 #endif /* DRV_BYTE_ORDER */ 335 } a3g4250d_fifo_src_reg_t; 336 337 #define A3G4250D_INT1_CFG 0x30U 338 typedef struct 339 { 340 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 341 uint8_t xlie : 1; 342 uint8_t xhie : 1; 343 uint8_t ylie : 1; 344 uint8_t yhie : 1; 345 uint8_t zlie : 1; 346 uint8_t zhie : 1; 347 uint8_t lir : 1; 348 uint8_t and_or : 1; 349 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 350 uint8_t and_or : 1; 351 uint8_t lir : 1; 352 uint8_t zhie : 1; 353 uint8_t zlie : 1; 354 uint8_t yhie : 1; 355 uint8_t ylie : 1; 356 uint8_t xhie : 1; 357 uint8_t xlie : 1; 358 #endif /* DRV_BYTE_ORDER */ 359 } a3g4250d_int1_cfg_t; 360 361 #define A3G4250D_INT1_SRC 0x31U 362 typedef struct 363 { 364 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 365 uint8_t xl : 1; 366 uint8_t xh : 1; 367 uint8_t yl : 1; 368 uint8_t yh : 1; 369 uint8_t zl : 1; 370 uint8_t zh : 1; 371 uint8_t ia : 1; 372 uint8_t not_used_01 : 1; 373 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 374 uint8_t not_used_01 : 1; 375 uint8_t ia : 1; 376 uint8_t zh : 1; 377 uint8_t zl : 1; 378 uint8_t yh : 1; 379 uint8_t yl : 1; 380 uint8_t xh : 1; 381 uint8_t xl : 1; 382 #endif /* DRV_BYTE_ORDER */ 383 } a3g4250d_int1_src_t; 384 385 #define A3G4250D_INT1_TSH_XH 0x32U 386 typedef struct 387 { 388 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 389 uint8_t thsx : 7; 390 uint8_t not_used_01 : 1; 391 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 392 uint8_t not_used_01 : 1; 393 uint8_t thsx : 7; 394 #endif /* DRV_BYTE_ORDER */ 395 } a3g4250d_int1_tsh_xh_t; 396 397 #define A3G4250D_INT1_TSH_XL 0x33U 398 typedef struct 399 { 400 uint8_t thsx : 8; 401 } a3g4250d_int1_tsh_xl_t; 402 403 #define A3G4250D_INT1_TSH_YH 0x34U 404 typedef struct 405 { 406 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 407 uint8_t thsy : 7; 408 uint8_t not_used_01 : 1; 409 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 410 uint8_t not_used_01 : 1; 411 uint8_t thsy : 7; 412 #endif /* DRV_BYTE_ORDER */ 413 } a3g4250d_int1_tsh_yh_t; 414 415 #define A3G4250D_INT1_TSH_YL 0x35U 416 typedef struct 417 { 418 uint8_t thsy : 8; 419 } a3g4250d_int1_tsh_yl_t; 420 421 #define A3G4250D_INT1_TSH_ZH 0x36U 422 typedef struct 423 { 424 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 425 uint8_t thsz : 7; 426 uint8_t not_used_01 : 1; 427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 428 uint8_t not_used_01 : 1; 429 uint8_t thsz : 7; 430 #endif /* DRV_BYTE_ORDER */ 431 } a3g4250d_int1_tsh_zh_t; 432 433 #define A3G4250D_INT1_TSH_ZL 0x37U 434 typedef struct 435 { 436 uint8_t thsz : 8; 437 } a3g4250d_int1_tsh_zl_t; 438 439 #define A3G4250D_INT1_DURATION 0x38U 440 typedef struct 441 { 442 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 443 uint8_t d : 7; 444 uint8_t wait : 1; 445 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 446 uint8_t wait : 1; 447 uint8_t d : 7; 448 #endif /* DRV_BYTE_ORDER */ 449 } a3g4250d_int1_duration_t; 450 451 /** 452 * @defgroup A3G4250D_Register_Union 453 * @brief This union group all the registers having a bit-field 454 * description. 455 * This union is useful but it's not needed by the driver. 456 * 457 * REMOVING this union you are compliant with: 458 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 459 * 460 * @{ 461 * 462 */ 463 464 typedef union 465 { 466 a3g4250d_ctrl_reg1_t ctrl_reg1; 467 a3g4250d_ctrl_reg2_t ctrl_reg2; 468 a3g4250d_ctrl_reg3_t ctrl_reg3; 469 a3g4250d_ctrl_reg4_t ctrl_reg4; 470 a3g4250d_ctrl_reg5_t ctrl_reg5; 471 a3g4250d_reference_t reference; 472 a3g4250d_status_reg_t status_reg; 473 a3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; 474 a3g4250d_fifo_src_reg_t fifo_src_reg; 475 a3g4250d_int1_cfg_t int1_cfg; 476 a3g4250d_int1_src_t int1_src; 477 a3g4250d_int1_tsh_xh_t int1_tsh_xh; 478 a3g4250d_int1_tsh_xl_t int1_tsh_xl; 479 a3g4250d_int1_tsh_yh_t int1_tsh_yh; 480 a3g4250d_int1_tsh_yl_t int1_tsh_yl; 481 a3g4250d_int1_tsh_zh_t int1_tsh_zh; 482 a3g4250d_int1_tsh_zl_t int1_tsh_zl; 483 a3g4250d_int1_duration_t int1_duration; 484 bitwise_t bitwise; 485 uint8_t byte; 486 } a3g4250d_reg_t; 487 488 /** 489 * @} 490 * 491 */ 492 493 #ifndef __weak 494 #define __weak __attribute__((weak)) 495 #endif /* __weak */ 496 497 /* 498 * These are the basic platform dependent I/O routines to read 499 * and write device registers connected on a standard bus. 500 * The driver keeps offering a default implementation based on function 501 * pointers to read/write routines for backward compatibility. 502 * The __weak directive allows the final application to overwrite 503 * them with a custom implementation. 504 */ 505 506 int32_t a3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 507 uint8_t *data, 508 uint16_t len); 509 int32_t a3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 510 uint8_t *data, 511 uint16_t len); 512 513 float_t a3g4250d_from_fs245dps_to_mdps(int16_t lsb); 514 float_t a3g4250d_from_lsb_to_celsius(int16_t lsb); 515 516 int32_t a3g4250d_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); 517 int32_t a3g4250d_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 518 519 int32_t a3g4250d_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); 520 int32_t a3g4250d_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 521 522 int32_t a3g4250d_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); 523 int32_t a3g4250d_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 524 525 typedef enum 526 { 527 A3G4250D_ODR_OFF = 0x00, 528 A3G4250D_ODR_SLEEP = 0x08, 529 A3G4250D_ODR_100Hz = 0x0F, 530 A3G4250D_ODR_200Hz = 0x1F, 531 A3G4250D_ODR_400Hz = 0x2F, 532 A3G4250D_ODR_800Hz = 0x3F, 533 } a3g4250d_dr_t; 534 int32_t a3g4250d_data_rate_set(const stmdev_ctx_t *ctx, a3g4250d_dr_t val); 535 int32_t a3g4250d_data_rate_get(const stmdev_ctx_t *ctx, a3g4250d_dr_t *val); 536 537 int32_t a3g4250d_status_reg_get(const stmdev_ctx_t *ctx, 538 a3g4250d_status_reg_t *val); 539 540 int32_t a3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 541 542 int32_t a3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 543 544 int32_t a3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 545 546 int32_t a3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 547 548 typedef enum 549 { 550 A3G4250D_GY_ST_DISABLE = 0, 551 A3G4250D_GY_ST_POSITIVE = 1, 552 A3G4250D_GY_ST_NEGATIVE = 3, 553 } a3g4250d_st_t; 554 int32_t a3g4250d_self_test_set(const stmdev_ctx_t *ctx, a3g4250d_st_t val); 555 int32_t a3g4250d_self_test_get(const stmdev_ctx_t *ctx, a3g4250d_st_t *val); 556 557 typedef enum 558 { 559 A3G4250D_AUX_LSB_AT_LOW_ADD = 0, 560 A3G4250D_AUX_MSB_AT_LOW_ADD = 1, 561 } a3g4250d_ble_t; 562 int32_t a3g4250d_data_format_set(const stmdev_ctx_t *ctx, a3g4250d_ble_t val); 563 int32_t a3g4250d_data_format_get(const stmdev_ctx_t *ctx, a3g4250d_ble_t *val); 564 565 int32_t a3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 566 int32_t a3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 567 568 typedef enum 569 { 570 A3G4250D_CUT_OFF_LOW = 0, 571 A3G4250D_CUT_OFF_MEDIUM = 1, 572 A3G4250D_CUT_OFF_HIGH = 2, 573 A3G4250D_CUT_OFF_VERY_HIGH = 3, 574 } a3g4250d_bw_t; 575 int32_t a3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_bw_t val); 576 int32_t a3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_bw_t *val); 577 578 typedef enum 579 { 580 A3G4250D_HP_LEVEL_0 = 0, 581 A3G4250D_HP_LEVEL_1 = 1, 582 A3G4250D_HP_LEVEL_2 = 2, 583 A3G4250D_HP_LEVEL_3 = 3, 584 A3G4250D_HP_LEVEL_4 = 4, 585 A3G4250D_HP_LEVEL_5 = 5, 586 A3G4250D_HP_LEVEL_6 = 6, 587 A3G4250D_HP_LEVEL_7 = 7, 588 A3G4250D_HP_LEVEL_8 = 8, 589 A3G4250D_HP_LEVEL_9 = 9, 590 } a3g4250d_hpcf_t; 591 int32_t a3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t val); 592 int32_t a3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, a3g4250d_hpcf_t *val); 593 594 typedef enum 595 { 596 A3G4250D_HP_NORMAL_MODE_WITH_RST = 0, 597 A3G4250D_HP_REFERENCE_SIGNAL = 1, 598 A3G4250D_HP_NORMAL_MODE = 2, 599 A3G4250D_HP_AUTO_RESET_ON_INT = 3, 600 } a3g4250d_hpm_t; 601 int32_t a3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, a3g4250d_hpm_t val); 602 int32_t a3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, a3g4250d_hpm_t *val); 603 604 typedef enum 605 { 606 A3G4250D_ONLY_LPF1_ON_OUT = 0, 607 A3G4250D_LPF1_HP_ON_OUT = 1, 608 A3G4250D_LPF1_LPF2_ON_OUT = 2, 609 A3G4250D_LPF1_HP_LPF2_ON_OUT = 6, 610 } a3g4250d_out_sel_t; 611 int32_t a3g4250d_filter_path_set(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t val); 612 int32_t a3g4250d_filter_path_get(const stmdev_ctx_t *ctx, a3g4250d_out_sel_t *val); 613 614 typedef enum 615 { 616 A3G4250D_ONLY_LPF1_ON_INT = 0, 617 A3G4250D_LPF1_HP_ON_INT = 1, 618 A3G4250D_LPF1_LPF2_ON_INT = 2, 619 A3G4250D_LPF1_HP_LPF2_ON_INT = 6, 620 } a3g4250d_int1_sel_t; 621 int32_t a3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx, 622 a3g4250d_int1_sel_t val); 623 int32_t a3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, 624 a3g4250d_int1_sel_t *val); 625 626 int32_t a3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx, uint8_t val); 627 int32_t a3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, uint8_t *val); 628 629 typedef enum 630 { 631 A3G4250D_SPI_4_WIRE = 0, 632 A3G4250D_SPI_3_WIRE = 1, 633 } a3g4250d_sim_t; 634 int32_t a3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, a3g4250d_sim_t val); 635 int32_t a3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, a3g4250d_sim_t *val); 636 637 typedef struct 638 { 639 uint8_t i1_int1 : 1; 640 uint8_t i1_boot : 1; 641 } a3g4250d_int1_route_t; 642 int32_t a3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx, 643 a3g4250d_int1_route_t val); 644 int32_t a3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, 645 a3g4250d_int1_route_t *val); 646 647 typedef struct 648 { 649 uint8_t i2_empty : 1; 650 uint8_t i2_orun : 1; 651 uint8_t i2_wtm : 1; 652 uint8_t i2_drdy : 1; 653 } a3g4250d_int2_route_t; 654 int32_t a3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx, 655 a3g4250d_int2_route_t val); 656 int32_t a3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, 657 a3g4250d_int2_route_t *val); 658 659 typedef enum 660 { 661 A3G4250D_PUSH_PULL = 0, 662 A3G4250D_OPEN_DRAIN = 1, 663 } a3g4250d_pp_od_t; 664 int32_t a3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, a3g4250d_pp_od_t val); 665 int32_t a3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, a3g4250d_pp_od_t *val); 666 667 typedef enum 668 { 669 A3G4250D_ACTIVE_HIGH = 0, 670 A3G4250D_ACTIVE_LOW = 1, 671 } a3g4250d_h_lactive_t; 672 int32_t a3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx, 673 a3g4250d_h_lactive_t val); 674 int32_t a3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, 675 a3g4250d_h_lactive_t *val); 676 677 typedef enum 678 { 679 A3G4250D_INT_PULSED = 0, 680 A3G4250D_INT_LATCHED = 1, 681 } a3g4250d_lir_t; 682 int32_t a3g4250d_int_notification_set(const stmdev_ctx_t *ctx, a3g4250d_lir_t val); 683 int32_t a3g4250d_int_notification_get(const stmdev_ctx_t *ctx, a3g4250d_lir_t *val); 684 685 int32_t a3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx, 686 a3g4250d_int1_cfg_t *val); 687 int32_t a3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx, 688 a3g4250d_int1_cfg_t *val); 689 690 typedef enum 691 { 692 A3G4250D_INT1_ON_TH_AND = 1, 693 A3G4250D_INT1_ON_TH_OR = 0, 694 } a3g4250d_and_or_t; 695 int32_t a3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, 696 a3g4250d_and_or_t val); 697 int32_t a3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, 698 a3g4250d_and_or_t *val); 699 700 int32_t a3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx, 701 a3g4250d_int1_src_t *val); 702 703 int32_t a3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 704 int32_t a3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 705 706 int32_t a3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 707 int32_t a3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 708 709 int32_t a3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 710 int32_t a3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 711 712 int32_t a3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 713 int32_t a3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 714 715 int32_t a3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val); 716 int32_t a3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val); 717 718 int32_t a3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 719 int32_t a3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 720 721 typedef enum 722 { 723 A3G4250D_FIFO_BYPASS_MODE = 0x00, 724 A3G4250D_FIFO_MODE = 0x01, 725 A3G4250D_FIFO_STREAM_MODE = 0x02, 726 } a3g4250d_fifo_mode_t; 727 int32_t a3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t val); 728 int32_t a3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, a3g4250d_fifo_mode_t *val); 729 730 int32_t a3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 731 732 int32_t a3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 733 734 int32_t a3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 735 736 int32_t a3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 737 738 /** 739 * @} 740 * 741 */ 742 743 #ifdef __cplusplus 744 } 745 #endif 746 747 #endif /* A3G4250D_REGS_H */ 748 749 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 750
