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49 <div class="headertitle"> 50<div class="title">RTE_Device.h File Reference</div> </div> 51</div><!--header--> 52<div class="contents"> 53<div class="textblock"><div class="dynheader"> 54This graph shows which files directly or indirectly include this file:</div> 55<div class="dyncontent"> 56<div class="center"><img src="a04732.png" border="0" usemap="#boardkit_2mek-mimx8qm_2_r_t_e___device_8hdep" alt=""/></div> 57<map name="boardkit_2mek-mimx8qm_2_r_t_e___device_8hdep" id="boardkit_2mek-mimx8qm_2_r_t_e___device_8hdep"> 58<area shape="rect" id="node2" href="a00758.html" title="The mekmimx8qm.h file defines GPIO pin mappings and on-board sensors information for mekmimx8qm board..." alt="" coords="5,95,164,136"/> 59</map> 60</div> 61</div> 62<p><a href="a04730_source.html">Go to the source code of this file.</a></p> 63<table class="memberdecls"> 64<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> 65Macros</h2></td></tr> 66<tr class="memitem:a7701382ade504d7eddda8c1231279cec"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a7701382ade504d7eddda8c1231279cec">LPI2C0</a>   CM4_0__LPI2C</td></tr> 67<tr class="separator:a7701382ade504d7eddda8c1231279cec"><td class="memSeparator" colspan="2"> </td></tr> 68<tr class="memitem:ae9ef15442986812d986ae9cc6b4cdf88"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ae9ef15442986812d986ae9cc6b4cdf88">LPI2C1</a>   CM4_1__LPI2C</td></tr> 69<tr class="separator:ae9ef15442986812d986ae9cc6b4cdf88"><td class="memSeparator" colspan="2"> </td></tr> 70<tr class="memitem:a0c971bafd33997b4d43d7cb61c6a6236"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a0c971bafd33997b4d43d7cb61c6a6236">LPI2C2</a>   DMA__LPI2C0</td></tr> 71<tr class="separator:a0c971bafd33997b4d43d7cb61c6a6236"><td class="memSeparator" colspan="2"> </td></tr> 72<tr class="memitem:af3c8daab94b3b0d2c0158e0cedb6c3fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#af3c8daab94b3b0d2c0158e0cedb6c3fc">LPI2C3</a>   DMA__LPI2C1</td></tr> 73<tr class="separator:af3c8daab94b3b0d2c0158e0cedb6c3fc"><td class="memSeparator" colspan="2"> </td></tr> 74<tr class="memitem:a046632a83702c613f8c0079752219d9b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a046632a83702c613f8c0079752219d9b">LPI2C4</a>   DMA__LPI2C2</td></tr> 75<tr class="separator:a046632a83702c613f8c0079752219d9b"><td class="memSeparator" colspan="2"> </td></tr> 76<tr class="memitem:a96978e509a91b8aea5b4246405dc762b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a96978e509a91b8aea5b4246405dc762b">LPI2C5</a>   DMA__LPI2C3</td></tr> 77<tr class="separator:a96978e509a91b8aea5b4246405dc762b"><td class="memSeparator" colspan="2"> </td></tr> 78<tr class="memitem:aff57940e609bbf508d3a366abd1ed466"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aff57940e609bbf508d3a366abd1ed466">LPI2C6</a>   DMA__LPI2C4</td></tr> 79<tr class="separator:aff57940e609bbf508d3a366abd1ed466"><td class="memSeparator" colspan="2"> </td></tr> 80<tr class="memitem:afdae116c2c595573ddee8725b6a4602a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#afdae116c2c595573ddee8725b6a4602a">RTE_I2C0</a>   0</td></tr> 81<tr class="separator:afdae116c2c595573ddee8725b6a4602a"><td class="memSeparator" colspan="2"> </td></tr> 82<tr class="memitem:ab3079b071b25a964033ece9a17ebc622"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ab3079b071b25a964033ece9a17ebc622">RTE_I2C0_DMA_EN</a>   0</td></tr> 83<tr class="separator:ab3079b071b25a964033ece9a17ebc622"><td class="memSeparator" colspan="2"> </td></tr> 84<tr class="memitem:aa4264010a207548708e4eb5030b77b42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aa4264010a207548708e4eb5030b77b42">RTE_I2C1</a>   0</td></tr> 85<tr class="separator:aa4264010a207548708e4eb5030b77b42"><td class="memSeparator" colspan="2"> </td></tr> 86<tr class="memitem:aac0deee79f0bfe76842a606f89347141"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aac0deee79f0bfe76842a606f89347141">RTE_I2C1_DMA_EN</a>   0</td></tr> 87<tr class="separator:aac0deee79f0bfe76842a606f89347141"><td class="memSeparator" colspan="2"> </td></tr> 88<tr class="memitem:a6b312911602934f2275e5bfdd964a3c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a6b312911602934f2275e5bfdd964a3c2">RTE_I2C2</a>   1</td></tr> 89<tr class="separator:a6b312911602934f2275e5bfdd964a3c2"><td class="memSeparator" colspan="2"> </td></tr> 90<tr class="memitem:aa6833427b8acb64e5b2cdca71adc4731"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aa6833427b8acb64e5b2cdca71adc4731">RTE_I2C2_DMA_EN</a>   0</td></tr> 91<tr class="separator:aa6833427b8acb64e5b2cdca71adc4731"><td class="memSeparator" colspan="2"> </td></tr> 92<tr class="memitem:a286e0b83a4a1806a5125d1e805afed5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a286e0b83a4a1806a5125d1e805afed5e">RTE_I2C3</a>   0</td></tr> 93<tr class="separator:a286e0b83a4a1806a5125d1e805afed5e"><td class="memSeparator" colspan="2"> </td></tr> 94<tr class="memitem:a7e2203f604dc9bfc5ae76af6364b8e38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a7e2203f604dc9bfc5ae76af6364b8e38">RTE_I2C3_DMA_EN</a>   0</td></tr> 95<tr class="separator:a7e2203f604dc9bfc5ae76af6364b8e38"><td class="memSeparator" colspan="2"> </td></tr> 96<tr class="memitem:aaefd2724bd50bf611680b12680c5cd47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aaefd2724bd50bf611680b12680c5cd47">RTE_I2C4</a>   0</td></tr> 97<tr class="separator:aaefd2724bd50bf611680b12680c5cd47"><td class="memSeparator" colspan="2"> </td></tr> 98<tr class="memitem:ad0881b5c0250fd24034d35a0db8e81d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ad0881b5c0250fd24034d35a0db8e81d6">RTE_I2C4_DMA_EN</a>   0</td></tr> 99<tr class="separator:ad0881b5c0250fd24034d35a0db8e81d6"><td class="memSeparator" colspan="2"> </td></tr> 100<tr class="memitem:af34a2837397fb473c1a29f942886f20a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#af34a2837397fb473c1a29f942886f20a">RTE_I2C5</a>   0</td></tr> 101<tr class="separator:af34a2837397fb473c1a29f942886f20a"><td class="memSeparator" colspan="2"> </td></tr> 102<tr class="memitem:a11fcca5364c2c59d91dcd1024a3741cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a11fcca5364c2c59d91dcd1024a3741cd">RTE_I2C5_DMA_EN</a>   0</td></tr> 103<tr class="separator:a11fcca5364c2c59d91dcd1024a3741cd"><td class="memSeparator" colspan="2"> </td></tr> 104<tr class="memitem:a3def854682bc112f022a79dd60ca29d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a3def854682bc112f022a79dd60ca29d7">RTE_I2C6</a>   0</td></tr> 105<tr class="separator:a3def854682bc112f022a79dd60ca29d7"><td class="memSeparator" colspan="2"> </td></tr> 106<tr class="memitem:a1c6ff3c4d303f391e5ec124aa238c08f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a1c6ff3c4d303f391e5ec124aa238c08f">RTE_I2C6_DMA_EN</a>   0</td></tr> 107<tr class="separator:a1c6ff3c4d303f391e5ec124aa238c08f"><td class="memSeparator" colspan="2"> </td></tr> 108<tr class="memitem:ad552d158bcba2b8f961993cc9a198538"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ad552d158bcba2b8f961993cc9a198538">LPSPI0</a>   DMA__LPSPI0</td></tr> 109<tr class="separator:ad552d158bcba2b8f961993cc9a198538"><td class="memSeparator" colspan="2"> </td></tr> 110<tr class="memitem:ac2fa96bc980d401c36834549b3688009"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ac2fa96bc980d401c36834549b3688009">LPSPI1</a>   DMA__LPSPI1</td></tr> 111<tr class="separator:ac2fa96bc980d401c36834549b3688009"><td class="memSeparator" colspan="2"> </td></tr> 112<tr class="memitem:ae45a21782e5f7d05636cdaac3bdda86d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ae45a21782e5f7d05636cdaac3bdda86d">LPSPI2</a>   DMA__LPSPI2</td></tr> 113<tr class="separator:ae45a21782e5f7d05636cdaac3bdda86d"><td class="memSeparator" colspan="2"> </td></tr> 114<tr class="memitem:a4850e0354a725db60884a96d957bc205"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a4850e0354a725db60884a96d957bc205">LPSPI3</a>   DMA__LPSPI3</td></tr> 115<tr class="separator:a4850e0354a725db60884a96d957bc205"><td class="memSeparator" colspan="2"> </td></tr> 116<tr class="memitem:a0529e9360e95f2b1e4c67b49ae2df44c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a0529e9360e95f2b1e4c67b49ae2df44c">RTE_SPI0</a>   0</td></tr> 117<tr class="separator:a0529e9360e95f2b1e4c67b49ae2df44c"><td class="memSeparator" colspan="2"> </td></tr> 118<tr class="memitem:a7dd0070f51cd6be78f323f82df082b74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a7dd0070f51cd6be78f323f82df082b74">RTE_SPI0_DMA_EN</a>   0</td></tr> 119<tr class="separator:a7dd0070f51cd6be78f323f82df082b74"><td class="memSeparator" colspan="2"> </td></tr> 120<tr class="memitem:adc244beab1014dda00966fcbbb65578c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#adc244beab1014dda00966fcbbb65578c">RTE_SPI1</a>   0</td></tr> 121<tr class="separator:adc244beab1014dda00966fcbbb65578c"><td class="memSeparator" colspan="2"> </td></tr> 122<tr class="memitem:aa77f48b8f0f046f17b57ee388ba986c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aa77f48b8f0f046f17b57ee388ba986c3">RTE_SPI1_DMA_EN</a>   0</td></tr> 123<tr class="separator:aa77f48b8f0f046f17b57ee388ba986c3"><td class="memSeparator" colspan="2"> </td></tr> 124<tr class="memitem:a23c083e17af81df6307b6a09c7b526bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a23c083e17af81df6307b6a09c7b526bd">RTE_SPI2</a>   1</td></tr> 125<tr class="separator:a23c083e17af81df6307b6a09c7b526bd"><td class="memSeparator" colspan="2"> </td></tr> 126<tr class="memitem:af6ec6eb776de0e8df30bc2acc19f9221"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#af6ec6eb776de0e8df30bc2acc19f9221">RTE_SPI2_DMA_EN</a>   0</td></tr> 127<tr class="separator:af6ec6eb776de0e8df30bc2acc19f9221"><td class="memSeparator" colspan="2"> </td></tr> 128<tr class="memitem:aa78a035aaa73a024f3e9ad91e3d28c18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aa78a035aaa73a024f3e9ad91e3d28c18">RTE_SPI3</a>   0</td></tr> 129<tr class="separator:aa78a035aaa73a024f3e9ad91e3d28c18"><td class="memSeparator" colspan="2"> </td></tr> 130<tr class="memitem:a262ea23b85408aacef35d7dea979abfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a262ea23b85408aacef35d7dea979abfd">RTE_SPI3_DMA_EN</a>   0</td></tr> 131<tr class="separator:a262ea23b85408aacef35d7dea979abfd"><td class="memSeparator" colspan="2"> </td></tr> 132<tr class="memitem:a5b2895bb50a19a21ddb954c28977629b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a5b2895bb50a19a21ddb954c28977629b">LPUART0</a>   CM4_0__LPUART</td></tr> 133<tr class="separator:a5b2895bb50a19a21ddb954c28977629b"><td class="memSeparator" colspan="2"> </td></tr> 134<tr class="memitem:a73eb37d103f4e4f2d18ec3d3f5208ab9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a73eb37d103f4e4f2d18ec3d3f5208ab9">LPUART1</a>   CM4_1__LPUART</td></tr> 135<tr class="separator:a73eb37d103f4e4f2d18ec3d3f5208ab9"><td class="memSeparator" colspan="2"> </td></tr> 136<tr class="memitem:aeb546d3c2b55e486a3d4711255c46fc9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aeb546d3c2b55e486a3d4711255c46fc9">LPUART2</a>   DMA__LPUART0</td></tr> 137<tr class="separator:aeb546d3c2b55e486a3d4711255c46fc9"><td class="memSeparator" colspan="2"> </td></tr> 138<tr class="memitem:abf380b4bd4c865aa97ff2420ec4718c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#abf380b4bd4c865aa97ff2420ec4718c3">LPUART3</a>   DMA__LPUART1</td></tr> 139<tr class="separator:abf380b4bd4c865aa97ff2420ec4718c3"><td class="memSeparator" colspan="2"> </td></tr> 140<tr class="memitem:a9d8ddb2d0d4d61a63ad00b6fd9df5f68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a9d8ddb2d0d4d61a63ad00b6fd9df5f68">LPUART4</a>   DMA__LPUART2</td></tr> 141<tr class="separator:a9d8ddb2d0d4d61a63ad00b6fd9df5f68"><td class="memSeparator" colspan="2"> </td></tr> 142<tr class="memitem:ab8b8889fd34c86c965bffbbe3be3774f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ab8b8889fd34c86c965bffbbe3be3774f">LPUART5</a>   DMA__LPUART3</td></tr> 143<tr class="separator:ab8b8889fd34c86c965bffbbe3be3774f"><td class="memSeparator" colspan="2"> </td></tr> 144<tr class="memitem:a353278699075ac94a78666fabfb6ecfc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a353278699075ac94a78666fabfb6ecfc">LPUART6</a>   DMA__LPUART4</td></tr> 145<tr class="separator:a353278699075ac94a78666fabfb6ecfc"><td class="memSeparator" colspan="2"> </td></tr> 146<tr class="memitem:a17b2c1002dc50e01a17a2ce94a628133"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a17b2c1002dc50e01a17a2ce94a628133">RTE_USART0</a>   0</td></tr> 147<tr class="separator:a17b2c1002dc50e01a17a2ce94a628133"><td class="memSeparator" colspan="2"> </td></tr> 148<tr class="memitem:a3071e002a5a0ce4ac87de6dcc87bb3da"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a3071e002a5a0ce4ac87de6dcc87bb3da">RTE_USART0_DMA_EN</a>   0</td></tr> 149<tr class="separator:a3071e002a5a0ce4ac87de6dcc87bb3da"><td class="memSeparator" colspan="2"> </td></tr> 150<tr class="memitem:ae8f0e0260407d14858ce86d2ffb75424"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ae8f0e0260407d14858ce86d2ffb75424">RTE_USART1</a>   0</td></tr> 151<tr class="separator:ae8f0e0260407d14858ce86d2ffb75424"><td class="memSeparator" colspan="2"> </td></tr> 152<tr class="memitem:a93373776f843912cefd1355e207352e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a93373776f843912cefd1355e207352e2">RTE_USART1_DMA_EN</a>   0</td></tr> 153<tr class="separator:a93373776f843912cefd1355e207352e2"><td class="memSeparator" colspan="2"> </td></tr> 154<tr class="memitem:af4f4f5e1f698d40d9f7d716257536d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#af4f4f5e1f698d40d9f7d716257536d42">RTE_USART2</a>   0</td></tr> 155<tr class="separator:af4f4f5e1f698d40d9f7d716257536d42"><td class="memSeparator" colspan="2"> </td></tr> 156<tr class="memitem:a125adde5b7b5906d3427a57420322722"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a125adde5b7b5906d3427a57420322722">RTE_USART2_DMA_EN</a>   0</td></tr> 157<tr class="separator:a125adde5b7b5906d3427a57420322722"><td class="memSeparator" colspan="2"> </td></tr> 158<tr class="memitem:ae6d7bafeb9d5b445ebadbd0f224bf1a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ae6d7bafeb9d5b445ebadbd0f224bf1a5">RTE_USART3</a>   0</td></tr> 159<tr class="separator:ae6d7bafeb9d5b445ebadbd0f224bf1a5"><td class="memSeparator" colspan="2"> </td></tr> 160<tr class="memitem:a64fade6195385d3c00eeb16517725bb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a64fade6195385d3c00eeb16517725bb5">RTE_USART3_DMA_EN</a>   0</td></tr> 161<tr class="separator:a64fade6195385d3c00eeb16517725bb5"><td class="memSeparator" colspan="2"> </td></tr> 162<tr class="memitem:a3716b269a4311d87ba183b633ebfad07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a3716b269a4311d87ba183b633ebfad07">RTE_USART4</a>   1</td></tr> 163<tr class="separator:a3716b269a4311d87ba183b633ebfad07"><td class="memSeparator" colspan="2"> </td></tr> 164<tr class="memitem:abccb132237192d276dec5fd1235d3124"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#abccb132237192d276dec5fd1235d3124">RTE_USART4_DMA_EN</a>   0</td></tr> 165<tr class="separator:abccb132237192d276dec5fd1235d3124"><td class="memSeparator" colspan="2"> </td></tr> 166<tr class="memitem:a5c2c625ac67c8f31440a92490b6d767e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a5c2c625ac67c8f31440a92490b6d767e">RTE_USART5</a>   0</td></tr> 167<tr class="separator:a5c2c625ac67c8f31440a92490b6d767e"><td class="memSeparator" colspan="2"> </td></tr> 168<tr class="memitem:aaf003f78b5c4c182d687b220e75e1dbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aaf003f78b5c4c182d687b220e75e1dbb">RTE_USART5_DMA_EN</a>   0</td></tr> 169<tr class="separator:aaf003f78b5c4c182d687b220e75e1dbb"><td class="memSeparator" colspan="2"> </td></tr> 170<tr class="memitem:af4a7b2970a0f7ac0ee0802298c09848c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#af4a7b2970a0f7ac0ee0802298c09848c">RTE_USART6</a>   0</td></tr> 171<tr class="separator:af4a7b2970a0f7ac0ee0802298c09848c"><td class="memSeparator" colspan="2"> </td></tr> 172<tr class="memitem:a46301a9b2d783e5c629b180d8f2344f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a46301a9b2d783e5c629b180d8f2344f6">RTE_USART6_DMA_EN</a>   0</td></tr> 173<tr class="separator:a46301a9b2d783e5c629b180d8f2344f6"><td class="memSeparator" colspan="2"> </td></tr> 174<tr class="memitem:aaafac93c554b337745d91aeeaa263ee3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aaafac93c554b337745d91aeeaa263ee3">RTE_I2C2_DMA_TX_CH</a>   1</td></tr> 175<tr class="separator:aaafac93c554b337745d91aeeaa263ee3"><td class="memSeparator" colspan="2"> </td></tr> 176<tr class="memitem:a282e3c43099524332084d89c4dc0370a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a282e3c43099524332084d89c4dc0370a">RTE_I2C2_DMA_TX_PERI_SEL</a>   1</td></tr> 177<tr class="separator:a282e3c43099524332084d89c4dc0370a"><td class="memSeparator" colspan="2"> </td></tr> 178<tr class="memitem:ad4f1a37be61763d2594b4f539ae03d44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ad4f1a37be61763d2594b4f539ae03d44">RTE_I2C2_DMA_TX_DMA_BASE</a>   DMA__DMA1</td></tr> 179<tr class="separator:ad4f1a37be61763d2594b4f539ae03d44"><td class="memSeparator" colspan="2"> </td></tr> 180<tr class="memitem:a762b3880f4254c392f2f152393776679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a762b3880f4254c392f2f152393776679">RTE_I2C2_DMA_RX_CH</a>   0</td></tr> 181<tr class="separator:a762b3880f4254c392f2f152393776679"><td class="memSeparator" colspan="2"> </td></tr> 182<tr class="memitem:ad7eb717542257f354c6b41ad348a1404"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ad7eb717542257f354c6b41ad348a1404">RTE_I2C2_DMA_RX_PERI_SEL</a>   0</td></tr> 183<tr class="separator:ad7eb717542257f354c6b41ad348a1404"><td class="memSeparator" colspan="2"> </td></tr> 184<tr class="memitem:a1ca82c1fea8b1c55875df9cf0e3e4266"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a1ca82c1fea8b1c55875df9cf0e3e4266">RTE_I2C2_DMA_RX_DMA_BASE</a>   DMA__DMA1</td></tr> 185<tr class="separator:a1ca82c1fea8b1c55875df9cf0e3e4266"><td class="memSeparator" colspan="2"> </td></tr> 186<tr class="memitem:a8d59722d63164553e1aa90f0b5531aa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a8d59722d63164553e1aa90f0b5531aa6">RTE_I2C3_DMA_TX_CH</a>   3</td></tr> 187<tr class="separator:a8d59722d63164553e1aa90f0b5531aa6"><td class="memSeparator" colspan="2"> </td></tr> 188<tr class="memitem:a1f3419a15ebd3e7915ab02ddb9d8e57a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a1f3419a15ebd3e7915ab02ddb9d8e57a">RTE_I2C3_DMA_TX_PERI_SEL</a>   3</td></tr> 189<tr class="separator:a1f3419a15ebd3e7915ab02ddb9d8e57a"><td class="memSeparator" colspan="2"> </td></tr> 190<tr class="memitem:a21c43b61ee31798e368937bdbc945eb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a21c43b61ee31798e368937bdbc945eb7">RTE_I2C3_DMA_TX_DMA_BASE</a>   DMA__DMA1</td></tr> 191<tr class="separator:a21c43b61ee31798e368937bdbc945eb7"><td class="memSeparator" colspan="2"> </td></tr> 192<tr class="memitem:ac78874337ab81de6e42b051fb9dce871"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ac78874337ab81de6e42b051fb9dce871">RTE_I2C3_DMA_RX_CH</a>   2</td></tr> 193<tr class="separator:ac78874337ab81de6e42b051fb9dce871"><td class="memSeparator" colspan="2"> </td></tr> 194<tr class="memitem:a0994b2eeb8af41123e69175ac6f9c7b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a0994b2eeb8af41123e69175ac6f9c7b0">RTE_I2C3_DMA_RX_PERI_SEL</a>   2</td></tr> 195<tr class="separator:a0994b2eeb8af41123e69175ac6f9c7b0"><td class="memSeparator" colspan="2"> </td></tr> 196<tr class="memitem:acfb03589150d28227ff1dd5393b0b893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#acfb03589150d28227ff1dd5393b0b893">RTE_I2C3_DMA_RX_DMA_BASE</a>   DMA__DMA1</td></tr> 197<tr class="separator:acfb03589150d28227ff1dd5393b0b893"><td class="memSeparator" colspan="2"> </td></tr> 198<tr class="memitem:a886533baa3ecbfdc24804b3bbd3c1fa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a886533baa3ecbfdc24804b3bbd3c1fa4">RTE_I2C4_DMA_TX_CH</a>   5</td></tr> 199<tr class="separator:a886533baa3ecbfdc24804b3bbd3c1fa4"><td class="memSeparator" colspan="2"> </td></tr> 200<tr class="memitem:acedae977949138b1e4bf418885238855"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#acedae977949138b1e4bf418885238855">RTE_I2C4_DMA_TX_PERI_SEL</a>   5</td></tr> 201<tr class="separator:acedae977949138b1e4bf418885238855"><td class="memSeparator" colspan="2"> </td></tr> 202<tr class="memitem:a1eeb5eb83698e059c5bbc3df7097102d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a1eeb5eb83698e059c5bbc3df7097102d">RTE_I2C4_DMA_TX_DMA_BASE</a>   DMA__DMA1</td></tr> 203<tr class="separator:a1eeb5eb83698e059c5bbc3df7097102d"><td class="memSeparator" colspan="2"> </td></tr> 204<tr class="memitem:adb24a07872f830d773e5a761b5b915ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#adb24a07872f830d773e5a761b5b915ea">RTE_I2C4_DMA_RX_CH</a>   4</td></tr> 205<tr class="separator:adb24a07872f830d773e5a761b5b915ea"><td class="memSeparator" colspan="2"> </td></tr> 206<tr class="memitem:aad4b2e8753e39ef0df22e30d47f5af87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aad4b2e8753e39ef0df22e30d47f5af87">RTE_I2C4_DMA_RX_PERI_SEL</a>   4</td></tr> 207<tr class="separator:aad4b2e8753e39ef0df22e30d47f5af87"><td class="memSeparator" colspan="2"> </td></tr> 208<tr class="memitem:aac8180353fa95d472f154af42998f3ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aac8180353fa95d472f154af42998f3ea">RTE_I2C4_DMA_RX_DMA_BASE</a>   DMA__DMA1</td></tr> 209<tr class="separator:aac8180353fa95d472f154af42998f3ea"><td class="memSeparator" colspan="2"> </td></tr> 210<tr class="memitem:aacc69b6a58c942604d55ab3c66c18331"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aacc69b6a58c942604d55ab3c66c18331">RTE_I2C5_DMA_TX_CH</a>   7</td></tr> 211<tr class="separator:aacc69b6a58c942604d55ab3c66c18331"><td class="memSeparator" colspan="2"> </td></tr> 212<tr class="memitem:aae327bc1bd7606f5ce0e12fa22c0c98f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aae327bc1bd7606f5ce0e12fa22c0c98f">RTE_I2C5_DMA_TX_PERI_SEL</a>   7</td></tr> 213<tr class="separator:aae327bc1bd7606f5ce0e12fa22c0c98f"><td class="memSeparator" colspan="2"> </td></tr> 214<tr class="memitem:a237c977557c35a9f367b3dad28755434"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a237c977557c35a9f367b3dad28755434">RTE_I2C5_DMA_TX_DMA_BASE</a>   DMA__DMA1</td></tr> 215<tr class="separator:a237c977557c35a9f367b3dad28755434"><td class="memSeparator" colspan="2"> </td></tr> 216<tr class="memitem:a49d74f3d89f709bcee704ed8bc62a389"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a49d74f3d89f709bcee704ed8bc62a389">RTE_I2C5_DMA_RX_CH</a>   6</td></tr> 217<tr class="separator:a49d74f3d89f709bcee704ed8bc62a389"><td class="memSeparator" colspan="2"> </td></tr> 218<tr class="memitem:af9a7eeea936066a06aa12642d206ffe1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#af9a7eeea936066a06aa12642d206ffe1">RTE_I2C5_DMA_RX_PERI_SEL</a>   6</td></tr> 219<tr class="separator:af9a7eeea936066a06aa12642d206ffe1"><td class="memSeparator" colspan="2"> </td></tr> 220<tr class="memitem:afffd01e1818a0941804aa6898e0f3480"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#afffd01e1818a0941804aa6898e0f3480">RTE_I2C5_DMA_RX_DMA_BASE</a>   DMA__DMA1</td></tr> 221<tr class="separator:afffd01e1818a0941804aa6898e0f3480"><td class="memSeparator" colspan="2"> </td></tr> 222<tr class="memitem:aa15456a15715d87b5d9fd1663b6def21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aa15456a15715d87b5d9fd1663b6def21">RTE_I2C6_DMA_TX_CH</a>   9</td></tr> 223<tr class="separator:aa15456a15715d87b5d9fd1663b6def21"><td class="memSeparator" colspan="2"> </td></tr> 224<tr class="memitem:a3376a9bd3c4accdc4e0d25251960563b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a3376a9bd3c4accdc4e0d25251960563b">RTE_I2C6_DMA_TX_PERI_SEL</a>   9</td></tr> 225<tr class="separator:a3376a9bd3c4accdc4e0d25251960563b"><td class="memSeparator" colspan="2"> </td></tr> 226<tr class="memitem:a3beb3f0a50107be726578869d167101a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a3beb3f0a50107be726578869d167101a">RTE_I2C6_DMA_TX_DMA_BASE</a>   DMA__DMA1</td></tr> 227<tr class="separator:a3beb3f0a50107be726578869d167101a"><td class="memSeparator" colspan="2"> </td></tr> 228<tr class="memitem:adbde0a01f889e105a70dea33e0b774fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#adbde0a01f889e105a70dea33e0b774fe">RTE_I2C6_DMA_RX_CH</a>   8</td></tr> 229<tr class="separator:adbde0a01f889e105a70dea33e0b774fe"><td class="memSeparator" colspan="2"> </td></tr> 230<tr class="memitem:a18a0ead9ea40c2c592a5a3a73d4f3916"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a18a0ead9ea40c2c592a5a3a73d4f3916">RTE_I2C6_DMA_RX_PERI_SEL</a>   8</td></tr> 231<tr class="separator:a18a0ead9ea40c2c592a5a3a73d4f3916"><td class="memSeparator" colspan="2"> </td></tr> 232<tr class="memitem:afdf4039762fae0cda1db8c9ea184e641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#afdf4039762fae0cda1db8c9ea184e641">RTE_I2C6_DMA_RX_DMA_BASE</a>   DMA__DMA1</td></tr> 233<tr class="separator:afdf4039762fae0cda1db8c9ea184e641"><td class="memSeparator" colspan="2"> </td></tr> 234<tr class="memitem:a43c0f3151f3f65559aec155908ac5804"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a43c0f3151f3f65559aec155908ac5804">USART_RX_BUFFER_LEN</a>   64</td></tr> 235<tr class="separator:a43c0f3151f3f65559aec155908ac5804"><td class="memSeparator" colspan="2"> </td></tr> 236<tr class="memitem:a42233d962f08392fe286ed2e652eb9b1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a42233d962f08392fe286ed2e652eb9b1">USART4_RX_BUFFER_ENABLE</a>   1</td></tr> 237<tr class="separator:a42233d962f08392fe286ed2e652eb9b1"><td class="memSeparator" colspan="2"> </td></tr> 238<tr class="memitem:a4da147c7ce755201a079c412c098128f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a4da147c7ce755201a079c412c098128f">RTE_USART2_DMA_TX_CH</a>   13</td></tr> 239<tr class="separator:a4da147c7ce755201a079c412c098128f"><td class="memSeparator" colspan="2"> </td></tr> 240<tr class="memitem:a1921b3ed005879e26052e379f23dbcb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a1921b3ed005879e26052e379f23dbcb2">RTE_USART2_DMA_TX_PERI_SEL</a>   13</td></tr> 241<tr class="separator:a1921b3ed005879e26052e379f23dbcb2"><td class="memSeparator" colspan="2"> </td></tr> 242<tr class="memitem:a667adae4bda8ac302bcc85d4a7a004cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a667adae4bda8ac302bcc85d4a7a004cd">RTE_USART2_DMA_TX_DMA_BASE</a>   DMA__DMA0</td></tr> 243<tr class="separator:a667adae4bda8ac302bcc85d4a7a004cd"><td class="memSeparator" colspan="2"> </td></tr> 244<tr class="memitem:aaf5d293f3353d103aa7fc672a3cf456d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aaf5d293f3353d103aa7fc672a3cf456d">RTE_USART2_DMA_RX_CH</a>   12</td></tr> 245<tr class="separator:aaf5d293f3353d103aa7fc672a3cf456d"><td class="memSeparator" colspan="2"> </td></tr> 246<tr class="memitem:ad8969d48f9a854dcd661e60ace8f2eac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ad8969d48f9a854dcd661e60ace8f2eac">RTE_USART2_DMA_RX_PERI_SEL</a>   12</td></tr> 247<tr class="separator:ad8969d48f9a854dcd661e60ace8f2eac"><td class="memSeparator" colspan="2"> </td></tr> 248<tr class="memitem:a54af00b2f29f1e9aeb10e1a59a4cde3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a54af00b2f29f1e9aeb10e1a59a4cde3d">RTE_USART2_DMA_RX_DMA_BASE</a>   DMA__DMA0</td></tr> 249<tr class="separator:a54af00b2f29f1e9aeb10e1a59a4cde3d"><td class="memSeparator" colspan="2"> </td></tr> 250<tr class="memitem:a371552d64a4c36aa553a256ab52c4737"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a371552d64a4c36aa553a256ab52c4737">RTE_USART3_DMA_TX_CH</a>   15</td></tr> 251<tr class="separator:a371552d64a4c36aa553a256ab52c4737"><td class="memSeparator" colspan="2"> </td></tr> 252<tr class="memitem:a298c8ca62c3080284bf1c1ddc9e52c74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a298c8ca62c3080284bf1c1ddc9e52c74">RTE_USART3_DMA_TX_PERI_SEL</a>   15</td></tr> 253<tr class="separator:a298c8ca62c3080284bf1c1ddc9e52c74"><td class="memSeparator" colspan="2"> </td></tr> 254<tr class="memitem:a230981b96cecea4add332ecd40533454"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a230981b96cecea4add332ecd40533454">RTE_USART3_DMA_TX_DMA_BASE</a>   DMA__DMA0</td></tr> 255<tr class="separator:a230981b96cecea4add332ecd40533454"><td class="memSeparator" colspan="2"> </td></tr> 256<tr class="memitem:ab09d3b40ddde8be68179be6d46400d45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ab09d3b40ddde8be68179be6d46400d45">RTE_USART3_DMA_RX_CH</a>   14</td></tr> 257<tr class="separator:ab09d3b40ddde8be68179be6d46400d45"><td class="memSeparator" colspan="2"> </td></tr> 258<tr class="memitem:ab310379c65913c108e059c4e317ce096"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ab310379c65913c108e059c4e317ce096">RTE_USART3_DMA_RX_PERI_SEL</a>   14</td></tr> 259<tr class="separator:ab310379c65913c108e059c4e317ce096"><td class="memSeparator" colspan="2"> </td></tr> 260<tr class="memitem:ae05b2c8a2baaa32c10d0af3457ce2e28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ae05b2c8a2baaa32c10d0af3457ce2e28">RTE_USART3_DMA_RX_DMA_BASE</a>   DMA__DMA0</td></tr> 261<tr class="separator:ae05b2c8a2baaa32c10d0af3457ce2e28"><td class="memSeparator" colspan="2"> </td></tr> 262<tr class="memitem:a583406cbb43d2e24e0cf8cafdb45d7d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a583406cbb43d2e24e0cf8cafdb45d7d9">RTE_USART4_DMA_TX_CH</a>   17</td></tr> 263<tr class="separator:a583406cbb43d2e24e0cf8cafdb45d7d9"><td class="memSeparator" colspan="2"> </td></tr> 264<tr class="memitem:a2b6f4b82acc33b81f3637afc63419169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a2b6f4b82acc33b81f3637afc63419169">RTE_USART4_DMA_TX_PERI_SEL</a>   17</td></tr> 265<tr class="separator:a2b6f4b82acc33b81f3637afc63419169"><td class="memSeparator" colspan="2"> </td></tr> 266<tr class="memitem:ac4abea21e4bfc3d03539f739892b0e7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ac4abea21e4bfc3d03539f739892b0e7f">RTE_USART4_DMA_TX_DMA_BASE</a>   DMA__DMA0</td></tr> 267<tr class="separator:ac4abea21e4bfc3d03539f739892b0e7f"><td class="memSeparator" colspan="2"> </td></tr> 268<tr class="memitem:ae3aa08740bc1278f56cb25413751053b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ae3aa08740bc1278f56cb25413751053b">RTE_USART4_DMA_RX_CH</a>   16</td></tr> 269<tr class="separator:ae3aa08740bc1278f56cb25413751053b"><td class="memSeparator" colspan="2"> </td></tr> 270<tr class="memitem:a2d133b10d9af3b93828d264638c01d69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a2d133b10d9af3b93828d264638c01d69">RTE_USART4_DMA_RX_PERI_SEL</a>   16</td></tr> 271<tr class="separator:a2d133b10d9af3b93828d264638c01d69"><td class="memSeparator" colspan="2"> </td></tr> 272<tr class="memitem:a84ae4f174efa1b7417b5a35d9b9e3de9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a84ae4f174efa1b7417b5a35d9b9e3de9">RTE_USART4_DMA_RX_DMA_BASE</a>   DMA__DMA0</td></tr> 273<tr class="separator:a84ae4f174efa1b7417b5a35d9b9e3de9"><td class="memSeparator" colspan="2"> </td></tr> 274<tr class="memitem:a5fc281007f625bf44a5b16d7f97c9f7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a5fc281007f625bf44a5b16d7f97c9f7b">RTE_USART5_DMA_TX_CH</a>   19</td></tr> 275<tr class="separator:a5fc281007f625bf44a5b16d7f97c9f7b"><td class="memSeparator" colspan="2"> </td></tr> 276<tr class="memitem:a3f34578afbd133748801bbb852f1cc46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a3f34578afbd133748801bbb852f1cc46">RTE_USART5_DMA_TX_PERI_SEL</a>   19</td></tr> 277<tr class="separator:a3f34578afbd133748801bbb852f1cc46"><td class="memSeparator" colspan="2"> </td></tr> 278<tr class="memitem:a530f52cd5d979b98f959163c96e4413b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a530f52cd5d979b98f959163c96e4413b">RTE_USART5_DMA_TX_DMA_BASE</a>   DMA__DMA0</td></tr> 279<tr class="separator:a530f52cd5d979b98f959163c96e4413b"><td class="memSeparator" colspan="2"> </td></tr> 280<tr class="memitem:af563379f0b22b56089642e1452293b94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#af563379f0b22b56089642e1452293b94">RTE_USART5_DMA_RX_CH</a>   18</td></tr> 281<tr class="separator:af563379f0b22b56089642e1452293b94"><td class="memSeparator" colspan="2"> </td></tr> 282<tr class="memitem:a4dc20b4bfb5766bac0d6de434bda7fd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a4dc20b4bfb5766bac0d6de434bda7fd8">RTE_USART5_DMA_RX_PERI_SEL</a>   18</td></tr> 283<tr class="separator:a4dc20b4bfb5766bac0d6de434bda7fd8"><td class="memSeparator" colspan="2"> </td></tr> 284<tr class="memitem:a665e630b27a6713ff3055c9893403090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a665e630b27a6713ff3055c9893403090">RTE_USART5_DMA_RX_DMA_BASE</a>   DMA__DMA0</td></tr> 285<tr class="separator:a665e630b27a6713ff3055c9893403090"><td class="memSeparator" colspan="2"> </td></tr> 286<tr class="memitem:a830ccf4153d422fc98971a8fc2d1ecba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a830ccf4153d422fc98971a8fc2d1ecba">RTE_USART6_DMA_TX_CH</a>   21</td></tr> 287<tr class="separator:a830ccf4153d422fc98971a8fc2d1ecba"><td class="memSeparator" colspan="2"> </td></tr> 288<tr class="memitem:ac1692d643111d558f2df528205966f28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ac1692d643111d558f2df528205966f28">RTE_USART6_DMA_TX_PERI_SEL</a>   21</td></tr> 289<tr class="separator:ac1692d643111d558f2df528205966f28"><td class="memSeparator" colspan="2"> </td></tr> 290<tr class="memitem:aa50f707f6ba72c2c400faa7e2c9b8b5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#aa50f707f6ba72c2c400faa7e2c9b8b5f">RTE_USART6_DMA_TX_DMA_BASE</a>   DMA__DMA0</td></tr> 291<tr class="separator:aa50f707f6ba72c2c400faa7e2c9b8b5f"><td class="memSeparator" colspan="2"> </td></tr> 292<tr class="memitem:a74e96a5225571536daf6ce2058f2ca11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a74e96a5225571536daf6ce2058f2ca11">RTE_USART6_DMA_RX_CH</a>   20</td></tr> 293<tr class="separator:a74e96a5225571536daf6ce2058f2ca11"><td class="memSeparator" colspan="2"> </td></tr> 294<tr class="memitem:ad55c040ec06f230089b7f190f5eb5589"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#ad55c040ec06f230089b7f190f5eb5589">RTE_USART6_DMA_RX_PERI_SEL</a>   20</td></tr> 295<tr class="separator:ad55c040ec06f230089b7f190f5eb5589"><td class="memSeparator" colspan="2"> </td></tr> 296<tr class="memitem:a5937989b65e91558a7ecd473a511e5e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04730.html#a5937989b65e91558a7ecd473a511e5e6">RTE_USART6_DMA_RX_DMA_BASE</a>   DMA__DMA0</td></tr> 297<tr class="separator:a5937989b65e91558a7ecd473a511e5e6"><td class="memSeparator" colspan="2"> </td></tr> 298</table> 299<h2 class="groupheader">Macro Definition Documentation</h2> 300<a id="a7701382ade504d7eddda8c1231279cec"></a> 301<h2 class="memtitle"><span class="permalink"><a href="#a7701382ade504d7eddda8c1231279cec">◆ </a></span>LPI2C0</h2> 302 303<div class="memitem"> 304<div class="memproto"> 305 <table class="memname"> 306 <tr> 307 <td class="memname">#define LPI2C0   CM4_0__LPI2C</td> 308 </tr> 309 </table> 310</div><div class="memdoc"> 311 312<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00012">12</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 313 314</div> 315</div> 316<a id="ae9ef15442986812d986ae9cc6b4cdf88"></a> 317<h2 class="memtitle"><span class="permalink"><a href="#ae9ef15442986812d986ae9cc6b4cdf88">◆ </a></span>LPI2C1</h2> 318 319<div class="memitem"> 320<div class="memproto"> 321 <table class="memname"> 322 <tr> 323 <td class="memname">#define LPI2C1   CM4_1__LPI2C</td> 324 </tr> 325 </table> 326</div><div class="memdoc"> 327 328<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00013">13</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 329 330</div> 331</div> 332<a id="a0c971bafd33997b4d43d7cb61c6a6236"></a> 333<h2 class="memtitle"><span class="permalink"><a href="#a0c971bafd33997b4d43d7cb61c6a6236">◆ </a></span>LPI2C2</h2> 334 335<div class="memitem"> 336<div class="memproto"> 337 <table class="memname"> 338 <tr> 339 <td class="memname">#define LPI2C2   DMA__LPI2C0</td> 340 </tr> 341 </table> 342</div><div class="memdoc"> 343 344<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00014">14</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 345 346</div> 347</div> 348<a id="af3c8daab94b3b0d2c0158e0cedb6c3fc"></a> 349<h2 class="memtitle"><span class="permalink"><a href="#af3c8daab94b3b0d2c0158e0cedb6c3fc">◆ </a></span>LPI2C3</h2> 350 351<div class="memitem"> 352<div class="memproto"> 353 <table class="memname"> 354 <tr> 355 <td class="memname">#define LPI2C3   DMA__LPI2C1</td> 356 </tr> 357 </table> 358</div><div class="memdoc"> 359 360<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00015">15</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 361 362</div> 363</div> 364<a id="a046632a83702c613f8c0079752219d9b"></a> 365<h2 class="memtitle"><span class="permalink"><a href="#a046632a83702c613f8c0079752219d9b">◆ </a></span>LPI2C4</h2> 366 367<div class="memitem"> 368<div class="memproto"> 369 <table class="memname"> 370 <tr> 371 <td class="memname">#define LPI2C4   DMA__LPI2C2</td> 372 </tr> 373 </table> 374</div><div class="memdoc"> 375 376<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00016">16</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 377 378</div> 379</div> 380<a id="a96978e509a91b8aea5b4246405dc762b"></a> 381<h2 class="memtitle"><span class="permalink"><a href="#a96978e509a91b8aea5b4246405dc762b">◆ </a></span>LPI2C5</h2> 382 383<div class="memitem"> 384<div class="memproto"> 385 <table class="memname"> 386 <tr> 387 <td class="memname">#define LPI2C5   DMA__LPI2C3</td> 388 </tr> 389 </table> 390</div><div class="memdoc"> 391 392<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00017">17</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 393 394</div> 395</div> 396<a id="aff57940e609bbf508d3a366abd1ed466"></a> 397<h2 class="memtitle"><span class="permalink"><a href="#aff57940e609bbf508d3a366abd1ed466">◆ </a></span>LPI2C6</h2> 398 399<div class="memitem"> 400<div class="memproto"> 401 <table class="memname"> 402 <tr> 403 <td class="memname">#define LPI2C6   DMA__LPI2C4</td> 404 </tr> 405 </table> 406</div><div class="memdoc"> 407 408<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00018">18</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 409 410</div> 411</div> 412<a id="ad552d158bcba2b8f961993cc9a198538"></a> 413<h2 class="memtitle"><span class="permalink"><a href="#ad552d158bcba2b8f961993cc9a198538">◆ </a></span>LPSPI0</h2> 414 415<div class="memitem"> 416<div class="memproto"> 417 <table class="memname"> 418 <tr> 419 <td class="memname">#define LPSPI0   DMA__LPSPI0</td> 420 </tr> 421 </table> 422</div><div class="memdoc"> 423 424<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00037">37</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 425 426</div> 427</div> 428<a id="ac2fa96bc980d401c36834549b3688009"></a> 429<h2 class="memtitle"><span class="permalink"><a href="#ac2fa96bc980d401c36834549b3688009">◆ </a></span>LPSPI1</h2> 430 431<div class="memitem"> 432<div class="memproto"> 433 <table class="memname"> 434 <tr> 435 <td class="memname">#define LPSPI1   DMA__LPSPI1</td> 436 </tr> 437 </table> 438</div><div class="memdoc"> 439 440<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00038">38</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 441 442</div> 443</div> 444<a id="ae45a21782e5f7d05636cdaac3bdda86d"></a> 445<h2 class="memtitle"><span class="permalink"><a href="#ae45a21782e5f7d05636cdaac3bdda86d">◆ </a></span>LPSPI2</h2> 446 447<div class="memitem"> 448<div class="memproto"> 449 <table class="memname"> 450 <tr> 451 <td class="memname">#define LPSPI2   DMA__LPSPI2</td> 452 </tr> 453 </table> 454</div><div class="memdoc"> 455 456<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00039">39</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 457 458</div> 459</div> 460<a id="a4850e0354a725db60884a96d957bc205"></a> 461<h2 class="memtitle"><span class="permalink"><a href="#a4850e0354a725db60884a96d957bc205">◆ </a></span>LPSPI3</h2> 462 463<div class="memitem"> 464<div class="memproto"> 465 <table class="memname"> 466 <tr> 467 <td class="memname">#define LPSPI3   DMA__LPSPI3</td> 468 </tr> 469 </table> 470</div><div class="memdoc"> 471 472<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00040">40</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 473 474</div> 475</div> 476<a id="a5b2895bb50a19a21ddb954c28977629b"></a> 477<h2 class="memtitle"><span class="permalink"><a href="#a5b2895bb50a19a21ddb954c28977629b">◆ </a></span>LPUART0</h2> 478 479<div class="memitem"> 480<div class="memproto"> 481 <table class="memname"> 482 <tr> 483 <td class="memname">#define LPUART0   CM4_0__LPUART</td> 484 </tr> 485 </table> 486</div><div class="memdoc"> 487 488<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00053">53</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 489 490</div> 491</div> 492<a id="a73eb37d103f4e4f2d18ec3d3f5208ab9"></a> 493<h2 class="memtitle"><span class="permalink"><a href="#a73eb37d103f4e4f2d18ec3d3f5208ab9">◆ </a></span>LPUART1</h2> 494 495<div class="memitem"> 496<div class="memproto"> 497 <table class="memname"> 498 <tr> 499 <td class="memname">#define LPUART1   CM4_1__LPUART</td> 500 </tr> 501 </table> 502</div><div class="memdoc"> 503 504<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00054">54</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 505 506</div> 507</div> 508<a id="aeb546d3c2b55e486a3d4711255c46fc9"></a> 509<h2 class="memtitle"><span class="permalink"><a href="#aeb546d3c2b55e486a3d4711255c46fc9">◆ </a></span>LPUART2</h2> 510 511<div class="memitem"> 512<div class="memproto"> 513 <table class="memname"> 514 <tr> 515 <td class="memname">#define LPUART2   DMA__LPUART0</td> 516 </tr> 517 </table> 518</div><div class="memdoc"> 519 520<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00055">55</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 521 522</div> 523</div> 524<a id="abf380b4bd4c865aa97ff2420ec4718c3"></a> 525<h2 class="memtitle"><span class="permalink"><a href="#abf380b4bd4c865aa97ff2420ec4718c3">◆ </a></span>LPUART3</h2> 526 527<div class="memitem"> 528<div class="memproto"> 529 <table class="memname"> 530 <tr> 531 <td class="memname">#define LPUART3   DMA__LPUART1</td> 532 </tr> 533 </table> 534</div><div class="memdoc"> 535 536<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00056">56</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 537 538</div> 539</div> 540<a id="a9d8ddb2d0d4d61a63ad00b6fd9df5f68"></a> 541<h2 class="memtitle"><span class="permalink"><a href="#a9d8ddb2d0d4d61a63ad00b6fd9df5f68">◆ </a></span>LPUART4</h2> 542 543<div class="memitem"> 544<div class="memproto"> 545 <table class="memname"> 546 <tr> 547 <td class="memname">#define LPUART4   DMA__LPUART2</td> 548 </tr> 549 </table> 550</div><div class="memdoc"> 551 552<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00057">57</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 553 554</div> 555</div> 556<a id="ab8b8889fd34c86c965bffbbe3be3774f"></a> 557<h2 class="memtitle"><span class="permalink"><a href="#ab8b8889fd34c86c965bffbbe3be3774f">◆ </a></span>LPUART5</h2> 558 559<div class="memitem"> 560<div class="memproto"> 561 <table class="memname"> 562 <tr> 563 <td class="memname">#define LPUART5   DMA__LPUART3</td> 564 </tr> 565 </table> 566</div><div class="memdoc"> 567 568<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00058">58</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 569 570</div> 571</div> 572<a id="a353278699075ac94a78666fabfb6ecfc"></a> 573<h2 class="memtitle"><span class="permalink"><a href="#a353278699075ac94a78666fabfb6ecfc">◆ </a></span>LPUART6</h2> 574 575<div class="memitem"> 576<div class="memproto"> 577 <table class="memname"> 578 <tr> 579 <td class="memname">#define LPUART6   DMA__LPUART4</td> 580 </tr> 581 </table> 582</div><div class="memdoc"> 583 584<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00059">59</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 585 586</div> 587</div> 588<a id="afdae116c2c595573ddee8725b6a4602a"></a> 589<h2 class="memtitle"><span class="permalink"><a href="#afdae116c2c595573ddee8725b6a4602a">◆ </a></span>RTE_I2C0</h2> 590 591<div class="memitem"> 592<div class="memproto"> 593 <table class="memname"> 594 <tr> 595 <td class="memname">#define RTE_I2C0   0</td> 596 </tr> 597 </table> 598</div><div class="memdoc"> 599 600<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00021">21</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 601 602</div> 603</div> 604<a id="ab3079b071b25a964033ece9a17ebc622"></a> 605<h2 class="memtitle"><span class="permalink"><a href="#ab3079b071b25a964033ece9a17ebc622">◆ </a></span>RTE_I2C0_DMA_EN</h2> 606 607<div class="memitem"> 608<div class="memproto"> 609 <table class="memname"> 610 <tr> 611 <td class="memname">#define RTE_I2C0_DMA_EN   0</td> 612 </tr> 613 </table> 614</div><div class="memdoc"> 615 616<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00022">22</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 617 618</div> 619</div> 620<a id="aa4264010a207548708e4eb5030b77b42"></a> 621<h2 class="memtitle"><span class="permalink"><a href="#aa4264010a207548708e4eb5030b77b42">◆ </a></span>RTE_I2C1</h2> 622 623<div class="memitem"> 624<div class="memproto"> 625 <table class="memname"> 626 <tr> 627 <td class="memname">#define RTE_I2C1   0</td> 628 </tr> 629 </table> 630</div><div class="memdoc"> 631 632<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00023">23</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 633 634</div> 635</div> 636<a id="aac0deee79f0bfe76842a606f89347141"></a> 637<h2 class="memtitle"><span class="permalink"><a href="#aac0deee79f0bfe76842a606f89347141">◆ </a></span>RTE_I2C1_DMA_EN</h2> 638 639<div class="memitem"> 640<div class="memproto"> 641 <table class="memname"> 642 <tr> 643 <td class="memname">#define RTE_I2C1_DMA_EN   0</td> 644 </tr> 645 </table> 646</div><div class="memdoc"> 647 648<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00024">24</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 649 650</div> 651</div> 652<a id="a6b312911602934f2275e5bfdd964a3c2"></a> 653<h2 class="memtitle"><span class="permalink"><a href="#a6b312911602934f2275e5bfdd964a3c2">◆ </a></span>RTE_I2C2</h2> 654 655<div class="memitem"> 656<div class="memproto"> 657 <table class="memname"> 658 <tr> 659 <td class="memname">#define RTE_I2C2   1</td> 660 </tr> 661 </table> 662</div><div class="memdoc"> 663 664<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00025">25</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 665 666</div> 667</div> 668<a id="aa6833427b8acb64e5b2cdca71adc4731"></a> 669<h2 class="memtitle"><span class="permalink"><a href="#aa6833427b8acb64e5b2cdca71adc4731">◆ </a></span>RTE_I2C2_DMA_EN</h2> 670 671<div class="memitem"> 672<div class="memproto"> 673 <table class="memname"> 674 <tr> 675 <td class="memname">#define RTE_I2C2_DMA_EN   0</td> 676 </tr> 677 </table> 678</div><div class="memdoc"> 679 680<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00026">26</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 681 682</div> 683</div> 684<a id="a762b3880f4254c392f2f152393776679"></a> 685<h2 class="memtitle"><span class="permalink"><a href="#a762b3880f4254c392f2f152393776679">◆ </a></span>RTE_I2C2_DMA_RX_CH</h2> 686 687<div class="memitem"> 688<div class="memproto"> 689 <table class="memname"> 690 <tr> 691 <td class="memname">#define RTE_I2C2_DMA_RX_CH   0</td> 692 </tr> 693 </table> 694</div><div class="memdoc"> 695 696<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00082">82</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 697 698</div> 699</div> 700<a id="a1ca82c1fea8b1c55875df9cf0e3e4266"></a> 701<h2 class="memtitle"><span class="permalink"><a href="#a1ca82c1fea8b1c55875df9cf0e3e4266">◆ </a></span>RTE_I2C2_DMA_RX_DMA_BASE</h2> 702 703<div class="memitem"> 704<div class="memproto"> 705 <table class="memname"> 706 <tr> 707 <td class="memname">#define RTE_I2C2_DMA_RX_DMA_BASE   DMA__DMA1</td> 708 </tr> 709 </table> 710</div><div class="memdoc"> 711 712<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00084">84</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 713 714</div> 715</div> 716<a id="ad7eb717542257f354c6b41ad348a1404"></a> 717<h2 class="memtitle"><span class="permalink"><a href="#ad7eb717542257f354c6b41ad348a1404">◆ </a></span>RTE_I2C2_DMA_RX_PERI_SEL</h2> 718 719<div class="memitem"> 720<div class="memproto"> 721 <table class="memname"> 722 <tr> 723 <td class="memname">#define RTE_I2C2_DMA_RX_PERI_SEL   0</td> 724 </tr> 725 </table> 726</div><div class="memdoc"> 727 728<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00083">83</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 729 730</div> 731</div> 732<a id="aaafac93c554b337745d91aeeaa263ee3"></a> 733<h2 class="memtitle"><span class="permalink"><a href="#aaafac93c554b337745d91aeeaa263ee3">◆ </a></span>RTE_I2C2_DMA_TX_CH</h2> 734 735<div class="memitem"> 736<div class="memproto"> 737 <table class="memname"> 738 <tr> 739 <td class="memname">#define RTE_I2C2_DMA_TX_CH   1</td> 740 </tr> 741 </table> 742</div><div class="memdoc"> 743 744<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00079">79</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 745 746</div> 747</div> 748<a id="ad4f1a37be61763d2594b4f539ae03d44"></a> 749<h2 class="memtitle"><span class="permalink"><a href="#ad4f1a37be61763d2594b4f539ae03d44">◆ </a></span>RTE_I2C2_DMA_TX_DMA_BASE</h2> 750 751<div class="memitem"> 752<div class="memproto"> 753 <table class="memname"> 754 <tr> 755 <td class="memname">#define RTE_I2C2_DMA_TX_DMA_BASE   DMA__DMA1</td> 756 </tr> 757 </table> 758</div><div class="memdoc"> 759 760<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00081">81</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 761 762</div> 763</div> 764<a id="a282e3c43099524332084d89c4dc0370a"></a> 765<h2 class="memtitle"><span class="permalink"><a href="#a282e3c43099524332084d89c4dc0370a">◆ </a></span>RTE_I2C2_DMA_TX_PERI_SEL</h2> 766 767<div class="memitem"> 768<div class="memproto"> 769 <table class="memname"> 770 <tr> 771 <td class="memname">#define RTE_I2C2_DMA_TX_PERI_SEL   1</td> 772 </tr> 773 </table> 774</div><div class="memdoc"> 775 776<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00080">80</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 777 778</div> 779</div> 780<a id="a286e0b83a4a1806a5125d1e805afed5e"></a> 781<h2 class="memtitle"><span class="permalink"><a href="#a286e0b83a4a1806a5125d1e805afed5e">◆ </a></span>RTE_I2C3</h2> 782 783<div class="memitem"> 784<div class="memproto"> 785 <table class="memname"> 786 <tr> 787 <td class="memname">#define RTE_I2C3   0</td> 788 </tr> 789 </table> 790</div><div class="memdoc"> 791 792<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00027">27</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 793 794</div> 795</div> 796<a id="a7e2203f604dc9bfc5ae76af6364b8e38"></a> 797<h2 class="memtitle"><span class="permalink"><a href="#a7e2203f604dc9bfc5ae76af6364b8e38">◆ </a></span>RTE_I2C3_DMA_EN</h2> 798 799<div class="memitem"> 800<div class="memproto"> 801 <table class="memname"> 802 <tr> 803 <td class="memname">#define RTE_I2C3_DMA_EN   0</td> 804 </tr> 805 </table> 806</div><div class="memdoc"> 807 808<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00028">28</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 809 810</div> 811</div> 812<a id="ac78874337ab81de6e42b051fb9dce871"></a> 813<h2 class="memtitle"><span class="permalink"><a href="#ac78874337ab81de6e42b051fb9dce871">◆ </a></span>RTE_I2C3_DMA_RX_CH</h2> 814 815<div class="memitem"> 816<div class="memproto"> 817 <table class="memname"> 818 <tr> 819 <td class="memname">#define RTE_I2C3_DMA_RX_CH   2</td> 820 </tr> 821 </table> 822</div><div class="memdoc"> 823 824<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00089">89</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 825 826</div> 827</div> 828<a id="acfb03589150d28227ff1dd5393b0b893"></a> 829<h2 class="memtitle"><span class="permalink"><a href="#acfb03589150d28227ff1dd5393b0b893">◆ </a></span>RTE_I2C3_DMA_RX_DMA_BASE</h2> 830 831<div class="memitem"> 832<div class="memproto"> 833 <table class="memname"> 834 <tr> 835 <td class="memname">#define RTE_I2C3_DMA_RX_DMA_BASE   DMA__DMA1</td> 836 </tr> 837 </table> 838</div><div class="memdoc"> 839 840<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00091">91</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 841 842</div> 843</div> 844<a id="a0994b2eeb8af41123e69175ac6f9c7b0"></a> 845<h2 class="memtitle"><span class="permalink"><a href="#a0994b2eeb8af41123e69175ac6f9c7b0">◆ </a></span>RTE_I2C3_DMA_RX_PERI_SEL</h2> 846 847<div class="memitem"> 848<div class="memproto"> 849 <table class="memname"> 850 <tr> 851 <td class="memname">#define RTE_I2C3_DMA_RX_PERI_SEL   2</td> 852 </tr> 853 </table> 854</div><div class="memdoc"> 855 856<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00090">90</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 857 858</div> 859</div> 860<a id="a8d59722d63164553e1aa90f0b5531aa6"></a> 861<h2 class="memtitle"><span class="permalink"><a href="#a8d59722d63164553e1aa90f0b5531aa6">◆ </a></span>RTE_I2C3_DMA_TX_CH</h2> 862 863<div class="memitem"> 864<div class="memproto"> 865 <table class="memname"> 866 <tr> 867 <td class="memname">#define RTE_I2C3_DMA_TX_CH   3</td> 868 </tr> 869 </table> 870</div><div class="memdoc"> 871 872<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00086">86</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 873 874</div> 875</div> 876<a id="a21c43b61ee31798e368937bdbc945eb7"></a> 877<h2 class="memtitle"><span class="permalink"><a href="#a21c43b61ee31798e368937bdbc945eb7">◆ </a></span>RTE_I2C3_DMA_TX_DMA_BASE</h2> 878 879<div class="memitem"> 880<div class="memproto"> 881 <table class="memname"> 882 <tr> 883 <td class="memname">#define RTE_I2C3_DMA_TX_DMA_BASE   DMA__DMA1</td> 884 </tr> 885 </table> 886</div><div class="memdoc"> 887 888<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00088">88</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 889 890</div> 891</div> 892<a id="a1f3419a15ebd3e7915ab02ddb9d8e57a"></a> 893<h2 class="memtitle"><span class="permalink"><a href="#a1f3419a15ebd3e7915ab02ddb9d8e57a">◆ </a></span>RTE_I2C3_DMA_TX_PERI_SEL</h2> 894 895<div class="memitem"> 896<div class="memproto"> 897 <table class="memname"> 898 <tr> 899 <td class="memname">#define RTE_I2C3_DMA_TX_PERI_SEL   3</td> 900 </tr> 901 </table> 902</div><div class="memdoc"> 903 904<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00087">87</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 905 906</div> 907</div> 908<a id="aaefd2724bd50bf611680b12680c5cd47"></a> 909<h2 class="memtitle"><span class="permalink"><a href="#aaefd2724bd50bf611680b12680c5cd47">◆ </a></span>RTE_I2C4</h2> 910 911<div class="memitem"> 912<div class="memproto"> 913 <table class="memname"> 914 <tr> 915 <td class="memname">#define RTE_I2C4   0</td> 916 </tr> 917 </table> 918</div><div class="memdoc"> 919 920<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00029">29</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 921 922</div> 923</div> 924<a id="ad0881b5c0250fd24034d35a0db8e81d6"></a> 925<h2 class="memtitle"><span class="permalink"><a href="#ad0881b5c0250fd24034d35a0db8e81d6">◆ </a></span>RTE_I2C4_DMA_EN</h2> 926 927<div class="memitem"> 928<div class="memproto"> 929 <table class="memname"> 930 <tr> 931 <td class="memname">#define RTE_I2C4_DMA_EN   0</td> 932 </tr> 933 </table> 934</div><div class="memdoc"> 935 936<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00030">30</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 937 938</div> 939</div> 940<a id="adb24a07872f830d773e5a761b5b915ea"></a> 941<h2 class="memtitle"><span class="permalink"><a href="#adb24a07872f830d773e5a761b5b915ea">◆ </a></span>RTE_I2C4_DMA_RX_CH</h2> 942 943<div class="memitem"> 944<div class="memproto"> 945 <table class="memname"> 946 <tr> 947 <td class="memname">#define RTE_I2C4_DMA_RX_CH   4</td> 948 </tr> 949 </table> 950</div><div class="memdoc"> 951 952<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00096">96</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 953 954</div> 955</div> 956<a id="aac8180353fa95d472f154af42998f3ea"></a> 957<h2 class="memtitle"><span class="permalink"><a href="#aac8180353fa95d472f154af42998f3ea">◆ </a></span>RTE_I2C4_DMA_RX_DMA_BASE</h2> 958 959<div class="memitem"> 960<div class="memproto"> 961 <table class="memname"> 962 <tr> 963 <td class="memname">#define RTE_I2C4_DMA_RX_DMA_BASE   DMA__DMA1</td> 964 </tr> 965 </table> 966</div><div class="memdoc"> 967 968<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00098">98</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 969 970</div> 971</div> 972<a id="aad4b2e8753e39ef0df22e30d47f5af87"></a> 973<h2 class="memtitle"><span class="permalink"><a href="#aad4b2e8753e39ef0df22e30d47f5af87">◆ </a></span>RTE_I2C4_DMA_RX_PERI_SEL</h2> 974 975<div class="memitem"> 976<div class="memproto"> 977 <table class="memname"> 978 <tr> 979 <td class="memname">#define RTE_I2C4_DMA_RX_PERI_SEL   4</td> 980 </tr> 981 </table> 982</div><div class="memdoc"> 983 984<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00097">97</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 985 986</div> 987</div> 988<a id="a886533baa3ecbfdc24804b3bbd3c1fa4"></a> 989<h2 class="memtitle"><span class="permalink"><a href="#a886533baa3ecbfdc24804b3bbd3c1fa4">◆ </a></span>RTE_I2C4_DMA_TX_CH</h2> 990 991<div class="memitem"> 992<div class="memproto"> 993 <table class="memname"> 994 <tr> 995 <td class="memname">#define RTE_I2C4_DMA_TX_CH   5</td> 996 </tr> 997 </table> 998</div><div class="memdoc"> 999 1000<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00093">93</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1001 1002</div> 1003</div> 1004<a id="a1eeb5eb83698e059c5bbc3df7097102d"></a> 1005<h2 class="memtitle"><span class="permalink"><a href="#a1eeb5eb83698e059c5bbc3df7097102d">◆ </a></span>RTE_I2C4_DMA_TX_DMA_BASE</h2> 1006 1007<div class="memitem"> 1008<div class="memproto"> 1009 <table class="memname"> 1010 <tr> 1011 <td class="memname">#define RTE_I2C4_DMA_TX_DMA_BASE   DMA__DMA1</td> 1012 </tr> 1013 </table> 1014</div><div class="memdoc"> 1015 1016<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00095">95</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1017 1018</div> 1019</div> 1020<a id="acedae977949138b1e4bf418885238855"></a> 1021<h2 class="memtitle"><span class="permalink"><a href="#acedae977949138b1e4bf418885238855">◆ </a></span>RTE_I2C4_DMA_TX_PERI_SEL</h2> 1022 1023<div class="memitem"> 1024<div class="memproto"> 1025 <table class="memname"> 1026 <tr> 1027 <td class="memname">#define RTE_I2C4_DMA_TX_PERI_SEL   5</td> 1028 </tr> 1029 </table> 1030</div><div class="memdoc"> 1031 1032<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00094">94</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1033 1034</div> 1035</div> 1036<a id="af34a2837397fb473c1a29f942886f20a"></a> 1037<h2 class="memtitle"><span class="permalink"><a href="#af34a2837397fb473c1a29f942886f20a">◆ </a></span>RTE_I2C5</h2> 1038 1039<div class="memitem"> 1040<div class="memproto"> 1041 <table class="memname"> 1042 <tr> 1043 <td class="memname">#define RTE_I2C5   0</td> 1044 </tr> 1045 </table> 1046</div><div class="memdoc"> 1047 1048<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00031">31</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1049 1050</div> 1051</div> 1052<a id="a11fcca5364c2c59d91dcd1024a3741cd"></a> 1053<h2 class="memtitle"><span class="permalink"><a href="#a11fcca5364c2c59d91dcd1024a3741cd">◆ </a></span>RTE_I2C5_DMA_EN</h2> 1054 1055<div class="memitem"> 1056<div class="memproto"> 1057 <table class="memname"> 1058 <tr> 1059 <td class="memname">#define RTE_I2C5_DMA_EN   0</td> 1060 </tr> 1061 </table> 1062</div><div class="memdoc"> 1063 1064<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00032">32</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1065 1066</div> 1067</div> 1068<a id="a49d74f3d89f709bcee704ed8bc62a389"></a> 1069<h2 class="memtitle"><span class="permalink"><a href="#a49d74f3d89f709bcee704ed8bc62a389">◆ </a></span>RTE_I2C5_DMA_RX_CH</h2> 1070 1071<div class="memitem"> 1072<div class="memproto"> 1073 <table class="memname"> 1074 <tr> 1075 <td class="memname">#define RTE_I2C5_DMA_RX_CH   6</td> 1076 </tr> 1077 </table> 1078</div><div class="memdoc"> 1079 1080<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00103">103</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1081 1082</div> 1083</div> 1084<a id="afffd01e1818a0941804aa6898e0f3480"></a> 1085<h2 class="memtitle"><span class="permalink"><a href="#afffd01e1818a0941804aa6898e0f3480">◆ </a></span>RTE_I2C5_DMA_RX_DMA_BASE</h2> 1086 1087<div class="memitem"> 1088<div class="memproto"> 1089 <table class="memname"> 1090 <tr> 1091 <td class="memname">#define RTE_I2C5_DMA_RX_DMA_BASE   DMA__DMA1</td> 1092 </tr> 1093 </table> 1094</div><div class="memdoc"> 1095 1096<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00105">105</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1097 1098</div> 1099</div> 1100<a id="af9a7eeea936066a06aa12642d206ffe1"></a> 1101<h2 class="memtitle"><span class="permalink"><a href="#af9a7eeea936066a06aa12642d206ffe1">◆ </a></span>RTE_I2C5_DMA_RX_PERI_SEL</h2> 1102 1103<div class="memitem"> 1104<div class="memproto"> 1105 <table class="memname"> 1106 <tr> 1107 <td class="memname">#define RTE_I2C5_DMA_RX_PERI_SEL   6</td> 1108 </tr> 1109 </table> 1110</div><div class="memdoc"> 1111 1112<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00104">104</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1113 1114</div> 1115</div> 1116<a id="aacc69b6a58c942604d55ab3c66c18331"></a> 1117<h2 class="memtitle"><span class="permalink"><a href="#aacc69b6a58c942604d55ab3c66c18331">◆ </a></span>RTE_I2C5_DMA_TX_CH</h2> 1118 1119<div class="memitem"> 1120<div class="memproto"> 1121 <table class="memname"> 1122 <tr> 1123 <td class="memname">#define RTE_I2C5_DMA_TX_CH   7</td> 1124 </tr> 1125 </table> 1126</div><div class="memdoc"> 1127 1128<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00100">100</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1129 1130</div> 1131</div> 1132<a id="a237c977557c35a9f367b3dad28755434"></a> 1133<h2 class="memtitle"><span class="permalink"><a href="#a237c977557c35a9f367b3dad28755434">◆ </a></span>RTE_I2C5_DMA_TX_DMA_BASE</h2> 1134 1135<div class="memitem"> 1136<div class="memproto"> 1137 <table class="memname"> 1138 <tr> 1139 <td class="memname">#define RTE_I2C5_DMA_TX_DMA_BASE   DMA__DMA1</td> 1140 </tr> 1141 </table> 1142</div><div class="memdoc"> 1143 1144<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00102">102</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1145 1146</div> 1147</div> 1148<a id="aae327bc1bd7606f5ce0e12fa22c0c98f"></a> 1149<h2 class="memtitle"><span class="permalink"><a href="#aae327bc1bd7606f5ce0e12fa22c0c98f">◆ </a></span>RTE_I2C5_DMA_TX_PERI_SEL</h2> 1150 1151<div class="memitem"> 1152<div class="memproto"> 1153 <table class="memname"> 1154 <tr> 1155 <td class="memname">#define RTE_I2C5_DMA_TX_PERI_SEL   7</td> 1156 </tr> 1157 </table> 1158</div><div class="memdoc"> 1159 1160<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00101">101</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1161 1162</div> 1163</div> 1164<a id="a3def854682bc112f022a79dd60ca29d7"></a> 1165<h2 class="memtitle"><span class="permalink"><a href="#a3def854682bc112f022a79dd60ca29d7">◆ </a></span>RTE_I2C6</h2> 1166 1167<div class="memitem"> 1168<div class="memproto"> 1169 <table class="memname"> 1170 <tr> 1171 <td class="memname">#define RTE_I2C6   0</td> 1172 </tr> 1173 </table> 1174</div><div class="memdoc"> 1175 1176<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00033">33</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1177 1178</div> 1179</div> 1180<a id="a1c6ff3c4d303f391e5ec124aa238c08f"></a> 1181<h2 class="memtitle"><span class="permalink"><a href="#a1c6ff3c4d303f391e5ec124aa238c08f">◆ </a></span>RTE_I2C6_DMA_EN</h2> 1182 1183<div class="memitem"> 1184<div class="memproto"> 1185 <table class="memname"> 1186 <tr> 1187 <td class="memname">#define RTE_I2C6_DMA_EN   0</td> 1188 </tr> 1189 </table> 1190</div><div class="memdoc"> 1191 1192<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00034">34</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1193 1194</div> 1195</div> 1196<a id="adbde0a01f889e105a70dea33e0b774fe"></a> 1197<h2 class="memtitle"><span class="permalink"><a href="#adbde0a01f889e105a70dea33e0b774fe">◆ </a></span>RTE_I2C6_DMA_RX_CH</h2> 1198 1199<div class="memitem"> 1200<div class="memproto"> 1201 <table class="memname"> 1202 <tr> 1203 <td class="memname">#define RTE_I2C6_DMA_RX_CH   8</td> 1204 </tr> 1205 </table> 1206</div><div class="memdoc"> 1207 1208<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00110">110</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1209 1210</div> 1211</div> 1212<a id="afdf4039762fae0cda1db8c9ea184e641"></a> 1213<h2 class="memtitle"><span class="permalink"><a href="#afdf4039762fae0cda1db8c9ea184e641">◆ </a></span>RTE_I2C6_DMA_RX_DMA_BASE</h2> 1214 1215<div class="memitem"> 1216<div class="memproto"> 1217 <table class="memname"> 1218 <tr> 1219 <td class="memname">#define RTE_I2C6_DMA_RX_DMA_BASE   DMA__DMA1</td> 1220 </tr> 1221 </table> 1222</div><div class="memdoc"> 1223 1224<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00112">112</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1225 1226</div> 1227</div> 1228<a id="a18a0ead9ea40c2c592a5a3a73d4f3916"></a> 1229<h2 class="memtitle"><span class="permalink"><a href="#a18a0ead9ea40c2c592a5a3a73d4f3916">◆ </a></span>RTE_I2C6_DMA_RX_PERI_SEL</h2> 1230 1231<div class="memitem"> 1232<div class="memproto"> 1233 <table class="memname"> 1234 <tr> 1235 <td class="memname">#define RTE_I2C6_DMA_RX_PERI_SEL   8</td> 1236 </tr> 1237 </table> 1238</div><div class="memdoc"> 1239 1240<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00111">111</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1241 1242</div> 1243</div> 1244<a id="aa15456a15715d87b5d9fd1663b6def21"></a> 1245<h2 class="memtitle"><span class="permalink"><a href="#aa15456a15715d87b5d9fd1663b6def21">◆ </a></span>RTE_I2C6_DMA_TX_CH</h2> 1246 1247<div class="memitem"> 1248<div class="memproto"> 1249 <table class="memname"> 1250 <tr> 1251 <td class="memname">#define RTE_I2C6_DMA_TX_CH   9</td> 1252 </tr> 1253 </table> 1254</div><div class="memdoc"> 1255 1256<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00107">107</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1257 1258</div> 1259</div> 1260<a id="a3beb3f0a50107be726578869d167101a"></a> 1261<h2 class="memtitle"><span class="permalink"><a href="#a3beb3f0a50107be726578869d167101a">◆ </a></span>RTE_I2C6_DMA_TX_DMA_BASE</h2> 1262 1263<div class="memitem"> 1264<div class="memproto"> 1265 <table class="memname"> 1266 <tr> 1267 <td class="memname">#define RTE_I2C6_DMA_TX_DMA_BASE   DMA__DMA1</td> 1268 </tr> 1269 </table> 1270</div><div class="memdoc"> 1271 1272<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00109">109</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1273 1274</div> 1275</div> 1276<a id="a3376a9bd3c4accdc4e0d25251960563b"></a> 1277<h2 class="memtitle"><span class="permalink"><a href="#a3376a9bd3c4accdc4e0d25251960563b">◆ </a></span>RTE_I2C6_DMA_TX_PERI_SEL</h2> 1278 1279<div class="memitem"> 1280<div class="memproto"> 1281 <table class="memname"> 1282 <tr> 1283 <td class="memname">#define RTE_I2C6_DMA_TX_PERI_SEL   9</td> 1284 </tr> 1285 </table> 1286</div><div class="memdoc"> 1287 1288<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00108">108</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1289 1290</div> 1291</div> 1292<a id="a0529e9360e95f2b1e4c67b49ae2df44c"></a> 1293<h2 class="memtitle"><span class="permalink"><a href="#a0529e9360e95f2b1e4c67b49ae2df44c">◆ </a></span>RTE_SPI0</h2> 1294 1295<div class="memitem"> 1296<div class="memproto"> 1297 <table class="memname"> 1298 <tr> 1299 <td class="memname">#define RTE_SPI0   0</td> 1300 </tr> 1301 </table> 1302</div><div class="memdoc"> 1303 1304<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00043">43</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1305 1306</div> 1307</div> 1308<a id="a7dd0070f51cd6be78f323f82df082b74"></a> 1309<h2 class="memtitle"><span class="permalink"><a href="#a7dd0070f51cd6be78f323f82df082b74">◆ </a></span>RTE_SPI0_DMA_EN</h2> 1310 1311<div class="memitem"> 1312<div class="memproto"> 1313 <table class="memname"> 1314 <tr> 1315 <td class="memname">#define RTE_SPI0_DMA_EN   0</td> 1316 </tr> 1317 </table> 1318</div><div class="memdoc"> 1319 1320<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00044">44</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1321 1322</div> 1323</div> 1324<a id="adc244beab1014dda00966fcbbb65578c"></a> 1325<h2 class="memtitle"><span class="permalink"><a href="#adc244beab1014dda00966fcbbb65578c">◆ </a></span>RTE_SPI1</h2> 1326 1327<div class="memitem"> 1328<div class="memproto"> 1329 <table class="memname"> 1330 <tr> 1331 <td class="memname">#define RTE_SPI1   0</td> 1332 </tr> 1333 </table> 1334</div><div class="memdoc"> 1335 1336<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00045">45</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1337 1338</div> 1339</div> 1340<a id="aa77f48b8f0f046f17b57ee388ba986c3"></a> 1341<h2 class="memtitle"><span class="permalink"><a href="#aa77f48b8f0f046f17b57ee388ba986c3">◆ </a></span>RTE_SPI1_DMA_EN</h2> 1342 1343<div class="memitem"> 1344<div class="memproto"> 1345 <table class="memname"> 1346 <tr> 1347 <td class="memname">#define RTE_SPI1_DMA_EN   0</td> 1348 </tr> 1349 </table> 1350</div><div class="memdoc"> 1351 1352<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00046">46</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1353 1354</div> 1355</div> 1356<a id="a23c083e17af81df6307b6a09c7b526bd"></a> 1357<h2 class="memtitle"><span class="permalink"><a href="#a23c083e17af81df6307b6a09c7b526bd">◆ </a></span>RTE_SPI2</h2> 1358 1359<div class="memitem"> 1360<div class="memproto"> 1361 <table class="memname"> 1362 <tr> 1363 <td class="memname">#define RTE_SPI2   1</td> 1364 </tr> 1365 </table> 1366</div><div class="memdoc"> 1367 1368<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00047">47</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1369 1370</div> 1371</div> 1372<a id="af6ec6eb776de0e8df30bc2acc19f9221"></a> 1373<h2 class="memtitle"><span class="permalink"><a href="#af6ec6eb776de0e8df30bc2acc19f9221">◆ </a></span>RTE_SPI2_DMA_EN</h2> 1374 1375<div class="memitem"> 1376<div class="memproto"> 1377 <table class="memname"> 1378 <tr> 1379 <td class="memname">#define RTE_SPI2_DMA_EN   0</td> 1380 </tr> 1381 </table> 1382</div><div class="memdoc"> 1383 1384<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00048">48</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1385 1386</div> 1387</div> 1388<a id="aa78a035aaa73a024f3e9ad91e3d28c18"></a> 1389<h2 class="memtitle"><span class="permalink"><a href="#aa78a035aaa73a024f3e9ad91e3d28c18">◆ </a></span>RTE_SPI3</h2> 1390 1391<div class="memitem"> 1392<div class="memproto"> 1393 <table class="memname"> 1394 <tr> 1395 <td class="memname">#define RTE_SPI3   0</td> 1396 </tr> 1397 </table> 1398</div><div class="memdoc"> 1399 1400<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00049">49</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1401 1402</div> 1403</div> 1404<a id="a262ea23b85408aacef35d7dea979abfd"></a> 1405<h2 class="memtitle"><span class="permalink"><a href="#a262ea23b85408aacef35d7dea979abfd">◆ </a></span>RTE_SPI3_DMA_EN</h2> 1406 1407<div class="memitem"> 1408<div class="memproto"> 1409 <table class="memname"> 1410 <tr> 1411 <td class="memname">#define RTE_SPI3_DMA_EN   0</td> 1412 </tr> 1413 </table> 1414</div><div class="memdoc"> 1415 1416<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00050">50</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1417 1418</div> 1419</div> 1420<a id="a17b2c1002dc50e01a17a2ce94a628133"></a> 1421<h2 class="memtitle"><span class="permalink"><a href="#a17b2c1002dc50e01a17a2ce94a628133">◆ </a></span>RTE_USART0</h2> 1422 1423<div class="memitem"> 1424<div class="memproto"> 1425 <table class="memname"> 1426 <tr> 1427 <td class="memname">#define RTE_USART0   0</td> 1428 </tr> 1429 </table> 1430</div><div class="memdoc"> 1431 1432<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00062">62</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1433 1434</div> 1435</div> 1436<a id="a3071e002a5a0ce4ac87de6dcc87bb3da"></a> 1437<h2 class="memtitle"><span class="permalink"><a href="#a3071e002a5a0ce4ac87de6dcc87bb3da">◆ </a></span>RTE_USART0_DMA_EN</h2> 1438 1439<div class="memitem"> 1440<div class="memproto"> 1441 <table class="memname"> 1442 <tr> 1443 <td class="memname">#define RTE_USART0_DMA_EN   0</td> 1444 </tr> 1445 </table> 1446</div><div class="memdoc"> 1447 1448<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00063">63</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1449 1450</div> 1451</div> 1452<a id="ae8f0e0260407d14858ce86d2ffb75424"></a> 1453<h2 class="memtitle"><span class="permalink"><a href="#ae8f0e0260407d14858ce86d2ffb75424">◆ </a></span>RTE_USART1</h2> 1454 1455<div class="memitem"> 1456<div class="memproto"> 1457 <table class="memname"> 1458 <tr> 1459 <td class="memname">#define RTE_USART1   0</td> 1460 </tr> 1461 </table> 1462</div><div class="memdoc"> 1463 1464<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00064">64</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1465 1466</div> 1467</div> 1468<a id="a93373776f843912cefd1355e207352e2"></a> 1469<h2 class="memtitle"><span class="permalink"><a href="#a93373776f843912cefd1355e207352e2">◆ </a></span>RTE_USART1_DMA_EN</h2> 1470 1471<div class="memitem"> 1472<div class="memproto"> 1473 <table class="memname"> 1474 <tr> 1475 <td class="memname">#define RTE_USART1_DMA_EN   0</td> 1476 </tr> 1477 </table> 1478</div><div class="memdoc"> 1479 1480<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00065">65</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1481 1482</div> 1483</div> 1484<a id="af4f4f5e1f698d40d9f7d716257536d42"></a> 1485<h2 class="memtitle"><span class="permalink"><a href="#af4f4f5e1f698d40d9f7d716257536d42">◆ </a></span>RTE_USART2</h2> 1486 1487<div class="memitem"> 1488<div class="memproto"> 1489 <table class="memname"> 1490 <tr> 1491 <td class="memname">#define RTE_USART2   0</td> 1492 </tr> 1493 </table> 1494</div><div class="memdoc"> 1495 1496<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00066">66</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1497 1498</div> 1499</div> 1500<a id="a125adde5b7b5906d3427a57420322722"></a> 1501<h2 class="memtitle"><span class="permalink"><a href="#a125adde5b7b5906d3427a57420322722">◆ </a></span>RTE_USART2_DMA_EN</h2> 1502 1503<div class="memitem"> 1504<div class="memproto"> 1505 <table class="memname"> 1506 <tr> 1507 <td class="memname">#define RTE_USART2_DMA_EN   0</td> 1508 </tr> 1509 </table> 1510</div><div class="memdoc"> 1511 1512<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00067">67</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1513 1514</div> 1515</div> 1516<a id="aaf5d293f3353d103aa7fc672a3cf456d"></a> 1517<h2 class="memtitle"><span class="permalink"><a href="#aaf5d293f3353d103aa7fc672a3cf456d">◆ </a></span>RTE_USART2_DMA_RX_CH</h2> 1518 1519<div class="memitem"> 1520<div class="memproto"> 1521 <table class="memname"> 1522 <tr> 1523 <td class="memname">#define RTE_USART2_DMA_RX_CH   12</td> 1524 </tr> 1525 </table> 1526</div><div class="memdoc"> 1527 1528<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00122">122</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1529 1530</div> 1531</div> 1532<a id="a54af00b2f29f1e9aeb10e1a59a4cde3d"></a> 1533<h2 class="memtitle"><span class="permalink"><a href="#a54af00b2f29f1e9aeb10e1a59a4cde3d">◆ </a></span>RTE_USART2_DMA_RX_DMA_BASE</h2> 1534 1535<div class="memitem"> 1536<div class="memproto"> 1537 <table class="memname"> 1538 <tr> 1539 <td class="memname">#define RTE_USART2_DMA_RX_DMA_BASE   DMA__DMA0</td> 1540 </tr> 1541 </table> 1542</div><div class="memdoc"> 1543 1544<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00124">124</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1545 1546</div> 1547</div> 1548<a id="ad8969d48f9a854dcd661e60ace8f2eac"></a> 1549<h2 class="memtitle"><span class="permalink"><a href="#ad8969d48f9a854dcd661e60ace8f2eac">◆ </a></span>RTE_USART2_DMA_RX_PERI_SEL</h2> 1550 1551<div class="memitem"> 1552<div class="memproto"> 1553 <table class="memname"> 1554 <tr> 1555 <td class="memname">#define RTE_USART2_DMA_RX_PERI_SEL   12</td> 1556 </tr> 1557 </table> 1558</div><div class="memdoc"> 1559 1560<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00123">123</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1561 1562</div> 1563</div> 1564<a id="a4da147c7ce755201a079c412c098128f"></a> 1565<h2 class="memtitle"><span class="permalink"><a href="#a4da147c7ce755201a079c412c098128f">◆ </a></span>RTE_USART2_DMA_TX_CH</h2> 1566 1567<div class="memitem"> 1568<div class="memproto"> 1569 <table class="memname"> 1570 <tr> 1571 <td class="memname">#define RTE_USART2_DMA_TX_CH   13</td> 1572 </tr> 1573 </table> 1574</div><div class="memdoc"> 1575 1576<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00119">119</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1577 1578</div> 1579</div> 1580<a id="a667adae4bda8ac302bcc85d4a7a004cd"></a> 1581<h2 class="memtitle"><span class="permalink"><a href="#a667adae4bda8ac302bcc85d4a7a004cd">◆ </a></span>RTE_USART2_DMA_TX_DMA_BASE</h2> 1582 1583<div class="memitem"> 1584<div class="memproto"> 1585 <table class="memname"> 1586 <tr> 1587 <td class="memname">#define RTE_USART2_DMA_TX_DMA_BASE   DMA__DMA0</td> 1588 </tr> 1589 </table> 1590</div><div class="memdoc"> 1591 1592<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00121">121</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1593 1594</div> 1595</div> 1596<a id="a1921b3ed005879e26052e379f23dbcb2"></a> 1597<h2 class="memtitle"><span class="permalink"><a href="#a1921b3ed005879e26052e379f23dbcb2">◆ </a></span>RTE_USART2_DMA_TX_PERI_SEL</h2> 1598 1599<div class="memitem"> 1600<div class="memproto"> 1601 <table class="memname"> 1602 <tr> 1603 <td class="memname">#define RTE_USART2_DMA_TX_PERI_SEL   13</td> 1604 </tr> 1605 </table> 1606</div><div class="memdoc"> 1607 1608<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00120">120</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1609 1610</div> 1611</div> 1612<a id="ae6d7bafeb9d5b445ebadbd0f224bf1a5"></a> 1613<h2 class="memtitle"><span class="permalink"><a href="#ae6d7bafeb9d5b445ebadbd0f224bf1a5">◆ </a></span>RTE_USART3</h2> 1614 1615<div class="memitem"> 1616<div class="memproto"> 1617 <table class="memname"> 1618 <tr> 1619 <td class="memname">#define RTE_USART3   0</td> 1620 </tr> 1621 </table> 1622</div><div class="memdoc"> 1623 1624<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00068">68</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1625 1626</div> 1627</div> 1628<a id="a64fade6195385d3c00eeb16517725bb5"></a> 1629<h2 class="memtitle"><span class="permalink"><a href="#a64fade6195385d3c00eeb16517725bb5">◆ </a></span>RTE_USART3_DMA_EN</h2> 1630 1631<div class="memitem"> 1632<div class="memproto"> 1633 <table class="memname"> 1634 <tr> 1635 <td class="memname">#define RTE_USART3_DMA_EN   0</td> 1636 </tr> 1637 </table> 1638</div><div class="memdoc"> 1639 1640<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00069">69</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1641 1642</div> 1643</div> 1644<a id="ab09d3b40ddde8be68179be6d46400d45"></a> 1645<h2 class="memtitle"><span class="permalink"><a href="#ab09d3b40ddde8be68179be6d46400d45">◆ </a></span>RTE_USART3_DMA_RX_CH</h2> 1646 1647<div class="memitem"> 1648<div class="memproto"> 1649 <table class="memname"> 1650 <tr> 1651 <td class="memname">#define RTE_USART3_DMA_RX_CH   14</td> 1652 </tr> 1653 </table> 1654</div><div class="memdoc"> 1655 1656<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00129">129</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1657 1658</div> 1659</div> 1660<a id="ae05b2c8a2baaa32c10d0af3457ce2e28"></a> 1661<h2 class="memtitle"><span class="permalink"><a href="#ae05b2c8a2baaa32c10d0af3457ce2e28">◆ </a></span>RTE_USART3_DMA_RX_DMA_BASE</h2> 1662 1663<div class="memitem"> 1664<div class="memproto"> 1665 <table class="memname"> 1666 <tr> 1667 <td class="memname">#define RTE_USART3_DMA_RX_DMA_BASE   DMA__DMA0</td> 1668 </tr> 1669 </table> 1670</div><div class="memdoc"> 1671 1672<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00131">131</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1673 1674</div> 1675</div> 1676<a id="ab310379c65913c108e059c4e317ce096"></a> 1677<h2 class="memtitle"><span class="permalink"><a href="#ab310379c65913c108e059c4e317ce096">◆ </a></span>RTE_USART3_DMA_RX_PERI_SEL</h2> 1678 1679<div class="memitem"> 1680<div class="memproto"> 1681 <table class="memname"> 1682 <tr> 1683 <td class="memname">#define RTE_USART3_DMA_RX_PERI_SEL   14</td> 1684 </tr> 1685 </table> 1686</div><div class="memdoc"> 1687 1688<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00130">130</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1689 1690</div> 1691</div> 1692<a id="a371552d64a4c36aa553a256ab52c4737"></a> 1693<h2 class="memtitle"><span class="permalink"><a href="#a371552d64a4c36aa553a256ab52c4737">◆ </a></span>RTE_USART3_DMA_TX_CH</h2> 1694 1695<div class="memitem"> 1696<div class="memproto"> 1697 <table class="memname"> 1698 <tr> 1699 <td class="memname">#define RTE_USART3_DMA_TX_CH   15</td> 1700 </tr> 1701 </table> 1702</div><div class="memdoc"> 1703 1704<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00126">126</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1705 1706</div> 1707</div> 1708<a id="a230981b96cecea4add332ecd40533454"></a> 1709<h2 class="memtitle"><span class="permalink"><a href="#a230981b96cecea4add332ecd40533454">◆ </a></span>RTE_USART3_DMA_TX_DMA_BASE</h2> 1710 1711<div class="memitem"> 1712<div class="memproto"> 1713 <table class="memname"> 1714 <tr> 1715 <td class="memname">#define RTE_USART3_DMA_TX_DMA_BASE   DMA__DMA0</td> 1716 </tr> 1717 </table> 1718</div><div class="memdoc"> 1719 1720<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00128">128</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1721 1722</div> 1723</div> 1724<a id="a298c8ca62c3080284bf1c1ddc9e52c74"></a> 1725<h2 class="memtitle"><span class="permalink"><a href="#a298c8ca62c3080284bf1c1ddc9e52c74">◆ </a></span>RTE_USART3_DMA_TX_PERI_SEL</h2> 1726 1727<div class="memitem"> 1728<div class="memproto"> 1729 <table class="memname"> 1730 <tr> 1731 <td class="memname">#define RTE_USART3_DMA_TX_PERI_SEL   15</td> 1732 </tr> 1733 </table> 1734</div><div class="memdoc"> 1735 1736<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00127">127</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1737 1738</div> 1739</div> 1740<a id="a3716b269a4311d87ba183b633ebfad07"></a> 1741<h2 class="memtitle"><span class="permalink"><a href="#a3716b269a4311d87ba183b633ebfad07">◆ </a></span>RTE_USART4</h2> 1742 1743<div class="memitem"> 1744<div class="memproto"> 1745 <table class="memname"> 1746 <tr> 1747 <td class="memname">#define RTE_USART4   1</td> 1748 </tr> 1749 </table> 1750</div><div class="memdoc"> 1751 1752<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00070">70</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1753 1754</div> 1755</div> 1756<a id="abccb132237192d276dec5fd1235d3124"></a> 1757<h2 class="memtitle"><span class="permalink"><a href="#abccb132237192d276dec5fd1235d3124">◆ </a></span>RTE_USART4_DMA_EN</h2> 1758 1759<div class="memitem"> 1760<div class="memproto"> 1761 <table class="memname"> 1762 <tr> 1763 <td class="memname">#define RTE_USART4_DMA_EN   0</td> 1764 </tr> 1765 </table> 1766</div><div class="memdoc"> 1767 1768<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00071">71</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1769 1770</div> 1771</div> 1772<a id="ae3aa08740bc1278f56cb25413751053b"></a> 1773<h2 class="memtitle"><span class="permalink"><a href="#ae3aa08740bc1278f56cb25413751053b">◆ </a></span>RTE_USART4_DMA_RX_CH</h2> 1774 1775<div class="memitem"> 1776<div class="memproto"> 1777 <table class="memname"> 1778 <tr> 1779 <td class="memname">#define RTE_USART4_DMA_RX_CH   16</td> 1780 </tr> 1781 </table> 1782</div><div class="memdoc"> 1783 1784<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00136">136</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1785 1786</div> 1787</div> 1788<a id="a84ae4f174efa1b7417b5a35d9b9e3de9"></a> 1789<h2 class="memtitle"><span class="permalink"><a href="#a84ae4f174efa1b7417b5a35d9b9e3de9">◆ </a></span>RTE_USART4_DMA_RX_DMA_BASE</h2> 1790 1791<div class="memitem"> 1792<div class="memproto"> 1793 <table class="memname"> 1794 <tr> 1795 <td class="memname">#define RTE_USART4_DMA_RX_DMA_BASE   DMA__DMA0</td> 1796 </tr> 1797 </table> 1798</div><div class="memdoc"> 1799 1800<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00138">138</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1801 1802</div> 1803</div> 1804<a id="a2d133b10d9af3b93828d264638c01d69"></a> 1805<h2 class="memtitle"><span class="permalink"><a href="#a2d133b10d9af3b93828d264638c01d69">◆ </a></span>RTE_USART4_DMA_RX_PERI_SEL</h2> 1806 1807<div class="memitem"> 1808<div class="memproto"> 1809 <table class="memname"> 1810 <tr> 1811 <td class="memname">#define RTE_USART4_DMA_RX_PERI_SEL   16</td> 1812 </tr> 1813 </table> 1814</div><div class="memdoc"> 1815 1816<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00137">137</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1817 1818</div> 1819</div> 1820<a id="a583406cbb43d2e24e0cf8cafdb45d7d9"></a> 1821<h2 class="memtitle"><span class="permalink"><a href="#a583406cbb43d2e24e0cf8cafdb45d7d9">◆ </a></span>RTE_USART4_DMA_TX_CH</h2> 1822 1823<div class="memitem"> 1824<div class="memproto"> 1825 <table class="memname"> 1826 <tr> 1827 <td class="memname">#define RTE_USART4_DMA_TX_CH   17</td> 1828 </tr> 1829 </table> 1830</div><div class="memdoc"> 1831 1832<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00133">133</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1833 1834</div> 1835</div> 1836<a id="ac4abea21e4bfc3d03539f739892b0e7f"></a> 1837<h2 class="memtitle"><span class="permalink"><a href="#ac4abea21e4bfc3d03539f739892b0e7f">◆ </a></span>RTE_USART4_DMA_TX_DMA_BASE</h2> 1838 1839<div class="memitem"> 1840<div class="memproto"> 1841 <table class="memname"> 1842 <tr> 1843 <td class="memname">#define RTE_USART4_DMA_TX_DMA_BASE   DMA__DMA0</td> 1844 </tr> 1845 </table> 1846</div><div class="memdoc"> 1847 1848<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00135">135</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1849 1850</div> 1851</div> 1852<a id="a2b6f4b82acc33b81f3637afc63419169"></a> 1853<h2 class="memtitle"><span class="permalink"><a href="#a2b6f4b82acc33b81f3637afc63419169">◆ </a></span>RTE_USART4_DMA_TX_PERI_SEL</h2> 1854 1855<div class="memitem"> 1856<div class="memproto"> 1857 <table class="memname"> 1858 <tr> 1859 <td class="memname">#define RTE_USART4_DMA_TX_PERI_SEL   17</td> 1860 </tr> 1861 </table> 1862</div><div class="memdoc"> 1863 1864<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00134">134</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1865 1866</div> 1867</div> 1868<a id="a5c2c625ac67c8f31440a92490b6d767e"></a> 1869<h2 class="memtitle"><span class="permalink"><a href="#a5c2c625ac67c8f31440a92490b6d767e">◆ </a></span>RTE_USART5</h2> 1870 1871<div class="memitem"> 1872<div class="memproto"> 1873 <table class="memname"> 1874 <tr> 1875 <td class="memname">#define RTE_USART5   0</td> 1876 </tr> 1877 </table> 1878</div><div class="memdoc"> 1879 1880<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00072">72</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1881 1882</div> 1883</div> 1884<a id="aaf003f78b5c4c182d687b220e75e1dbb"></a> 1885<h2 class="memtitle"><span class="permalink"><a href="#aaf003f78b5c4c182d687b220e75e1dbb">◆ </a></span>RTE_USART5_DMA_EN</h2> 1886 1887<div class="memitem"> 1888<div class="memproto"> 1889 <table class="memname"> 1890 <tr> 1891 <td class="memname">#define RTE_USART5_DMA_EN   0</td> 1892 </tr> 1893 </table> 1894</div><div class="memdoc"> 1895 1896<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00073">73</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1897 1898</div> 1899</div> 1900<a id="af563379f0b22b56089642e1452293b94"></a> 1901<h2 class="memtitle"><span class="permalink"><a href="#af563379f0b22b56089642e1452293b94">◆ </a></span>RTE_USART5_DMA_RX_CH</h2> 1902 1903<div class="memitem"> 1904<div class="memproto"> 1905 <table class="memname"> 1906 <tr> 1907 <td class="memname">#define RTE_USART5_DMA_RX_CH   18</td> 1908 </tr> 1909 </table> 1910</div><div class="memdoc"> 1911 1912<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00143">143</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1913 1914</div> 1915</div> 1916<a id="a665e630b27a6713ff3055c9893403090"></a> 1917<h2 class="memtitle"><span class="permalink"><a href="#a665e630b27a6713ff3055c9893403090">◆ </a></span>RTE_USART5_DMA_RX_DMA_BASE</h2> 1918 1919<div class="memitem"> 1920<div class="memproto"> 1921 <table class="memname"> 1922 <tr> 1923 <td class="memname">#define RTE_USART5_DMA_RX_DMA_BASE   DMA__DMA0</td> 1924 </tr> 1925 </table> 1926</div><div class="memdoc"> 1927 1928<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00145">145</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1929 1930</div> 1931</div> 1932<a id="a4dc20b4bfb5766bac0d6de434bda7fd8"></a> 1933<h2 class="memtitle"><span class="permalink"><a href="#a4dc20b4bfb5766bac0d6de434bda7fd8">◆ </a></span>RTE_USART5_DMA_RX_PERI_SEL</h2> 1934 1935<div class="memitem"> 1936<div class="memproto"> 1937 <table class="memname"> 1938 <tr> 1939 <td class="memname">#define RTE_USART5_DMA_RX_PERI_SEL   18</td> 1940 </tr> 1941 </table> 1942</div><div class="memdoc"> 1943 1944<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00144">144</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1945 1946</div> 1947</div> 1948<a id="a5fc281007f625bf44a5b16d7f97c9f7b"></a> 1949<h2 class="memtitle"><span class="permalink"><a href="#a5fc281007f625bf44a5b16d7f97c9f7b">◆ </a></span>RTE_USART5_DMA_TX_CH</h2> 1950 1951<div class="memitem"> 1952<div class="memproto"> 1953 <table class="memname"> 1954 <tr> 1955 <td class="memname">#define RTE_USART5_DMA_TX_CH   19</td> 1956 </tr> 1957 </table> 1958</div><div class="memdoc"> 1959 1960<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00140">140</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1961 1962</div> 1963</div> 1964<a id="a530f52cd5d979b98f959163c96e4413b"></a> 1965<h2 class="memtitle"><span class="permalink"><a href="#a530f52cd5d979b98f959163c96e4413b">◆ </a></span>RTE_USART5_DMA_TX_DMA_BASE</h2> 1966 1967<div class="memitem"> 1968<div class="memproto"> 1969 <table class="memname"> 1970 <tr> 1971 <td class="memname">#define RTE_USART5_DMA_TX_DMA_BASE   DMA__DMA0</td> 1972 </tr> 1973 </table> 1974</div><div class="memdoc"> 1975 1976<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00142">142</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1977 1978</div> 1979</div> 1980<a id="a3f34578afbd133748801bbb852f1cc46"></a> 1981<h2 class="memtitle"><span class="permalink"><a href="#a3f34578afbd133748801bbb852f1cc46">◆ </a></span>RTE_USART5_DMA_TX_PERI_SEL</h2> 1982 1983<div class="memitem"> 1984<div class="memproto"> 1985 <table class="memname"> 1986 <tr> 1987 <td class="memname">#define RTE_USART5_DMA_TX_PERI_SEL   19</td> 1988 </tr> 1989 </table> 1990</div><div class="memdoc"> 1991 1992<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00141">141</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 1993 1994</div> 1995</div> 1996<a id="af4a7b2970a0f7ac0ee0802298c09848c"></a> 1997<h2 class="memtitle"><span class="permalink"><a href="#af4a7b2970a0f7ac0ee0802298c09848c">◆ </a></span>RTE_USART6</h2> 1998 1999<div class="memitem"> 2000<div class="memproto"> 2001 <table class="memname"> 2002 <tr> 2003 <td class="memname">#define RTE_USART6   0</td> 2004 </tr> 2005 </table> 2006</div><div class="memdoc"> 2007 2008<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00074">74</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2009 2010</div> 2011</div> 2012<a id="a46301a9b2d783e5c629b180d8f2344f6"></a> 2013<h2 class="memtitle"><span class="permalink"><a href="#a46301a9b2d783e5c629b180d8f2344f6">◆ </a></span>RTE_USART6_DMA_EN</h2> 2014 2015<div class="memitem"> 2016<div class="memproto"> 2017 <table class="memname"> 2018 <tr> 2019 <td class="memname">#define RTE_USART6_DMA_EN   0</td> 2020 </tr> 2021 </table> 2022</div><div class="memdoc"> 2023 2024<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00075">75</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2025 2026</div> 2027</div> 2028<a id="a74e96a5225571536daf6ce2058f2ca11"></a> 2029<h2 class="memtitle"><span class="permalink"><a href="#a74e96a5225571536daf6ce2058f2ca11">◆ </a></span>RTE_USART6_DMA_RX_CH</h2> 2030 2031<div class="memitem"> 2032<div class="memproto"> 2033 <table class="memname"> 2034 <tr> 2035 <td class="memname">#define RTE_USART6_DMA_RX_CH   20</td> 2036 </tr> 2037 </table> 2038</div><div class="memdoc"> 2039 2040<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00150">150</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2041 2042</div> 2043</div> 2044<a id="a5937989b65e91558a7ecd473a511e5e6"></a> 2045<h2 class="memtitle"><span class="permalink"><a href="#a5937989b65e91558a7ecd473a511e5e6">◆ </a></span>RTE_USART6_DMA_RX_DMA_BASE</h2> 2046 2047<div class="memitem"> 2048<div class="memproto"> 2049 <table class="memname"> 2050 <tr> 2051 <td class="memname">#define RTE_USART6_DMA_RX_DMA_BASE   DMA__DMA0</td> 2052 </tr> 2053 </table> 2054</div><div class="memdoc"> 2055 2056<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00152">152</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2057 2058</div> 2059</div> 2060<a id="ad55c040ec06f230089b7f190f5eb5589"></a> 2061<h2 class="memtitle"><span class="permalink"><a href="#ad55c040ec06f230089b7f190f5eb5589">◆ </a></span>RTE_USART6_DMA_RX_PERI_SEL</h2> 2062 2063<div class="memitem"> 2064<div class="memproto"> 2065 <table class="memname"> 2066 <tr> 2067 <td class="memname">#define RTE_USART6_DMA_RX_PERI_SEL   20</td> 2068 </tr> 2069 </table> 2070</div><div class="memdoc"> 2071 2072<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00151">151</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2073 2074</div> 2075</div> 2076<a id="a830ccf4153d422fc98971a8fc2d1ecba"></a> 2077<h2 class="memtitle"><span class="permalink"><a href="#a830ccf4153d422fc98971a8fc2d1ecba">◆ </a></span>RTE_USART6_DMA_TX_CH</h2> 2078 2079<div class="memitem"> 2080<div class="memproto"> 2081 <table class="memname"> 2082 <tr> 2083 <td class="memname">#define RTE_USART6_DMA_TX_CH   21</td> 2084 </tr> 2085 </table> 2086</div><div class="memdoc"> 2087 2088<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00147">147</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2089 2090</div> 2091</div> 2092<a id="aa50f707f6ba72c2c400faa7e2c9b8b5f"></a> 2093<h2 class="memtitle"><span class="permalink"><a href="#aa50f707f6ba72c2c400faa7e2c9b8b5f">◆ </a></span>RTE_USART6_DMA_TX_DMA_BASE</h2> 2094 2095<div class="memitem"> 2096<div class="memproto"> 2097 <table class="memname"> 2098 <tr> 2099 <td class="memname">#define RTE_USART6_DMA_TX_DMA_BASE   DMA__DMA0</td> 2100 </tr> 2101 </table> 2102</div><div class="memdoc"> 2103 2104<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00149">149</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2105 2106</div> 2107</div> 2108<a id="ac1692d643111d558f2df528205966f28"></a> 2109<h2 class="memtitle"><span class="permalink"><a href="#ac1692d643111d558f2df528205966f28">◆ </a></span>RTE_USART6_DMA_TX_PERI_SEL</h2> 2110 2111<div class="memitem"> 2112<div class="memproto"> 2113 <table class="memname"> 2114 <tr> 2115 <td class="memname">#define RTE_USART6_DMA_TX_PERI_SEL   21</td> 2116 </tr> 2117 </table> 2118</div><div class="memdoc"> 2119 2120<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00148">148</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2121 2122</div> 2123</div> 2124<a id="a42233d962f08392fe286ed2e652eb9b1"></a> 2125<h2 class="memtitle"><span class="permalink"><a href="#a42233d962f08392fe286ed2e652eb9b1">◆ </a></span>USART4_RX_BUFFER_ENABLE</h2> 2126 2127<div class="memitem"> 2128<div class="memproto"> 2129 <table class="memname"> 2130 <tr> 2131 <td class="memname">#define USART4_RX_BUFFER_ENABLE   1</td> 2132 </tr> 2133 </table> 2134</div><div class="memdoc"> 2135 2136<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00116">116</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2137 2138</div> 2139</div> 2140<a id="a43c0f3151f3f65559aec155908ac5804"></a> 2141<h2 class="memtitle"><span class="permalink"><a href="#a43c0f3151f3f65559aec155908ac5804">◆ </a></span>USART_RX_BUFFER_LEN</h2> 2142 2143<div class="memitem"> 2144<div class="memproto"> 2145 <table class="memname"> 2146 <tr> 2147 <td class="memname">#define USART_RX_BUFFER_LEN   64</td> 2148 </tr> 2149 </table> 2150</div><div class="memdoc"> 2151 2152<p class="definition">Definition at line <a class="el" href="a04730_source.html#l00115">115</a> of file <a class="el" href="a04730_source.html">RTE_Device.h</a>.</p> 2153 2154</div> 2155</div> 2156</div><!-- contents --> 2157 2158<hr class="footer"/><address class="footer"><small> 2159© Copyright 2016-2022 NXP. All Rights Reserved. SPDX-License-Identifier: BSD-3-Clause 2160</small></address> 2161</body> 2162</html> 2163
