1<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 2<html xmlns="http://www.w3.org/1999/xhtml"> 3<head> 4<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> 5<meta http-equiv="X-UA-Compatible" content="IE=9"/> 6<meta name="generator" content="Doxygen 1.8.13"/> 7<meta name="viewport" content="width=device-width, initial-scale=1"/> 8<title>ISSDK: boardkit/evk-mimxrt1170/RTE_Device.h Source File</title> 9<link href="tabs.css" rel="stylesheet" type="text/css"/> 10<script type="text/javascript" src="jquery.js"></script> 11<script type="text/javascript" src="dynsections.js"></script> 12<link href="issdk_stylesheet.css" rel="stylesheet" type="text/css" /> 13</head> 14<body> 15<div id="top"><!-- do not remove this div, it is closed by doxygen! --> 16<div id="titlearea"> 17<table cellspacing="0" cellpadding="0"> 18 <tbody> 19 <tr style="height: 56px;"> 20 <td id="projectlogo"><img alt="Logo" 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class="title">RTE_Device.h</div> </div> 49</div><!--header--> 50<div class="contents"> 51<a href="a04727.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span> <span class="comment">/*</span></div><div class="line"><a name="l00002"></a><span class="lineno"> 2</span> <span class="comment"> * Copyright 2018 NXP</span></div><div class="line"><a name="l00003"></a><span class="lineno"> 3</span> <span class="comment"> * All rights reserved.</span></div><div class="line"><a name="l00004"></a><span class="lineno"> 4</span> <span class="comment"> *</span></div><div class="line"><a name="l00005"></a><span class="lineno"> 5</span> <span class="comment"> *</span></div><div class="line"><a name="l00006"></a><span class="lineno"> 6</span> <span class="comment"> * SPDX-License-Identifier: BSD-3-Clause</span></div><div class="line"><a name="l00007"></a><span class="lineno"> 7</span> <span class="comment"> */</span></div><div class="line"><a name="l00008"></a><span class="lineno"> 8</span> </div><div class="line"><a name="l00009"></a><span class="lineno"> 9</span> <span class="preprocessor">#ifndef __RTE_DEVICE_H</span></div><div class="line"><a name="l00010"></a><span class="lineno"> 10</span> <span class="preprocessor">#define __RTE_DEVICE_H</span></div><div class="line"><a name="l00011"></a><span class="lineno"> 11</span> </div><div class="line"><a name="l00012"></a><span class="lineno"> 12</span> <span class="comment">/* Driver name mapping. */</span></div><div class="line"><a name="l00013"></a><span class="lineno"><a class="line" href="a04727.html#aa4264010a207548708e4eb5030b77b42"> 13</a></span> <span class="preprocessor">#define RTE_I2C1 1</span></div><div class="line"><a name="l00014"></a><span class="lineno"><a class="line" href="a04727.html#aac0deee79f0bfe76842a606f89347141"> 14</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_EN 0</span></div><div class="line"><a name="l00015"></a><span class="lineno"><a class="line" href="a04727.html#a6b312911602934f2275e5bfdd964a3c2"> 15</a></span> <span class="preprocessor">#define RTE_I2C2 0</span></div><div class="line"><a name="l00016"></a><span class="lineno"><a class="line" href="a04727.html#aa6833427b8acb64e5b2cdca71adc4731"> 16</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_EN 0</span></div><div class="line"><a name="l00017"></a><span class="lineno"><a class="line" href="a04727.html#a286e0b83a4a1806a5125d1e805afed5e"> 17</a></span> <span class="preprocessor">#define RTE_I2C3 0</span></div><div class="line"><a name="l00018"></a><span class="lineno"><a class="line" href="a04727.html#a7e2203f604dc9bfc5ae76af6364b8e38"> 18</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_EN 0</span></div><div class="line"><a name="l00019"></a><span class="lineno"><a class="line" href="a04727.html#aaefd2724bd50bf611680b12680c5cd47"> 19</a></span> <span class="preprocessor">#define RTE_I2C4 0</span></div><div class="line"><a name="l00020"></a><span class="lineno"><a class="line" href="a04727.html#ad0881b5c0250fd24034d35a0db8e81d6"> 20</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_EN 0</span></div><div class="line"><a name="l00021"></a><span class="lineno"><a class="line" href="a04727.html#af34a2837397fb473c1a29f942886f20a"> 21</a></span> <span class="preprocessor">#define RTE_I2C5 0</span></div><div class="line"><a name="l00022"></a><span class="lineno"><a class="line" href="a04727.html#a11fcca5364c2c59d91dcd1024a3741cd"> 22</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_EN 0</span></div><div class="line"><a name="l00023"></a><span class="lineno"><a class="line" href="a04727.html#a3def854682bc112f022a79dd60ca29d7"> 23</a></span> <span class="preprocessor">#define RTE_I2C6 0</span></div><div class="line"><a name="l00024"></a><span class="lineno"><a class="line" href="a04727.html#a1c6ff3c4d303f391e5ec124aa238c08f"> 24</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_EN 0</span></div><div class="line"><a name="l00025"></a><span class="lineno"> 25</span> </div><div class="line"><a name="l00026"></a><span class="lineno"><a class="line" href="a04727.html#adc244beab1014dda00966fcbbb65578c"> 26</a></span> <span class="preprocessor">#define RTE_SPI1 1</span></div><div class="line"><a name="l00027"></a><span class="lineno"><a class="line" href="a04727.html#aa77f48b8f0f046f17b57ee388ba986c3"> 27</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_EN 0</span></div><div class="line"><a name="l00028"></a><span class="lineno"><a class="line" href="a04727.html#a23c083e17af81df6307b6a09c7b526bd"> 28</a></span> <span class="preprocessor">#define RTE_SPI2 0</span></div><div class="line"><a name="l00029"></a><span class="lineno"><a class="line" href="a04727.html#af6ec6eb776de0e8df30bc2acc19f9221"> 29</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_EN 0</span></div><div class="line"><a name="l00030"></a><span class="lineno"><a class="line" href="a04727.html#aa78a035aaa73a024f3e9ad91e3d28c18"> 30</a></span> <span class="preprocessor">#define RTE_SPI3 0</span></div><div class="line"><a name="l00031"></a><span class="lineno"><a class="line" href="a04727.html#a262ea23b85408aacef35d7dea979abfd"> 31</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_EN 0</span></div><div class="line"><a name="l00032"></a><span class="lineno"><a class="line" href="a04727.html#ab5ea31062ae6c550905351bfac679210"> 32</a></span> <span class="preprocessor">#define RTE_SPI4 0</span></div><div class="line"><a name="l00033"></a><span class="lineno"><a class="line" href="a04727.html#a0a82c99593680766a8a846cd0b1b0169"> 33</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_EN 0</span></div><div class="line"><a name="l00034"></a><span class="lineno"><a class="line" href="a04727.html#a2f9df7e872c3d3fe6576c2c22b77bd81"> 34</a></span> <span class="preprocessor">#define RTE_SPI5 0</span></div><div class="line"><a name="l00035"></a><span class="lineno"><a class="line" href="a04727.html#abfa9a5f5a97226220d95a9ecd3a6b51d"> 35</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_EN 0</span></div><div class="line"><a name="l00036"></a><span class="lineno"><a class="line" href="a04727.html#a4cd9d936e75552e96b2996a3f3c42081"> 36</a></span> <span class="preprocessor">#define RTE_SPI6 0</span></div><div class="line"><a name="l00037"></a><span class="lineno"><a class="line" href="a04727.html#a5f1d64bf1a9b4de1bc0643cbec0eaadb"> 37</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_EN 0</span></div><div class="line"><a name="l00038"></a><span class="lineno"> 38</span> </div><div class="line"><a name="l00039"></a><span class="lineno"><a class="line" href="a04727.html#ae8f0e0260407d14858ce86d2ffb75424"> 39</a></span> <span class="preprocessor">#define RTE_USART1 1</span></div><div class="line"><a name="l00040"></a><span class="lineno"><a class="line" href="a04727.html#a93373776f843912cefd1355e207352e2"> 40</a></span> <span class="preprocessor">#define RTE_USART1_DMA_EN 1</span></div><div class="line"><a name="l00041"></a><span class="lineno"><a class="line" href="a04727.html#af4f4f5e1f698d40d9f7d716257536d42"> 41</a></span> <span class="preprocessor">#define RTE_USART2 0</span></div><div class="line"><a name="l00042"></a><span class="lineno"><a class="line" href="a04727.html#a125adde5b7b5906d3427a57420322722"> 42</a></span> <span class="preprocessor">#define RTE_USART2_DMA_EN 0</span></div><div class="line"><a name="l00043"></a><span class="lineno"><a class="line" href="a04727.html#ae6d7bafeb9d5b445ebadbd0f224bf1a5"> 43</a></span> <span class="preprocessor">#define RTE_USART3 0</span></div><div class="line"><a name="l00044"></a><span class="lineno"><a class="line" href="a04727.html#a64fade6195385d3c00eeb16517725bb5"> 44</a></span> <span class="preprocessor">#define RTE_USART3_DMA_EN 0</span></div><div class="line"><a name="l00045"></a><span class="lineno"><a class="line" href="a04727.html#a3716b269a4311d87ba183b633ebfad07"> 45</a></span> <span class="preprocessor">#define RTE_USART4 0</span></div><div class="line"><a name="l00046"></a><span class="lineno"><a class="line" href="a04727.html#abccb132237192d276dec5fd1235d3124"> 46</a></span> <span class="preprocessor">#define RTE_USART4_DMA_EN 0</span></div><div class="line"><a name="l00047"></a><span class="lineno"><a class="line" href="a04727.html#a5c2c625ac67c8f31440a92490b6d767e"> 47</a></span> <span class="preprocessor">#define RTE_USART5 0</span></div><div class="line"><a name="l00048"></a><span class="lineno"><a class="line" href="a04727.html#aaf003f78b5c4c182d687b220e75e1dbb"> 48</a></span> <span class="preprocessor">#define RTE_USART5_DMA_EN 0</span></div><div class="line"><a name="l00049"></a><span class="lineno"><a class="line" href="a04727.html#af4a7b2970a0f7ac0ee0802298c09848c"> 49</a></span> <span class="preprocessor">#define RTE_USART6 0</span></div><div class="line"><a name="l00050"></a><span class="lineno"><a class="line" href="a04727.html#a46301a9b2d783e5c629b180d8f2344f6"> 50</a></span> <span class="preprocessor">#define RTE_USART6_DMA_EN 0</span></div><div class="line"><a name="l00051"></a><span class="lineno"><a class="line" href="a04727.html#a416995bb1dd6c68b54b5b2dd85f8bc08"> 51</a></span> <span class="preprocessor">#define RTE_USART7 0</span></div><div class="line"><a name="l00052"></a><span class="lineno"><a class="line" href="a04727.html#abde2f17d347b0f02c34cd1875f8bcaba"> 52</a></span> <span class="preprocessor">#define RTE_USART7_DMA_EN 0</span></div><div class="line"><a name="l00053"></a><span class="lineno"><a class="line" href="a04727.html#a40f133071df7d0c18dd19c6f24e45d7a"> 53</a></span> <span class="preprocessor">#define RTE_USART8 0</span></div><div class="line"><a name="l00054"></a><span class="lineno"><a class="line" href="a04727.html#a8f35821f094b48ab18d0ee7eb9049686"> 54</a></span> <span class="preprocessor">#define RTE_USART8_DMA_EN 0</span></div><div class="line"><a name="l00055"></a><span class="lineno"><a class="line" href="a04727.html#a17247f1beecc5e8c6714787be8ec8949"> 55</a></span> <span class="preprocessor">#define RTE_USART9 0</span></div><div class="line"><a name="l00056"></a><span class="lineno"><a class="line" href="a04727.html#a7b2e03393b77773fcaaf18e32eb3104a"> 56</a></span> <span class="preprocessor">#define RTE_USART9_DMA_EN 0</span></div><div class="line"><a name="l00057"></a><span class="lineno"><a class="line" href="a04727.html#a726a89447c240f729e73b7622385d749"> 57</a></span> <span class="preprocessor">#define RTE_USART10 0</span></div><div class="line"><a name="l00058"></a><span class="lineno"><a class="line" href="a04727.html#a5bc420b9d099c3b7361ccb79d698f94d"> 58</a></span> <span class="preprocessor">#define RTE_USART10_DMA_EN 0</span></div><div class="line"><a name="l00059"></a><span class="lineno"><a class="line" href="a04727.html#aaeff216fa2e399a92a774e746ea0c040"> 59</a></span> <span class="preprocessor">#define RTE_USART11 0</span></div><div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="a04727.html#acdd2ab3e608c3f12e233bc2c1f1cd2c6"> 60</a></span> <span class="preprocessor">#define RTE_USART11_DMA_EN 0</span></div><div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="a04727.html#a9661c4bf5c6330fdb494edbdc700a34c"> 61</a></span> <span class="preprocessor">#define RTE_USART12 0</span></div><div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="a04727.html#a0f7079dac6a22e2e95b64448c1f2a808"> 62</a></span> <span class="preprocessor">#define RTE_USART12_DMA_EN 0</span></div><div class="line"><a name="l00063"></a><span class="lineno"> 63</span> </div><div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="comment">/* LPI2C configuration. */</span></div><div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="a04727.html#a922ec75cfe937a214fb6c32fdba48bf6"> 65</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_TX_CH 0</span></div><div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="a04727.html#acf249cbd0797a3dce6412b81aba70ee1"> 66</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C1</span></div><div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="a04727.html#a031737ed543170a29d6ad6eda661c80b"> 67</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="a04727.html#afb1a3403b4c83f7db9bc032bf18c552b"> 68</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="a04727.html#ac612ac434bff32c83c18d02d2c6c1ec6"> 69</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_RX_CH 1</span></div><div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="a04727.html#adedcadc34e22d206d48b9a325155d9b6"> 70</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C1</span></div><div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="a04727.html#ab7f7eefcb6f619df42b0730e84bcf2f3"> 71</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="a04727.html#ae19c26f2205b861f3408141ee8ed7d48"> 72</a></span> <span class="preprocessor">#define RTE_I2C1_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00073"></a><span class="lineno"> 73</span> </div><div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="a04727.html#aaafac93c554b337745d91aeeaa263ee3"> 74</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_TX_CH 2</span></div><div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="a04727.html#a282e3c43099524332084d89c4dc0370a"> 75</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C2</span></div><div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="a04727.html#ac431de1cf16795d33d163d16e67db4ad"> 76</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="a04727.html#ad4f1a37be61763d2594b4f539ae03d44"> 77</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="a04727.html#a762b3880f4254c392f2f152393776679"> 78</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_RX_CH 3</span></div><div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="a04727.html#ad7eb717542257f354c6b41ad348a1404"> 79</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C2</span></div><div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="a04727.html#a042db32af91bc5b35e78566581ed403e"> 80</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="a04727.html#a1ca82c1fea8b1c55875df9cf0e3e4266"> 81</a></span> <span class="preprocessor">#define RTE_I2C2_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00082"></a><span class="lineno"> 82</span> </div><div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="a04727.html#a8d59722d63164553e1aa90f0b5531aa6"> 83</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_TX_CH 4</span></div><div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="a04727.html#a1f3419a15ebd3e7915ab02ddb9d8e57a"> 84</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C3</span></div><div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="a04727.html#a44e673920f642335b203389fc038fa14"> 85</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="a04727.html#a21c43b61ee31798e368937bdbc945eb7"> 86</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="a04727.html#ac78874337ab81de6e42b051fb9dce871"> 87</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_RX_CH 5</span></div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="a04727.html#a0994b2eeb8af41123e69175ac6f9c7b0"> 88</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C3</span></div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="a04727.html#a24a23c8a15b60cf1095ef24463ff5807"> 89</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="a04727.html#acfb03589150d28227ff1dd5393b0b893"> 90</a></span> <span class="preprocessor">#define RTE_I2C3_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00091"></a><span class="lineno"> 91</span> </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="a04727.html#a886533baa3ecbfdc24804b3bbd3c1fa4"> 92</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_TX_CH 6</span></div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="a04727.html#acedae977949138b1e4bf418885238855"> 93</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C4</span></div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="a04727.html#aa525658413a982f217bdb99ad955080d"> 94</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="a04727.html#a1eeb5eb83698e059c5bbc3df7097102d"> 95</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="a04727.html#adb24a07872f830d773e5a761b5b915ea"> 96</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_RX_CH 7</span></div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="a04727.html#aad4b2e8753e39ef0df22e30d47f5af87"> 97</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C4</span></div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="a04727.html#ad22896233f83e8ab47e7102eda51b807"> 98</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="a04727.html#aac8180353fa95d472f154af42998f3ea"> 99</a></span> <span class="preprocessor">#define RTE_I2C4_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00100"></a><span class="lineno"> 100</span> </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="a04727.html#aacc69b6a58c942604d55ab3c66c18331"> 101</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_TX_CH 8</span></div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="a04727.html#aae327bc1bd7606f5ce0e12fa22c0c98f"> 102</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C5</span></div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="a04727.html#adc753a7570b84d60d982dfd4c887628c"> 103</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="a04727.html#a237c977557c35a9f367b3dad28755434"> 104</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="a04727.html#a49d74f3d89f709bcee704ed8bc62a389"> 105</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_RX_CH 9</span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="a04727.html#af9a7eeea936066a06aa12642d206ffe1"> 106</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C5</span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="a04727.html#af9e8145e5e8dd332f85fc24a18cb96a1"> 107</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="a04727.html#afffd01e1818a0941804aa6898e0f3480"> 108</a></span> <span class="preprocessor">#define RTE_I2C5_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00109"></a><span class="lineno"> 109</span> </div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="a04727.html#aa15456a15715d87b5d9fd1663b6def21"> 110</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_TX_CH 10</span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="a04727.html#a3376a9bd3c4accdc4e0d25251960563b"> 111</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C6</span></div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="a04727.html#aba9fea9269019c4c2148393ec799bfb7"> 112</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="a04727.html#a3beb3f0a50107be726578869d167101a"> 113</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="a04727.html#adbde0a01f889e105a70dea33e0b774fe"> 114</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_RX_CH 11</span></div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="a04727.html#a18a0ead9ea40c2c592a5a3a73d4f3916"> 115</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPI2C6</span></div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="a04727.html#a73fd097ff81b41936c278b29bc2ad4eb"> 116</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="a04727.html#afdf4039762fae0cda1db8c9ea184e641"> 117</a></span> <span class="preprocessor">#define RTE_I2C6_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00118"></a><span class="lineno"> 118</span> </div><div class="line"><a name="l00119"></a><span class="lineno"> 119</span> <span class="comment">/* SPI configuration. */</span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="a04727.html#a30ffc6ece84420ad1bb78ad539a527ae"> 120</a></span> <span class="preprocessor">#define RTE_SPI1_PCS_TO_SCK_DELAY 1000</span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="a04727.html#a88c1db58a1c06f875bdec06c74b85072"> 121</a></span> <span class="preprocessor">#define RTE_SPI1_SCK_TO_PSC_DELAY 1000</span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="a04727.html#a951ee008b6f3fccf7c09fb32ef53b288"> 122</a></span> <span class="preprocessor">#define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000</span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="a04727.html#a0e587c674c92f4898da5f4a2dd7da875"> 123</a></span> <span class="preprocessor">#define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)</span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="a04727.html#a5b23957d812a8a11c221bee23ddbe2a7"> 124</a></span> <span class="preprocessor">#define RTE_SPI1_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0)</span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="a04727.html#af7837804201c3faa8cb122bafb79b78a"> 125</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_TX_CH 0</span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="a04727.html#adacfa67a7428af81b9a41471e1c52a15"> 126</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI1Tx</span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="a04727.html#a808f6eb3a927615c6881d185981238c8"> 127</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="a04727.html#a2510e3e47782aa110b9863228c6b20ff"> 128</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="a04727.html#a237cd1f72122246b424ced52d44d7374"> 129</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_RX_CH 1</span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="a04727.html#a1675b80e211aeb65f52be311273d1054"> 130</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI1Rx</span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="a04727.html#a092a5b393859e6a07fc97a666e3841f9"> 131</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="a04727.html#a08060b8c17ac92da6cde2af7d67ee095"> 132</a></span> <span class="preprocessor">#define RTE_SPI1_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00133"></a><span class="lineno"> 133</span> </div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="a04727.html#ae3c6c661ee5134156e7083458fa9d0d0"> 134</a></span> <span class="preprocessor">#define RTE_SPI2_PCS_TO_SCK_DELAY 1000</span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="a04727.html#a5f946c38b63485806d78f455fb199c36"> 135</a></span> <span class="preprocessor">#define RTE_SPI2_SCK_TO_PSC_DELAY 1000</span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="a04727.html#a99923674038030fbcc6c203a048e7092"> 136</a></span> <span class="preprocessor">#define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000</span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="a04727.html#aaf87c891b68f466cded78517bda33f66"> 137</a></span> <span class="preprocessor">#define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)</span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="a04727.html#a50c8dea7ad8a4df3477cc5ec811a7726"> 138</a></span> <span class="preprocessor">#define RTE_SPI2_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0)</span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="a04727.html#a2f55409f83ccf9410d19a06c89592cf7"> 139</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_TX_CH 2</span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="a04727.html#a18b7f6d5915fbcbed92062f953c23b73"> 140</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI2Tx</span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="a04727.html#a33414279775ff91c959e0d6238f6f5a8"> 141</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="a04727.html#ad2c8040af8a79e4d3817c130ac28df6d"> 142</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="a04727.html#a2e9a89fc7b4cd0e7b9ddbd9dc747ea84"> 143</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_RX_CH 3</span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="a04727.html#a819c248900eebba240a37d7c57ab5408"> 144</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI2Tx</span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="a04727.html#a83c234032df3316eea62c35db921df98"> 145</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="a04727.html#ae14cfbbd7990b4e16da76447fd0f71d0"> 146</a></span> <span class="preprocessor">#define RTE_SPI2_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00147"></a><span class="lineno"> 147</span> </div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="a04727.html#aa73000740183c3947717fa583d165815"> 148</a></span> <span class="preprocessor">#define RTE_SPI3_PCS_TO_SCK_DELAY 1000</span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="a04727.html#a0e7623e6ba7a9f5e22314ffd3cedba06"> 149</a></span> <span class="preprocessor">#define RTE_SPI3_SCK_TO_PSC_DELAY 1000</span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="a04727.html#aea2bec62dec8ae43dd4866d04a7a210f"> 150</a></span> <span class="preprocessor">#define RTE_SPI3_BETWEEN_TRANSFER_DELAY 1000</span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="a04727.html#ae246a17a5a03704c5f4d44cd40df50d7"> 151</a></span> <span class="preprocessor">#define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)</span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="a04727.html#a63dc1c7865592a39f5bf323f14cbcf9d"> 152</a></span> <span class="preprocessor">#define RTE_SPI3_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0)</span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="a04727.html#aede43b66781471d6f7824e1d8a5d678a"> 153</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_TX_CH 4</span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="a04727.html#a7a1d1794b26a340e85bd3569d80b1470"> 154</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI3Tx</span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="a04727.html#a957637aad66f6d5deed94db4d18e3ca8"> 155</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="a04727.html#a9237e29a834083e9cff82ba51800ec0d"> 156</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="a04727.html#adb5a87ba91d16c71a803610ffbf40c13"> 157</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_RX_CH 5</span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="a04727.html#a1a3261f383900579c450e714a8c9c4e9"> 158</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI3Rx</span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="a04727.html#ae8eb8e1701ada3c43faacf46f163c1f5"> 159</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="a04727.html#aad946150307e0a2d3f1e4e030550dc68"> 160</a></span> <span class="preprocessor">#define RTE_SPI3_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00161"></a><span class="lineno"> 161</span> </div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="a04727.html#a902fd47282cf03f90965dd9c28c5fbad"> 162</a></span> <span class="preprocessor">#define RTE_SPI4_PCS_TO_SCK_DELAY 1000</span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="a04727.html#addde6066970e78ac95c304f81e3d4224"> 163</a></span> <span class="preprocessor">#define RTE_SPI4_SCK_TO_PSC_DELAY 1000</span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="a04727.html#aaf2ab4cef9c8fd5fd873954d6312630e"> 164</a></span> <span class="preprocessor">#define RTE_SPI4_BETWEEN_TRANSFER_DELAY 1000</span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="a04727.html#a14b93ec25540b16bf3adac9417b18d98"> 165</a></span> <span class="preprocessor">#define RTE_SPI4_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)</span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="a04727.html#a1ffa2d5a7b8e5ad0b1b5bf96270e9427"> 166</a></span> <span class="preprocessor">#define RTE_SPI4_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0)</span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="a04727.html#a956855c142636770f6a7debe2aa013e6"> 167</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_TX_CH 6</span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="a04727.html#a26a43c2ab8b1d1c288cb34ecd416f7c0"> 168</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI4Tx</span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="a04727.html#ae3eaa3789e307502d95d5bcb22557f21"> 169</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="a04727.html#aa3ec0db7635e3be6822ac3d6b522aed9"> 170</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="a04727.html#a7dd6e0050f362bd1bfd3a07a7e86b57a"> 171</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_RX_CH 7</span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="a04727.html#ada325d25817cdcfd6760ec56d55ebd9e"> 172</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI4Rx</span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="a04727.html#a478cb5cd7ebeaf47470f623dac24f71b"> 173</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="a04727.html#a968c662515159592bfb826495d2d3c5d"> 174</a></span> <span class="preprocessor">#define RTE_SPI4_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00175"></a><span class="lineno"> 175</span> </div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="a04727.html#a37d29d6dcbb2e3de3425057411bb99c4"> 176</a></span> <span class="preprocessor">#define RTE_SPI5_PCS_TO_SCK_DELAY 1000</span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="a04727.html#ab940dc32781a18c0af66e85d7afccd8f"> 177</a></span> <span class="preprocessor">#define RTE_SPI5_SCK_TO_PSC_DELAY 1000</span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="a04727.html#ad61947178295915a471db020e41d1811"> 178</a></span> <span class="preprocessor">#define RTE_SPI5_BETWEEN_TRANSFER_DELAY 1000</span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="a04727.html#abf2aea43f4b4b480fadb99bcc4e22de6"> 179</a></span> <span class="preprocessor">#define RTE_SPI5_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)</span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="a04727.html#a87e3d2b881cd6ffc6d436cc4f6cbbf7b"> 180</a></span> <span class="preprocessor">#define RTE_SPI5_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0)</span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="a04727.html#a1041985ad6bcd91b3bb3cccd837aaaae"> 181</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_TX_CH 8</span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="a04727.html#a0ecaf278dd6946934ec7d5a6c4b18a7b"> 182</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI5Tx</span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="a04727.html#a0e5b5dbcfb4dde49887559b4f303a0b6"> 183</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="a04727.html#a8d306bb116961953c118532b719cc5a9"> 184</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="a04727.html#a6aa0bdc35c2121855560c7a6455dbddf"> 185</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_RX_CH 9</span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="a04727.html#aa17446d7236876fb326323f1222fcb8d"> 186</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI5Rx</span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="a04727.html#a7661d8743ca1a17dda22cb8e0e0f68bb"> 187</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="a04727.html#ab382c8c01e5955ace12e26b487622a05"> 188</a></span> <span class="preprocessor">#define RTE_SPI5_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00189"></a><span class="lineno"> 189</span> </div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="a04727.html#a2f70806a3b60d1adc11f421229f14461"> 190</a></span> <span class="preprocessor">#define RTE_SPI6_PCS_TO_SCK_DELAY 1000</span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="a04727.html#aa477179de6b38381621f7479ddc3b3dd"> 191</a></span> <span class="preprocessor">#define RTE_SPI6_SCK_TO_PSC_DELAY 1000</span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="a04727.html#a2a8fa79cc3fd9b4b0f04cbf226410c4b"> 192</a></span> <span class="preprocessor">#define RTE_SPI6_BETWEEN_TRANSFER_DELAY 1000</span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="a04727.html#a624b496f8c43b43734656fc972eb44d0"> 193</a></span> <span class="preprocessor">#define RTE_SPI6_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)</span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="a04727.html#a7a2616e6e511c3fd735af6ffb2efba85"> 194</a></span> <span class="preprocessor">#define RTE_SPI6_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0)</span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="a04727.html#a500837b546f2c5c5d340c70b8316cd75"> 195</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_TX_CH 10</span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="a04727.html#ada1fda3c07011611352d8a49a7bf4d3f"> 196</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI6Tx</span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="a04727.html#a45d09e085504ada169bc3b97358b4c04"> 197</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="a04727.html#a562a146c7a128d2087eb47d8e19a2b2a"> 198</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="a04727.html#acdb61b6c3e30ad9a0877b9931b6d6904"> 199</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_RX_CH 11</span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="a04727.html#aa4a398c69b8dac0ebc7d7a9f40b7609f"> 200</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPSPI6Rx</span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="a04727.html#a113aed2c7ed2624fab109cf0748ac052"> 201</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="a04727.html#acab2a9b0b3033d3425ac33918ec17c03"> 202</a></span> <span class="preprocessor">#define RTE_SPI6_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00203"></a><span class="lineno"> 203</span> </div><div class="line"><a name="l00204"></a><span class="lineno"> 204</span> <span class="comment">/* UART configuration. */</span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="a04727.html#a272ab6f694a794b54d6d0bacf4b030c3"> 205</a></span> <span class="preprocessor">#define RTE_USART1_DMA_TX_CH 0</span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="a04727.html#ab360b9072ab5034fe19c591b11ddaa4f"> 206</a></span> <span class="preprocessor">#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Tx</span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="a04727.html#a28ef4acc4180de985e24a0bb392e42c8"> 207</a></span> <span class="preprocessor">#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="a04727.html#a7804081da977b330578221c5ce5ba89e"> 208</a></span> <span class="preprocessor">#define RTE_USART1_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="a04727.html#af78c326f4aa3f8ba10614f88755ac30e"> 209</a></span> <span class="preprocessor">#define RTE_USART1_DMA_RX_CH 1</span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="a04727.html#a2e6bd424c90e5734c38eb4f198ed0347"> 210</a></span> <span class="preprocessor">#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART1Rx</span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="a04727.html#ad71e62366aea28e6c003f082a3ff5227"> 211</a></span> <span class="preprocessor">#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="a04727.html#ab58d0f95baca5b61fd1183daed257004"> 212</a></span> <span class="preprocessor">#define RTE_USART1_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00213"></a><span class="lineno"> 213</span> </div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="a04727.html#a4da147c7ce755201a079c412c098128f"> 214</a></span> <span class="preprocessor">#define RTE_USART2_DMA_TX_CH 2</span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="a04727.html#a1921b3ed005879e26052e379f23dbcb2"> 215</a></span> <span class="preprocessor">#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Tx</span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="a04727.html#a35e29209a15939cab26f74b2d1f6daf9"> 216</a></span> <span class="preprocessor">#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="a04727.html#a667adae4bda8ac302bcc85d4a7a004cd"> 217</a></span> <span class="preprocessor">#define RTE_USART2_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="a04727.html#aaf5d293f3353d103aa7fc672a3cf456d"> 218</a></span> <span class="preprocessor">#define RTE_USART2_DMA_RX_CH 3</span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="a04727.html#ad8969d48f9a854dcd661e60ace8f2eac"> 219</a></span> <span class="preprocessor">#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART2Rx</span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="a04727.html#a4e45bca95b4f0c419b7aa5b27655e0f8"> 220</a></span> <span class="preprocessor">#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="a04727.html#a54af00b2f29f1e9aeb10e1a59a4cde3d"> 221</a></span> <span class="preprocessor">#define RTE_USART2_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00222"></a><span class="lineno"> 222</span> </div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="a04727.html#a371552d64a4c36aa553a256ab52c4737"> 223</a></span> <span class="preprocessor">#define RTE_USART3_DMA_TX_CH 4</span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="a04727.html#a298c8ca62c3080284bf1c1ddc9e52c74"> 224</a></span> <span class="preprocessor">#define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Tx</span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="a04727.html#a05781de3d61d146f982ffb787d36f3fe"> 225</a></span> <span class="preprocessor">#define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="a04727.html#a230981b96cecea4add332ecd40533454"> 226</a></span> <span class="preprocessor">#define RTE_USART3_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="a04727.html#ab09d3b40ddde8be68179be6d46400d45"> 227</a></span> <span class="preprocessor">#define RTE_USART3_DMA_RX_CH 5</span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="a04727.html#ab310379c65913c108e059c4e317ce096"> 228</a></span> <span class="preprocessor">#define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART3Rx</span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="a04727.html#a7ce8b3cab8b376e492e0599890bb4ad0"> 229</a></span> <span class="preprocessor">#define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="a04727.html#ae05b2c8a2baaa32c10d0af3457ce2e28"> 230</a></span> <span class="preprocessor">#define RTE_USART3_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00231"></a><span class="lineno"> 231</span> </div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="a04727.html#a583406cbb43d2e24e0cf8cafdb45d7d9"> 232</a></span> <span class="preprocessor">#define RTE_USART4_DMA_TX_CH 6</span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="a04727.html#a2b6f4b82acc33b81f3637afc63419169"> 233</a></span> <span class="preprocessor">#define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Tx</span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="a04727.html#a23d221d38fab3da9b28d9de859af9f48"> 234</a></span> <span class="preprocessor">#define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="a04727.html#ac4abea21e4bfc3d03539f739892b0e7f"> 235</a></span> <span class="preprocessor">#define RTE_USART4_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="a04727.html#ae3aa08740bc1278f56cb25413751053b"> 236</a></span> <span class="preprocessor">#define RTE_USART4_DMA_RX_CH 7</span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="a04727.html#a2d133b10d9af3b93828d264638c01d69"> 237</a></span> <span class="preprocessor">#define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART4Rx</span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="a04727.html#a0af7a32050ae6ea721dc3bfe51cec886"> 238</a></span> <span class="preprocessor">#define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="a04727.html#a84ae4f174efa1b7417b5a35d9b9e3de9"> 239</a></span> <span class="preprocessor">#define RTE_USART4_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00240"></a><span class="lineno"> 240</span> </div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="a04727.html#a5fc281007f625bf44a5b16d7f97c9f7b"> 241</a></span> <span class="preprocessor">#define RTE_USART5_DMA_TX_CH 8</span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="a04727.html#a3f34578afbd133748801bbb852f1cc46"> 242</a></span> <span class="preprocessor">#define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Tx</span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="a04727.html#ae6732d5a38b93890d64314a0837a1d34"> 243</a></span> <span class="preprocessor">#define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="a04727.html#a530f52cd5d979b98f959163c96e4413b"> 244</a></span> <span class="preprocessor">#define RTE_USART5_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="a04727.html#af563379f0b22b56089642e1452293b94"> 245</a></span> <span class="preprocessor">#define RTE_USART5_DMA_RX_CH 9</span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="a04727.html#a4dc20b4bfb5766bac0d6de434bda7fd8"> 246</a></span> <span class="preprocessor">#define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART5Rx</span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="a04727.html#a7a8f2581e0cbec8210edb6f89f7b187c"> 247</a></span> <span class="preprocessor">#define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="a04727.html#a665e630b27a6713ff3055c9893403090"> 248</a></span> <span class="preprocessor">#define RTE_USART5_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00249"></a><span class="lineno"> 249</span> </div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="a04727.html#a830ccf4153d422fc98971a8fc2d1ecba"> 250</a></span> <span class="preprocessor">#define RTE_USART6_DMA_TX_CH 10</span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="a04727.html#ac1692d643111d558f2df528205966f28"> 251</a></span> <span class="preprocessor">#define RTE_USART6_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Tx</span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="a04727.html#af6111a4ca33179e72211e0a267f1b40e"> 252</a></span> <span class="preprocessor">#define RTE_USART6_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="a04727.html#aa50f707f6ba72c2c400faa7e2c9b8b5f"> 253</a></span> <span class="preprocessor">#define RTE_USART6_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="a04727.html#a74e96a5225571536daf6ce2058f2ca11"> 254</a></span> <span class="preprocessor">#define RTE_USART6_DMA_RX_CH 11</span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="a04727.html#ad55c040ec06f230089b7f190f5eb5589"> 255</a></span> <span class="preprocessor">#define RTE_USART6_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART6Rx</span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="a04727.html#aeb3cf21340277e8390db8a14d63ee5d5"> 256</a></span> <span class="preprocessor">#define RTE_USART6_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="a04727.html#a5937989b65e91558a7ecd473a511e5e6"> 257</a></span> <span class="preprocessor">#define RTE_USART6_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00258"></a><span class="lineno"> 258</span> </div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="a04727.html#a4f3d104ac7e9a07019d58c26bd53e9a1"> 259</a></span> <span class="preprocessor">#define RTE_USART7_DMA_TX_CH 12</span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="a04727.html#a9105787bef980157f54fc11f21ee84b5"> 260</a></span> <span class="preprocessor">#define RTE_USART7_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Tx</span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="a04727.html#a8b9a5d583e90a47e3f535b114da2512f"> 261</a></span> <span class="preprocessor">#define RTE_USART7_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="a04727.html#a9417cafd6534bd6b4be87b6bea6ac16c"> 262</a></span> <span class="preprocessor">#define RTE_USART7_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="a04727.html#a18ee2a3fba2891c00a7a2d126a81b91f"> 263</a></span> <span class="preprocessor">#define RTE_USART7_DMA_RX_CH 13</span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="a04727.html#a5a048d82fae4604ff6183679a90197c3"> 264</a></span> <span class="preprocessor">#define RTE_USART7_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART7Rx</span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="a04727.html#a82d952d94e0f421c0928b7bb9271650f"> 265</a></span> <span class="preprocessor">#define RTE_USART7_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="a04727.html#aff3f3b4435760ac40c7d6a8837642f76"> 266</a></span> <span class="preprocessor">#define RTE_USART7_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00267"></a><span class="lineno"> 267</span> </div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="a04727.html#abcc6c1f63b1f4885829e6b98f2f99230"> 268</a></span> <span class="preprocessor">#define RTE_USART8_DMA_TX_CH 14</span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="a04727.html#a32cb9cebe1faa5aaa4103e3bbc5053e8"> 269</a></span> <span class="preprocessor">#define RTE_USART8_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Tx</span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="a04727.html#a8819d5c827bdd7fbdc30d885547cbf0d"> 270</a></span> <span class="preprocessor">#define RTE_USART8_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="a04727.html#a0bba1923dd63a116b3c4ef8fcebe26c7"> 271</a></span> <span class="preprocessor">#define RTE_USART8_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="a04727.html#a2b464e7a19d4ae0e950dac79aff6adbc"> 272</a></span> <span class="preprocessor">#define RTE_USART8_DMA_RX_CH 15</span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="a04727.html#a5c16789d134aa6368dbe2d7a7110211c"> 273</a></span> <span class="preprocessor">#define RTE_USART8_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART8Rx</span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="a04727.html#a155ae73ee7cdaff86bb2ddefa2873dcb"> 274</a></span> <span class="preprocessor">#define RTE_USART8_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="a04727.html#a35b22acc74d0ae6d339a14fdebc5e4d5"> 275</a></span> <span class="preprocessor">#define RTE_USART8_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00276"></a><span class="lineno"> 276</span> </div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="a04727.html#a3fcb81ca746a43a1ca1437f697eb27fc"> 277</a></span> <span class="preprocessor">#define RTE_USART9_DMA_TX_CH 16</span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="a04727.html#a97dd4ab8c461b660212839a0a83a8854"> 278</a></span> <span class="preprocessor">#define RTE_USART9_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART9Tx</span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="a04727.html#a9501ce390ace1147e1e2b64f2a7e16c7"> 279</a></span> <span class="preprocessor">#define RTE_USART9_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="a04727.html#a2d6c62e2fc4b1e0a71103c653cbd52cd"> 280</a></span> <span class="preprocessor">#define RTE_USART9_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="a04727.html#ac9a2bb67aec256c83d9fe501eb43c43b"> 281</a></span> <span class="preprocessor">#define RTE_USART9_DMA_RX_CH 17</span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="a04727.html#ad17f943b2877b59baa700768f299ac1f"> 282</a></span> <span class="preprocessor">#define RTE_USART9_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART9Rx</span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="a04727.html#a4cf1f6bbfe5beb45a546c685a7832da9"> 283</a></span> <span class="preprocessor">#define RTE_USART9_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="a04727.html#a3774cca453a9602c146e45d5f3f15744"> 284</a></span> <span class="preprocessor">#define RTE_USART9_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00285"></a><span class="lineno"> 285</span> </div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="a04727.html#ac1c4424e09f62bdd3cf7bbb029140c17"> 286</a></span> <span class="preprocessor">#define RTE_USART10_DMA_TX_CH 18</span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="a04727.html#a9025a7019ac18036afbe7bb6e731e34a"> 287</a></span> <span class="preprocessor">#define RTE_USART10_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART10Tx</span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="a04727.html#a8b82b82de6825554dbc282331be2e14c"> 288</a></span> <span class="preprocessor">#define RTE_USART10_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="a04727.html#ac89cc69566cd1ccfbb73b08ebfaf599b"> 289</a></span> <span class="preprocessor">#define RTE_USART10_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="a04727.html#aa4a9ae606f683f73cbbd54d10f3ec658"> 290</a></span> <span class="preprocessor">#define RTE_USART10_DMA_RX_CH 19</span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="a04727.html#a146ac727fae8b5c5ad182a2790d15ea8"> 291</a></span> <span class="preprocessor">#define RTE_USART10_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART10Rx</span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="a04727.html#ac9255f1d8fa4c2b82923fb2cbb5ef01d"> 292</a></span> <span class="preprocessor">#define RTE_USART10_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="a04727.html#ae022eaa77af7a1693a272196ad51950c"> 293</a></span> <span class="preprocessor">#define RTE_USART10_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00294"></a><span class="lineno"> 294</span> </div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="a04727.html#afef0e458bbb3edb75f54cbc2da697dbc"> 295</a></span> <span class="preprocessor">#define RTE_USART11_DMA_TX_CH 20</span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="a04727.html#aae9a792f4082ddbbcaae5b6f848e6eb1"> 296</a></span> <span class="preprocessor">#define RTE_USART11_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART11Tx</span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="a04727.html#a852a29cb0416d2e37e58edc7b1fb3496"> 297</a></span> <span class="preprocessor">#define RTE_USART11_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="a04727.html#afaf6ab6ee029bf827b5cab368b49ee37"> 298</a></span> <span class="preprocessor">#define RTE_USART11_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="a04727.html#a4bfe881bb9c8462aad1bc3f06d0dfc83"> 299</a></span> <span class="preprocessor">#define RTE_USART11_DMA_RX_CH 21</span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="a04727.html#ad555cdd0b0ec893ba0cea60976ddcf4b"> 300</a></span> <span class="preprocessor">#define RTE_USART11_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART11Rx</span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="a04727.html#ab788dfbb8d8dcbda921836ce50b5dde2"> 301</a></span> <span class="preprocessor">#define RTE_USART11_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="a04727.html#a654d5afcc2b4c510fa9675540c63fb34"> 302</a></span> <span class="preprocessor">#define RTE_USART11_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00303"></a><span class="lineno"> 303</span> </div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="a04727.html#aed212423cf63e159f699aea7e37ce39f"> 304</a></span> <span class="preprocessor">#define RTE_USART12_DMA_TX_CH 22</span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="a04727.html#ab12cbeb7458aaf1a1957e008c47a0ab8"> 305</a></span> <span class="preprocessor">#define RTE_USART12_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART12Tx</span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="a04727.html#ac276d7c1ce31e2bede292792eaaebc1e"> 306</a></span> <span class="preprocessor">#define RTE_USART12_DMA_TX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="a04727.html#ac85dd474fc3f113f46d7e2bae0409164"> 307</a></span> <span class="preprocessor">#define RTE_USART12_DMA_TX_DMA_BASE DMA0</span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="a04727.html#aae9c7555e205d5ed4749041941268e81"> 308</a></span> <span class="preprocessor">#define RTE_USART12_DMA_RX_CH 23</span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="a04727.html#a8507e55c77a9739c3d396b4fb8f8d818"> 309</a></span> <span class="preprocessor">#define RTE_USART12_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMuxLPUART12Rx</span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="a04727.html#a029a7ee79606fd5cbe7a023ccb95cf62"> 310</a></span> <span class="preprocessor">#define RTE_USART12_DMA_RX_DMAMUX_BASE DMAMUX0</span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="a04727.html#ac4d11009e0e0d76ac14cc3be97f1d920"> 311</a></span> <span class="preprocessor">#define RTE_USART12_DMA_RX_DMA_BASE DMA0</span></div><div class="line"><a name="l00312"></a><span class="lineno"> 312</span> </div><div class="line"><a name="l00313"></a><span class="lineno"> 313</span> <span class="preprocessor">#endif </span><span class="comment">/* __RTE_DEVICE_H */</span><span class="preprocessor"></span></div></div><!-- fragment --></div><!-- contents --> 52 53<hr class="footer"/><address class="footer"><small> 54© Copyright 2016-2022 NXP. All Rights Reserved. SPDX-License-Identifier: BSD-3-Clause 55</small></address> 56</body> 57</html> 58
