1<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 2<html xmlns="http://www.w3.org/1999/xhtml"> 3<head> 4<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> 5<meta http-equiv="X-UA-Compatible" content="IE=9"/> 6<meta name="generator" content="Doxygen 1.8.13"/> 7<meta name="viewport" content="width=device-width, initial-scale=1"/> 8<title>ISSDK: boardkit/evk-mimxrt1170/RTE_Device.h File Reference</title> 9<link href="tabs.css" rel="stylesheet" type="text/css"/> 10<script type="text/javascript" src="jquery.js"></script> 11<script type="text/javascript" src="dynsections.js"></script> 12<link href="issdk_stylesheet.css" rel="stylesheet" type="text/css" /> 13</head> 14<body> 15<div id="top"><!-- do not remove this div, it is closed by doxygen! --> 16<div id="titlearea"> 17<table cellspacing="0" cellpadding="0"> 18 <tbody> 19 <tr style="height: 56px;"> 20 <td id="projectlogo"><img alt="Logo" src="nxp_logo_small.png"/></td> 21 <td id="projectalign" style="padding-left: 0.5em;"> 22 <div id="projectname">ISSDK 23  <span id="projectnumber">1.8</span> 24 </div> 25 <div id="projectbrief">IoT Sensing Software Development Kit</div> 26 </td> 27 </tr> 28 </tbody> 29</table> 30</div> 31<!-- end header part --> 32<!-- Generated by Doxygen 1.8.13 --> 33<script type="text/javascript" src="menudata.js"></script> 34<script type="text/javascript" src="menu.js"></script> 35<script type="text/javascript"> 36$(function() { 37 initMenu('',false,false,'search.php','Search'); 38}); 39</script> 40<div id="main-nav"></div> 41<div id="nav-path" class="navpath"> 42 <ul> 43<li class="navelem"><a class="el" href="dir_6994211064bad48d3d63a6227f5100d6.html">boardkit</a></li><li class="navelem"><a class="el" href="dir_ca828fa6c7b8f5e58ad88cad4394b679.html">evk-mimxrt1170</a></li> </ul> 44</div> 45</div><!-- top --> 46<div class="header"> 47 <div class="summary"> 48<a href="#define-members">Macros</a> </div> 49 <div class="headertitle"> 50<div class="title">RTE_Device.h File Reference</div> </div> 51</div><!--header--> 52<div class="contents"> 53<div class="textblock"><div class="dynheader"> 54This graph shows which files directly or indirectly include this file:</div> 55<div class="dyncontent"> 56<div class="center"><img src="a04729.png" border="0" usemap="#boardkit_2evk-mimxrt1170_2_r_t_e___device_8hdep" alt=""/></div> 57<map name="boardkit_2evk-mimxrt1170_2_r_t_e___device_8hdep" id="boardkit_2evk-mimxrt1170_2_r_t_e___device_8hdep"> 58<area shape="rect" id="node2" href="a00752.html" title="The evkmimxrt1170.h file defines GPIO pin mappings for evkmimxrt1170 board. " alt="" coords="5,95,168,136"/> 59</map> 60</div> 61</div> 62<p><a href="a04727_source.html">Go to the source code of this file.</a></p> 63<table class="memberdecls"> 64<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> 65Macros</h2></td></tr> 66<tr class="memitem:aa4264010a207548708e4eb5030b77b42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa4264010a207548708e4eb5030b77b42">RTE_I2C1</a>   1</td></tr> 67<tr class="separator:aa4264010a207548708e4eb5030b77b42"><td class="memSeparator" colspan="2"> </td></tr> 68<tr class="memitem:aac0deee79f0bfe76842a606f89347141"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aac0deee79f0bfe76842a606f89347141">RTE_I2C1_DMA_EN</a>   0</td></tr> 69<tr class="separator:aac0deee79f0bfe76842a606f89347141"><td class="memSeparator" colspan="2"> </td></tr> 70<tr class="memitem:a6b312911602934f2275e5bfdd964a3c2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a6b312911602934f2275e5bfdd964a3c2">RTE_I2C2</a>   0</td></tr> 71<tr class="separator:a6b312911602934f2275e5bfdd964a3c2"><td class="memSeparator" colspan="2"> </td></tr> 72<tr class="memitem:aa6833427b8acb64e5b2cdca71adc4731"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa6833427b8acb64e5b2cdca71adc4731">RTE_I2C2_DMA_EN</a>   0</td></tr> 73<tr class="separator:aa6833427b8acb64e5b2cdca71adc4731"><td class="memSeparator" colspan="2"> </td></tr> 74<tr class="memitem:a286e0b83a4a1806a5125d1e805afed5e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a286e0b83a4a1806a5125d1e805afed5e">RTE_I2C3</a>   0</td></tr> 75<tr class="separator:a286e0b83a4a1806a5125d1e805afed5e"><td class="memSeparator" colspan="2"> </td></tr> 76<tr class="memitem:a7e2203f604dc9bfc5ae76af6364b8e38"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7e2203f604dc9bfc5ae76af6364b8e38">RTE_I2C3_DMA_EN</a>   0</td></tr> 77<tr class="separator:a7e2203f604dc9bfc5ae76af6364b8e38"><td class="memSeparator" colspan="2"> </td></tr> 78<tr class="memitem:aaefd2724bd50bf611680b12680c5cd47"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aaefd2724bd50bf611680b12680c5cd47">RTE_I2C4</a>   0</td></tr> 79<tr class="separator:aaefd2724bd50bf611680b12680c5cd47"><td class="memSeparator" colspan="2"> </td></tr> 80<tr class="memitem:ad0881b5c0250fd24034d35a0db8e81d6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad0881b5c0250fd24034d35a0db8e81d6">RTE_I2C4_DMA_EN</a>   0</td></tr> 81<tr class="separator:ad0881b5c0250fd24034d35a0db8e81d6"><td class="memSeparator" colspan="2"> </td></tr> 82<tr class="memitem:af34a2837397fb473c1a29f942886f20a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af34a2837397fb473c1a29f942886f20a">RTE_I2C5</a>   0</td></tr> 83<tr class="separator:af34a2837397fb473c1a29f942886f20a"><td class="memSeparator" colspan="2"> </td></tr> 84<tr class="memitem:a11fcca5364c2c59d91dcd1024a3741cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a11fcca5364c2c59d91dcd1024a3741cd">RTE_I2C5_DMA_EN</a>   0</td></tr> 85<tr class="separator:a11fcca5364c2c59d91dcd1024a3741cd"><td class="memSeparator" colspan="2"> </td></tr> 86<tr class="memitem:a3def854682bc112f022a79dd60ca29d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a3def854682bc112f022a79dd60ca29d7">RTE_I2C6</a>   0</td></tr> 87<tr class="separator:a3def854682bc112f022a79dd60ca29d7"><td class="memSeparator" colspan="2"> </td></tr> 88<tr class="memitem:a1c6ff3c4d303f391e5ec124aa238c08f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1c6ff3c4d303f391e5ec124aa238c08f">RTE_I2C6_DMA_EN</a>   0</td></tr> 89<tr class="separator:a1c6ff3c4d303f391e5ec124aa238c08f"><td class="memSeparator" colspan="2"> </td></tr> 90<tr class="memitem:adc244beab1014dda00966fcbbb65578c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#adc244beab1014dda00966fcbbb65578c">RTE_SPI1</a>   1</td></tr> 91<tr class="separator:adc244beab1014dda00966fcbbb65578c"><td class="memSeparator" colspan="2"> </td></tr> 92<tr class="memitem:aa77f48b8f0f046f17b57ee388ba986c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa77f48b8f0f046f17b57ee388ba986c3">RTE_SPI1_DMA_EN</a>   0</td></tr> 93<tr class="separator:aa77f48b8f0f046f17b57ee388ba986c3"><td class="memSeparator" colspan="2"> </td></tr> 94<tr class="memitem:a23c083e17af81df6307b6a09c7b526bd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a23c083e17af81df6307b6a09c7b526bd">RTE_SPI2</a>   0</td></tr> 95<tr class="separator:a23c083e17af81df6307b6a09c7b526bd"><td class="memSeparator" colspan="2"> </td></tr> 96<tr class="memitem:af6ec6eb776de0e8df30bc2acc19f9221"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af6ec6eb776de0e8df30bc2acc19f9221">RTE_SPI2_DMA_EN</a>   0</td></tr> 97<tr class="separator:af6ec6eb776de0e8df30bc2acc19f9221"><td class="memSeparator" colspan="2"> </td></tr> 98<tr class="memitem:aa78a035aaa73a024f3e9ad91e3d28c18"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa78a035aaa73a024f3e9ad91e3d28c18">RTE_SPI3</a>   0</td></tr> 99<tr class="separator:aa78a035aaa73a024f3e9ad91e3d28c18"><td class="memSeparator" colspan="2"> </td></tr> 100<tr class="memitem:a262ea23b85408aacef35d7dea979abfd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a262ea23b85408aacef35d7dea979abfd">RTE_SPI3_DMA_EN</a>   0</td></tr> 101<tr class="separator:a262ea23b85408aacef35d7dea979abfd"><td class="memSeparator" colspan="2"> </td></tr> 102<tr class="memitem:ab5ea31062ae6c550905351bfac679210"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab5ea31062ae6c550905351bfac679210">RTE_SPI4</a>   0</td></tr> 103<tr class="separator:ab5ea31062ae6c550905351bfac679210"><td class="memSeparator" colspan="2"> </td></tr> 104<tr class="memitem:a0a82c99593680766a8a846cd0b1b0169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0a82c99593680766a8a846cd0b1b0169">RTE_SPI4_DMA_EN</a>   0</td></tr> 105<tr class="separator:a0a82c99593680766a8a846cd0b1b0169"><td class="memSeparator" colspan="2"> </td></tr> 106<tr class="memitem:a2f9df7e872c3d3fe6576c2c22b77bd81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2f9df7e872c3d3fe6576c2c22b77bd81">RTE_SPI5</a>   0</td></tr> 107<tr class="separator:a2f9df7e872c3d3fe6576c2c22b77bd81"><td class="memSeparator" colspan="2"> </td></tr> 108<tr class="memitem:abfa9a5f5a97226220d95a9ecd3a6b51d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#abfa9a5f5a97226220d95a9ecd3a6b51d">RTE_SPI5_DMA_EN</a>   0</td></tr> 109<tr class="separator:abfa9a5f5a97226220d95a9ecd3a6b51d"><td class="memSeparator" colspan="2"> </td></tr> 110<tr class="memitem:a4cd9d936e75552e96b2996a3f3c42081"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a4cd9d936e75552e96b2996a3f3c42081">RTE_SPI6</a>   0</td></tr> 111<tr class="separator:a4cd9d936e75552e96b2996a3f3c42081"><td class="memSeparator" colspan="2"> </td></tr> 112<tr class="memitem:a5f1d64bf1a9b4de1bc0643cbec0eaadb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5f1d64bf1a9b4de1bc0643cbec0eaadb">RTE_SPI6_DMA_EN</a>   0</td></tr> 113<tr class="separator:a5f1d64bf1a9b4de1bc0643cbec0eaadb"><td class="memSeparator" colspan="2"> </td></tr> 114<tr class="memitem:ae8f0e0260407d14858ce86d2ffb75424"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae8f0e0260407d14858ce86d2ffb75424">RTE_USART1</a>   1</td></tr> 115<tr class="separator:ae8f0e0260407d14858ce86d2ffb75424"><td class="memSeparator" colspan="2"> </td></tr> 116<tr class="memitem:a93373776f843912cefd1355e207352e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a93373776f843912cefd1355e207352e2">RTE_USART1_DMA_EN</a>   1</td></tr> 117<tr class="separator:a93373776f843912cefd1355e207352e2"><td class="memSeparator" colspan="2"> </td></tr> 118<tr class="memitem:af4f4f5e1f698d40d9f7d716257536d42"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af4f4f5e1f698d40d9f7d716257536d42">RTE_USART2</a>   0</td></tr> 119<tr class="separator:af4f4f5e1f698d40d9f7d716257536d42"><td class="memSeparator" colspan="2"> </td></tr> 120<tr class="memitem:a125adde5b7b5906d3427a57420322722"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a125adde5b7b5906d3427a57420322722">RTE_USART2_DMA_EN</a>   0</td></tr> 121<tr class="separator:a125adde5b7b5906d3427a57420322722"><td class="memSeparator" colspan="2"> </td></tr> 122<tr class="memitem:ae6d7bafeb9d5b445ebadbd0f224bf1a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae6d7bafeb9d5b445ebadbd0f224bf1a5">RTE_USART3</a>   0</td></tr> 123<tr class="separator:ae6d7bafeb9d5b445ebadbd0f224bf1a5"><td class="memSeparator" colspan="2"> </td></tr> 124<tr class="memitem:a64fade6195385d3c00eeb16517725bb5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a64fade6195385d3c00eeb16517725bb5">RTE_USART3_DMA_EN</a>   0</td></tr> 125<tr class="separator:a64fade6195385d3c00eeb16517725bb5"><td class="memSeparator" colspan="2"> </td></tr> 126<tr class="memitem:a3716b269a4311d87ba183b633ebfad07"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a3716b269a4311d87ba183b633ebfad07">RTE_USART4</a>   0</td></tr> 127<tr class="separator:a3716b269a4311d87ba183b633ebfad07"><td class="memSeparator" colspan="2"> </td></tr> 128<tr class="memitem:abccb132237192d276dec5fd1235d3124"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#abccb132237192d276dec5fd1235d3124">RTE_USART4_DMA_EN</a>   0</td></tr> 129<tr class="separator:abccb132237192d276dec5fd1235d3124"><td class="memSeparator" colspan="2"> </td></tr> 130<tr class="memitem:a5c2c625ac67c8f31440a92490b6d767e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5c2c625ac67c8f31440a92490b6d767e">RTE_USART5</a>   0</td></tr> 131<tr class="separator:a5c2c625ac67c8f31440a92490b6d767e"><td class="memSeparator" colspan="2"> </td></tr> 132<tr class="memitem:aaf003f78b5c4c182d687b220e75e1dbb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aaf003f78b5c4c182d687b220e75e1dbb">RTE_USART5_DMA_EN</a>   0</td></tr> 133<tr class="separator:aaf003f78b5c4c182d687b220e75e1dbb"><td class="memSeparator" colspan="2"> </td></tr> 134<tr class="memitem:af4a7b2970a0f7ac0ee0802298c09848c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af4a7b2970a0f7ac0ee0802298c09848c">RTE_USART6</a>   0</td></tr> 135<tr class="separator:af4a7b2970a0f7ac0ee0802298c09848c"><td class="memSeparator" colspan="2"> </td></tr> 136<tr class="memitem:a46301a9b2d783e5c629b180d8f2344f6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a46301a9b2d783e5c629b180d8f2344f6">RTE_USART6_DMA_EN</a>   0</td></tr> 137<tr class="separator:a46301a9b2d783e5c629b180d8f2344f6"><td class="memSeparator" colspan="2"> </td></tr> 138<tr class="memitem:a416995bb1dd6c68b54b5b2dd85f8bc08"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a416995bb1dd6c68b54b5b2dd85f8bc08">RTE_USART7</a>   0</td></tr> 139<tr class="separator:a416995bb1dd6c68b54b5b2dd85f8bc08"><td class="memSeparator" colspan="2"> </td></tr> 140<tr class="memitem:abde2f17d347b0f02c34cd1875f8bcaba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#abde2f17d347b0f02c34cd1875f8bcaba">RTE_USART7_DMA_EN</a>   0</td></tr> 141<tr class="separator:abde2f17d347b0f02c34cd1875f8bcaba"><td class="memSeparator" colspan="2"> </td></tr> 142<tr class="memitem:a40f133071df7d0c18dd19c6f24e45d7a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a40f133071df7d0c18dd19c6f24e45d7a">RTE_USART8</a>   0</td></tr> 143<tr class="separator:a40f133071df7d0c18dd19c6f24e45d7a"><td class="memSeparator" colspan="2"> </td></tr> 144<tr class="memitem:a8f35821f094b48ab18d0ee7eb9049686"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a8f35821f094b48ab18d0ee7eb9049686">RTE_USART8_DMA_EN</a>   0</td></tr> 145<tr class="separator:a8f35821f094b48ab18d0ee7eb9049686"><td class="memSeparator" colspan="2"> </td></tr> 146<tr class="memitem:a17247f1beecc5e8c6714787be8ec8949"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a17247f1beecc5e8c6714787be8ec8949">RTE_USART9</a>   0</td></tr> 147<tr class="separator:a17247f1beecc5e8c6714787be8ec8949"><td class="memSeparator" colspan="2"> </td></tr> 148<tr class="memitem:a7b2e03393b77773fcaaf18e32eb3104a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7b2e03393b77773fcaaf18e32eb3104a">RTE_USART9_DMA_EN</a>   0</td></tr> 149<tr class="separator:a7b2e03393b77773fcaaf18e32eb3104a"><td class="memSeparator" colspan="2"> </td></tr> 150<tr class="memitem:a726a89447c240f729e73b7622385d749"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a726a89447c240f729e73b7622385d749">RTE_USART10</a>   0</td></tr> 151<tr class="separator:a726a89447c240f729e73b7622385d749"><td class="memSeparator" colspan="2"> </td></tr> 152<tr class="memitem:a5bc420b9d099c3b7361ccb79d698f94d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5bc420b9d099c3b7361ccb79d698f94d">RTE_USART10_DMA_EN</a>   0</td></tr> 153<tr class="separator:a5bc420b9d099c3b7361ccb79d698f94d"><td class="memSeparator" colspan="2"> </td></tr> 154<tr class="memitem:aaeff216fa2e399a92a774e746ea0c040"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aaeff216fa2e399a92a774e746ea0c040">RTE_USART11</a>   0</td></tr> 155<tr class="separator:aaeff216fa2e399a92a774e746ea0c040"><td class="memSeparator" colspan="2"> </td></tr> 156<tr class="memitem:acdd2ab3e608c3f12e233bc2c1f1cd2c6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#acdd2ab3e608c3f12e233bc2c1f1cd2c6">RTE_USART11_DMA_EN</a>   0</td></tr> 157<tr class="separator:acdd2ab3e608c3f12e233bc2c1f1cd2c6"><td class="memSeparator" colspan="2"> </td></tr> 158<tr class="memitem:a9661c4bf5c6330fdb494edbdc700a34c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a9661c4bf5c6330fdb494edbdc700a34c">RTE_USART12</a>   0</td></tr> 159<tr class="separator:a9661c4bf5c6330fdb494edbdc700a34c"><td class="memSeparator" colspan="2"> </td></tr> 160<tr class="memitem:a0f7079dac6a22e2e95b64448c1f2a808"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0f7079dac6a22e2e95b64448c1f2a808">RTE_USART12_DMA_EN</a>   0</td></tr> 161<tr class="separator:a0f7079dac6a22e2e95b64448c1f2a808"><td class="memSeparator" colspan="2"> </td></tr> 162<tr class="memitem:a922ec75cfe937a214fb6c32fdba48bf6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a922ec75cfe937a214fb6c32fdba48bf6">RTE_I2C1_DMA_TX_CH</a>   0</td></tr> 163<tr class="separator:a922ec75cfe937a214fb6c32fdba48bf6"><td class="memSeparator" colspan="2"> </td></tr> 164<tr class="memitem:acf249cbd0797a3dce6412b81aba70ee1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#acf249cbd0797a3dce6412b81aba70ee1">RTE_I2C1_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C1</td></tr> 165<tr class="separator:acf249cbd0797a3dce6412b81aba70ee1"><td class="memSeparator" colspan="2"> </td></tr> 166<tr class="memitem:a031737ed543170a29d6ad6eda661c80b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a031737ed543170a29d6ad6eda661c80b">RTE_I2C1_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 167<tr class="separator:a031737ed543170a29d6ad6eda661c80b"><td class="memSeparator" colspan="2"> </td></tr> 168<tr class="memitem:afb1a3403b4c83f7db9bc032bf18c552b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#afb1a3403b4c83f7db9bc032bf18c552b">RTE_I2C1_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 169<tr class="separator:afb1a3403b4c83f7db9bc032bf18c552b"><td class="memSeparator" colspan="2"> </td></tr> 170<tr class="memitem:ac612ac434bff32c83c18d02d2c6c1ec6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac612ac434bff32c83c18d02d2c6c1ec6">RTE_I2C1_DMA_RX_CH</a>   1</td></tr> 171<tr class="separator:ac612ac434bff32c83c18d02d2c6c1ec6"><td class="memSeparator" colspan="2"> </td></tr> 172<tr class="memitem:adedcadc34e22d206d48b9a325155d9b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#adedcadc34e22d206d48b9a325155d9b6">RTE_I2C1_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C1</td></tr> 173<tr class="separator:adedcadc34e22d206d48b9a325155d9b6"><td class="memSeparator" colspan="2"> </td></tr> 174<tr class="memitem:ab7f7eefcb6f619df42b0730e84bcf2f3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab7f7eefcb6f619df42b0730e84bcf2f3">RTE_I2C1_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 175<tr class="separator:ab7f7eefcb6f619df42b0730e84bcf2f3"><td class="memSeparator" colspan="2"> </td></tr> 176<tr class="memitem:ae19c26f2205b861f3408141ee8ed7d48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae19c26f2205b861f3408141ee8ed7d48">RTE_I2C1_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 177<tr class="separator:ae19c26f2205b861f3408141ee8ed7d48"><td class="memSeparator" colspan="2"> </td></tr> 178<tr class="memitem:aaafac93c554b337745d91aeeaa263ee3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aaafac93c554b337745d91aeeaa263ee3">RTE_I2C2_DMA_TX_CH</a>   2</td></tr> 179<tr class="separator:aaafac93c554b337745d91aeeaa263ee3"><td class="memSeparator" colspan="2"> </td></tr> 180<tr class="memitem:a282e3c43099524332084d89c4dc0370a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a282e3c43099524332084d89c4dc0370a">RTE_I2C2_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C2</td></tr> 181<tr class="separator:a282e3c43099524332084d89c4dc0370a"><td class="memSeparator" colspan="2"> </td></tr> 182<tr class="memitem:ac431de1cf16795d33d163d16e67db4ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac431de1cf16795d33d163d16e67db4ad">RTE_I2C2_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 183<tr class="separator:ac431de1cf16795d33d163d16e67db4ad"><td class="memSeparator" colspan="2"> </td></tr> 184<tr class="memitem:ad4f1a37be61763d2594b4f539ae03d44"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad4f1a37be61763d2594b4f539ae03d44">RTE_I2C2_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 185<tr class="separator:ad4f1a37be61763d2594b4f539ae03d44"><td class="memSeparator" colspan="2"> </td></tr> 186<tr class="memitem:a762b3880f4254c392f2f152393776679"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a762b3880f4254c392f2f152393776679">RTE_I2C2_DMA_RX_CH</a>   3</td></tr> 187<tr class="separator:a762b3880f4254c392f2f152393776679"><td class="memSeparator" colspan="2"> </td></tr> 188<tr class="memitem:ad7eb717542257f354c6b41ad348a1404"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad7eb717542257f354c6b41ad348a1404">RTE_I2C2_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C2</td></tr> 189<tr class="separator:ad7eb717542257f354c6b41ad348a1404"><td class="memSeparator" colspan="2"> </td></tr> 190<tr class="memitem:a042db32af91bc5b35e78566581ed403e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a042db32af91bc5b35e78566581ed403e">RTE_I2C2_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 191<tr class="separator:a042db32af91bc5b35e78566581ed403e"><td class="memSeparator" colspan="2"> </td></tr> 192<tr class="memitem:a1ca82c1fea8b1c55875df9cf0e3e4266"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1ca82c1fea8b1c55875df9cf0e3e4266">RTE_I2C2_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 193<tr class="separator:a1ca82c1fea8b1c55875df9cf0e3e4266"><td class="memSeparator" colspan="2"> </td></tr> 194<tr class="memitem:a8d59722d63164553e1aa90f0b5531aa6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a8d59722d63164553e1aa90f0b5531aa6">RTE_I2C3_DMA_TX_CH</a>   4</td></tr> 195<tr class="separator:a8d59722d63164553e1aa90f0b5531aa6"><td class="memSeparator" colspan="2"> </td></tr> 196<tr class="memitem:a1f3419a15ebd3e7915ab02ddb9d8e57a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1f3419a15ebd3e7915ab02ddb9d8e57a">RTE_I2C3_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C3</td></tr> 197<tr class="separator:a1f3419a15ebd3e7915ab02ddb9d8e57a"><td class="memSeparator" colspan="2"> </td></tr> 198<tr class="memitem:a44e673920f642335b203389fc038fa14"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a44e673920f642335b203389fc038fa14">RTE_I2C3_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 199<tr class="separator:a44e673920f642335b203389fc038fa14"><td class="memSeparator" colspan="2"> </td></tr> 200<tr class="memitem:a21c43b61ee31798e368937bdbc945eb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a21c43b61ee31798e368937bdbc945eb7">RTE_I2C3_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 201<tr class="separator:a21c43b61ee31798e368937bdbc945eb7"><td class="memSeparator" colspan="2"> </td></tr> 202<tr class="memitem:ac78874337ab81de6e42b051fb9dce871"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac78874337ab81de6e42b051fb9dce871">RTE_I2C3_DMA_RX_CH</a>   5</td></tr> 203<tr class="separator:ac78874337ab81de6e42b051fb9dce871"><td class="memSeparator" colspan="2"> </td></tr> 204<tr class="memitem:a0994b2eeb8af41123e69175ac6f9c7b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0994b2eeb8af41123e69175ac6f9c7b0">RTE_I2C3_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C3</td></tr> 205<tr class="separator:a0994b2eeb8af41123e69175ac6f9c7b0"><td class="memSeparator" colspan="2"> </td></tr> 206<tr class="memitem:a24a23c8a15b60cf1095ef24463ff5807"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a24a23c8a15b60cf1095ef24463ff5807">RTE_I2C3_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 207<tr class="separator:a24a23c8a15b60cf1095ef24463ff5807"><td class="memSeparator" colspan="2"> </td></tr> 208<tr class="memitem:acfb03589150d28227ff1dd5393b0b893"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#acfb03589150d28227ff1dd5393b0b893">RTE_I2C3_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 209<tr class="separator:acfb03589150d28227ff1dd5393b0b893"><td class="memSeparator" colspan="2"> </td></tr> 210<tr class="memitem:a886533baa3ecbfdc24804b3bbd3c1fa4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a886533baa3ecbfdc24804b3bbd3c1fa4">RTE_I2C4_DMA_TX_CH</a>   6</td></tr> 211<tr class="separator:a886533baa3ecbfdc24804b3bbd3c1fa4"><td class="memSeparator" colspan="2"> </td></tr> 212<tr class="memitem:acedae977949138b1e4bf418885238855"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#acedae977949138b1e4bf418885238855">RTE_I2C4_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C4</td></tr> 213<tr class="separator:acedae977949138b1e4bf418885238855"><td class="memSeparator" colspan="2"> </td></tr> 214<tr class="memitem:aa525658413a982f217bdb99ad955080d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa525658413a982f217bdb99ad955080d">RTE_I2C4_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 215<tr class="separator:aa525658413a982f217bdb99ad955080d"><td class="memSeparator" colspan="2"> </td></tr> 216<tr class="memitem:a1eeb5eb83698e059c5bbc3df7097102d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1eeb5eb83698e059c5bbc3df7097102d">RTE_I2C4_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 217<tr class="separator:a1eeb5eb83698e059c5bbc3df7097102d"><td class="memSeparator" colspan="2"> </td></tr> 218<tr class="memitem:adb24a07872f830d773e5a761b5b915ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#adb24a07872f830d773e5a761b5b915ea">RTE_I2C4_DMA_RX_CH</a>   7</td></tr> 219<tr class="separator:adb24a07872f830d773e5a761b5b915ea"><td class="memSeparator" colspan="2"> </td></tr> 220<tr class="memitem:aad4b2e8753e39ef0df22e30d47f5af87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aad4b2e8753e39ef0df22e30d47f5af87">RTE_I2C4_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C4</td></tr> 221<tr class="separator:aad4b2e8753e39ef0df22e30d47f5af87"><td class="memSeparator" colspan="2"> </td></tr> 222<tr class="memitem:ad22896233f83e8ab47e7102eda51b807"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad22896233f83e8ab47e7102eda51b807">RTE_I2C4_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 223<tr class="separator:ad22896233f83e8ab47e7102eda51b807"><td class="memSeparator" colspan="2"> </td></tr> 224<tr class="memitem:aac8180353fa95d472f154af42998f3ea"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aac8180353fa95d472f154af42998f3ea">RTE_I2C4_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 225<tr class="separator:aac8180353fa95d472f154af42998f3ea"><td class="memSeparator" colspan="2"> </td></tr> 226<tr class="memitem:aacc69b6a58c942604d55ab3c66c18331"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aacc69b6a58c942604d55ab3c66c18331">RTE_I2C5_DMA_TX_CH</a>   8</td></tr> 227<tr class="separator:aacc69b6a58c942604d55ab3c66c18331"><td class="memSeparator" colspan="2"> </td></tr> 228<tr class="memitem:aae327bc1bd7606f5ce0e12fa22c0c98f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aae327bc1bd7606f5ce0e12fa22c0c98f">RTE_I2C5_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C5</td></tr> 229<tr class="separator:aae327bc1bd7606f5ce0e12fa22c0c98f"><td class="memSeparator" colspan="2"> </td></tr> 230<tr class="memitem:adc753a7570b84d60d982dfd4c887628c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#adc753a7570b84d60d982dfd4c887628c">RTE_I2C5_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 231<tr class="separator:adc753a7570b84d60d982dfd4c887628c"><td class="memSeparator" colspan="2"> </td></tr> 232<tr class="memitem:a237c977557c35a9f367b3dad28755434"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a237c977557c35a9f367b3dad28755434">RTE_I2C5_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 233<tr class="separator:a237c977557c35a9f367b3dad28755434"><td class="memSeparator" colspan="2"> </td></tr> 234<tr class="memitem:a49d74f3d89f709bcee704ed8bc62a389"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a49d74f3d89f709bcee704ed8bc62a389">RTE_I2C5_DMA_RX_CH</a>   9</td></tr> 235<tr class="separator:a49d74f3d89f709bcee704ed8bc62a389"><td class="memSeparator" colspan="2"> </td></tr> 236<tr class="memitem:af9a7eeea936066a06aa12642d206ffe1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af9a7eeea936066a06aa12642d206ffe1">RTE_I2C5_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C5</td></tr> 237<tr class="separator:af9a7eeea936066a06aa12642d206ffe1"><td class="memSeparator" colspan="2"> </td></tr> 238<tr class="memitem:af9e8145e5e8dd332f85fc24a18cb96a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af9e8145e5e8dd332f85fc24a18cb96a1">RTE_I2C5_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 239<tr class="separator:af9e8145e5e8dd332f85fc24a18cb96a1"><td class="memSeparator" colspan="2"> </td></tr> 240<tr class="memitem:afffd01e1818a0941804aa6898e0f3480"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#afffd01e1818a0941804aa6898e0f3480">RTE_I2C5_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 241<tr class="separator:afffd01e1818a0941804aa6898e0f3480"><td class="memSeparator" colspan="2"> </td></tr> 242<tr class="memitem:aa15456a15715d87b5d9fd1663b6def21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa15456a15715d87b5d9fd1663b6def21">RTE_I2C6_DMA_TX_CH</a>   10</td></tr> 243<tr class="separator:aa15456a15715d87b5d9fd1663b6def21"><td class="memSeparator" colspan="2"> </td></tr> 244<tr class="memitem:a3376a9bd3c4accdc4e0d25251960563b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a3376a9bd3c4accdc4e0d25251960563b">RTE_I2C6_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C6</td></tr> 245<tr class="separator:a3376a9bd3c4accdc4e0d25251960563b"><td class="memSeparator" colspan="2"> </td></tr> 246<tr class="memitem:aba9fea9269019c4c2148393ec799bfb7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aba9fea9269019c4c2148393ec799bfb7">RTE_I2C6_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 247<tr class="separator:aba9fea9269019c4c2148393ec799bfb7"><td class="memSeparator" colspan="2"> </td></tr> 248<tr class="memitem:a3beb3f0a50107be726578869d167101a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a3beb3f0a50107be726578869d167101a">RTE_I2C6_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 249<tr class="separator:a3beb3f0a50107be726578869d167101a"><td class="memSeparator" colspan="2"> </td></tr> 250<tr class="memitem:adbde0a01f889e105a70dea33e0b774fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#adbde0a01f889e105a70dea33e0b774fe">RTE_I2C6_DMA_RX_CH</a>   11</td></tr> 251<tr class="separator:adbde0a01f889e105a70dea33e0b774fe"><td class="memSeparator" colspan="2"> </td></tr> 252<tr class="memitem:a18a0ead9ea40c2c592a5a3a73d4f3916"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a18a0ead9ea40c2c592a5a3a73d4f3916">RTE_I2C6_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPI2C6</td></tr> 253<tr class="separator:a18a0ead9ea40c2c592a5a3a73d4f3916"><td class="memSeparator" colspan="2"> </td></tr> 254<tr class="memitem:a73fd097ff81b41936c278b29bc2ad4eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a73fd097ff81b41936c278b29bc2ad4eb">RTE_I2C6_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 255<tr class="separator:a73fd097ff81b41936c278b29bc2ad4eb"><td class="memSeparator" colspan="2"> </td></tr> 256<tr class="memitem:afdf4039762fae0cda1db8c9ea184e641"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#afdf4039762fae0cda1db8c9ea184e641">RTE_I2C6_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 257<tr class="separator:afdf4039762fae0cda1db8c9ea184e641"><td class="memSeparator" colspan="2"> </td></tr> 258<tr class="memitem:a30ffc6ece84420ad1bb78ad539a527ae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a30ffc6ece84420ad1bb78ad539a527ae">RTE_SPI1_PCS_TO_SCK_DELAY</a>   1000</td></tr> 259<tr class="separator:a30ffc6ece84420ad1bb78ad539a527ae"><td class="memSeparator" colspan="2"> </td></tr> 260<tr class="memitem:a88c1db58a1c06f875bdec06c74b85072"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a88c1db58a1c06f875bdec06c74b85072">RTE_SPI1_SCK_TO_PSC_DELAY</a>   1000</td></tr> 261<tr class="separator:a88c1db58a1c06f875bdec06c74b85072"><td class="memSeparator" colspan="2"> </td></tr> 262<tr class="memitem:a951ee008b6f3fccf7c09fb32ef53b288"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a951ee008b6f3fccf7c09fb32ef53b288">RTE_SPI1_BETWEEN_TRANSFER_DELAY</a>   1000</td></tr> 263<tr class="separator:a951ee008b6f3fccf7c09fb32ef53b288"><td class="memSeparator" colspan="2"> </td></tr> 264<tr class="memitem:a0e587c674c92f4898da5f4a2dd7da875"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0e587c674c92f4898da5f4a2dd7da875">RTE_SPI1_MASTER_PCS_PIN_SEL</a>   (kLPSPI_MasterPcs0)</td></tr> 265<tr class="separator:a0e587c674c92f4898da5f4a2dd7da875"><td class="memSeparator" colspan="2"> </td></tr> 266<tr class="memitem:a5b23957d812a8a11c221bee23ddbe2a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5b23957d812a8a11c221bee23ddbe2a7">RTE_SPI1_SLAVE_PCS_PIN_SEL</a>   (kLPSPI_SlavePcs0)</td></tr> 267<tr class="separator:a5b23957d812a8a11c221bee23ddbe2a7"><td class="memSeparator" colspan="2"> </td></tr> 268<tr class="memitem:af7837804201c3faa8cb122bafb79b78a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af7837804201c3faa8cb122bafb79b78a">RTE_SPI1_DMA_TX_CH</a>   0</td></tr> 269<tr class="separator:af7837804201c3faa8cb122bafb79b78a"><td class="memSeparator" colspan="2"> </td></tr> 270<tr class="memitem:adacfa67a7428af81b9a41471e1c52a15"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#adacfa67a7428af81b9a41471e1c52a15">RTE_SPI1_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI1Tx</td></tr> 271<tr class="separator:adacfa67a7428af81b9a41471e1c52a15"><td class="memSeparator" colspan="2"> </td></tr> 272<tr class="memitem:a808f6eb3a927615c6881d185981238c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a808f6eb3a927615c6881d185981238c8">RTE_SPI1_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 273<tr class="separator:a808f6eb3a927615c6881d185981238c8"><td class="memSeparator" colspan="2"> </td></tr> 274<tr class="memitem:a2510e3e47782aa110b9863228c6b20ff"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2510e3e47782aa110b9863228c6b20ff">RTE_SPI1_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 275<tr class="separator:a2510e3e47782aa110b9863228c6b20ff"><td class="memSeparator" colspan="2"> </td></tr> 276<tr class="memitem:a237cd1f72122246b424ced52d44d7374"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a237cd1f72122246b424ced52d44d7374">RTE_SPI1_DMA_RX_CH</a>   1</td></tr> 277<tr class="separator:a237cd1f72122246b424ced52d44d7374"><td class="memSeparator" colspan="2"> </td></tr> 278<tr class="memitem:a1675b80e211aeb65f52be311273d1054"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1675b80e211aeb65f52be311273d1054">RTE_SPI1_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI1Rx</td></tr> 279<tr class="separator:a1675b80e211aeb65f52be311273d1054"><td class="memSeparator" colspan="2"> </td></tr> 280<tr class="memitem:a092a5b393859e6a07fc97a666e3841f9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a092a5b393859e6a07fc97a666e3841f9">RTE_SPI1_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 281<tr class="separator:a092a5b393859e6a07fc97a666e3841f9"><td class="memSeparator" colspan="2"> </td></tr> 282<tr class="memitem:a08060b8c17ac92da6cde2af7d67ee095"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a08060b8c17ac92da6cde2af7d67ee095">RTE_SPI1_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 283<tr class="separator:a08060b8c17ac92da6cde2af7d67ee095"><td class="memSeparator" colspan="2"> </td></tr> 284<tr class="memitem:ae3c6c661ee5134156e7083458fa9d0d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae3c6c661ee5134156e7083458fa9d0d0">RTE_SPI2_PCS_TO_SCK_DELAY</a>   1000</td></tr> 285<tr class="separator:ae3c6c661ee5134156e7083458fa9d0d0"><td class="memSeparator" colspan="2"> </td></tr> 286<tr class="memitem:a5f946c38b63485806d78f455fb199c36"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5f946c38b63485806d78f455fb199c36">RTE_SPI2_SCK_TO_PSC_DELAY</a>   1000</td></tr> 287<tr class="separator:a5f946c38b63485806d78f455fb199c36"><td class="memSeparator" colspan="2"> </td></tr> 288<tr class="memitem:a99923674038030fbcc6c203a048e7092"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a99923674038030fbcc6c203a048e7092">RTE_SPI2_BETWEEN_TRANSFER_DELAY</a>   1000</td></tr> 289<tr class="separator:a99923674038030fbcc6c203a048e7092"><td class="memSeparator" colspan="2"> </td></tr> 290<tr class="memitem:aaf87c891b68f466cded78517bda33f66"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aaf87c891b68f466cded78517bda33f66">RTE_SPI2_MASTER_PCS_PIN_SEL</a>   (kLPSPI_MasterPcs0)</td></tr> 291<tr class="separator:aaf87c891b68f466cded78517bda33f66"><td class="memSeparator" colspan="2"> </td></tr> 292<tr class="memitem:a50c8dea7ad8a4df3477cc5ec811a7726"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a50c8dea7ad8a4df3477cc5ec811a7726">RTE_SPI2_SLAVE_PCS_PIN_SEL</a>   (kLPSPI_SlavePcs0)</td></tr> 293<tr class="separator:a50c8dea7ad8a4df3477cc5ec811a7726"><td class="memSeparator" colspan="2"> </td></tr> 294<tr class="memitem:a2f55409f83ccf9410d19a06c89592cf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2f55409f83ccf9410d19a06c89592cf7">RTE_SPI2_DMA_TX_CH</a>   2</td></tr> 295<tr class="separator:a2f55409f83ccf9410d19a06c89592cf7"><td class="memSeparator" colspan="2"> </td></tr> 296<tr class="memitem:a18b7f6d5915fbcbed92062f953c23b73"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a18b7f6d5915fbcbed92062f953c23b73">RTE_SPI2_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI2Tx</td></tr> 297<tr class="separator:a18b7f6d5915fbcbed92062f953c23b73"><td class="memSeparator" colspan="2"> </td></tr> 298<tr class="memitem:a33414279775ff91c959e0d6238f6f5a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a33414279775ff91c959e0d6238f6f5a8">RTE_SPI2_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 299<tr class="separator:a33414279775ff91c959e0d6238f6f5a8"><td class="memSeparator" colspan="2"> </td></tr> 300<tr class="memitem:ad2c8040af8a79e4d3817c130ac28df6d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad2c8040af8a79e4d3817c130ac28df6d">RTE_SPI2_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 301<tr class="separator:ad2c8040af8a79e4d3817c130ac28df6d"><td class="memSeparator" colspan="2"> </td></tr> 302<tr class="memitem:a2e9a89fc7b4cd0e7b9ddbd9dc747ea84"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2e9a89fc7b4cd0e7b9ddbd9dc747ea84">RTE_SPI2_DMA_RX_CH</a>   3</td></tr> 303<tr class="separator:a2e9a89fc7b4cd0e7b9ddbd9dc747ea84"><td class="memSeparator" colspan="2"> </td></tr> 304<tr class="memitem:a819c248900eebba240a37d7c57ab5408"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a819c248900eebba240a37d7c57ab5408">RTE_SPI2_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI2Tx</td></tr> 305<tr class="separator:a819c248900eebba240a37d7c57ab5408"><td class="memSeparator" colspan="2"> </td></tr> 306<tr class="memitem:a83c234032df3316eea62c35db921df98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a83c234032df3316eea62c35db921df98">RTE_SPI2_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 307<tr class="separator:a83c234032df3316eea62c35db921df98"><td class="memSeparator" colspan="2"> </td></tr> 308<tr class="memitem:ae14cfbbd7990b4e16da76447fd0f71d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae14cfbbd7990b4e16da76447fd0f71d0">RTE_SPI2_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 309<tr class="separator:ae14cfbbd7990b4e16da76447fd0f71d0"><td class="memSeparator" colspan="2"> </td></tr> 310<tr class="memitem:aa73000740183c3947717fa583d165815"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa73000740183c3947717fa583d165815">RTE_SPI3_PCS_TO_SCK_DELAY</a>   1000</td></tr> 311<tr class="separator:aa73000740183c3947717fa583d165815"><td class="memSeparator" colspan="2"> </td></tr> 312<tr class="memitem:a0e7623e6ba7a9f5e22314ffd3cedba06"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0e7623e6ba7a9f5e22314ffd3cedba06">RTE_SPI3_SCK_TO_PSC_DELAY</a>   1000</td></tr> 313<tr class="separator:a0e7623e6ba7a9f5e22314ffd3cedba06"><td class="memSeparator" colspan="2"> </td></tr> 314<tr class="memitem:aea2bec62dec8ae43dd4866d04a7a210f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aea2bec62dec8ae43dd4866d04a7a210f">RTE_SPI3_BETWEEN_TRANSFER_DELAY</a>   1000</td></tr> 315<tr class="separator:aea2bec62dec8ae43dd4866d04a7a210f"><td class="memSeparator" colspan="2"> </td></tr> 316<tr class="memitem:ae246a17a5a03704c5f4d44cd40df50d7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae246a17a5a03704c5f4d44cd40df50d7">RTE_SPI3_MASTER_PCS_PIN_SEL</a>   (kLPSPI_MasterPcs0)</td></tr> 317<tr class="separator:ae246a17a5a03704c5f4d44cd40df50d7"><td class="memSeparator" colspan="2"> </td></tr> 318<tr class="memitem:a63dc1c7865592a39f5bf323f14cbcf9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a63dc1c7865592a39f5bf323f14cbcf9d">RTE_SPI3_SLAVE_PCS_PIN_SEL</a>   (kLPSPI_SlavePcs0)</td></tr> 319<tr class="separator:a63dc1c7865592a39f5bf323f14cbcf9d"><td class="memSeparator" colspan="2"> </td></tr> 320<tr class="memitem:aede43b66781471d6f7824e1d8a5d678a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aede43b66781471d6f7824e1d8a5d678a">RTE_SPI3_DMA_TX_CH</a>   4</td></tr> 321<tr class="separator:aede43b66781471d6f7824e1d8a5d678a"><td class="memSeparator" colspan="2"> </td></tr> 322<tr class="memitem:a7a1d1794b26a340e85bd3569d80b1470"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7a1d1794b26a340e85bd3569d80b1470">RTE_SPI3_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI3Tx</td></tr> 323<tr class="separator:a7a1d1794b26a340e85bd3569d80b1470"><td class="memSeparator" colspan="2"> </td></tr> 324<tr class="memitem:a957637aad66f6d5deed94db4d18e3ca8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a957637aad66f6d5deed94db4d18e3ca8">RTE_SPI3_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 325<tr class="separator:a957637aad66f6d5deed94db4d18e3ca8"><td class="memSeparator" colspan="2"> </td></tr> 326<tr class="memitem:a9237e29a834083e9cff82ba51800ec0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a9237e29a834083e9cff82ba51800ec0d">RTE_SPI3_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 327<tr class="separator:a9237e29a834083e9cff82ba51800ec0d"><td class="memSeparator" colspan="2"> </td></tr> 328<tr class="memitem:adb5a87ba91d16c71a803610ffbf40c13"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#adb5a87ba91d16c71a803610ffbf40c13">RTE_SPI3_DMA_RX_CH</a>   5</td></tr> 329<tr class="separator:adb5a87ba91d16c71a803610ffbf40c13"><td class="memSeparator" colspan="2"> </td></tr> 330<tr class="memitem:a1a3261f383900579c450e714a8c9c4e9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1a3261f383900579c450e714a8c9c4e9">RTE_SPI3_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI3Rx</td></tr> 331<tr class="separator:a1a3261f383900579c450e714a8c9c4e9"><td class="memSeparator" colspan="2"> </td></tr> 332<tr class="memitem:ae8eb8e1701ada3c43faacf46f163c1f5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae8eb8e1701ada3c43faacf46f163c1f5">RTE_SPI3_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 333<tr class="separator:ae8eb8e1701ada3c43faacf46f163c1f5"><td class="memSeparator" colspan="2"> </td></tr> 334<tr class="memitem:aad946150307e0a2d3f1e4e030550dc68"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aad946150307e0a2d3f1e4e030550dc68">RTE_SPI3_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 335<tr class="separator:aad946150307e0a2d3f1e4e030550dc68"><td class="memSeparator" colspan="2"> </td></tr> 336<tr class="memitem:a902fd47282cf03f90965dd9c28c5fbad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a902fd47282cf03f90965dd9c28c5fbad">RTE_SPI4_PCS_TO_SCK_DELAY</a>   1000</td></tr> 337<tr class="separator:a902fd47282cf03f90965dd9c28c5fbad"><td class="memSeparator" colspan="2"> </td></tr> 338<tr class="memitem:addde6066970e78ac95c304f81e3d4224"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#addde6066970e78ac95c304f81e3d4224">RTE_SPI4_SCK_TO_PSC_DELAY</a>   1000</td></tr> 339<tr class="separator:addde6066970e78ac95c304f81e3d4224"><td class="memSeparator" colspan="2"> </td></tr> 340<tr class="memitem:aaf2ab4cef9c8fd5fd873954d6312630e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aaf2ab4cef9c8fd5fd873954d6312630e">RTE_SPI4_BETWEEN_TRANSFER_DELAY</a>   1000</td></tr> 341<tr class="separator:aaf2ab4cef9c8fd5fd873954d6312630e"><td class="memSeparator" colspan="2"> </td></tr> 342<tr class="memitem:a14b93ec25540b16bf3adac9417b18d98"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a14b93ec25540b16bf3adac9417b18d98">RTE_SPI4_MASTER_PCS_PIN_SEL</a>   (kLPSPI_MasterPcs0)</td></tr> 343<tr class="separator:a14b93ec25540b16bf3adac9417b18d98"><td class="memSeparator" colspan="2"> </td></tr> 344<tr class="memitem:a1ffa2d5a7b8e5ad0b1b5bf96270e9427"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1ffa2d5a7b8e5ad0b1b5bf96270e9427">RTE_SPI4_SLAVE_PCS_PIN_SEL</a>   (kLPSPI_SlavePcs0)</td></tr> 345<tr class="separator:a1ffa2d5a7b8e5ad0b1b5bf96270e9427"><td class="memSeparator" colspan="2"> </td></tr> 346<tr class="memitem:a956855c142636770f6a7debe2aa013e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a956855c142636770f6a7debe2aa013e6">RTE_SPI4_DMA_TX_CH</a>   6</td></tr> 347<tr class="separator:a956855c142636770f6a7debe2aa013e6"><td class="memSeparator" colspan="2"> </td></tr> 348<tr class="memitem:a26a43c2ab8b1d1c288cb34ecd416f7c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a26a43c2ab8b1d1c288cb34ecd416f7c0">RTE_SPI4_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI4Tx</td></tr> 349<tr class="separator:a26a43c2ab8b1d1c288cb34ecd416f7c0"><td class="memSeparator" colspan="2"> </td></tr> 350<tr class="memitem:ae3eaa3789e307502d95d5bcb22557f21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae3eaa3789e307502d95d5bcb22557f21">RTE_SPI4_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 351<tr class="separator:ae3eaa3789e307502d95d5bcb22557f21"><td class="memSeparator" colspan="2"> </td></tr> 352<tr class="memitem:aa3ec0db7635e3be6822ac3d6b522aed9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa3ec0db7635e3be6822ac3d6b522aed9">RTE_SPI4_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 353<tr class="separator:aa3ec0db7635e3be6822ac3d6b522aed9"><td class="memSeparator" colspan="2"> </td></tr> 354<tr class="memitem:a7dd6e0050f362bd1bfd3a07a7e86b57a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7dd6e0050f362bd1bfd3a07a7e86b57a">RTE_SPI4_DMA_RX_CH</a>   7</td></tr> 355<tr class="separator:a7dd6e0050f362bd1bfd3a07a7e86b57a"><td class="memSeparator" colspan="2"> </td></tr> 356<tr class="memitem:ada325d25817cdcfd6760ec56d55ebd9e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ada325d25817cdcfd6760ec56d55ebd9e">RTE_SPI4_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI4Rx</td></tr> 357<tr class="separator:ada325d25817cdcfd6760ec56d55ebd9e"><td class="memSeparator" colspan="2"> </td></tr> 358<tr class="memitem:a478cb5cd7ebeaf47470f623dac24f71b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a478cb5cd7ebeaf47470f623dac24f71b">RTE_SPI4_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 359<tr class="separator:a478cb5cd7ebeaf47470f623dac24f71b"><td class="memSeparator" colspan="2"> </td></tr> 360<tr class="memitem:a968c662515159592bfb826495d2d3c5d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a968c662515159592bfb826495d2d3c5d">RTE_SPI4_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 361<tr class="separator:a968c662515159592bfb826495d2d3c5d"><td class="memSeparator" colspan="2"> </td></tr> 362<tr class="memitem:a37d29d6dcbb2e3de3425057411bb99c4"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a37d29d6dcbb2e3de3425057411bb99c4">RTE_SPI5_PCS_TO_SCK_DELAY</a>   1000</td></tr> 363<tr class="separator:a37d29d6dcbb2e3de3425057411bb99c4"><td class="memSeparator" colspan="2"> </td></tr> 364<tr class="memitem:ab940dc32781a18c0af66e85d7afccd8f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab940dc32781a18c0af66e85d7afccd8f">RTE_SPI5_SCK_TO_PSC_DELAY</a>   1000</td></tr> 365<tr class="separator:ab940dc32781a18c0af66e85d7afccd8f"><td class="memSeparator" colspan="2"> </td></tr> 366<tr class="memitem:ad61947178295915a471db020e41d1811"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad61947178295915a471db020e41d1811">RTE_SPI5_BETWEEN_TRANSFER_DELAY</a>   1000</td></tr> 367<tr class="separator:ad61947178295915a471db020e41d1811"><td class="memSeparator" colspan="2"> </td></tr> 368<tr class="memitem:abf2aea43f4b4b480fadb99bcc4e22de6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#abf2aea43f4b4b480fadb99bcc4e22de6">RTE_SPI5_MASTER_PCS_PIN_SEL</a>   (kLPSPI_MasterPcs0)</td></tr> 369<tr class="separator:abf2aea43f4b4b480fadb99bcc4e22de6"><td class="memSeparator" colspan="2"> </td></tr> 370<tr class="memitem:a87e3d2b881cd6ffc6d436cc4f6cbbf7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a87e3d2b881cd6ffc6d436cc4f6cbbf7b">RTE_SPI5_SLAVE_PCS_PIN_SEL</a>   (kLPSPI_SlavePcs0)</td></tr> 371<tr class="separator:a87e3d2b881cd6ffc6d436cc4f6cbbf7b"><td class="memSeparator" colspan="2"> </td></tr> 372<tr class="memitem:a1041985ad6bcd91b3bb3cccd837aaaae"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1041985ad6bcd91b3bb3cccd837aaaae">RTE_SPI5_DMA_TX_CH</a>   8</td></tr> 373<tr class="separator:a1041985ad6bcd91b3bb3cccd837aaaae"><td class="memSeparator" colspan="2"> </td></tr> 374<tr class="memitem:a0ecaf278dd6946934ec7d5a6c4b18a7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0ecaf278dd6946934ec7d5a6c4b18a7b">RTE_SPI5_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI5Tx</td></tr> 375<tr class="separator:a0ecaf278dd6946934ec7d5a6c4b18a7b"><td class="memSeparator" colspan="2"> </td></tr> 376<tr class="memitem:a0e5b5dbcfb4dde49887559b4f303a0b6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0e5b5dbcfb4dde49887559b4f303a0b6">RTE_SPI5_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 377<tr class="separator:a0e5b5dbcfb4dde49887559b4f303a0b6"><td class="memSeparator" colspan="2"> </td></tr> 378<tr class="memitem:a8d306bb116961953c118532b719cc5a9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a8d306bb116961953c118532b719cc5a9">RTE_SPI5_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 379<tr class="separator:a8d306bb116961953c118532b719cc5a9"><td class="memSeparator" colspan="2"> </td></tr> 380<tr class="memitem:a6aa0bdc35c2121855560c7a6455dbddf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a6aa0bdc35c2121855560c7a6455dbddf">RTE_SPI5_DMA_RX_CH</a>   9</td></tr> 381<tr class="separator:a6aa0bdc35c2121855560c7a6455dbddf"><td class="memSeparator" colspan="2"> </td></tr> 382<tr class="memitem:aa17446d7236876fb326323f1222fcb8d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa17446d7236876fb326323f1222fcb8d">RTE_SPI5_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI5Rx</td></tr> 383<tr class="separator:aa17446d7236876fb326323f1222fcb8d"><td class="memSeparator" colspan="2"> </td></tr> 384<tr class="memitem:a7661d8743ca1a17dda22cb8e0e0f68bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7661d8743ca1a17dda22cb8e0e0f68bb">RTE_SPI5_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 385<tr class="separator:a7661d8743ca1a17dda22cb8e0e0f68bb"><td class="memSeparator" colspan="2"> </td></tr> 386<tr class="memitem:ab382c8c01e5955ace12e26b487622a05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab382c8c01e5955ace12e26b487622a05">RTE_SPI5_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 387<tr class="separator:ab382c8c01e5955ace12e26b487622a05"><td class="memSeparator" colspan="2"> </td></tr> 388<tr class="memitem:a2f70806a3b60d1adc11f421229f14461"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2f70806a3b60d1adc11f421229f14461">RTE_SPI6_PCS_TO_SCK_DELAY</a>   1000</td></tr> 389<tr class="separator:a2f70806a3b60d1adc11f421229f14461"><td class="memSeparator" colspan="2"> </td></tr> 390<tr class="memitem:aa477179de6b38381621f7479ddc3b3dd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa477179de6b38381621f7479ddc3b3dd">RTE_SPI6_SCK_TO_PSC_DELAY</a>   1000</td></tr> 391<tr class="separator:aa477179de6b38381621f7479ddc3b3dd"><td class="memSeparator" colspan="2"> </td></tr> 392<tr class="memitem:a2a8fa79cc3fd9b4b0f04cbf226410c4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2a8fa79cc3fd9b4b0f04cbf226410c4b">RTE_SPI6_BETWEEN_TRANSFER_DELAY</a>   1000</td></tr> 393<tr class="separator:a2a8fa79cc3fd9b4b0f04cbf226410c4b"><td class="memSeparator" colspan="2"> </td></tr> 394<tr class="memitem:a624b496f8c43b43734656fc972eb44d0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a624b496f8c43b43734656fc972eb44d0">RTE_SPI6_MASTER_PCS_PIN_SEL</a>   (kLPSPI_MasterPcs0)</td></tr> 395<tr class="separator:a624b496f8c43b43734656fc972eb44d0"><td class="memSeparator" colspan="2"> </td></tr> 396<tr class="memitem:a7a2616e6e511c3fd735af6ffb2efba85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7a2616e6e511c3fd735af6ffb2efba85">RTE_SPI6_SLAVE_PCS_PIN_SEL</a>   (kLPSPI_SlavePcs0)</td></tr> 397<tr class="separator:a7a2616e6e511c3fd735af6ffb2efba85"><td class="memSeparator" colspan="2"> </td></tr> 398<tr class="memitem:a500837b546f2c5c5d340c70b8316cd75"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a500837b546f2c5c5d340c70b8316cd75">RTE_SPI6_DMA_TX_CH</a>   10</td></tr> 399<tr class="separator:a500837b546f2c5c5d340c70b8316cd75"><td class="memSeparator" colspan="2"> </td></tr> 400<tr class="memitem:ada1fda3c07011611352d8a49a7bf4d3f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ada1fda3c07011611352d8a49a7bf4d3f">RTE_SPI6_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI6Tx</td></tr> 401<tr class="separator:ada1fda3c07011611352d8a49a7bf4d3f"><td class="memSeparator" colspan="2"> </td></tr> 402<tr class="memitem:a45d09e085504ada169bc3b97358b4c04"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a45d09e085504ada169bc3b97358b4c04">RTE_SPI6_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 403<tr class="separator:a45d09e085504ada169bc3b97358b4c04"><td class="memSeparator" colspan="2"> </td></tr> 404<tr class="memitem:a562a146c7a128d2087eb47d8e19a2b2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a562a146c7a128d2087eb47d8e19a2b2a">RTE_SPI6_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 405<tr class="separator:a562a146c7a128d2087eb47d8e19a2b2a"><td class="memSeparator" colspan="2"> </td></tr> 406<tr class="memitem:acdb61b6c3e30ad9a0877b9931b6d6904"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#acdb61b6c3e30ad9a0877b9931b6d6904">RTE_SPI6_DMA_RX_CH</a>   11</td></tr> 407<tr class="separator:acdb61b6c3e30ad9a0877b9931b6d6904"><td class="memSeparator" colspan="2"> </td></tr> 408<tr class="memitem:aa4a398c69b8dac0ebc7d7a9f40b7609f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa4a398c69b8dac0ebc7d7a9f40b7609f">RTE_SPI6_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPSPI6Rx</td></tr> 409<tr class="separator:aa4a398c69b8dac0ebc7d7a9f40b7609f"><td class="memSeparator" colspan="2"> </td></tr> 410<tr class="memitem:a113aed2c7ed2624fab109cf0748ac052"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a113aed2c7ed2624fab109cf0748ac052">RTE_SPI6_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 411<tr class="separator:a113aed2c7ed2624fab109cf0748ac052"><td class="memSeparator" colspan="2"> </td></tr> 412<tr class="memitem:acab2a9b0b3033d3425ac33918ec17c03"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#acab2a9b0b3033d3425ac33918ec17c03">RTE_SPI6_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 413<tr class="separator:acab2a9b0b3033d3425ac33918ec17c03"><td class="memSeparator" colspan="2"> </td></tr> 414<tr class="memitem:a272ab6f694a794b54d6d0bacf4b030c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a272ab6f694a794b54d6d0bacf4b030c3">RTE_USART1_DMA_TX_CH</a>   0</td></tr> 415<tr class="separator:a272ab6f694a794b54d6d0bacf4b030c3"><td class="memSeparator" colspan="2"> </td></tr> 416<tr class="memitem:ab360b9072ab5034fe19c591b11ddaa4f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab360b9072ab5034fe19c591b11ddaa4f">RTE_USART1_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART1Tx</td></tr> 417<tr class="separator:ab360b9072ab5034fe19c591b11ddaa4f"><td class="memSeparator" colspan="2"> </td></tr> 418<tr class="memitem:a28ef4acc4180de985e24a0bb392e42c8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a28ef4acc4180de985e24a0bb392e42c8">RTE_USART1_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 419<tr class="separator:a28ef4acc4180de985e24a0bb392e42c8"><td class="memSeparator" colspan="2"> </td></tr> 420<tr class="memitem:a7804081da977b330578221c5ce5ba89e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7804081da977b330578221c5ce5ba89e">RTE_USART1_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 421<tr class="separator:a7804081da977b330578221c5ce5ba89e"><td class="memSeparator" colspan="2"> </td></tr> 422<tr class="memitem:af78c326f4aa3f8ba10614f88755ac30e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af78c326f4aa3f8ba10614f88755ac30e">RTE_USART1_DMA_RX_CH</a>   1</td></tr> 423<tr class="separator:af78c326f4aa3f8ba10614f88755ac30e"><td class="memSeparator" colspan="2"> </td></tr> 424<tr class="memitem:a2e6bd424c90e5734c38eb4f198ed0347"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2e6bd424c90e5734c38eb4f198ed0347">RTE_USART1_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART1Rx</td></tr> 425<tr class="separator:a2e6bd424c90e5734c38eb4f198ed0347"><td class="memSeparator" colspan="2"> </td></tr> 426<tr class="memitem:ad71e62366aea28e6c003f082a3ff5227"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad71e62366aea28e6c003f082a3ff5227">RTE_USART1_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 427<tr class="separator:ad71e62366aea28e6c003f082a3ff5227"><td class="memSeparator" colspan="2"> </td></tr> 428<tr class="memitem:ab58d0f95baca5b61fd1183daed257004"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab58d0f95baca5b61fd1183daed257004">RTE_USART1_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 429<tr class="separator:ab58d0f95baca5b61fd1183daed257004"><td class="memSeparator" colspan="2"> </td></tr> 430<tr class="memitem:a4da147c7ce755201a079c412c098128f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a4da147c7ce755201a079c412c098128f">RTE_USART2_DMA_TX_CH</a>   2</td></tr> 431<tr class="separator:a4da147c7ce755201a079c412c098128f"><td class="memSeparator" colspan="2"> </td></tr> 432<tr class="memitem:a1921b3ed005879e26052e379f23dbcb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a1921b3ed005879e26052e379f23dbcb2">RTE_USART2_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART2Tx</td></tr> 433<tr class="separator:a1921b3ed005879e26052e379f23dbcb2"><td class="memSeparator" colspan="2"> </td></tr> 434<tr class="memitem:a35e29209a15939cab26f74b2d1f6daf9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a35e29209a15939cab26f74b2d1f6daf9">RTE_USART2_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 435<tr class="separator:a35e29209a15939cab26f74b2d1f6daf9"><td class="memSeparator" colspan="2"> </td></tr> 436<tr class="memitem:a667adae4bda8ac302bcc85d4a7a004cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a667adae4bda8ac302bcc85d4a7a004cd">RTE_USART2_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 437<tr class="separator:a667adae4bda8ac302bcc85d4a7a004cd"><td class="memSeparator" colspan="2"> </td></tr> 438<tr class="memitem:aaf5d293f3353d103aa7fc672a3cf456d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aaf5d293f3353d103aa7fc672a3cf456d">RTE_USART2_DMA_RX_CH</a>   3</td></tr> 439<tr class="separator:aaf5d293f3353d103aa7fc672a3cf456d"><td class="memSeparator" colspan="2"> </td></tr> 440<tr class="memitem:ad8969d48f9a854dcd661e60ace8f2eac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad8969d48f9a854dcd661e60ace8f2eac">RTE_USART2_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART2Rx</td></tr> 441<tr class="separator:ad8969d48f9a854dcd661e60ace8f2eac"><td class="memSeparator" colspan="2"> </td></tr> 442<tr class="memitem:a4e45bca95b4f0c419b7aa5b27655e0f8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a4e45bca95b4f0c419b7aa5b27655e0f8">RTE_USART2_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 443<tr class="separator:a4e45bca95b4f0c419b7aa5b27655e0f8"><td class="memSeparator" colspan="2"> </td></tr> 444<tr class="memitem:a54af00b2f29f1e9aeb10e1a59a4cde3d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a54af00b2f29f1e9aeb10e1a59a4cde3d">RTE_USART2_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 445<tr class="separator:a54af00b2f29f1e9aeb10e1a59a4cde3d"><td class="memSeparator" colspan="2"> </td></tr> 446<tr class="memitem:a371552d64a4c36aa553a256ab52c4737"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a371552d64a4c36aa553a256ab52c4737">RTE_USART3_DMA_TX_CH</a>   4</td></tr> 447<tr class="separator:a371552d64a4c36aa553a256ab52c4737"><td class="memSeparator" colspan="2"> </td></tr> 448<tr class="memitem:a298c8ca62c3080284bf1c1ddc9e52c74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a298c8ca62c3080284bf1c1ddc9e52c74">RTE_USART3_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART3Tx</td></tr> 449<tr class="separator:a298c8ca62c3080284bf1c1ddc9e52c74"><td class="memSeparator" colspan="2"> </td></tr> 450<tr class="memitem:a05781de3d61d146f982ffb787d36f3fe"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a05781de3d61d146f982ffb787d36f3fe">RTE_USART3_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 451<tr class="separator:a05781de3d61d146f982ffb787d36f3fe"><td class="memSeparator" colspan="2"> </td></tr> 452<tr class="memitem:a230981b96cecea4add332ecd40533454"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a230981b96cecea4add332ecd40533454">RTE_USART3_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 453<tr class="separator:a230981b96cecea4add332ecd40533454"><td class="memSeparator" colspan="2"> </td></tr> 454<tr class="memitem:ab09d3b40ddde8be68179be6d46400d45"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab09d3b40ddde8be68179be6d46400d45">RTE_USART3_DMA_RX_CH</a>   5</td></tr> 455<tr class="separator:ab09d3b40ddde8be68179be6d46400d45"><td class="memSeparator" colspan="2"> </td></tr> 456<tr class="memitem:ab310379c65913c108e059c4e317ce096"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab310379c65913c108e059c4e317ce096">RTE_USART3_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART3Rx</td></tr> 457<tr class="separator:ab310379c65913c108e059c4e317ce096"><td class="memSeparator" colspan="2"> </td></tr> 458<tr class="memitem:a7ce8b3cab8b376e492e0599890bb4ad0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7ce8b3cab8b376e492e0599890bb4ad0">RTE_USART3_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 459<tr class="separator:a7ce8b3cab8b376e492e0599890bb4ad0"><td class="memSeparator" colspan="2"> </td></tr> 460<tr class="memitem:ae05b2c8a2baaa32c10d0af3457ce2e28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae05b2c8a2baaa32c10d0af3457ce2e28">RTE_USART3_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 461<tr class="separator:ae05b2c8a2baaa32c10d0af3457ce2e28"><td class="memSeparator" colspan="2"> </td></tr> 462<tr class="memitem:a583406cbb43d2e24e0cf8cafdb45d7d9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a583406cbb43d2e24e0cf8cafdb45d7d9">RTE_USART4_DMA_TX_CH</a>   6</td></tr> 463<tr class="separator:a583406cbb43d2e24e0cf8cafdb45d7d9"><td class="memSeparator" colspan="2"> </td></tr> 464<tr class="memitem:a2b6f4b82acc33b81f3637afc63419169"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2b6f4b82acc33b81f3637afc63419169">RTE_USART4_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART4Tx</td></tr> 465<tr class="separator:a2b6f4b82acc33b81f3637afc63419169"><td class="memSeparator" colspan="2"> </td></tr> 466<tr class="memitem:a23d221d38fab3da9b28d9de859af9f48"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a23d221d38fab3da9b28d9de859af9f48">RTE_USART4_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 467<tr class="separator:a23d221d38fab3da9b28d9de859af9f48"><td class="memSeparator" colspan="2"> </td></tr> 468<tr class="memitem:ac4abea21e4bfc3d03539f739892b0e7f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac4abea21e4bfc3d03539f739892b0e7f">RTE_USART4_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 469<tr class="separator:ac4abea21e4bfc3d03539f739892b0e7f"><td class="memSeparator" colspan="2"> </td></tr> 470<tr class="memitem:ae3aa08740bc1278f56cb25413751053b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae3aa08740bc1278f56cb25413751053b">RTE_USART4_DMA_RX_CH</a>   7</td></tr> 471<tr class="separator:ae3aa08740bc1278f56cb25413751053b"><td class="memSeparator" colspan="2"> </td></tr> 472<tr class="memitem:a2d133b10d9af3b93828d264638c01d69"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2d133b10d9af3b93828d264638c01d69">RTE_USART4_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART4Rx</td></tr> 473<tr class="separator:a2d133b10d9af3b93828d264638c01d69"><td class="memSeparator" colspan="2"> </td></tr> 474<tr class="memitem:a0af7a32050ae6ea721dc3bfe51cec886"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0af7a32050ae6ea721dc3bfe51cec886">RTE_USART4_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 475<tr class="separator:a0af7a32050ae6ea721dc3bfe51cec886"><td class="memSeparator" colspan="2"> </td></tr> 476<tr class="memitem:a84ae4f174efa1b7417b5a35d9b9e3de9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a84ae4f174efa1b7417b5a35d9b9e3de9">RTE_USART4_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 477<tr class="separator:a84ae4f174efa1b7417b5a35d9b9e3de9"><td class="memSeparator" colspan="2"> </td></tr> 478<tr class="memitem:a5fc281007f625bf44a5b16d7f97c9f7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5fc281007f625bf44a5b16d7f97c9f7b">RTE_USART5_DMA_TX_CH</a>   8</td></tr> 479<tr class="separator:a5fc281007f625bf44a5b16d7f97c9f7b"><td class="memSeparator" colspan="2"> </td></tr> 480<tr class="memitem:a3f34578afbd133748801bbb852f1cc46"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a3f34578afbd133748801bbb852f1cc46">RTE_USART5_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART5Tx</td></tr> 481<tr class="separator:a3f34578afbd133748801bbb852f1cc46"><td class="memSeparator" colspan="2"> </td></tr> 482<tr class="memitem:ae6732d5a38b93890d64314a0837a1d34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae6732d5a38b93890d64314a0837a1d34">RTE_USART5_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 483<tr class="separator:ae6732d5a38b93890d64314a0837a1d34"><td class="memSeparator" colspan="2"> </td></tr> 484<tr class="memitem:a530f52cd5d979b98f959163c96e4413b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a530f52cd5d979b98f959163c96e4413b">RTE_USART5_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 485<tr class="separator:a530f52cd5d979b98f959163c96e4413b"><td class="memSeparator" colspan="2"> </td></tr> 486<tr class="memitem:af563379f0b22b56089642e1452293b94"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af563379f0b22b56089642e1452293b94">RTE_USART5_DMA_RX_CH</a>   9</td></tr> 487<tr class="separator:af563379f0b22b56089642e1452293b94"><td class="memSeparator" colspan="2"> </td></tr> 488<tr class="memitem:a4dc20b4bfb5766bac0d6de434bda7fd8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a4dc20b4bfb5766bac0d6de434bda7fd8">RTE_USART5_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART5Rx</td></tr> 489<tr class="separator:a4dc20b4bfb5766bac0d6de434bda7fd8"><td class="memSeparator" colspan="2"> </td></tr> 490<tr class="memitem:a7a8f2581e0cbec8210edb6f89f7b187c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a7a8f2581e0cbec8210edb6f89f7b187c">RTE_USART5_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 491<tr class="separator:a7a8f2581e0cbec8210edb6f89f7b187c"><td class="memSeparator" colspan="2"> </td></tr> 492<tr class="memitem:a665e630b27a6713ff3055c9893403090"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a665e630b27a6713ff3055c9893403090">RTE_USART5_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 493<tr class="separator:a665e630b27a6713ff3055c9893403090"><td class="memSeparator" colspan="2"> </td></tr> 494<tr class="memitem:a830ccf4153d422fc98971a8fc2d1ecba"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a830ccf4153d422fc98971a8fc2d1ecba">RTE_USART6_DMA_TX_CH</a>   10</td></tr> 495<tr class="separator:a830ccf4153d422fc98971a8fc2d1ecba"><td class="memSeparator" colspan="2"> </td></tr> 496<tr class="memitem:ac1692d643111d558f2df528205966f28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac1692d643111d558f2df528205966f28">RTE_USART6_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART6Tx</td></tr> 497<tr class="separator:ac1692d643111d558f2df528205966f28"><td class="memSeparator" colspan="2"> </td></tr> 498<tr class="memitem:af6111a4ca33179e72211e0a267f1b40e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#af6111a4ca33179e72211e0a267f1b40e">RTE_USART6_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 499<tr class="separator:af6111a4ca33179e72211e0a267f1b40e"><td class="memSeparator" colspan="2"> </td></tr> 500<tr class="memitem:aa50f707f6ba72c2c400faa7e2c9b8b5f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa50f707f6ba72c2c400faa7e2c9b8b5f">RTE_USART6_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 501<tr class="separator:aa50f707f6ba72c2c400faa7e2c9b8b5f"><td class="memSeparator" colspan="2"> </td></tr> 502<tr class="memitem:a74e96a5225571536daf6ce2058f2ca11"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a74e96a5225571536daf6ce2058f2ca11">RTE_USART6_DMA_RX_CH</a>   11</td></tr> 503<tr class="separator:a74e96a5225571536daf6ce2058f2ca11"><td class="memSeparator" colspan="2"> </td></tr> 504<tr class="memitem:ad55c040ec06f230089b7f190f5eb5589"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad55c040ec06f230089b7f190f5eb5589">RTE_USART6_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART6Rx</td></tr> 505<tr class="separator:ad55c040ec06f230089b7f190f5eb5589"><td class="memSeparator" colspan="2"> </td></tr> 506<tr class="memitem:aeb3cf21340277e8390db8a14d63ee5d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aeb3cf21340277e8390db8a14d63ee5d5">RTE_USART6_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 507<tr class="separator:aeb3cf21340277e8390db8a14d63ee5d5"><td class="memSeparator" colspan="2"> </td></tr> 508<tr class="memitem:a5937989b65e91558a7ecd473a511e5e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5937989b65e91558a7ecd473a511e5e6">RTE_USART6_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 509<tr class="separator:a5937989b65e91558a7ecd473a511e5e6"><td class="memSeparator" colspan="2"> </td></tr> 510<tr class="memitem:a4f3d104ac7e9a07019d58c26bd53e9a1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a4f3d104ac7e9a07019d58c26bd53e9a1">RTE_USART7_DMA_TX_CH</a>   12</td></tr> 511<tr class="separator:a4f3d104ac7e9a07019d58c26bd53e9a1"><td class="memSeparator" colspan="2"> </td></tr> 512<tr class="memitem:a9105787bef980157f54fc11f21ee84b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a9105787bef980157f54fc11f21ee84b5">RTE_USART7_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART7Tx</td></tr> 513<tr class="separator:a9105787bef980157f54fc11f21ee84b5"><td class="memSeparator" colspan="2"> </td></tr> 514<tr class="memitem:a8b9a5d583e90a47e3f535b114da2512f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a8b9a5d583e90a47e3f535b114da2512f">RTE_USART7_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 515<tr class="separator:a8b9a5d583e90a47e3f535b114da2512f"><td class="memSeparator" colspan="2"> </td></tr> 516<tr class="memitem:a9417cafd6534bd6b4be87b6bea6ac16c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a9417cafd6534bd6b4be87b6bea6ac16c">RTE_USART7_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 517<tr class="separator:a9417cafd6534bd6b4be87b6bea6ac16c"><td class="memSeparator" colspan="2"> </td></tr> 518<tr class="memitem:a18ee2a3fba2891c00a7a2d126a81b91f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a18ee2a3fba2891c00a7a2d126a81b91f">RTE_USART7_DMA_RX_CH</a>   13</td></tr> 519<tr class="separator:a18ee2a3fba2891c00a7a2d126a81b91f"><td class="memSeparator" colspan="2"> </td></tr> 520<tr class="memitem:a5a048d82fae4604ff6183679a90197c3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5a048d82fae4604ff6183679a90197c3">RTE_USART7_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART7Rx</td></tr> 521<tr class="separator:a5a048d82fae4604ff6183679a90197c3"><td class="memSeparator" colspan="2"> </td></tr> 522<tr class="memitem:a82d952d94e0f421c0928b7bb9271650f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a82d952d94e0f421c0928b7bb9271650f">RTE_USART7_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 523<tr class="separator:a82d952d94e0f421c0928b7bb9271650f"><td class="memSeparator" colspan="2"> </td></tr> 524<tr class="memitem:aff3f3b4435760ac40c7d6a8837642f76"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aff3f3b4435760ac40c7d6a8837642f76">RTE_USART7_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 525<tr class="separator:aff3f3b4435760ac40c7d6a8837642f76"><td class="memSeparator" colspan="2"> </td></tr> 526<tr class="memitem:abcc6c1f63b1f4885829e6b98f2f99230"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#abcc6c1f63b1f4885829e6b98f2f99230">RTE_USART8_DMA_TX_CH</a>   14</td></tr> 527<tr class="separator:abcc6c1f63b1f4885829e6b98f2f99230"><td class="memSeparator" colspan="2"> </td></tr> 528<tr class="memitem:a32cb9cebe1faa5aaa4103e3bbc5053e8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a32cb9cebe1faa5aaa4103e3bbc5053e8">RTE_USART8_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART8Tx</td></tr> 529<tr class="separator:a32cb9cebe1faa5aaa4103e3bbc5053e8"><td class="memSeparator" colspan="2"> </td></tr> 530<tr class="memitem:a8819d5c827bdd7fbdc30d885547cbf0d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a8819d5c827bdd7fbdc30d885547cbf0d">RTE_USART8_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 531<tr class="separator:a8819d5c827bdd7fbdc30d885547cbf0d"><td class="memSeparator" colspan="2"> </td></tr> 532<tr class="memitem:a0bba1923dd63a116b3c4ef8fcebe26c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a0bba1923dd63a116b3c4ef8fcebe26c7">RTE_USART8_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 533<tr class="separator:a0bba1923dd63a116b3c4ef8fcebe26c7"><td class="memSeparator" colspan="2"> </td></tr> 534<tr class="memitem:a2b464e7a19d4ae0e950dac79aff6adbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2b464e7a19d4ae0e950dac79aff6adbc">RTE_USART8_DMA_RX_CH</a>   15</td></tr> 535<tr class="separator:a2b464e7a19d4ae0e950dac79aff6adbc"><td class="memSeparator" colspan="2"> </td></tr> 536<tr class="memitem:a5c16789d134aa6368dbe2d7a7110211c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a5c16789d134aa6368dbe2d7a7110211c">RTE_USART8_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART8Rx</td></tr> 537<tr class="separator:a5c16789d134aa6368dbe2d7a7110211c"><td class="memSeparator" colspan="2"> </td></tr> 538<tr class="memitem:a155ae73ee7cdaff86bb2ddefa2873dcb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a155ae73ee7cdaff86bb2ddefa2873dcb">RTE_USART8_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 539<tr class="separator:a155ae73ee7cdaff86bb2ddefa2873dcb"><td class="memSeparator" colspan="2"> </td></tr> 540<tr class="memitem:a35b22acc74d0ae6d339a14fdebc5e4d5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a35b22acc74d0ae6d339a14fdebc5e4d5">RTE_USART8_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 541<tr class="separator:a35b22acc74d0ae6d339a14fdebc5e4d5"><td class="memSeparator" colspan="2"> </td></tr> 542<tr class="memitem:a3fcb81ca746a43a1ca1437f697eb27fc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a3fcb81ca746a43a1ca1437f697eb27fc">RTE_USART9_DMA_TX_CH</a>   16</td></tr> 543<tr class="separator:a3fcb81ca746a43a1ca1437f697eb27fc"><td class="memSeparator" colspan="2"> </td></tr> 544<tr class="memitem:a97dd4ab8c461b660212839a0a83a8854"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a97dd4ab8c461b660212839a0a83a8854">RTE_USART9_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART9Tx</td></tr> 545<tr class="separator:a97dd4ab8c461b660212839a0a83a8854"><td class="memSeparator" colspan="2"> </td></tr> 546<tr class="memitem:a9501ce390ace1147e1e2b64f2a7e16c7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a9501ce390ace1147e1e2b64f2a7e16c7">RTE_USART9_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 547<tr class="separator:a9501ce390ace1147e1e2b64f2a7e16c7"><td class="memSeparator" colspan="2"> </td></tr> 548<tr class="memitem:a2d6c62e2fc4b1e0a71103c653cbd52cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a2d6c62e2fc4b1e0a71103c653cbd52cd">RTE_USART9_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 549<tr class="separator:a2d6c62e2fc4b1e0a71103c653cbd52cd"><td class="memSeparator" colspan="2"> </td></tr> 550<tr class="memitem:ac9a2bb67aec256c83d9fe501eb43c43b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac9a2bb67aec256c83d9fe501eb43c43b">RTE_USART9_DMA_RX_CH</a>   17</td></tr> 551<tr class="separator:ac9a2bb67aec256c83d9fe501eb43c43b"><td class="memSeparator" colspan="2"> </td></tr> 552<tr class="memitem:ad17f943b2877b59baa700768f299ac1f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad17f943b2877b59baa700768f299ac1f">RTE_USART9_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART9Rx</td></tr> 553<tr class="separator:ad17f943b2877b59baa700768f299ac1f"><td class="memSeparator" colspan="2"> </td></tr> 554<tr class="memitem:a4cf1f6bbfe5beb45a546c685a7832da9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a4cf1f6bbfe5beb45a546c685a7832da9">RTE_USART9_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 555<tr class="separator:a4cf1f6bbfe5beb45a546c685a7832da9"><td class="memSeparator" colspan="2"> </td></tr> 556<tr class="memitem:a3774cca453a9602c146e45d5f3f15744"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a3774cca453a9602c146e45d5f3f15744">RTE_USART9_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 557<tr class="separator:a3774cca453a9602c146e45d5f3f15744"><td class="memSeparator" colspan="2"> </td></tr> 558<tr class="memitem:ac1c4424e09f62bdd3cf7bbb029140c17"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac1c4424e09f62bdd3cf7bbb029140c17">RTE_USART10_DMA_TX_CH</a>   18</td></tr> 559<tr class="separator:ac1c4424e09f62bdd3cf7bbb029140c17"><td class="memSeparator" colspan="2"> </td></tr> 560<tr class="memitem:a9025a7019ac18036afbe7bb6e731e34a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a9025a7019ac18036afbe7bb6e731e34a">RTE_USART10_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART10Tx</td></tr> 561<tr class="separator:a9025a7019ac18036afbe7bb6e731e34a"><td class="memSeparator" colspan="2"> </td></tr> 562<tr class="memitem:a8b82b82de6825554dbc282331be2e14c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a8b82b82de6825554dbc282331be2e14c">RTE_USART10_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 563<tr class="separator:a8b82b82de6825554dbc282331be2e14c"><td class="memSeparator" colspan="2"> </td></tr> 564<tr class="memitem:ac89cc69566cd1ccfbb73b08ebfaf599b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac89cc69566cd1ccfbb73b08ebfaf599b">RTE_USART10_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 565<tr class="separator:ac89cc69566cd1ccfbb73b08ebfaf599b"><td class="memSeparator" colspan="2"> </td></tr> 566<tr class="memitem:aa4a9ae606f683f73cbbd54d10f3ec658"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aa4a9ae606f683f73cbbd54d10f3ec658">RTE_USART10_DMA_RX_CH</a>   19</td></tr> 567<tr class="separator:aa4a9ae606f683f73cbbd54d10f3ec658"><td class="memSeparator" colspan="2"> </td></tr> 568<tr class="memitem:a146ac727fae8b5c5ad182a2790d15ea8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a146ac727fae8b5c5ad182a2790d15ea8">RTE_USART10_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART10Rx</td></tr> 569<tr class="separator:a146ac727fae8b5c5ad182a2790d15ea8"><td class="memSeparator" colspan="2"> </td></tr> 570<tr class="memitem:ac9255f1d8fa4c2b82923fb2cbb5ef01d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac9255f1d8fa4c2b82923fb2cbb5ef01d">RTE_USART10_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 571<tr class="separator:ac9255f1d8fa4c2b82923fb2cbb5ef01d"><td class="memSeparator" colspan="2"> </td></tr> 572<tr class="memitem:ae022eaa77af7a1693a272196ad51950c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ae022eaa77af7a1693a272196ad51950c">RTE_USART10_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 573<tr class="separator:ae022eaa77af7a1693a272196ad51950c"><td class="memSeparator" colspan="2"> </td></tr> 574<tr class="memitem:afef0e458bbb3edb75f54cbc2da697dbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#afef0e458bbb3edb75f54cbc2da697dbc">RTE_USART11_DMA_TX_CH</a>   20</td></tr> 575<tr class="separator:afef0e458bbb3edb75f54cbc2da697dbc"><td class="memSeparator" colspan="2"> </td></tr> 576<tr class="memitem:aae9a792f4082ddbbcaae5b6f848e6eb1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aae9a792f4082ddbbcaae5b6f848e6eb1">RTE_USART11_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART11Tx</td></tr> 577<tr class="separator:aae9a792f4082ddbbcaae5b6f848e6eb1"><td class="memSeparator" colspan="2"> </td></tr> 578<tr class="memitem:a852a29cb0416d2e37e58edc7b1fb3496"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a852a29cb0416d2e37e58edc7b1fb3496">RTE_USART11_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 579<tr class="separator:a852a29cb0416d2e37e58edc7b1fb3496"><td class="memSeparator" colspan="2"> </td></tr> 580<tr class="memitem:afaf6ab6ee029bf827b5cab368b49ee37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#afaf6ab6ee029bf827b5cab368b49ee37">RTE_USART11_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 581<tr class="separator:afaf6ab6ee029bf827b5cab368b49ee37"><td class="memSeparator" colspan="2"> </td></tr> 582<tr class="memitem:a4bfe881bb9c8462aad1bc3f06d0dfc83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a4bfe881bb9c8462aad1bc3f06d0dfc83">RTE_USART11_DMA_RX_CH</a>   21</td></tr> 583<tr class="separator:a4bfe881bb9c8462aad1bc3f06d0dfc83"><td class="memSeparator" colspan="2"> </td></tr> 584<tr class="memitem:ad555cdd0b0ec893ba0cea60976ddcf4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ad555cdd0b0ec893ba0cea60976ddcf4b">RTE_USART11_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART11Rx</td></tr> 585<tr class="separator:ad555cdd0b0ec893ba0cea60976ddcf4b"><td class="memSeparator" colspan="2"> </td></tr> 586<tr class="memitem:ab788dfbb8d8dcbda921836ce50b5dde2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab788dfbb8d8dcbda921836ce50b5dde2">RTE_USART11_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 587<tr class="separator:ab788dfbb8d8dcbda921836ce50b5dde2"><td class="memSeparator" colspan="2"> </td></tr> 588<tr class="memitem:a654d5afcc2b4c510fa9675540c63fb34"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a654d5afcc2b4c510fa9675540c63fb34">RTE_USART11_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 589<tr class="separator:a654d5afcc2b4c510fa9675540c63fb34"><td class="memSeparator" colspan="2"> </td></tr> 590<tr class="memitem:aed212423cf63e159f699aea7e37ce39f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aed212423cf63e159f699aea7e37ce39f">RTE_USART12_DMA_TX_CH</a>   22</td></tr> 591<tr class="separator:aed212423cf63e159f699aea7e37ce39f"><td class="memSeparator" colspan="2"> </td></tr> 592<tr class="memitem:ab12cbeb7458aaf1a1957e008c47a0ab8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ab12cbeb7458aaf1a1957e008c47a0ab8">RTE_USART12_DMA_TX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART12Tx</td></tr> 593<tr class="separator:ab12cbeb7458aaf1a1957e008c47a0ab8"><td class="memSeparator" colspan="2"> </td></tr> 594<tr class="memitem:ac276d7c1ce31e2bede292792eaaebc1e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac276d7c1ce31e2bede292792eaaebc1e">RTE_USART12_DMA_TX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 595<tr class="separator:ac276d7c1ce31e2bede292792eaaebc1e"><td class="memSeparator" colspan="2"> </td></tr> 596<tr class="memitem:ac85dd474fc3f113f46d7e2bae0409164"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac85dd474fc3f113f46d7e2bae0409164">RTE_USART12_DMA_TX_DMA_BASE</a>   DMA0</td></tr> 597<tr class="separator:ac85dd474fc3f113f46d7e2bae0409164"><td class="memSeparator" colspan="2"> </td></tr> 598<tr class="memitem:aae9c7555e205d5ed4749041941268e81"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#aae9c7555e205d5ed4749041941268e81">RTE_USART12_DMA_RX_CH</a>   23</td></tr> 599<tr class="separator:aae9c7555e205d5ed4749041941268e81"><td class="memSeparator" colspan="2"> </td></tr> 600<tr class="memitem:a8507e55c77a9739c3d396b4fb8f8d818"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a8507e55c77a9739c3d396b4fb8f8d818">RTE_USART12_DMA_RX_PERI_SEL</a>   (uint8_t) kDmaRequestMuxLPUART12Rx</td></tr> 601<tr class="separator:a8507e55c77a9739c3d396b4fb8f8d818"><td class="memSeparator" colspan="2"> </td></tr> 602<tr class="memitem:a029a7ee79606fd5cbe7a023ccb95cf62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#a029a7ee79606fd5cbe7a023ccb95cf62">RTE_USART12_DMA_RX_DMAMUX_BASE</a>   DMAMUX0</td></tr> 603<tr class="separator:a029a7ee79606fd5cbe7a023ccb95cf62"><td class="memSeparator" colspan="2"> </td></tr> 604<tr class="memitem:ac4d11009e0e0d76ac14cc3be97f1d920"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04727.html#ac4d11009e0e0d76ac14cc3be97f1d920">RTE_USART12_DMA_RX_DMA_BASE</a>   DMA0</td></tr> 605<tr class="separator:ac4d11009e0e0d76ac14cc3be97f1d920"><td class="memSeparator" colspan="2"> </td></tr> 606</table> 607<h2 class="groupheader">Macro Definition Documentation</h2> 608<a id="aa4264010a207548708e4eb5030b77b42"></a> 609<h2 class="memtitle"><span class="permalink"><a href="#aa4264010a207548708e4eb5030b77b42">◆ </a></span>RTE_I2C1</h2> 610 611<div class="memitem"> 612<div class="memproto"> 613 <table class="memname"> 614 <tr> 615 <td class="memname">#define RTE_I2C1   1</td> 616 </tr> 617 </table> 618</div><div class="memdoc"> 619 620<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00013">13</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 621 622</div> 623</div> 624<a id="aac0deee79f0bfe76842a606f89347141"></a> 625<h2 class="memtitle"><span class="permalink"><a href="#aac0deee79f0bfe76842a606f89347141">◆ </a></span>RTE_I2C1_DMA_EN</h2> 626 627<div class="memitem"> 628<div class="memproto"> 629 <table class="memname"> 630 <tr> 631 <td class="memname">#define RTE_I2C1_DMA_EN   0</td> 632 </tr> 633 </table> 634</div><div class="memdoc"> 635 636<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00014">14</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 637 638</div> 639</div> 640<a id="ac612ac434bff32c83c18d02d2c6c1ec6"></a> 641<h2 class="memtitle"><span class="permalink"><a href="#ac612ac434bff32c83c18d02d2c6c1ec6">◆ </a></span>RTE_I2C1_DMA_RX_CH</h2> 642 643<div class="memitem"> 644<div class="memproto"> 645 <table class="memname"> 646 <tr> 647 <td class="memname">#define RTE_I2C1_DMA_RX_CH   1</td> 648 </tr> 649 </table> 650</div><div class="memdoc"> 651 652<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00069">69</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 653 654</div> 655</div> 656<a id="ae19c26f2205b861f3408141ee8ed7d48"></a> 657<h2 class="memtitle"><span class="permalink"><a href="#ae19c26f2205b861f3408141ee8ed7d48">◆ </a></span>RTE_I2C1_DMA_RX_DMA_BASE</h2> 658 659<div class="memitem"> 660<div class="memproto"> 661 <table class="memname"> 662 <tr> 663 <td class="memname">#define RTE_I2C1_DMA_RX_DMA_BASE   DMA0</td> 664 </tr> 665 </table> 666</div><div class="memdoc"> 667 668<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00072">72</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 669 670</div> 671</div> 672<a id="ab7f7eefcb6f619df42b0730e84bcf2f3"></a> 673<h2 class="memtitle"><span class="permalink"><a href="#ab7f7eefcb6f619df42b0730e84bcf2f3">◆ </a></span>RTE_I2C1_DMA_RX_DMAMUX_BASE</h2> 674 675<div class="memitem"> 676<div class="memproto"> 677 <table class="memname"> 678 <tr> 679 <td class="memname">#define RTE_I2C1_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 680 </tr> 681 </table> 682</div><div class="memdoc"> 683 684<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00071">71</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 685 686</div> 687</div> 688<a id="adedcadc34e22d206d48b9a325155d9b6"></a> 689<h2 class="memtitle"><span class="permalink"><a href="#adedcadc34e22d206d48b9a325155d9b6">◆ </a></span>RTE_I2C1_DMA_RX_PERI_SEL</h2> 690 691<div class="memitem"> 692<div class="memproto"> 693 <table class="memname"> 694 <tr> 695 <td class="memname">#define RTE_I2C1_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C1</td> 696 </tr> 697 </table> 698</div><div class="memdoc"> 699 700<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00070">70</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 701 702</div> 703</div> 704<a id="a922ec75cfe937a214fb6c32fdba48bf6"></a> 705<h2 class="memtitle"><span class="permalink"><a href="#a922ec75cfe937a214fb6c32fdba48bf6">◆ </a></span>RTE_I2C1_DMA_TX_CH</h2> 706 707<div class="memitem"> 708<div class="memproto"> 709 <table class="memname"> 710 <tr> 711 <td class="memname">#define RTE_I2C1_DMA_TX_CH   0</td> 712 </tr> 713 </table> 714</div><div class="memdoc"> 715 716<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00065">65</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 717 718</div> 719</div> 720<a id="afb1a3403b4c83f7db9bc032bf18c552b"></a> 721<h2 class="memtitle"><span class="permalink"><a href="#afb1a3403b4c83f7db9bc032bf18c552b">◆ </a></span>RTE_I2C1_DMA_TX_DMA_BASE</h2> 722 723<div class="memitem"> 724<div class="memproto"> 725 <table class="memname"> 726 <tr> 727 <td class="memname">#define RTE_I2C1_DMA_TX_DMA_BASE   DMA0</td> 728 </tr> 729 </table> 730</div><div class="memdoc"> 731 732<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00068">68</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 733 734</div> 735</div> 736<a id="a031737ed543170a29d6ad6eda661c80b"></a> 737<h2 class="memtitle"><span class="permalink"><a href="#a031737ed543170a29d6ad6eda661c80b">◆ </a></span>RTE_I2C1_DMA_TX_DMAMUX_BASE</h2> 738 739<div class="memitem"> 740<div class="memproto"> 741 <table class="memname"> 742 <tr> 743 <td class="memname">#define RTE_I2C1_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 744 </tr> 745 </table> 746</div><div class="memdoc"> 747 748<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00067">67</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 749 750</div> 751</div> 752<a id="acf249cbd0797a3dce6412b81aba70ee1"></a> 753<h2 class="memtitle"><span class="permalink"><a href="#acf249cbd0797a3dce6412b81aba70ee1">◆ </a></span>RTE_I2C1_DMA_TX_PERI_SEL</h2> 754 755<div class="memitem"> 756<div class="memproto"> 757 <table class="memname"> 758 <tr> 759 <td class="memname">#define RTE_I2C1_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C1</td> 760 </tr> 761 </table> 762</div><div class="memdoc"> 763 764<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00066">66</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 765 766</div> 767</div> 768<a id="a6b312911602934f2275e5bfdd964a3c2"></a> 769<h2 class="memtitle"><span class="permalink"><a href="#a6b312911602934f2275e5bfdd964a3c2">◆ </a></span>RTE_I2C2</h2> 770 771<div class="memitem"> 772<div class="memproto"> 773 <table class="memname"> 774 <tr> 775 <td class="memname">#define RTE_I2C2   0</td> 776 </tr> 777 </table> 778</div><div class="memdoc"> 779 780<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00015">15</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 781 782</div> 783</div> 784<a id="aa6833427b8acb64e5b2cdca71adc4731"></a> 785<h2 class="memtitle"><span class="permalink"><a href="#aa6833427b8acb64e5b2cdca71adc4731">◆ </a></span>RTE_I2C2_DMA_EN</h2> 786 787<div class="memitem"> 788<div class="memproto"> 789 <table class="memname"> 790 <tr> 791 <td class="memname">#define RTE_I2C2_DMA_EN   0</td> 792 </tr> 793 </table> 794</div><div class="memdoc"> 795 796<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00016">16</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 797 798</div> 799</div> 800<a id="a762b3880f4254c392f2f152393776679"></a> 801<h2 class="memtitle"><span class="permalink"><a href="#a762b3880f4254c392f2f152393776679">◆ </a></span>RTE_I2C2_DMA_RX_CH</h2> 802 803<div class="memitem"> 804<div class="memproto"> 805 <table class="memname"> 806 <tr> 807 <td class="memname">#define RTE_I2C2_DMA_RX_CH   3</td> 808 </tr> 809 </table> 810</div><div class="memdoc"> 811 812<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00078">78</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 813 814</div> 815</div> 816<a id="a1ca82c1fea8b1c55875df9cf0e3e4266"></a> 817<h2 class="memtitle"><span class="permalink"><a href="#a1ca82c1fea8b1c55875df9cf0e3e4266">◆ </a></span>RTE_I2C2_DMA_RX_DMA_BASE</h2> 818 819<div class="memitem"> 820<div class="memproto"> 821 <table class="memname"> 822 <tr> 823 <td class="memname">#define RTE_I2C2_DMA_RX_DMA_BASE   DMA0</td> 824 </tr> 825 </table> 826</div><div class="memdoc"> 827 828<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00081">81</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 829 830</div> 831</div> 832<a id="a042db32af91bc5b35e78566581ed403e"></a> 833<h2 class="memtitle"><span class="permalink"><a href="#a042db32af91bc5b35e78566581ed403e">◆ </a></span>RTE_I2C2_DMA_RX_DMAMUX_BASE</h2> 834 835<div class="memitem"> 836<div class="memproto"> 837 <table class="memname"> 838 <tr> 839 <td class="memname">#define RTE_I2C2_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 840 </tr> 841 </table> 842</div><div class="memdoc"> 843 844<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00080">80</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 845 846</div> 847</div> 848<a id="ad7eb717542257f354c6b41ad348a1404"></a> 849<h2 class="memtitle"><span class="permalink"><a href="#ad7eb717542257f354c6b41ad348a1404">◆ </a></span>RTE_I2C2_DMA_RX_PERI_SEL</h2> 850 851<div class="memitem"> 852<div class="memproto"> 853 <table class="memname"> 854 <tr> 855 <td class="memname">#define RTE_I2C2_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C2</td> 856 </tr> 857 </table> 858</div><div class="memdoc"> 859 860<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00079">79</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 861 862</div> 863</div> 864<a id="aaafac93c554b337745d91aeeaa263ee3"></a> 865<h2 class="memtitle"><span class="permalink"><a href="#aaafac93c554b337745d91aeeaa263ee3">◆ </a></span>RTE_I2C2_DMA_TX_CH</h2> 866 867<div class="memitem"> 868<div class="memproto"> 869 <table class="memname"> 870 <tr> 871 <td class="memname">#define RTE_I2C2_DMA_TX_CH   2</td> 872 </tr> 873 </table> 874</div><div class="memdoc"> 875 876<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00074">74</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 877 878</div> 879</div> 880<a id="ad4f1a37be61763d2594b4f539ae03d44"></a> 881<h2 class="memtitle"><span class="permalink"><a href="#ad4f1a37be61763d2594b4f539ae03d44">◆ </a></span>RTE_I2C2_DMA_TX_DMA_BASE</h2> 882 883<div class="memitem"> 884<div class="memproto"> 885 <table class="memname"> 886 <tr> 887 <td class="memname">#define RTE_I2C2_DMA_TX_DMA_BASE   DMA0</td> 888 </tr> 889 </table> 890</div><div class="memdoc"> 891 892<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00077">77</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 893 894</div> 895</div> 896<a id="ac431de1cf16795d33d163d16e67db4ad"></a> 897<h2 class="memtitle"><span class="permalink"><a href="#ac431de1cf16795d33d163d16e67db4ad">◆ </a></span>RTE_I2C2_DMA_TX_DMAMUX_BASE</h2> 898 899<div class="memitem"> 900<div class="memproto"> 901 <table class="memname"> 902 <tr> 903 <td class="memname">#define RTE_I2C2_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 904 </tr> 905 </table> 906</div><div class="memdoc"> 907 908<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00076">76</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 909 910</div> 911</div> 912<a id="a282e3c43099524332084d89c4dc0370a"></a> 913<h2 class="memtitle"><span class="permalink"><a href="#a282e3c43099524332084d89c4dc0370a">◆ </a></span>RTE_I2C2_DMA_TX_PERI_SEL</h2> 914 915<div class="memitem"> 916<div class="memproto"> 917 <table class="memname"> 918 <tr> 919 <td class="memname">#define RTE_I2C2_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C2</td> 920 </tr> 921 </table> 922</div><div class="memdoc"> 923 924<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00075">75</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 925 926</div> 927</div> 928<a id="a286e0b83a4a1806a5125d1e805afed5e"></a> 929<h2 class="memtitle"><span class="permalink"><a href="#a286e0b83a4a1806a5125d1e805afed5e">◆ </a></span>RTE_I2C3</h2> 930 931<div class="memitem"> 932<div class="memproto"> 933 <table class="memname"> 934 <tr> 935 <td class="memname">#define RTE_I2C3   0</td> 936 </tr> 937 </table> 938</div><div class="memdoc"> 939 940<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00017">17</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 941 942</div> 943</div> 944<a id="a7e2203f604dc9bfc5ae76af6364b8e38"></a> 945<h2 class="memtitle"><span class="permalink"><a href="#a7e2203f604dc9bfc5ae76af6364b8e38">◆ </a></span>RTE_I2C3_DMA_EN</h2> 946 947<div class="memitem"> 948<div class="memproto"> 949 <table class="memname"> 950 <tr> 951 <td class="memname">#define RTE_I2C3_DMA_EN   0</td> 952 </tr> 953 </table> 954</div><div class="memdoc"> 955 956<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00018">18</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 957 958</div> 959</div> 960<a id="ac78874337ab81de6e42b051fb9dce871"></a> 961<h2 class="memtitle"><span class="permalink"><a href="#ac78874337ab81de6e42b051fb9dce871">◆ </a></span>RTE_I2C3_DMA_RX_CH</h2> 962 963<div class="memitem"> 964<div class="memproto"> 965 <table class="memname"> 966 <tr> 967 <td class="memname">#define RTE_I2C3_DMA_RX_CH   5</td> 968 </tr> 969 </table> 970</div><div class="memdoc"> 971 972<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00087">87</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 973 974</div> 975</div> 976<a id="acfb03589150d28227ff1dd5393b0b893"></a> 977<h2 class="memtitle"><span class="permalink"><a href="#acfb03589150d28227ff1dd5393b0b893">◆ </a></span>RTE_I2C3_DMA_RX_DMA_BASE</h2> 978 979<div class="memitem"> 980<div class="memproto"> 981 <table class="memname"> 982 <tr> 983 <td class="memname">#define RTE_I2C3_DMA_RX_DMA_BASE   DMA0</td> 984 </tr> 985 </table> 986</div><div class="memdoc"> 987 988<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00090">90</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 989 990</div> 991</div> 992<a id="a24a23c8a15b60cf1095ef24463ff5807"></a> 993<h2 class="memtitle"><span class="permalink"><a href="#a24a23c8a15b60cf1095ef24463ff5807">◆ </a></span>RTE_I2C3_DMA_RX_DMAMUX_BASE</h2> 994 995<div class="memitem"> 996<div class="memproto"> 997 <table class="memname"> 998 <tr> 999 <td class="memname">#define RTE_I2C3_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 1000 </tr> 1001 </table> 1002</div><div class="memdoc"> 1003 1004<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00089">89</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1005 1006</div> 1007</div> 1008<a id="a0994b2eeb8af41123e69175ac6f9c7b0"></a> 1009<h2 class="memtitle"><span class="permalink"><a href="#a0994b2eeb8af41123e69175ac6f9c7b0">◆ </a></span>RTE_I2C3_DMA_RX_PERI_SEL</h2> 1010 1011<div class="memitem"> 1012<div class="memproto"> 1013 <table class="memname"> 1014 <tr> 1015 <td class="memname">#define RTE_I2C3_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C3</td> 1016 </tr> 1017 </table> 1018</div><div class="memdoc"> 1019 1020<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00088">88</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1021 1022</div> 1023</div> 1024<a id="a8d59722d63164553e1aa90f0b5531aa6"></a> 1025<h2 class="memtitle"><span class="permalink"><a href="#a8d59722d63164553e1aa90f0b5531aa6">◆ </a></span>RTE_I2C3_DMA_TX_CH</h2> 1026 1027<div class="memitem"> 1028<div class="memproto"> 1029 <table class="memname"> 1030 <tr> 1031 <td class="memname">#define RTE_I2C3_DMA_TX_CH   4</td> 1032 </tr> 1033 </table> 1034</div><div class="memdoc"> 1035 1036<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00083">83</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1037 1038</div> 1039</div> 1040<a id="a21c43b61ee31798e368937bdbc945eb7"></a> 1041<h2 class="memtitle"><span class="permalink"><a href="#a21c43b61ee31798e368937bdbc945eb7">◆ </a></span>RTE_I2C3_DMA_TX_DMA_BASE</h2> 1042 1043<div class="memitem"> 1044<div class="memproto"> 1045 <table class="memname"> 1046 <tr> 1047 <td class="memname">#define RTE_I2C3_DMA_TX_DMA_BASE   DMA0</td> 1048 </tr> 1049 </table> 1050</div><div class="memdoc"> 1051 1052<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00086">86</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1053 1054</div> 1055</div> 1056<a id="a44e673920f642335b203389fc038fa14"></a> 1057<h2 class="memtitle"><span class="permalink"><a href="#a44e673920f642335b203389fc038fa14">◆ </a></span>RTE_I2C3_DMA_TX_DMAMUX_BASE</h2> 1058 1059<div class="memitem"> 1060<div class="memproto"> 1061 <table class="memname"> 1062 <tr> 1063 <td class="memname">#define RTE_I2C3_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 1064 </tr> 1065 </table> 1066</div><div class="memdoc"> 1067 1068<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00085">85</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1069 1070</div> 1071</div> 1072<a id="a1f3419a15ebd3e7915ab02ddb9d8e57a"></a> 1073<h2 class="memtitle"><span class="permalink"><a href="#a1f3419a15ebd3e7915ab02ddb9d8e57a">◆ </a></span>RTE_I2C3_DMA_TX_PERI_SEL</h2> 1074 1075<div class="memitem"> 1076<div class="memproto"> 1077 <table class="memname"> 1078 <tr> 1079 <td class="memname">#define RTE_I2C3_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C3</td> 1080 </tr> 1081 </table> 1082</div><div class="memdoc"> 1083 1084<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00084">84</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1085 1086</div> 1087</div> 1088<a id="aaefd2724bd50bf611680b12680c5cd47"></a> 1089<h2 class="memtitle"><span class="permalink"><a href="#aaefd2724bd50bf611680b12680c5cd47">◆ </a></span>RTE_I2C4</h2> 1090 1091<div class="memitem"> 1092<div class="memproto"> 1093 <table class="memname"> 1094 <tr> 1095 <td class="memname">#define RTE_I2C4   0</td> 1096 </tr> 1097 </table> 1098</div><div class="memdoc"> 1099 1100<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00019">19</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1101 1102</div> 1103</div> 1104<a id="ad0881b5c0250fd24034d35a0db8e81d6"></a> 1105<h2 class="memtitle"><span class="permalink"><a href="#ad0881b5c0250fd24034d35a0db8e81d6">◆ </a></span>RTE_I2C4_DMA_EN</h2> 1106 1107<div class="memitem"> 1108<div class="memproto"> 1109 <table class="memname"> 1110 <tr> 1111 <td class="memname">#define RTE_I2C4_DMA_EN   0</td> 1112 </tr> 1113 </table> 1114</div><div class="memdoc"> 1115 1116<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00020">20</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1117 1118</div> 1119</div> 1120<a id="adb24a07872f830d773e5a761b5b915ea"></a> 1121<h2 class="memtitle"><span class="permalink"><a href="#adb24a07872f830d773e5a761b5b915ea">◆ </a></span>RTE_I2C4_DMA_RX_CH</h2> 1122 1123<div class="memitem"> 1124<div class="memproto"> 1125 <table class="memname"> 1126 <tr> 1127 <td class="memname">#define RTE_I2C4_DMA_RX_CH   7</td> 1128 </tr> 1129 </table> 1130</div><div class="memdoc"> 1131 1132<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00096">96</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1133 1134</div> 1135</div> 1136<a id="aac8180353fa95d472f154af42998f3ea"></a> 1137<h2 class="memtitle"><span class="permalink"><a href="#aac8180353fa95d472f154af42998f3ea">◆ </a></span>RTE_I2C4_DMA_RX_DMA_BASE</h2> 1138 1139<div class="memitem"> 1140<div class="memproto"> 1141 <table class="memname"> 1142 <tr> 1143 <td class="memname">#define RTE_I2C4_DMA_RX_DMA_BASE   DMA0</td> 1144 </tr> 1145 </table> 1146</div><div class="memdoc"> 1147 1148<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00099">99</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1149 1150</div> 1151</div> 1152<a id="ad22896233f83e8ab47e7102eda51b807"></a> 1153<h2 class="memtitle"><span class="permalink"><a href="#ad22896233f83e8ab47e7102eda51b807">◆ </a></span>RTE_I2C4_DMA_RX_DMAMUX_BASE</h2> 1154 1155<div class="memitem"> 1156<div class="memproto"> 1157 <table class="memname"> 1158 <tr> 1159 <td class="memname">#define RTE_I2C4_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 1160 </tr> 1161 </table> 1162</div><div class="memdoc"> 1163 1164<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00098">98</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1165 1166</div> 1167</div> 1168<a id="aad4b2e8753e39ef0df22e30d47f5af87"></a> 1169<h2 class="memtitle"><span class="permalink"><a href="#aad4b2e8753e39ef0df22e30d47f5af87">◆ </a></span>RTE_I2C4_DMA_RX_PERI_SEL</h2> 1170 1171<div class="memitem"> 1172<div class="memproto"> 1173 <table class="memname"> 1174 <tr> 1175 <td class="memname">#define RTE_I2C4_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C4</td> 1176 </tr> 1177 </table> 1178</div><div class="memdoc"> 1179 1180<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00097">97</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1181 1182</div> 1183</div> 1184<a id="a886533baa3ecbfdc24804b3bbd3c1fa4"></a> 1185<h2 class="memtitle"><span class="permalink"><a href="#a886533baa3ecbfdc24804b3bbd3c1fa4">◆ </a></span>RTE_I2C4_DMA_TX_CH</h2> 1186 1187<div class="memitem"> 1188<div class="memproto"> 1189 <table class="memname"> 1190 <tr> 1191 <td class="memname">#define RTE_I2C4_DMA_TX_CH   6</td> 1192 </tr> 1193 </table> 1194</div><div class="memdoc"> 1195 1196<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00092">92</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1197 1198</div> 1199</div> 1200<a id="a1eeb5eb83698e059c5bbc3df7097102d"></a> 1201<h2 class="memtitle"><span class="permalink"><a href="#a1eeb5eb83698e059c5bbc3df7097102d">◆ </a></span>RTE_I2C4_DMA_TX_DMA_BASE</h2> 1202 1203<div class="memitem"> 1204<div class="memproto"> 1205 <table class="memname"> 1206 <tr> 1207 <td class="memname">#define RTE_I2C4_DMA_TX_DMA_BASE   DMA0</td> 1208 </tr> 1209 </table> 1210</div><div class="memdoc"> 1211 1212<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00095">95</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1213 1214</div> 1215</div> 1216<a id="aa525658413a982f217bdb99ad955080d"></a> 1217<h2 class="memtitle"><span class="permalink"><a href="#aa525658413a982f217bdb99ad955080d">◆ </a></span>RTE_I2C4_DMA_TX_DMAMUX_BASE</h2> 1218 1219<div class="memitem"> 1220<div class="memproto"> 1221 <table class="memname"> 1222 <tr> 1223 <td class="memname">#define RTE_I2C4_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 1224 </tr> 1225 </table> 1226</div><div class="memdoc"> 1227 1228<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00094">94</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1229 1230</div> 1231</div> 1232<a id="acedae977949138b1e4bf418885238855"></a> 1233<h2 class="memtitle"><span class="permalink"><a href="#acedae977949138b1e4bf418885238855">◆ </a></span>RTE_I2C4_DMA_TX_PERI_SEL</h2> 1234 1235<div class="memitem"> 1236<div class="memproto"> 1237 <table class="memname"> 1238 <tr> 1239 <td class="memname">#define RTE_I2C4_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C4</td> 1240 </tr> 1241 </table> 1242</div><div class="memdoc"> 1243 1244<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00093">93</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1245 1246</div> 1247</div> 1248<a id="af34a2837397fb473c1a29f942886f20a"></a> 1249<h2 class="memtitle"><span class="permalink"><a href="#af34a2837397fb473c1a29f942886f20a">◆ </a></span>RTE_I2C5</h2> 1250 1251<div class="memitem"> 1252<div class="memproto"> 1253 <table class="memname"> 1254 <tr> 1255 <td class="memname">#define RTE_I2C5   0</td> 1256 </tr> 1257 </table> 1258</div><div class="memdoc"> 1259 1260<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00021">21</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1261 1262</div> 1263</div> 1264<a id="a11fcca5364c2c59d91dcd1024a3741cd"></a> 1265<h2 class="memtitle"><span class="permalink"><a href="#a11fcca5364c2c59d91dcd1024a3741cd">◆ </a></span>RTE_I2C5_DMA_EN</h2> 1266 1267<div class="memitem"> 1268<div class="memproto"> 1269 <table class="memname"> 1270 <tr> 1271 <td class="memname">#define RTE_I2C5_DMA_EN   0</td> 1272 </tr> 1273 </table> 1274</div><div class="memdoc"> 1275 1276<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00022">22</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1277 1278</div> 1279</div> 1280<a id="a49d74f3d89f709bcee704ed8bc62a389"></a> 1281<h2 class="memtitle"><span class="permalink"><a href="#a49d74f3d89f709bcee704ed8bc62a389">◆ </a></span>RTE_I2C5_DMA_RX_CH</h2> 1282 1283<div class="memitem"> 1284<div class="memproto"> 1285 <table class="memname"> 1286 <tr> 1287 <td class="memname">#define RTE_I2C5_DMA_RX_CH   9</td> 1288 </tr> 1289 </table> 1290</div><div class="memdoc"> 1291 1292<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00105">105</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1293 1294</div> 1295</div> 1296<a id="afffd01e1818a0941804aa6898e0f3480"></a> 1297<h2 class="memtitle"><span class="permalink"><a href="#afffd01e1818a0941804aa6898e0f3480">◆ </a></span>RTE_I2C5_DMA_RX_DMA_BASE</h2> 1298 1299<div class="memitem"> 1300<div class="memproto"> 1301 <table class="memname"> 1302 <tr> 1303 <td class="memname">#define RTE_I2C5_DMA_RX_DMA_BASE   DMA0</td> 1304 </tr> 1305 </table> 1306</div><div class="memdoc"> 1307 1308<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00108">108</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1309 1310</div> 1311</div> 1312<a id="af9e8145e5e8dd332f85fc24a18cb96a1"></a> 1313<h2 class="memtitle"><span class="permalink"><a href="#af9e8145e5e8dd332f85fc24a18cb96a1">◆ </a></span>RTE_I2C5_DMA_RX_DMAMUX_BASE</h2> 1314 1315<div class="memitem"> 1316<div class="memproto"> 1317 <table class="memname"> 1318 <tr> 1319 <td class="memname">#define RTE_I2C5_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 1320 </tr> 1321 </table> 1322</div><div class="memdoc"> 1323 1324<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00107">107</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1325 1326</div> 1327</div> 1328<a id="af9a7eeea936066a06aa12642d206ffe1"></a> 1329<h2 class="memtitle"><span class="permalink"><a href="#af9a7eeea936066a06aa12642d206ffe1">◆ </a></span>RTE_I2C5_DMA_RX_PERI_SEL</h2> 1330 1331<div class="memitem"> 1332<div class="memproto"> 1333 <table class="memname"> 1334 <tr> 1335 <td class="memname">#define RTE_I2C5_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C5</td> 1336 </tr> 1337 </table> 1338</div><div class="memdoc"> 1339 1340<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00106">106</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1341 1342</div> 1343</div> 1344<a id="aacc69b6a58c942604d55ab3c66c18331"></a> 1345<h2 class="memtitle"><span class="permalink"><a href="#aacc69b6a58c942604d55ab3c66c18331">◆ </a></span>RTE_I2C5_DMA_TX_CH</h2> 1346 1347<div class="memitem"> 1348<div class="memproto"> 1349 <table class="memname"> 1350 <tr> 1351 <td class="memname">#define RTE_I2C5_DMA_TX_CH   8</td> 1352 </tr> 1353 </table> 1354</div><div class="memdoc"> 1355 1356<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00101">101</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1357 1358</div> 1359</div> 1360<a id="a237c977557c35a9f367b3dad28755434"></a> 1361<h2 class="memtitle"><span class="permalink"><a href="#a237c977557c35a9f367b3dad28755434">◆ </a></span>RTE_I2C5_DMA_TX_DMA_BASE</h2> 1362 1363<div class="memitem"> 1364<div class="memproto"> 1365 <table class="memname"> 1366 <tr> 1367 <td class="memname">#define RTE_I2C5_DMA_TX_DMA_BASE   DMA0</td> 1368 </tr> 1369 </table> 1370</div><div class="memdoc"> 1371 1372<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00104">104</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1373 1374</div> 1375</div> 1376<a id="adc753a7570b84d60d982dfd4c887628c"></a> 1377<h2 class="memtitle"><span class="permalink"><a href="#adc753a7570b84d60d982dfd4c887628c">◆ </a></span>RTE_I2C5_DMA_TX_DMAMUX_BASE</h2> 1378 1379<div class="memitem"> 1380<div class="memproto"> 1381 <table class="memname"> 1382 <tr> 1383 <td class="memname">#define RTE_I2C5_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 1384 </tr> 1385 </table> 1386</div><div class="memdoc"> 1387 1388<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00103">103</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1389 1390</div> 1391</div> 1392<a id="aae327bc1bd7606f5ce0e12fa22c0c98f"></a> 1393<h2 class="memtitle"><span class="permalink"><a href="#aae327bc1bd7606f5ce0e12fa22c0c98f">◆ </a></span>RTE_I2C5_DMA_TX_PERI_SEL</h2> 1394 1395<div class="memitem"> 1396<div class="memproto"> 1397 <table class="memname"> 1398 <tr> 1399 <td class="memname">#define RTE_I2C5_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C5</td> 1400 </tr> 1401 </table> 1402</div><div class="memdoc"> 1403 1404<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00102">102</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1405 1406</div> 1407</div> 1408<a id="a3def854682bc112f022a79dd60ca29d7"></a> 1409<h2 class="memtitle"><span class="permalink"><a href="#a3def854682bc112f022a79dd60ca29d7">◆ </a></span>RTE_I2C6</h2> 1410 1411<div class="memitem"> 1412<div class="memproto"> 1413 <table class="memname"> 1414 <tr> 1415 <td class="memname">#define RTE_I2C6   0</td> 1416 </tr> 1417 </table> 1418</div><div class="memdoc"> 1419 1420<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00023">23</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1421 1422</div> 1423</div> 1424<a id="a1c6ff3c4d303f391e5ec124aa238c08f"></a> 1425<h2 class="memtitle"><span class="permalink"><a href="#a1c6ff3c4d303f391e5ec124aa238c08f">◆ </a></span>RTE_I2C6_DMA_EN</h2> 1426 1427<div class="memitem"> 1428<div class="memproto"> 1429 <table class="memname"> 1430 <tr> 1431 <td class="memname">#define RTE_I2C6_DMA_EN   0</td> 1432 </tr> 1433 </table> 1434</div><div class="memdoc"> 1435 1436<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00024">24</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1437 1438</div> 1439</div> 1440<a id="adbde0a01f889e105a70dea33e0b774fe"></a> 1441<h2 class="memtitle"><span class="permalink"><a href="#adbde0a01f889e105a70dea33e0b774fe">◆ </a></span>RTE_I2C6_DMA_RX_CH</h2> 1442 1443<div class="memitem"> 1444<div class="memproto"> 1445 <table class="memname"> 1446 <tr> 1447 <td class="memname">#define RTE_I2C6_DMA_RX_CH   11</td> 1448 </tr> 1449 </table> 1450</div><div class="memdoc"> 1451 1452<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00114">114</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1453 1454</div> 1455</div> 1456<a id="afdf4039762fae0cda1db8c9ea184e641"></a> 1457<h2 class="memtitle"><span class="permalink"><a href="#afdf4039762fae0cda1db8c9ea184e641">◆ </a></span>RTE_I2C6_DMA_RX_DMA_BASE</h2> 1458 1459<div class="memitem"> 1460<div class="memproto"> 1461 <table class="memname"> 1462 <tr> 1463 <td class="memname">#define RTE_I2C6_DMA_RX_DMA_BASE   DMA0</td> 1464 </tr> 1465 </table> 1466</div><div class="memdoc"> 1467 1468<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00117">117</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1469 1470</div> 1471</div> 1472<a id="a73fd097ff81b41936c278b29bc2ad4eb"></a> 1473<h2 class="memtitle"><span class="permalink"><a href="#a73fd097ff81b41936c278b29bc2ad4eb">◆ </a></span>RTE_I2C6_DMA_RX_DMAMUX_BASE</h2> 1474 1475<div class="memitem"> 1476<div class="memproto"> 1477 <table class="memname"> 1478 <tr> 1479 <td class="memname">#define RTE_I2C6_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 1480 </tr> 1481 </table> 1482</div><div class="memdoc"> 1483 1484<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00116">116</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1485 1486</div> 1487</div> 1488<a id="a18a0ead9ea40c2c592a5a3a73d4f3916"></a> 1489<h2 class="memtitle"><span class="permalink"><a href="#a18a0ead9ea40c2c592a5a3a73d4f3916">◆ </a></span>RTE_I2C6_DMA_RX_PERI_SEL</h2> 1490 1491<div class="memitem"> 1492<div class="memproto"> 1493 <table class="memname"> 1494 <tr> 1495 <td class="memname">#define RTE_I2C6_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C6</td> 1496 </tr> 1497 </table> 1498</div><div class="memdoc"> 1499 1500<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00115">115</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1501 1502</div> 1503</div> 1504<a id="aa15456a15715d87b5d9fd1663b6def21"></a> 1505<h2 class="memtitle"><span class="permalink"><a href="#aa15456a15715d87b5d9fd1663b6def21">◆ </a></span>RTE_I2C6_DMA_TX_CH</h2> 1506 1507<div class="memitem"> 1508<div class="memproto"> 1509 <table class="memname"> 1510 <tr> 1511 <td class="memname">#define RTE_I2C6_DMA_TX_CH   10</td> 1512 </tr> 1513 </table> 1514</div><div class="memdoc"> 1515 1516<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00110">110</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1517 1518</div> 1519</div> 1520<a id="a3beb3f0a50107be726578869d167101a"></a> 1521<h2 class="memtitle"><span class="permalink"><a href="#a3beb3f0a50107be726578869d167101a">◆ </a></span>RTE_I2C6_DMA_TX_DMA_BASE</h2> 1522 1523<div class="memitem"> 1524<div class="memproto"> 1525 <table class="memname"> 1526 <tr> 1527 <td class="memname">#define RTE_I2C6_DMA_TX_DMA_BASE   DMA0</td> 1528 </tr> 1529 </table> 1530</div><div class="memdoc"> 1531 1532<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00113">113</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1533 1534</div> 1535</div> 1536<a id="aba9fea9269019c4c2148393ec799bfb7"></a> 1537<h2 class="memtitle"><span class="permalink"><a href="#aba9fea9269019c4c2148393ec799bfb7">◆ </a></span>RTE_I2C6_DMA_TX_DMAMUX_BASE</h2> 1538 1539<div class="memitem"> 1540<div class="memproto"> 1541 <table class="memname"> 1542 <tr> 1543 <td class="memname">#define RTE_I2C6_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 1544 </tr> 1545 </table> 1546</div><div class="memdoc"> 1547 1548<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00112">112</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1549 1550</div> 1551</div> 1552<a id="a3376a9bd3c4accdc4e0d25251960563b"></a> 1553<h2 class="memtitle"><span class="permalink"><a href="#a3376a9bd3c4accdc4e0d25251960563b">◆ </a></span>RTE_I2C6_DMA_TX_PERI_SEL</h2> 1554 1555<div class="memitem"> 1556<div class="memproto"> 1557 <table class="memname"> 1558 <tr> 1559 <td class="memname">#define RTE_I2C6_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPI2C6</td> 1560 </tr> 1561 </table> 1562</div><div class="memdoc"> 1563 1564<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00111">111</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1565 1566</div> 1567</div> 1568<a id="adc244beab1014dda00966fcbbb65578c"></a> 1569<h2 class="memtitle"><span class="permalink"><a href="#adc244beab1014dda00966fcbbb65578c">◆ </a></span>RTE_SPI1</h2> 1570 1571<div class="memitem"> 1572<div class="memproto"> 1573 <table class="memname"> 1574 <tr> 1575 <td class="memname">#define RTE_SPI1   1</td> 1576 </tr> 1577 </table> 1578</div><div class="memdoc"> 1579 1580<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00026">26</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1581 1582</div> 1583</div> 1584<a id="a951ee008b6f3fccf7c09fb32ef53b288"></a> 1585<h2 class="memtitle"><span class="permalink"><a href="#a951ee008b6f3fccf7c09fb32ef53b288">◆ </a></span>RTE_SPI1_BETWEEN_TRANSFER_DELAY</h2> 1586 1587<div class="memitem"> 1588<div class="memproto"> 1589 <table class="memname"> 1590 <tr> 1591 <td class="memname">#define RTE_SPI1_BETWEEN_TRANSFER_DELAY   1000</td> 1592 </tr> 1593 </table> 1594</div><div class="memdoc"> 1595 1596<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00122">122</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1597 1598</div> 1599</div> 1600<a id="aa77f48b8f0f046f17b57ee388ba986c3"></a> 1601<h2 class="memtitle"><span class="permalink"><a href="#aa77f48b8f0f046f17b57ee388ba986c3">◆ </a></span>RTE_SPI1_DMA_EN</h2> 1602 1603<div class="memitem"> 1604<div class="memproto"> 1605 <table class="memname"> 1606 <tr> 1607 <td class="memname">#define RTE_SPI1_DMA_EN   0</td> 1608 </tr> 1609 </table> 1610</div><div class="memdoc"> 1611 1612<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00027">27</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1613 1614</div> 1615</div> 1616<a id="a237cd1f72122246b424ced52d44d7374"></a> 1617<h2 class="memtitle"><span class="permalink"><a href="#a237cd1f72122246b424ced52d44d7374">◆ </a></span>RTE_SPI1_DMA_RX_CH</h2> 1618 1619<div class="memitem"> 1620<div class="memproto"> 1621 <table class="memname"> 1622 <tr> 1623 <td class="memname">#define RTE_SPI1_DMA_RX_CH   1</td> 1624 </tr> 1625 </table> 1626</div><div class="memdoc"> 1627 1628<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00129">129</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1629 1630</div> 1631</div> 1632<a id="a08060b8c17ac92da6cde2af7d67ee095"></a> 1633<h2 class="memtitle"><span class="permalink"><a href="#a08060b8c17ac92da6cde2af7d67ee095">◆ </a></span>RTE_SPI1_DMA_RX_DMA_BASE</h2> 1634 1635<div class="memitem"> 1636<div class="memproto"> 1637 <table class="memname"> 1638 <tr> 1639 <td class="memname">#define RTE_SPI1_DMA_RX_DMA_BASE   DMA0</td> 1640 </tr> 1641 </table> 1642</div><div class="memdoc"> 1643 1644<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00132">132</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1645 1646</div> 1647</div> 1648<a id="a092a5b393859e6a07fc97a666e3841f9"></a> 1649<h2 class="memtitle"><span class="permalink"><a href="#a092a5b393859e6a07fc97a666e3841f9">◆ </a></span>RTE_SPI1_DMA_RX_DMAMUX_BASE</h2> 1650 1651<div class="memitem"> 1652<div class="memproto"> 1653 <table class="memname"> 1654 <tr> 1655 <td class="memname">#define RTE_SPI1_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 1656 </tr> 1657 </table> 1658</div><div class="memdoc"> 1659 1660<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00131">131</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1661 1662</div> 1663</div> 1664<a id="a1675b80e211aeb65f52be311273d1054"></a> 1665<h2 class="memtitle"><span class="permalink"><a href="#a1675b80e211aeb65f52be311273d1054">◆ </a></span>RTE_SPI1_DMA_RX_PERI_SEL</h2> 1666 1667<div class="memitem"> 1668<div class="memproto"> 1669 <table class="memname"> 1670 <tr> 1671 <td class="memname">#define RTE_SPI1_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI1Rx</td> 1672 </tr> 1673 </table> 1674</div><div class="memdoc"> 1675 1676<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00130">130</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1677 1678</div> 1679</div> 1680<a id="af7837804201c3faa8cb122bafb79b78a"></a> 1681<h2 class="memtitle"><span class="permalink"><a href="#af7837804201c3faa8cb122bafb79b78a">◆ </a></span>RTE_SPI1_DMA_TX_CH</h2> 1682 1683<div class="memitem"> 1684<div class="memproto"> 1685 <table class="memname"> 1686 <tr> 1687 <td class="memname">#define RTE_SPI1_DMA_TX_CH   0</td> 1688 </tr> 1689 </table> 1690</div><div class="memdoc"> 1691 1692<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00125">125</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1693 1694</div> 1695</div> 1696<a id="a2510e3e47782aa110b9863228c6b20ff"></a> 1697<h2 class="memtitle"><span class="permalink"><a href="#a2510e3e47782aa110b9863228c6b20ff">◆ </a></span>RTE_SPI1_DMA_TX_DMA_BASE</h2> 1698 1699<div class="memitem"> 1700<div class="memproto"> 1701 <table class="memname"> 1702 <tr> 1703 <td class="memname">#define RTE_SPI1_DMA_TX_DMA_BASE   DMA0</td> 1704 </tr> 1705 </table> 1706</div><div class="memdoc"> 1707 1708<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00128">128</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1709 1710</div> 1711</div> 1712<a id="a808f6eb3a927615c6881d185981238c8"></a> 1713<h2 class="memtitle"><span class="permalink"><a href="#a808f6eb3a927615c6881d185981238c8">◆ </a></span>RTE_SPI1_DMA_TX_DMAMUX_BASE</h2> 1714 1715<div class="memitem"> 1716<div class="memproto"> 1717 <table class="memname"> 1718 <tr> 1719 <td class="memname">#define RTE_SPI1_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 1720 </tr> 1721 </table> 1722</div><div class="memdoc"> 1723 1724<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00127">127</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1725 1726</div> 1727</div> 1728<a id="adacfa67a7428af81b9a41471e1c52a15"></a> 1729<h2 class="memtitle"><span class="permalink"><a href="#adacfa67a7428af81b9a41471e1c52a15">◆ </a></span>RTE_SPI1_DMA_TX_PERI_SEL</h2> 1730 1731<div class="memitem"> 1732<div class="memproto"> 1733 <table class="memname"> 1734 <tr> 1735 <td class="memname">#define RTE_SPI1_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI1Tx</td> 1736 </tr> 1737 </table> 1738</div><div class="memdoc"> 1739 1740<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00126">126</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1741 1742</div> 1743</div> 1744<a id="a0e587c674c92f4898da5f4a2dd7da875"></a> 1745<h2 class="memtitle"><span class="permalink"><a href="#a0e587c674c92f4898da5f4a2dd7da875">◆ </a></span>RTE_SPI1_MASTER_PCS_PIN_SEL</h2> 1746 1747<div class="memitem"> 1748<div class="memproto"> 1749 <table class="memname"> 1750 <tr> 1751 <td class="memname">#define RTE_SPI1_MASTER_PCS_PIN_SEL   (kLPSPI_MasterPcs0)</td> 1752 </tr> 1753 </table> 1754</div><div class="memdoc"> 1755 1756<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00123">123</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1757 1758</div> 1759</div> 1760<a id="a30ffc6ece84420ad1bb78ad539a527ae"></a> 1761<h2 class="memtitle"><span class="permalink"><a href="#a30ffc6ece84420ad1bb78ad539a527ae">◆ </a></span>RTE_SPI1_PCS_TO_SCK_DELAY</h2> 1762 1763<div class="memitem"> 1764<div class="memproto"> 1765 <table class="memname"> 1766 <tr> 1767 <td class="memname">#define RTE_SPI1_PCS_TO_SCK_DELAY   1000</td> 1768 </tr> 1769 </table> 1770</div><div class="memdoc"> 1771 1772<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00120">120</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1773 1774</div> 1775</div> 1776<a id="a88c1db58a1c06f875bdec06c74b85072"></a> 1777<h2 class="memtitle"><span class="permalink"><a href="#a88c1db58a1c06f875bdec06c74b85072">◆ </a></span>RTE_SPI1_SCK_TO_PSC_DELAY</h2> 1778 1779<div class="memitem"> 1780<div class="memproto"> 1781 <table class="memname"> 1782 <tr> 1783 <td class="memname">#define RTE_SPI1_SCK_TO_PSC_DELAY   1000</td> 1784 </tr> 1785 </table> 1786</div><div class="memdoc"> 1787 1788<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00121">121</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1789 1790</div> 1791</div> 1792<a id="a5b23957d812a8a11c221bee23ddbe2a7"></a> 1793<h2 class="memtitle"><span class="permalink"><a href="#a5b23957d812a8a11c221bee23ddbe2a7">◆ </a></span>RTE_SPI1_SLAVE_PCS_PIN_SEL</h2> 1794 1795<div class="memitem"> 1796<div class="memproto"> 1797 <table class="memname"> 1798 <tr> 1799 <td class="memname">#define RTE_SPI1_SLAVE_PCS_PIN_SEL   (kLPSPI_SlavePcs0)</td> 1800 </tr> 1801 </table> 1802</div><div class="memdoc"> 1803 1804<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00124">124</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1805 1806</div> 1807</div> 1808<a id="a23c083e17af81df6307b6a09c7b526bd"></a> 1809<h2 class="memtitle"><span class="permalink"><a href="#a23c083e17af81df6307b6a09c7b526bd">◆ </a></span>RTE_SPI2</h2> 1810 1811<div class="memitem"> 1812<div class="memproto"> 1813 <table class="memname"> 1814 <tr> 1815 <td class="memname">#define RTE_SPI2   0</td> 1816 </tr> 1817 </table> 1818</div><div class="memdoc"> 1819 1820<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00028">28</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1821 1822</div> 1823</div> 1824<a id="a99923674038030fbcc6c203a048e7092"></a> 1825<h2 class="memtitle"><span class="permalink"><a href="#a99923674038030fbcc6c203a048e7092">◆ </a></span>RTE_SPI2_BETWEEN_TRANSFER_DELAY</h2> 1826 1827<div class="memitem"> 1828<div class="memproto"> 1829 <table class="memname"> 1830 <tr> 1831 <td class="memname">#define RTE_SPI2_BETWEEN_TRANSFER_DELAY   1000</td> 1832 </tr> 1833 </table> 1834</div><div class="memdoc"> 1835 1836<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00136">136</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1837 1838</div> 1839</div> 1840<a id="af6ec6eb776de0e8df30bc2acc19f9221"></a> 1841<h2 class="memtitle"><span class="permalink"><a href="#af6ec6eb776de0e8df30bc2acc19f9221">◆ </a></span>RTE_SPI2_DMA_EN</h2> 1842 1843<div class="memitem"> 1844<div class="memproto"> 1845 <table class="memname"> 1846 <tr> 1847 <td class="memname">#define RTE_SPI2_DMA_EN   0</td> 1848 </tr> 1849 </table> 1850</div><div class="memdoc"> 1851 1852<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00029">29</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1853 1854</div> 1855</div> 1856<a id="a2e9a89fc7b4cd0e7b9ddbd9dc747ea84"></a> 1857<h2 class="memtitle"><span class="permalink"><a href="#a2e9a89fc7b4cd0e7b9ddbd9dc747ea84">◆ </a></span>RTE_SPI2_DMA_RX_CH</h2> 1858 1859<div class="memitem"> 1860<div class="memproto"> 1861 <table class="memname"> 1862 <tr> 1863 <td class="memname">#define RTE_SPI2_DMA_RX_CH   3</td> 1864 </tr> 1865 </table> 1866</div><div class="memdoc"> 1867 1868<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00143">143</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1869 1870</div> 1871</div> 1872<a id="ae14cfbbd7990b4e16da76447fd0f71d0"></a> 1873<h2 class="memtitle"><span class="permalink"><a href="#ae14cfbbd7990b4e16da76447fd0f71d0">◆ </a></span>RTE_SPI2_DMA_RX_DMA_BASE</h2> 1874 1875<div class="memitem"> 1876<div class="memproto"> 1877 <table class="memname"> 1878 <tr> 1879 <td class="memname">#define RTE_SPI2_DMA_RX_DMA_BASE   DMA0</td> 1880 </tr> 1881 </table> 1882</div><div class="memdoc"> 1883 1884<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00146">146</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1885 1886</div> 1887</div> 1888<a id="a83c234032df3316eea62c35db921df98"></a> 1889<h2 class="memtitle"><span class="permalink"><a href="#a83c234032df3316eea62c35db921df98">◆ </a></span>RTE_SPI2_DMA_RX_DMAMUX_BASE</h2> 1890 1891<div class="memitem"> 1892<div class="memproto"> 1893 <table class="memname"> 1894 <tr> 1895 <td class="memname">#define RTE_SPI2_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 1896 </tr> 1897 </table> 1898</div><div class="memdoc"> 1899 1900<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00145">145</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1901 1902</div> 1903</div> 1904<a id="a819c248900eebba240a37d7c57ab5408"></a> 1905<h2 class="memtitle"><span class="permalink"><a href="#a819c248900eebba240a37d7c57ab5408">◆ </a></span>RTE_SPI2_DMA_RX_PERI_SEL</h2> 1906 1907<div class="memitem"> 1908<div class="memproto"> 1909 <table class="memname"> 1910 <tr> 1911 <td class="memname">#define RTE_SPI2_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI2Tx</td> 1912 </tr> 1913 </table> 1914</div><div class="memdoc"> 1915 1916<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00144">144</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1917 1918</div> 1919</div> 1920<a id="a2f55409f83ccf9410d19a06c89592cf7"></a> 1921<h2 class="memtitle"><span class="permalink"><a href="#a2f55409f83ccf9410d19a06c89592cf7">◆ </a></span>RTE_SPI2_DMA_TX_CH</h2> 1922 1923<div class="memitem"> 1924<div class="memproto"> 1925 <table class="memname"> 1926 <tr> 1927 <td class="memname">#define RTE_SPI2_DMA_TX_CH   2</td> 1928 </tr> 1929 </table> 1930</div><div class="memdoc"> 1931 1932<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00139">139</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1933 1934</div> 1935</div> 1936<a id="ad2c8040af8a79e4d3817c130ac28df6d"></a> 1937<h2 class="memtitle"><span class="permalink"><a href="#ad2c8040af8a79e4d3817c130ac28df6d">◆ </a></span>RTE_SPI2_DMA_TX_DMA_BASE</h2> 1938 1939<div class="memitem"> 1940<div class="memproto"> 1941 <table class="memname"> 1942 <tr> 1943 <td class="memname">#define RTE_SPI2_DMA_TX_DMA_BASE   DMA0</td> 1944 </tr> 1945 </table> 1946</div><div class="memdoc"> 1947 1948<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00142">142</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1949 1950</div> 1951</div> 1952<a id="a33414279775ff91c959e0d6238f6f5a8"></a> 1953<h2 class="memtitle"><span class="permalink"><a href="#a33414279775ff91c959e0d6238f6f5a8">◆ </a></span>RTE_SPI2_DMA_TX_DMAMUX_BASE</h2> 1954 1955<div class="memitem"> 1956<div class="memproto"> 1957 <table class="memname"> 1958 <tr> 1959 <td class="memname">#define RTE_SPI2_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 1960 </tr> 1961 </table> 1962</div><div class="memdoc"> 1963 1964<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00141">141</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1965 1966</div> 1967</div> 1968<a id="a18b7f6d5915fbcbed92062f953c23b73"></a> 1969<h2 class="memtitle"><span class="permalink"><a href="#a18b7f6d5915fbcbed92062f953c23b73">◆ </a></span>RTE_SPI2_DMA_TX_PERI_SEL</h2> 1970 1971<div class="memitem"> 1972<div class="memproto"> 1973 <table class="memname"> 1974 <tr> 1975 <td class="memname">#define RTE_SPI2_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI2Tx</td> 1976 </tr> 1977 </table> 1978</div><div class="memdoc"> 1979 1980<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00140">140</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1981 1982</div> 1983</div> 1984<a id="aaf87c891b68f466cded78517bda33f66"></a> 1985<h2 class="memtitle"><span class="permalink"><a href="#aaf87c891b68f466cded78517bda33f66">◆ </a></span>RTE_SPI2_MASTER_PCS_PIN_SEL</h2> 1986 1987<div class="memitem"> 1988<div class="memproto"> 1989 <table class="memname"> 1990 <tr> 1991 <td class="memname">#define RTE_SPI2_MASTER_PCS_PIN_SEL   (kLPSPI_MasterPcs0)</td> 1992 </tr> 1993 </table> 1994</div><div class="memdoc"> 1995 1996<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00137">137</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 1997 1998</div> 1999</div> 2000<a id="ae3c6c661ee5134156e7083458fa9d0d0"></a> 2001<h2 class="memtitle"><span class="permalink"><a href="#ae3c6c661ee5134156e7083458fa9d0d0">◆ </a></span>RTE_SPI2_PCS_TO_SCK_DELAY</h2> 2002 2003<div class="memitem"> 2004<div class="memproto"> 2005 <table class="memname"> 2006 <tr> 2007 <td class="memname">#define RTE_SPI2_PCS_TO_SCK_DELAY   1000</td> 2008 </tr> 2009 </table> 2010</div><div class="memdoc"> 2011 2012<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00134">134</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2013 2014</div> 2015</div> 2016<a id="a5f946c38b63485806d78f455fb199c36"></a> 2017<h2 class="memtitle"><span class="permalink"><a href="#a5f946c38b63485806d78f455fb199c36">◆ </a></span>RTE_SPI2_SCK_TO_PSC_DELAY</h2> 2018 2019<div class="memitem"> 2020<div class="memproto"> 2021 <table class="memname"> 2022 <tr> 2023 <td class="memname">#define RTE_SPI2_SCK_TO_PSC_DELAY   1000</td> 2024 </tr> 2025 </table> 2026</div><div class="memdoc"> 2027 2028<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00135">135</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2029 2030</div> 2031</div> 2032<a id="a50c8dea7ad8a4df3477cc5ec811a7726"></a> 2033<h2 class="memtitle"><span class="permalink"><a href="#a50c8dea7ad8a4df3477cc5ec811a7726">◆ </a></span>RTE_SPI2_SLAVE_PCS_PIN_SEL</h2> 2034 2035<div class="memitem"> 2036<div class="memproto"> 2037 <table class="memname"> 2038 <tr> 2039 <td class="memname">#define RTE_SPI2_SLAVE_PCS_PIN_SEL   (kLPSPI_SlavePcs0)</td> 2040 </tr> 2041 </table> 2042</div><div class="memdoc"> 2043 2044<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00138">138</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2045 2046</div> 2047</div> 2048<a id="aa78a035aaa73a024f3e9ad91e3d28c18"></a> 2049<h2 class="memtitle"><span class="permalink"><a href="#aa78a035aaa73a024f3e9ad91e3d28c18">◆ </a></span>RTE_SPI3</h2> 2050 2051<div class="memitem"> 2052<div class="memproto"> 2053 <table class="memname"> 2054 <tr> 2055 <td class="memname">#define RTE_SPI3   0</td> 2056 </tr> 2057 </table> 2058</div><div class="memdoc"> 2059 2060<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00030">30</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2061 2062</div> 2063</div> 2064<a id="aea2bec62dec8ae43dd4866d04a7a210f"></a> 2065<h2 class="memtitle"><span class="permalink"><a href="#aea2bec62dec8ae43dd4866d04a7a210f">◆ </a></span>RTE_SPI3_BETWEEN_TRANSFER_DELAY</h2> 2066 2067<div class="memitem"> 2068<div class="memproto"> 2069 <table class="memname"> 2070 <tr> 2071 <td class="memname">#define RTE_SPI3_BETWEEN_TRANSFER_DELAY   1000</td> 2072 </tr> 2073 </table> 2074</div><div class="memdoc"> 2075 2076<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00150">150</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2077 2078</div> 2079</div> 2080<a id="a262ea23b85408aacef35d7dea979abfd"></a> 2081<h2 class="memtitle"><span class="permalink"><a href="#a262ea23b85408aacef35d7dea979abfd">◆ </a></span>RTE_SPI3_DMA_EN</h2> 2082 2083<div class="memitem"> 2084<div class="memproto"> 2085 <table class="memname"> 2086 <tr> 2087 <td class="memname">#define RTE_SPI3_DMA_EN   0</td> 2088 </tr> 2089 </table> 2090</div><div class="memdoc"> 2091 2092<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00031">31</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2093 2094</div> 2095</div> 2096<a id="adb5a87ba91d16c71a803610ffbf40c13"></a> 2097<h2 class="memtitle"><span class="permalink"><a href="#adb5a87ba91d16c71a803610ffbf40c13">◆ </a></span>RTE_SPI3_DMA_RX_CH</h2> 2098 2099<div class="memitem"> 2100<div class="memproto"> 2101 <table class="memname"> 2102 <tr> 2103 <td class="memname">#define RTE_SPI3_DMA_RX_CH   5</td> 2104 </tr> 2105 </table> 2106</div><div class="memdoc"> 2107 2108<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00157">157</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2109 2110</div> 2111</div> 2112<a id="aad946150307e0a2d3f1e4e030550dc68"></a> 2113<h2 class="memtitle"><span class="permalink"><a href="#aad946150307e0a2d3f1e4e030550dc68">◆ </a></span>RTE_SPI3_DMA_RX_DMA_BASE</h2> 2114 2115<div class="memitem"> 2116<div class="memproto"> 2117 <table class="memname"> 2118 <tr> 2119 <td class="memname">#define RTE_SPI3_DMA_RX_DMA_BASE   DMA0</td> 2120 </tr> 2121 </table> 2122</div><div class="memdoc"> 2123 2124<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00160">160</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2125 2126</div> 2127</div> 2128<a id="ae8eb8e1701ada3c43faacf46f163c1f5"></a> 2129<h2 class="memtitle"><span class="permalink"><a href="#ae8eb8e1701ada3c43faacf46f163c1f5">◆ </a></span>RTE_SPI3_DMA_RX_DMAMUX_BASE</h2> 2130 2131<div class="memitem"> 2132<div class="memproto"> 2133 <table class="memname"> 2134 <tr> 2135 <td class="memname">#define RTE_SPI3_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 2136 </tr> 2137 </table> 2138</div><div class="memdoc"> 2139 2140<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00159">159</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2141 2142</div> 2143</div> 2144<a id="a1a3261f383900579c450e714a8c9c4e9"></a> 2145<h2 class="memtitle"><span class="permalink"><a href="#a1a3261f383900579c450e714a8c9c4e9">◆ </a></span>RTE_SPI3_DMA_RX_PERI_SEL</h2> 2146 2147<div class="memitem"> 2148<div class="memproto"> 2149 <table class="memname"> 2150 <tr> 2151 <td class="memname">#define RTE_SPI3_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI3Rx</td> 2152 </tr> 2153 </table> 2154</div><div class="memdoc"> 2155 2156<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00158">158</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2157 2158</div> 2159</div> 2160<a id="aede43b66781471d6f7824e1d8a5d678a"></a> 2161<h2 class="memtitle"><span class="permalink"><a href="#aede43b66781471d6f7824e1d8a5d678a">◆ </a></span>RTE_SPI3_DMA_TX_CH</h2> 2162 2163<div class="memitem"> 2164<div class="memproto"> 2165 <table class="memname"> 2166 <tr> 2167 <td class="memname">#define RTE_SPI3_DMA_TX_CH   4</td> 2168 </tr> 2169 </table> 2170</div><div class="memdoc"> 2171 2172<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00153">153</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2173 2174</div> 2175</div> 2176<a id="a9237e29a834083e9cff82ba51800ec0d"></a> 2177<h2 class="memtitle"><span class="permalink"><a href="#a9237e29a834083e9cff82ba51800ec0d">◆ </a></span>RTE_SPI3_DMA_TX_DMA_BASE</h2> 2178 2179<div class="memitem"> 2180<div class="memproto"> 2181 <table class="memname"> 2182 <tr> 2183 <td class="memname">#define RTE_SPI3_DMA_TX_DMA_BASE   DMA0</td> 2184 </tr> 2185 </table> 2186</div><div class="memdoc"> 2187 2188<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00156">156</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2189 2190</div> 2191</div> 2192<a id="a957637aad66f6d5deed94db4d18e3ca8"></a> 2193<h2 class="memtitle"><span class="permalink"><a href="#a957637aad66f6d5deed94db4d18e3ca8">◆ </a></span>RTE_SPI3_DMA_TX_DMAMUX_BASE</h2> 2194 2195<div class="memitem"> 2196<div class="memproto"> 2197 <table class="memname"> 2198 <tr> 2199 <td class="memname">#define RTE_SPI3_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 2200 </tr> 2201 </table> 2202</div><div class="memdoc"> 2203 2204<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00155">155</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2205 2206</div> 2207</div> 2208<a id="a7a1d1794b26a340e85bd3569d80b1470"></a> 2209<h2 class="memtitle"><span class="permalink"><a href="#a7a1d1794b26a340e85bd3569d80b1470">◆ </a></span>RTE_SPI3_DMA_TX_PERI_SEL</h2> 2210 2211<div class="memitem"> 2212<div class="memproto"> 2213 <table class="memname"> 2214 <tr> 2215 <td class="memname">#define RTE_SPI3_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI3Tx</td> 2216 </tr> 2217 </table> 2218</div><div class="memdoc"> 2219 2220<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00154">154</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2221 2222</div> 2223</div> 2224<a id="ae246a17a5a03704c5f4d44cd40df50d7"></a> 2225<h2 class="memtitle"><span class="permalink"><a href="#ae246a17a5a03704c5f4d44cd40df50d7">◆ </a></span>RTE_SPI3_MASTER_PCS_PIN_SEL</h2> 2226 2227<div class="memitem"> 2228<div class="memproto"> 2229 <table class="memname"> 2230 <tr> 2231 <td class="memname">#define RTE_SPI3_MASTER_PCS_PIN_SEL   (kLPSPI_MasterPcs0)</td> 2232 </tr> 2233 </table> 2234</div><div class="memdoc"> 2235 2236<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00151">151</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2237 2238</div> 2239</div> 2240<a id="aa73000740183c3947717fa583d165815"></a> 2241<h2 class="memtitle"><span class="permalink"><a href="#aa73000740183c3947717fa583d165815">◆ </a></span>RTE_SPI3_PCS_TO_SCK_DELAY</h2> 2242 2243<div class="memitem"> 2244<div class="memproto"> 2245 <table class="memname"> 2246 <tr> 2247 <td class="memname">#define RTE_SPI3_PCS_TO_SCK_DELAY   1000</td> 2248 </tr> 2249 </table> 2250</div><div class="memdoc"> 2251 2252<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00148">148</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2253 2254</div> 2255</div> 2256<a id="a0e7623e6ba7a9f5e22314ffd3cedba06"></a> 2257<h2 class="memtitle"><span class="permalink"><a href="#a0e7623e6ba7a9f5e22314ffd3cedba06">◆ </a></span>RTE_SPI3_SCK_TO_PSC_DELAY</h2> 2258 2259<div class="memitem"> 2260<div class="memproto"> 2261 <table class="memname"> 2262 <tr> 2263 <td class="memname">#define RTE_SPI3_SCK_TO_PSC_DELAY   1000</td> 2264 </tr> 2265 </table> 2266</div><div class="memdoc"> 2267 2268<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00149">149</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2269 2270</div> 2271</div> 2272<a id="a63dc1c7865592a39f5bf323f14cbcf9d"></a> 2273<h2 class="memtitle"><span class="permalink"><a href="#a63dc1c7865592a39f5bf323f14cbcf9d">◆ </a></span>RTE_SPI3_SLAVE_PCS_PIN_SEL</h2> 2274 2275<div class="memitem"> 2276<div class="memproto"> 2277 <table class="memname"> 2278 <tr> 2279 <td class="memname">#define RTE_SPI3_SLAVE_PCS_PIN_SEL   (kLPSPI_SlavePcs0)</td> 2280 </tr> 2281 </table> 2282</div><div class="memdoc"> 2283 2284<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00152">152</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2285 2286</div> 2287</div> 2288<a id="ab5ea31062ae6c550905351bfac679210"></a> 2289<h2 class="memtitle"><span class="permalink"><a href="#ab5ea31062ae6c550905351bfac679210">◆ </a></span>RTE_SPI4</h2> 2290 2291<div class="memitem"> 2292<div class="memproto"> 2293 <table class="memname"> 2294 <tr> 2295 <td class="memname">#define RTE_SPI4   0</td> 2296 </tr> 2297 </table> 2298</div><div class="memdoc"> 2299 2300<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00032">32</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2301 2302</div> 2303</div> 2304<a id="aaf2ab4cef9c8fd5fd873954d6312630e"></a> 2305<h2 class="memtitle"><span class="permalink"><a href="#aaf2ab4cef9c8fd5fd873954d6312630e">◆ </a></span>RTE_SPI4_BETWEEN_TRANSFER_DELAY</h2> 2306 2307<div class="memitem"> 2308<div class="memproto"> 2309 <table class="memname"> 2310 <tr> 2311 <td class="memname">#define RTE_SPI4_BETWEEN_TRANSFER_DELAY   1000</td> 2312 </tr> 2313 </table> 2314</div><div class="memdoc"> 2315 2316<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00164">164</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2317 2318</div> 2319</div> 2320<a id="a0a82c99593680766a8a846cd0b1b0169"></a> 2321<h2 class="memtitle"><span class="permalink"><a href="#a0a82c99593680766a8a846cd0b1b0169">◆ </a></span>RTE_SPI4_DMA_EN</h2> 2322 2323<div class="memitem"> 2324<div class="memproto"> 2325 <table class="memname"> 2326 <tr> 2327 <td class="memname">#define RTE_SPI4_DMA_EN   0</td> 2328 </tr> 2329 </table> 2330</div><div class="memdoc"> 2331 2332<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00033">33</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2333 2334</div> 2335</div> 2336<a id="a7dd6e0050f362bd1bfd3a07a7e86b57a"></a> 2337<h2 class="memtitle"><span class="permalink"><a href="#a7dd6e0050f362bd1bfd3a07a7e86b57a">◆ </a></span>RTE_SPI4_DMA_RX_CH</h2> 2338 2339<div class="memitem"> 2340<div class="memproto"> 2341 <table class="memname"> 2342 <tr> 2343 <td class="memname">#define RTE_SPI4_DMA_RX_CH   7</td> 2344 </tr> 2345 </table> 2346</div><div class="memdoc"> 2347 2348<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00171">171</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2349 2350</div> 2351</div> 2352<a id="a968c662515159592bfb826495d2d3c5d"></a> 2353<h2 class="memtitle"><span class="permalink"><a href="#a968c662515159592bfb826495d2d3c5d">◆ </a></span>RTE_SPI4_DMA_RX_DMA_BASE</h2> 2354 2355<div class="memitem"> 2356<div class="memproto"> 2357 <table class="memname"> 2358 <tr> 2359 <td class="memname">#define RTE_SPI4_DMA_RX_DMA_BASE   DMA0</td> 2360 </tr> 2361 </table> 2362</div><div class="memdoc"> 2363 2364<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00174">174</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2365 2366</div> 2367</div> 2368<a id="a478cb5cd7ebeaf47470f623dac24f71b"></a> 2369<h2 class="memtitle"><span class="permalink"><a href="#a478cb5cd7ebeaf47470f623dac24f71b">◆ </a></span>RTE_SPI4_DMA_RX_DMAMUX_BASE</h2> 2370 2371<div class="memitem"> 2372<div class="memproto"> 2373 <table class="memname"> 2374 <tr> 2375 <td class="memname">#define RTE_SPI4_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 2376 </tr> 2377 </table> 2378</div><div class="memdoc"> 2379 2380<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00173">173</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2381 2382</div> 2383</div> 2384<a id="ada325d25817cdcfd6760ec56d55ebd9e"></a> 2385<h2 class="memtitle"><span class="permalink"><a href="#ada325d25817cdcfd6760ec56d55ebd9e">◆ </a></span>RTE_SPI4_DMA_RX_PERI_SEL</h2> 2386 2387<div class="memitem"> 2388<div class="memproto"> 2389 <table class="memname"> 2390 <tr> 2391 <td class="memname">#define RTE_SPI4_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI4Rx</td> 2392 </tr> 2393 </table> 2394</div><div class="memdoc"> 2395 2396<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00172">172</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2397 2398</div> 2399</div> 2400<a id="a956855c142636770f6a7debe2aa013e6"></a> 2401<h2 class="memtitle"><span class="permalink"><a href="#a956855c142636770f6a7debe2aa013e6">◆ </a></span>RTE_SPI4_DMA_TX_CH</h2> 2402 2403<div class="memitem"> 2404<div class="memproto"> 2405 <table class="memname"> 2406 <tr> 2407 <td class="memname">#define RTE_SPI4_DMA_TX_CH   6</td> 2408 </tr> 2409 </table> 2410</div><div class="memdoc"> 2411 2412<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00167">167</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2413 2414</div> 2415</div> 2416<a id="aa3ec0db7635e3be6822ac3d6b522aed9"></a> 2417<h2 class="memtitle"><span class="permalink"><a href="#aa3ec0db7635e3be6822ac3d6b522aed9">◆ </a></span>RTE_SPI4_DMA_TX_DMA_BASE</h2> 2418 2419<div class="memitem"> 2420<div class="memproto"> 2421 <table class="memname"> 2422 <tr> 2423 <td class="memname">#define RTE_SPI4_DMA_TX_DMA_BASE   DMA0</td> 2424 </tr> 2425 </table> 2426</div><div class="memdoc"> 2427 2428<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00170">170</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2429 2430</div> 2431</div> 2432<a id="ae3eaa3789e307502d95d5bcb22557f21"></a> 2433<h2 class="memtitle"><span class="permalink"><a href="#ae3eaa3789e307502d95d5bcb22557f21">◆ </a></span>RTE_SPI4_DMA_TX_DMAMUX_BASE</h2> 2434 2435<div class="memitem"> 2436<div class="memproto"> 2437 <table class="memname"> 2438 <tr> 2439 <td class="memname">#define RTE_SPI4_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 2440 </tr> 2441 </table> 2442</div><div class="memdoc"> 2443 2444<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00169">169</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2445 2446</div> 2447</div> 2448<a id="a26a43c2ab8b1d1c288cb34ecd416f7c0"></a> 2449<h2 class="memtitle"><span class="permalink"><a href="#a26a43c2ab8b1d1c288cb34ecd416f7c0">◆ </a></span>RTE_SPI4_DMA_TX_PERI_SEL</h2> 2450 2451<div class="memitem"> 2452<div class="memproto"> 2453 <table class="memname"> 2454 <tr> 2455 <td class="memname">#define RTE_SPI4_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI4Tx</td> 2456 </tr> 2457 </table> 2458</div><div class="memdoc"> 2459 2460<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00168">168</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2461 2462</div> 2463</div> 2464<a id="a14b93ec25540b16bf3adac9417b18d98"></a> 2465<h2 class="memtitle"><span class="permalink"><a href="#a14b93ec25540b16bf3adac9417b18d98">◆ </a></span>RTE_SPI4_MASTER_PCS_PIN_SEL</h2> 2466 2467<div class="memitem"> 2468<div class="memproto"> 2469 <table class="memname"> 2470 <tr> 2471 <td class="memname">#define RTE_SPI4_MASTER_PCS_PIN_SEL   (kLPSPI_MasterPcs0)</td> 2472 </tr> 2473 </table> 2474</div><div class="memdoc"> 2475 2476<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00165">165</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2477 2478</div> 2479</div> 2480<a id="a902fd47282cf03f90965dd9c28c5fbad"></a> 2481<h2 class="memtitle"><span class="permalink"><a href="#a902fd47282cf03f90965dd9c28c5fbad">◆ </a></span>RTE_SPI4_PCS_TO_SCK_DELAY</h2> 2482 2483<div class="memitem"> 2484<div class="memproto"> 2485 <table class="memname"> 2486 <tr> 2487 <td class="memname">#define RTE_SPI4_PCS_TO_SCK_DELAY   1000</td> 2488 </tr> 2489 </table> 2490</div><div class="memdoc"> 2491 2492<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00162">162</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2493 2494</div> 2495</div> 2496<a id="addde6066970e78ac95c304f81e3d4224"></a> 2497<h2 class="memtitle"><span class="permalink"><a href="#addde6066970e78ac95c304f81e3d4224">◆ </a></span>RTE_SPI4_SCK_TO_PSC_DELAY</h2> 2498 2499<div class="memitem"> 2500<div class="memproto"> 2501 <table class="memname"> 2502 <tr> 2503 <td class="memname">#define RTE_SPI4_SCK_TO_PSC_DELAY   1000</td> 2504 </tr> 2505 </table> 2506</div><div class="memdoc"> 2507 2508<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00163">163</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2509 2510</div> 2511</div> 2512<a id="a1ffa2d5a7b8e5ad0b1b5bf96270e9427"></a> 2513<h2 class="memtitle"><span class="permalink"><a href="#a1ffa2d5a7b8e5ad0b1b5bf96270e9427">◆ </a></span>RTE_SPI4_SLAVE_PCS_PIN_SEL</h2> 2514 2515<div class="memitem"> 2516<div class="memproto"> 2517 <table class="memname"> 2518 <tr> 2519 <td class="memname">#define RTE_SPI4_SLAVE_PCS_PIN_SEL   (kLPSPI_SlavePcs0)</td> 2520 </tr> 2521 </table> 2522</div><div class="memdoc"> 2523 2524<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00166">166</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2525 2526</div> 2527</div> 2528<a id="a2f9df7e872c3d3fe6576c2c22b77bd81"></a> 2529<h2 class="memtitle"><span class="permalink"><a href="#a2f9df7e872c3d3fe6576c2c22b77bd81">◆ </a></span>RTE_SPI5</h2> 2530 2531<div class="memitem"> 2532<div class="memproto"> 2533 <table class="memname"> 2534 <tr> 2535 <td class="memname">#define RTE_SPI5   0</td> 2536 </tr> 2537 </table> 2538</div><div class="memdoc"> 2539 2540<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00034">34</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2541 2542</div> 2543</div> 2544<a id="ad61947178295915a471db020e41d1811"></a> 2545<h2 class="memtitle"><span class="permalink"><a href="#ad61947178295915a471db020e41d1811">◆ </a></span>RTE_SPI5_BETWEEN_TRANSFER_DELAY</h2> 2546 2547<div class="memitem"> 2548<div class="memproto"> 2549 <table class="memname"> 2550 <tr> 2551 <td class="memname">#define RTE_SPI5_BETWEEN_TRANSFER_DELAY   1000</td> 2552 </tr> 2553 </table> 2554</div><div class="memdoc"> 2555 2556<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00178">178</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2557 2558</div> 2559</div> 2560<a id="abfa9a5f5a97226220d95a9ecd3a6b51d"></a> 2561<h2 class="memtitle"><span class="permalink"><a href="#abfa9a5f5a97226220d95a9ecd3a6b51d">◆ </a></span>RTE_SPI5_DMA_EN</h2> 2562 2563<div class="memitem"> 2564<div class="memproto"> 2565 <table class="memname"> 2566 <tr> 2567 <td class="memname">#define RTE_SPI5_DMA_EN   0</td> 2568 </tr> 2569 </table> 2570</div><div class="memdoc"> 2571 2572<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00035">35</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2573 2574</div> 2575</div> 2576<a id="a6aa0bdc35c2121855560c7a6455dbddf"></a> 2577<h2 class="memtitle"><span class="permalink"><a href="#a6aa0bdc35c2121855560c7a6455dbddf">◆ </a></span>RTE_SPI5_DMA_RX_CH</h2> 2578 2579<div class="memitem"> 2580<div class="memproto"> 2581 <table class="memname"> 2582 <tr> 2583 <td class="memname">#define RTE_SPI5_DMA_RX_CH   9</td> 2584 </tr> 2585 </table> 2586</div><div class="memdoc"> 2587 2588<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00185">185</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2589 2590</div> 2591</div> 2592<a id="ab382c8c01e5955ace12e26b487622a05"></a> 2593<h2 class="memtitle"><span class="permalink"><a href="#ab382c8c01e5955ace12e26b487622a05">◆ </a></span>RTE_SPI5_DMA_RX_DMA_BASE</h2> 2594 2595<div class="memitem"> 2596<div class="memproto"> 2597 <table class="memname"> 2598 <tr> 2599 <td class="memname">#define RTE_SPI5_DMA_RX_DMA_BASE   DMA0</td> 2600 </tr> 2601 </table> 2602</div><div class="memdoc"> 2603 2604<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00188">188</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2605 2606</div> 2607</div> 2608<a id="a7661d8743ca1a17dda22cb8e0e0f68bb"></a> 2609<h2 class="memtitle"><span class="permalink"><a href="#a7661d8743ca1a17dda22cb8e0e0f68bb">◆ </a></span>RTE_SPI5_DMA_RX_DMAMUX_BASE</h2> 2610 2611<div class="memitem"> 2612<div class="memproto"> 2613 <table class="memname"> 2614 <tr> 2615 <td class="memname">#define RTE_SPI5_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 2616 </tr> 2617 </table> 2618</div><div class="memdoc"> 2619 2620<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00187">187</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2621 2622</div> 2623</div> 2624<a id="aa17446d7236876fb326323f1222fcb8d"></a> 2625<h2 class="memtitle"><span class="permalink"><a href="#aa17446d7236876fb326323f1222fcb8d">◆ </a></span>RTE_SPI5_DMA_RX_PERI_SEL</h2> 2626 2627<div class="memitem"> 2628<div class="memproto"> 2629 <table class="memname"> 2630 <tr> 2631 <td class="memname">#define RTE_SPI5_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI5Rx</td> 2632 </tr> 2633 </table> 2634</div><div class="memdoc"> 2635 2636<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00186">186</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2637 2638</div> 2639</div> 2640<a id="a1041985ad6bcd91b3bb3cccd837aaaae"></a> 2641<h2 class="memtitle"><span class="permalink"><a href="#a1041985ad6bcd91b3bb3cccd837aaaae">◆ </a></span>RTE_SPI5_DMA_TX_CH</h2> 2642 2643<div class="memitem"> 2644<div class="memproto"> 2645 <table class="memname"> 2646 <tr> 2647 <td class="memname">#define RTE_SPI5_DMA_TX_CH   8</td> 2648 </tr> 2649 </table> 2650</div><div class="memdoc"> 2651 2652<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00181">181</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2653 2654</div> 2655</div> 2656<a id="a8d306bb116961953c118532b719cc5a9"></a> 2657<h2 class="memtitle"><span class="permalink"><a href="#a8d306bb116961953c118532b719cc5a9">◆ </a></span>RTE_SPI5_DMA_TX_DMA_BASE</h2> 2658 2659<div class="memitem"> 2660<div class="memproto"> 2661 <table class="memname"> 2662 <tr> 2663 <td class="memname">#define RTE_SPI5_DMA_TX_DMA_BASE   DMA0</td> 2664 </tr> 2665 </table> 2666</div><div class="memdoc"> 2667 2668<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00184">184</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2669 2670</div> 2671</div> 2672<a id="a0e5b5dbcfb4dde49887559b4f303a0b6"></a> 2673<h2 class="memtitle"><span class="permalink"><a href="#a0e5b5dbcfb4dde49887559b4f303a0b6">◆ </a></span>RTE_SPI5_DMA_TX_DMAMUX_BASE</h2> 2674 2675<div class="memitem"> 2676<div class="memproto"> 2677 <table class="memname"> 2678 <tr> 2679 <td class="memname">#define RTE_SPI5_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 2680 </tr> 2681 </table> 2682</div><div class="memdoc"> 2683 2684<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00183">183</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2685 2686</div> 2687</div> 2688<a id="a0ecaf278dd6946934ec7d5a6c4b18a7b"></a> 2689<h2 class="memtitle"><span class="permalink"><a href="#a0ecaf278dd6946934ec7d5a6c4b18a7b">◆ </a></span>RTE_SPI5_DMA_TX_PERI_SEL</h2> 2690 2691<div class="memitem"> 2692<div class="memproto"> 2693 <table class="memname"> 2694 <tr> 2695 <td class="memname">#define RTE_SPI5_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI5Tx</td> 2696 </tr> 2697 </table> 2698</div><div class="memdoc"> 2699 2700<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00182">182</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2701 2702</div> 2703</div> 2704<a id="abf2aea43f4b4b480fadb99bcc4e22de6"></a> 2705<h2 class="memtitle"><span class="permalink"><a href="#abf2aea43f4b4b480fadb99bcc4e22de6">◆ </a></span>RTE_SPI5_MASTER_PCS_PIN_SEL</h2> 2706 2707<div class="memitem"> 2708<div class="memproto"> 2709 <table class="memname"> 2710 <tr> 2711 <td class="memname">#define RTE_SPI5_MASTER_PCS_PIN_SEL   (kLPSPI_MasterPcs0)</td> 2712 </tr> 2713 </table> 2714</div><div class="memdoc"> 2715 2716<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00179">179</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2717 2718</div> 2719</div> 2720<a id="a37d29d6dcbb2e3de3425057411bb99c4"></a> 2721<h2 class="memtitle"><span class="permalink"><a href="#a37d29d6dcbb2e3de3425057411bb99c4">◆ </a></span>RTE_SPI5_PCS_TO_SCK_DELAY</h2> 2722 2723<div class="memitem"> 2724<div class="memproto"> 2725 <table class="memname"> 2726 <tr> 2727 <td class="memname">#define RTE_SPI5_PCS_TO_SCK_DELAY   1000</td> 2728 </tr> 2729 </table> 2730</div><div class="memdoc"> 2731 2732<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00176">176</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2733 2734</div> 2735</div> 2736<a id="ab940dc32781a18c0af66e85d7afccd8f"></a> 2737<h2 class="memtitle"><span class="permalink"><a href="#ab940dc32781a18c0af66e85d7afccd8f">◆ </a></span>RTE_SPI5_SCK_TO_PSC_DELAY</h2> 2738 2739<div class="memitem"> 2740<div class="memproto"> 2741 <table class="memname"> 2742 <tr> 2743 <td class="memname">#define RTE_SPI5_SCK_TO_PSC_DELAY   1000</td> 2744 </tr> 2745 </table> 2746</div><div class="memdoc"> 2747 2748<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00177">177</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2749 2750</div> 2751</div> 2752<a id="a87e3d2b881cd6ffc6d436cc4f6cbbf7b"></a> 2753<h2 class="memtitle"><span class="permalink"><a href="#a87e3d2b881cd6ffc6d436cc4f6cbbf7b">◆ </a></span>RTE_SPI5_SLAVE_PCS_PIN_SEL</h2> 2754 2755<div class="memitem"> 2756<div class="memproto"> 2757 <table class="memname"> 2758 <tr> 2759 <td class="memname">#define RTE_SPI5_SLAVE_PCS_PIN_SEL   (kLPSPI_SlavePcs0)</td> 2760 </tr> 2761 </table> 2762</div><div class="memdoc"> 2763 2764<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00180">180</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2765 2766</div> 2767</div> 2768<a id="a4cd9d936e75552e96b2996a3f3c42081"></a> 2769<h2 class="memtitle"><span class="permalink"><a href="#a4cd9d936e75552e96b2996a3f3c42081">◆ </a></span>RTE_SPI6</h2> 2770 2771<div class="memitem"> 2772<div class="memproto"> 2773 <table class="memname"> 2774 <tr> 2775 <td class="memname">#define RTE_SPI6   0</td> 2776 </tr> 2777 </table> 2778</div><div class="memdoc"> 2779 2780<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00036">36</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2781 2782</div> 2783</div> 2784<a id="a2a8fa79cc3fd9b4b0f04cbf226410c4b"></a> 2785<h2 class="memtitle"><span class="permalink"><a href="#a2a8fa79cc3fd9b4b0f04cbf226410c4b">◆ </a></span>RTE_SPI6_BETWEEN_TRANSFER_DELAY</h2> 2786 2787<div class="memitem"> 2788<div class="memproto"> 2789 <table class="memname"> 2790 <tr> 2791 <td class="memname">#define RTE_SPI6_BETWEEN_TRANSFER_DELAY   1000</td> 2792 </tr> 2793 </table> 2794</div><div class="memdoc"> 2795 2796<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00192">192</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2797 2798</div> 2799</div> 2800<a id="a5f1d64bf1a9b4de1bc0643cbec0eaadb"></a> 2801<h2 class="memtitle"><span class="permalink"><a href="#a5f1d64bf1a9b4de1bc0643cbec0eaadb">◆ </a></span>RTE_SPI6_DMA_EN</h2> 2802 2803<div class="memitem"> 2804<div class="memproto"> 2805 <table class="memname"> 2806 <tr> 2807 <td class="memname">#define RTE_SPI6_DMA_EN   0</td> 2808 </tr> 2809 </table> 2810</div><div class="memdoc"> 2811 2812<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00037">37</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2813 2814</div> 2815</div> 2816<a id="acdb61b6c3e30ad9a0877b9931b6d6904"></a> 2817<h2 class="memtitle"><span class="permalink"><a href="#acdb61b6c3e30ad9a0877b9931b6d6904">◆ </a></span>RTE_SPI6_DMA_RX_CH</h2> 2818 2819<div class="memitem"> 2820<div class="memproto"> 2821 <table class="memname"> 2822 <tr> 2823 <td class="memname">#define RTE_SPI6_DMA_RX_CH   11</td> 2824 </tr> 2825 </table> 2826</div><div class="memdoc"> 2827 2828<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00199">199</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2829 2830</div> 2831</div> 2832<a id="acab2a9b0b3033d3425ac33918ec17c03"></a> 2833<h2 class="memtitle"><span class="permalink"><a href="#acab2a9b0b3033d3425ac33918ec17c03">◆ </a></span>RTE_SPI6_DMA_RX_DMA_BASE</h2> 2834 2835<div class="memitem"> 2836<div class="memproto"> 2837 <table class="memname"> 2838 <tr> 2839 <td class="memname">#define RTE_SPI6_DMA_RX_DMA_BASE   DMA0</td> 2840 </tr> 2841 </table> 2842</div><div class="memdoc"> 2843 2844<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00202">202</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2845 2846</div> 2847</div> 2848<a id="a113aed2c7ed2624fab109cf0748ac052"></a> 2849<h2 class="memtitle"><span class="permalink"><a href="#a113aed2c7ed2624fab109cf0748ac052">◆ </a></span>RTE_SPI6_DMA_RX_DMAMUX_BASE</h2> 2850 2851<div class="memitem"> 2852<div class="memproto"> 2853 <table class="memname"> 2854 <tr> 2855 <td class="memname">#define RTE_SPI6_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 2856 </tr> 2857 </table> 2858</div><div class="memdoc"> 2859 2860<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00201">201</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2861 2862</div> 2863</div> 2864<a id="aa4a398c69b8dac0ebc7d7a9f40b7609f"></a> 2865<h2 class="memtitle"><span class="permalink"><a href="#aa4a398c69b8dac0ebc7d7a9f40b7609f">◆ </a></span>RTE_SPI6_DMA_RX_PERI_SEL</h2> 2866 2867<div class="memitem"> 2868<div class="memproto"> 2869 <table class="memname"> 2870 <tr> 2871 <td class="memname">#define RTE_SPI6_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI6Rx</td> 2872 </tr> 2873 </table> 2874</div><div class="memdoc"> 2875 2876<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00200">200</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2877 2878</div> 2879</div> 2880<a id="a500837b546f2c5c5d340c70b8316cd75"></a> 2881<h2 class="memtitle"><span class="permalink"><a href="#a500837b546f2c5c5d340c70b8316cd75">◆ </a></span>RTE_SPI6_DMA_TX_CH</h2> 2882 2883<div class="memitem"> 2884<div class="memproto"> 2885 <table class="memname"> 2886 <tr> 2887 <td class="memname">#define RTE_SPI6_DMA_TX_CH   10</td> 2888 </tr> 2889 </table> 2890</div><div class="memdoc"> 2891 2892<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00195">195</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2893 2894</div> 2895</div> 2896<a id="a562a146c7a128d2087eb47d8e19a2b2a"></a> 2897<h2 class="memtitle"><span class="permalink"><a href="#a562a146c7a128d2087eb47d8e19a2b2a">◆ </a></span>RTE_SPI6_DMA_TX_DMA_BASE</h2> 2898 2899<div class="memitem"> 2900<div class="memproto"> 2901 <table class="memname"> 2902 <tr> 2903 <td class="memname">#define RTE_SPI6_DMA_TX_DMA_BASE   DMA0</td> 2904 </tr> 2905 </table> 2906</div><div class="memdoc"> 2907 2908<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00198">198</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2909 2910</div> 2911</div> 2912<a id="a45d09e085504ada169bc3b97358b4c04"></a> 2913<h2 class="memtitle"><span class="permalink"><a href="#a45d09e085504ada169bc3b97358b4c04">◆ </a></span>RTE_SPI6_DMA_TX_DMAMUX_BASE</h2> 2914 2915<div class="memitem"> 2916<div class="memproto"> 2917 <table class="memname"> 2918 <tr> 2919 <td class="memname">#define RTE_SPI6_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 2920 </tr> 2921 </table> 2922</div><div class="memdoc"> 2923 2924<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00197">197</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2925 2926</div> 2927</div> 2928<a id="ada1fda3c07011611352d8a49a7bf4d3f"></a> 2929<h2 class="memtitle"><span class="permalink"><a href="#ada1fda3c07011611352d8a49a7bf4d3f">◆ </a></span>RTE_SPI6_DMA_TX_PERI_SEL</h2> 2930 2931<div class="memitem"> 2932<div class="memproto"> 2933 <table class="memname"> 2934 <tr> 2935 <td class="memname">#define RTE_SPI6_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPSPI6Tx</td> 2936 </tr> 2937 </table> 2938</div><div class="memdoc"> 2939 2940<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00196">196</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2941 2942</div> 2943</div> 2944<a id="a624b496f8c43b43734656fc972eb44d0"></a> 2945<h2 class="memtitle"><span class="permalink"><a href="#a624b496f8c43b43734656fc972eb44d0">◆ </a></span>RTE_SPI6_MASTER_PCS_PIN_SEL</h2> 2946 2947<div class="memitem"> 2948<div class="memproto"> 2949 <table class="memname"> 2950 <tr> 2951 <td class="memname">#define RTE_SPI6_MASTER_PCS_PIN_SEL   (kLPSPI_MasterPcs0)</td> 2952 </tr> 2953 </table> 2954</div><div class="memdoc"> 2955 2956<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00193">193</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2957 2958</div> 2959</div> 2960<a id="a2f70806a3b60d1adc11f421229f14461"></a> 2961<h2 class="memtitle"><span class="permalink"><a href="#a2f70806a3b60d1adc11f421229f14461">◆ </a></span>RTE_SPI6_PCS_TO_SCK_DELAY</h2> 2962 2963<div class="memitem"> 2964<div class="memproto"> 2965 <table class="memname"> 2966 <tr> 2967 <td class="memname">#define RTE_SPI6_PCS_TO_SCK_DELAY   1000</td> 2968 </tr> 2969 </table> 2970</div><div class="memdoc"> 2971 2972<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00190">190</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2973 2974</div> 2975</div> 2976<a id="aa477179de6b38381621f7479ddc3b3dd"></a> 2977<h2 class="memtitle"><span class="permalink"><a href="#aa477179de6b38381621f7479ddc3b3dd">◆ </a></span>RTE_SPI6_SCK_TO_PSC_DELAY</h2> 2978 2979<div class="memitem"> 2980<div class="memproto"> 2981 <table class="memname"> 2982 <tr> 2983 <td class="memname">#define RTE_SPI6_SCK_TO_PSC_DELAY   1000</td> 2984 </tr> 2985 </table> 2986</div><div class="memdoc"> 2987 2988<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00191">191</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 2989 2990</div> 2991</div> 2992<a id="a7a2616e6e511c3fd735af6ffb2efba85"></a> 2993<h2 class="memtitle"><span class="permalink"><a href="#a7a2616e6e511c3fd735af6ffb2efba85">◆ </a></span>RTE_SPI6_SLAVE_PCS_PIN_SEL</h2> 2994 2995<div class="memitem"> 2996<div class="memproto"> 2997 <table class="memname"> 2998 <tr> 2999 <td class="memname">#define RTE_SPI6_SLAVE_PCS_PIN_SEL   (kLPSPI_SlavePcs0)</td> 3000 </tr> 3001 </table> 3002</div><div class="memdoc"> 3003 3004<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00194">194</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3005 3006</div> 3007</div> 3008<a id="ae8f0e0260407d14858ce86d2ffb75424"></a> 3009<h2 class="memtitle"><span class="permalink"><a href="#ae8f0e0260407d14858ce86d2ffb75424">◆ </a></span>RTE_USART1</h2> 3010 3011<div class="memitem"> 3012<div class="memproto"> 3013 <table class="memname"> 3014 <tr> 3015 <td class="memname">#define RTE_USART1   1</td> 3016 </tr> 3017 </table> 3018</div><div class="memdoc"> 3019 3020<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00039">39</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3021 3022</div> 3023</div> 3024<a id="a726a89447c240f729e73b7622385d749"></a> 3025<h2 class="memtitle"><span class="permalink"><a href="#a726a89447c240f729e73b7622385d749">◆ </a></span>RTE_USART10</h2> 3026 3027<div class="memitem"> 3028<div class="memproto"> 3029 <table class="memname"> 3030 <tr> 3031 <td class="memname">#define RTE_USART10   0</td> 3032 </tr> 3033 </table> 3034</div><div class="memdoc"> 3035 3036<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00057">57</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3037 3038</div> 3039</div> 3040<a id="a5bc420b9d099c3b7361ccb79d698f94d"></a> 3041<h2 class="memtitle"><span class="permalink"><a href="#a5bc420b9d099c3b7361ccb79d698f94d">◆ </a></span>RTE_USART10_DMA_EN</h2> 3042 3043<div class="memitem"> 3044<div class="memproto"> 3045 <table class="memname"> 3046 <tr> 3047 <td class="memname">#define RTE_USART10_DMA_EN   0</td> 3048 </tr> 3049 </table> 3050</div><div class="memdoc"> 3051 3052<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00058">58</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3053 3054</div> 3055</div> 3056<a id="aa4a9ae606f683f73cbbd54d10f3ec658"></a> 3057<h2 class="memtitle"><span class="permalink"><a href="#aa4a9ae606f683f73cbbd54d10f3ec658">◆ </a></span>RTE_USART10_DMA_RX_CH</h2> 3058 3059<div class="memitem"> 3060<div class="memproto"> 3061 <table class="memname"> 3062 <tr> 3063 <td class="memname">#define RTE_USART10_DMA_RX_CH   19</td> 3064 </tr> 3065 </table> 3066</div><div class="memdoc"> 3067 3068<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00290">290</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3069 3070</div> 3071</div> 3072<a id="ae022eaa77af7a1693a272196ad51950c"></a> 3073<h2 class="memtitle"><span class="permalink"><a href="#ae022eaa77af7a1693a272196ad51950c">◆ </a></span>RTE_USART10_DMA_RX_DMA_BASE</h2> 3074 3075<div class="memitem"> 3076<div class="memproto"> 3077 <table class="memname"> 3078 <tr> 3079 <td class="memname">#define RTE_USART10_DMA_RX_DMA_BASE   DMA0</td> 3080 </tr> 3081 </table> 3082</div><div class="memdoc"> 3083 3084<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00293">293</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3085 3086</div> 3087</div> 3088<a id="ac9255f1d8fa4c2b82923fb2cbb5ef01d"></a> 3089<h2 class="memtitle"><span class="permalink"><a href="#ac9255f1d8fa4c2b82923fb2cbb5ef01d">◆ </a></span>RTE_USART10_DMA_RX_DMAMUX_BASE</h2> 3090 3091<div class="memitem"> 3092<div class="memproto"> 3093 <table class="memname"> 3094 <tr> 3095 <td class="memname">#define RTE_USART10_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 3096 </tr> 3097 </table> 3098</div><div class="memdoc"> 3099 3100<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00292">292</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3101 3102</div> 3103</div> 3104<a id="a146ac727fae8b5c5ad182a2790d15ea8"></a> 3105<h2 class="memtitle"><span class="permalink"><a href="#a146ac727fae8b5c5ad182a2790d15ea8">◆ </a></span>RTE_USART10_DMA_RX_PERI_SEL</h2> 3106 3107<div class="memitem"> 3108<div class="memproto"> 3109 <table class="memname"> 3110 <tr> 3111 <td class="memname">#define RTE_USART10_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART10Rx</td> 3112 </tr> 3113 </table> 3114</div><div class="memdoc"> 3115 3116<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00291">291</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3117 3118</div> 3119</div> 3120<a id="ac1c4424e09f62bdd3cf7bbb029140c17"></a> 3121<h2 class="memtitle"><span class="permalink"><a href="#ac1c4424e09f62bdd3cf7bbb029140c17">◆ </a></span>RTE_USART10_DMA_TX_CH</h2> 3122 3123<div class="memitem"> 3124<div class="memproto"> 3125 <table class="memname"> 3126 <tr> 3127 <td class="memname">#define RTE_USART10_DMA_TX_CH   18</td> 3128 </tr> 3129 </table> 3130</div><div class="memdoc"> 3131 3132<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00286">286</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3133 3134</div> 3135</div> 3136<a id="ac89cc69566cd1ccfbb73b08ebfaf599b"></a> 3137<h2 class="memtitle"><span class="permalink"><a href="#ac89cc69566cd1ccfbb73b08ebfaf599b">◆ </a></span>RTE_USART10_DMA_TX_DMA_BASE</h2> 3138 3139<div class="memitem"> 3140<div class="memproto"> 3141 <table class="memname"> 3142 <tr> 3143 <td class="memname">#define RTE_USART10_DMA_TX_DMA_BASE   DMA0</td> 3144 </tr> 3145 </table> 3146</div><div class="memdoc"> 3147 3148<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00289">289</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3149 3150</div> 3151</div> 3152<a id="a8b82b82de6825554dbc282331be2e14c"></a> 3153<h2 class="memtitle"><span class="permalink"><a href="#a8b82b82de6825554dbc282331be2e14c">◆ </a></span>RTE_USART10_DMA_TX_DMAMUX_BASE</h2> 3154 3155<div class="memitem"> 3156<div class="memproto"> 3157 <table class="memname"> 3158 <tr> 3159 <td class="memname">#define RTE_USART10_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 3160 </tr> 3161 </table> 3162</div><div class="memdoc"> 3163 3164<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00288">288</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3165 3166</div> 3167</div> 3168<a id="a9025a7019ac18036afbe7bb6e731e34a"></a> 3169<h2 class="memtitle"><span class="permalink"><a href="#a9025a7019ac18036afbe7bb6e731e34a">◆ </a></span>RTE_USART10_DMA_TX_PERI_SEL</h2> 3170 3171<div class="memitem"> 3172<div class="memproto"> 3173 <table class="memname"> 3174 <tr> 3175 <td class="memname">#define RTE_USART10_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART10Tx</td> 3176 </tr> 3177 </table> 3178</div><div class="memdoc"> 3179 3180<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00287">287</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3181 3182</div> 3183</div> 3184<a id="aaeff216fa2e399a92a774e746ea0c040"></a> 3185<h2 class="memtitle"><span class="permalink"><a href="#aaeff216fa2e399a92a774e746ea0c040">◆ </a></span>RTE_USART11</h2> 3186 3187<div class="memitem"> 3188<div class="memproto"> 3189 <table class="memname"> 3190 <tr> 3191 <td class="memname">#define RTE_USART11   0</td> 3192 </tr> 3193 </table> 3194</div><div class="memdoc"> 3195 3196<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00059">59</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3197 3198</div> 3199</div> 3200<a id="acdd2ab3e608c3f12e233bc2c1f1cd2c6"></a> 3201<h2 class="memtitle"><span class="permalink"><a href="#acdd2ab3e608c3f12e233bc2c1f1cd2c6">◆ </a></span>RTE_USART11_DMA_EN</h2> 3202 3203<div class="memitem"> 3204<div class="memproto"> 3205 <table class="memname"> 3206 <tr> 3207 <td class="memname">#define RTE_USART11_DMA_EN   0</td> 3208 </tr> 3209 </table> 3210</div><div class="memdoc"> 3211 3212<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00060">60</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3213 3214</div> 3215</div> 3216<a id="a4bfe881bb9c8462aad1bc3f06d0dfc83"></a> 3217<h2 class="memtitle"><span class="permalink"><a href="#a4bfe881bb9c8462aad1bc3f06d0dfc83">◆ </a></span>RTE_USART11_DMA_RX_CH</h2> 3218 3219<div class="memitem"> 3220<div class="memproto"> 3221 <table class="memname"> 3222 <tr> 3223 <td class="memname">#define RTE_USART11_DMA_RX_CH   21</td> 3224 </tr> 3225 </table> 3226</div><div class="memdoc"> 3227 3228<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00299">299</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3229 3230</div> 3231</div> 3232<a id="a654d5afcc2b4c510fa9675540c63fb34"></a> 3233<h2 class="memtitle"><span class="permalink"><a href="#a654d5afcc2b4c510fa9675540c63fb34">◆ </a></span>RTE_USART11_DMA_RX_DMA_BASE</h2> 3234 3235<div class="memitem"> 3236<div class="memproto"> 3237 <table class="memname"> 3238 <tr> 3239 <td class="memname">#define RTE_USART11_DMA_RX_DMA_BASE   DMA0</td> 3240 </tr> 3241 </table> 3242</div><div class="memdoc"> 3243 3244<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00302">302</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3245 3246</div> 3247</div> 3248<a id="ab788dfbb8d8dcbda921836ce50b5dde2"></a> 3249<h2 class="memtitle"><span class="permalink"><a href="#ab788dfbb8d8dcbda921836ce50b5dde2">◆ </a></span>RTE_USART11_DMA_RX_DMAMUX_BASE</h2> 3250 3251<div class="memitem"> 3252<div class="memproto"> 3253 <table class="memname"> 3254 <tr> 3255 <td class="memname">#define RTE_USART11_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 3256 </tr> 3257 </table> 3258</div><div class="memdoc"> 3259 3260<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00301">301</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3261 3262</div> 3263</div> 3264<a id="ad555cdd0b0ec893ba0cea60976ddcf4b"></a> 3265<h2 class="memtitle"><span class="permalink"><a href="#ad555cdd0b0ec893ba0cea60976ddcf4b">◆ </a></span>RTE_USART11_DMA_RX_PERI_SEL</h2> 3266 3267<div class="memitem"> 3268<div class="memproto"> 3269 <table class="memname"> 3270 <tr> 3271 <td class="memname">#define RTE_USART11_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART11Rx</td> 3272 </tr> 3273 </table> 3274</div><div class="memdoc"> 3275 3276<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00300">300</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3277 3278</div> 3279</div> 3280<a id="afef0e458bbb3edb75f54cbc2da697dbc"></a> 3281<h2 class="memtitle"><span class="permalink"><a href="#afef0e458bbb3edb75f54cbc2da697dbc">◆ </a></span>RTE_USART11_DMA_TX_CH</h2> 3282 3283<div class="memitem"> 3284<div class="memproto"> 3285 <table class="memname"> 3286 <tr> 3287 <td class="memname">#define RTE_USART11_DMA_TX_CH   20</td> 3288 </tr> 3289 </table> 3290</div><div class="memdoc"> 3291 3292<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00295">295</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3293 3294</div> 3295</div> 3296<a id="afaf6ab6ee029bf827b5cab368b49ee37"></a> 3297<h2 class="memtitle"><span class="permalink"><a href="#afaf6ab6ee029bf827b5cab368b49ee37">◆ </a></span>RTE_USART11_DMA_TX_DMA_BASE</h2> 3298 3299<div class="memitem"> 3300<div class="memproto"> 3301 <table class="memname"> 3302 <tr> 3303 <td class="memname">#define RTE_USART11_DMA_TX_DMA_BASE   DMA0</td> 3304 </tr> 3305 </table> 3306</div><div class="memdoc"> 3307 3308<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00298">298</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3309 3310</div> 3311</div> 3312<a id="a852a29cb0416d2e37e58edc7b1fb3496"></a> 3313<h2 class="memtitle"><span class="permalink"><a href="#a852a29cb0416d2e37e58edc7b1fb3496">◆ </a></span>RTE_USART11_DMA_TX_DMAMUX_BASE</h2> 3314 3315<div class="memitem"> 3316<div class="memproto"> 3317 <table class="memname"> 3318 <tr> 3319 <td class="memname">#define RTE_USART11_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 3320 </tr> 3321 </table> 3322</div><div class="memdoc"> 3323 3324<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00297">297</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3325 3326</div> 3327</div> 3328<a id="aae9a792f4082ddbbcaae5b6f848e6eb1"></a> 3329<h2 class="memtitle"><span class="permalink"><a href="#aae9a792f4082ddbbcaae5b6f848e6eb1">◆ </a></span>RTE_USART11_DMA_TX_PERI_SEL</h2> 3330 3331<div class="memitem"> 3332<div class="memproto"> 3333 <table class="memname"> 3334 <tr> 3335 <td class="memname">#define RTE_USART11_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART11Tx</td> 3336 </tr> 3337 </table> 3338</div><div class="memdoc"> 3339 3340<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00296">296</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3341 3342</div> 3343</div> 3344<a id="a9661c4bf5c6330fdb494edbdc700a34c"></a> 3345<h2 class="memtitle"><span class="permalink"><a href="#a9661c4bf5c6330fdb494edbdc700a34c">◆ </a></span>RTE_USART12</h2> 3346 3347<div class="memitem"> 3348<div class="memproto"> 3349 <table class="memname"> 3350 <tr> 3351 <td class="memname">#define RTE_USART12   0</td> 3352 </tr> 3353 </table> 3354</div><div class="memdoc"> 3355 3356<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00061">61</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3357 3358</div> 3359</div> 3360<a id="a0f7079dac6a22e2e95b64448c1f2a808"></a> 3361<h2 class="memtitle"><span class="permalink"><a href="#a0f7079dac6a22e2e95b64448c1f2a808">◆ </a></span>RTE_USART12_DMA_EN</h2> 3362 3363<div class="memitem"> 3364<div class="memproto"> 3365 <table class="memname"> 3366 <tr> 3367 <td class="memname">#define RTE_USART12_DMA_EN   0</td> 3368 </tr> 3369 </table> 3370</div><div class="memdoc"> 3371 3372<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00062">62</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3373 3374</div> 3375</div> 3376<a id="aae9c7555e205d5ed4749041941268e81"></a> 3377<h2 class="memtitle"><span class="permalink"><a href="#aae9c7555e205d5ed4749041941268e81">◆ </a></span>RTE_USART12_DMA_RX_CH</h2> 3378 3379<div class="memitem"> 3380<div class="memproto"> 3381 <table class="memname"> 3382 <tr> 3383 <td class="memname">#define RTE_USART12_DMA_RX_CH   23</td> 3384 </tr> 3385 </table> 3386</div><div class="memdoc"> 3387 3388<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00308">308</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3389 3390</div> 3391</div> 3392<a id="ac4d11009e0e0d76ac14cc3be97f1d920"></a> 3393<h2 class="memtitle"><span class="permalink"><a href="#ac4d11009e0e0d76ac14cc3be97f1d920">◆ </a></span>RTE_USART12_DMA_RX_DMA_BASE</h2> 3394 3395<div class="memitem"> 3396<div class="memproto"> 3397 <table class="memname"> 3398 <tr> 3399 <td class="memname">#define RTE_USART12_DMA_RX_DMA_BASE   DMA0</td> 3400 </tr> 3401 </table> 3402</div><div class="memdoc"> 3403 3404<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00311">311</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3405 3406</div> 3407</div> 3408<a id="a029a7ee79606fd5cbe7a023ccb95cf62"></a> 3409<h2 class="memtitle"><span class="permalink"><a href="#a029a7ee79606fd5cbe7a023ccb95cf62">◆ </a></span>RTE_USART12_DMA_RX_DMAMUX_BASE</h2> 3410 3411<div class="memitem"> 3412<div class="memproto"> 3413 <table class="memname"> 3414 <tr> 3415 <td class="memname">#define RTE_USART12_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 3416 </tr> 3417 </table> 3418</div><div class="memdoc"> 3419 3420<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00310">310</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3421 3422</div> 3423</div> 3424<a id="a8507e55c77a9739c3d396b4fb8f8d818"></a> 3425<h2 class="memtitle"><span class="permalink"><a href="#a8507e55c77a9739c3d396b4fb8f8d818">◆ </a></span>RTE_USART12_DMA_RX_PERI_SEL</h2> 3426 3427<div class="memitem"> 3428<div class="memproto"> 3429 <table class="memname"> 3430 <tr> 3431 <td class="memname">#define RTE_USART12_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART12Rx</td> 3432 </tr> 3433 </table> 3434</div><div class="memdoc"> 3435 3436<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00309">309</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3437 3438</div> 3439</div> 3440<a id="aed212423cf63e159f699aea7e37ce39f"></a> 3441<h2 class="memtitle"><span class="permalink"><a href="#aed212423cf63e159f699aea7e37ce39f">◆ </a></span>RTE_USART12_DMA_TX_CH</h2> 3442 3443<div class="memitem"> 3444<div class="memproto"> 3445 <table class="memname"> 3446 <tr> 3447 <td class="memname">#define RTE_USART12_DMA_TX_CH   22</td> 3448 </tr> 3449 </table> 3450</div><div class="memdoc"> 3451 3452<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00304">304</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3453 3454</div> 3455</div> 3456<a id="ac85dd474fc3f113f46d7e2bae0409164"></a> 3457<h2 class="memtitle"><span class="permalink"><a href="#ac85dd474fc3f113f46d7e2bae0409164">◆ </a></span>RTE_USART12_DMA_TX_DMA_BASE</h2> 3458 3459<div class="memitem"> 3460<div class="memproto"> 3461 <table class="memname"> 3462 <tr> 3463 <td class="memname">#define RTE_USART12_DMA_TX_DMA_BASE   DMA0</td> 3464 </tr> 3465 </table> 3466</div><div class="memdoc"> 3467 3468<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00307">307</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3469 3470</div> 3471</div> 3472<a id="ac276d7c1ce31e2bede292792eaaebc1e"></a> 3473<h2 class="memtitle"><span class="permalink"><a href="#ac276d7c1ce31e2bede292792eaaebc1e">◆ </a></span>RTE_USART12_DMA_TX_DMAMUX_BASE</h2> 3474 3475<div class="memitem"> 3476<div class="memproto"> 3477 <table class="memname"> 3478 <tr> 3479 <td class="memname">#define RTE_USART12_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 3480 </tr> 3481 </table> 3482</div><div class="memdoc"> 3483 3484<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00306">306</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3485 3486</div> 3487</div> 3488<a id="ab12cbeb7458aaf1a1957e008c47a0ab8"></a> 3489<h2 class="memtitle"><span class="permalink"><a href="#ab12cbeb7458aaf1a1957e008c47a0ab8">◆ </a></span>RTE_USART12_DMA_TX_PERI_SEL</h2> 3490 3491<div class="memitem"> 3492<div class="memproto"> 3493 <table class="memname"> 3494 <tr> 3495 <td class="memname">#define RTE_USART12_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART12Tx</td> 3496 </tr> 3497 </table> 3498</div><div class="memdoc"> 3499 3500<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00305">305</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3501 3502</div> 3503</div> 3504<a id="a93373776f843912cefd1355e207352e2"></a> 3505<h2 class="memtitle"><span class="permalink"><a href="#a93373776f843912cefd1355e207352e2">◆ </a></span>RTE_USART1_DMA_EN</h2> 3506 3507<div class="memitem"> 3508<div class="memproto"> 3509 <table class="memname"> 3510 <tr> 3511 <td class="memname">#define RTE_USART1_DMA_EN   1</td> 3512 </tr> 3513 </table> 3514</div><div class="memdoc"> 3515 3516<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00040">40</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3517 3518</div> 3519</div> 3520<a id="af78c326f4aa3f8ba10614f88755ac30e"></a> 3521<h2 class="memtitle"><span class="permalink"><a href="#af78c326f4aa3f8ba10614f88755ac30e">◆ </a></span>RTE_USART1_DMA_RX_CH</h2> 3522 3523<div class="memitem"> 3524<div class="memproto"> 3525 <table class="memname"> 3526 <tr> 3527 <td class="memname">#define RTE_USART1_DMA_RX_CH   1</td> 3528 </tr> 3529 </table> 3530</div><div class="memdoc"> 3531 3532<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00209">209</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3533 3534</div> 3535</div> 3536<a id="ab58d0f95baca5b61fd1183daed257004"></a> 3537<h2 class="memtitle"><span class="permalink"><a href="#ab58d0f95baca5b61fd1183daed257004">◆ </a></span>RTE_USART1_DMA_RX_DMA_BASE</h2> 3538 3539<div class="memitem"> 3540<div class="memproto"> 3541 <table class="memname"> 3542 <tr> 3543 <td class="memname">#define RTE_USART1_DMA_RX_DMA_BASE   DMA0</td> 3544 </tr> 3545 </table> 3546</div><div class="memdoc"> 3547 3548<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00212">212</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3549 3550</div> 3551</div> 3552<a id="ad71e62366aea28e6c003f082a3ff5227"></a> 3553<h2 class="memtitle"><span class="permalink"><a href="#ad71e62366aea28e6c003f082a3ff5227">◆ </a></span>RTE_USART1_DMA_RX_DMAMUX_BASE</h2> 3554 3555<div class="memitem"> 3556<div class="memproto"> 3557 <table class="memname"> 3558 <tr> 3559 <td class="memname">#define RTE_USART1_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 3560 </tr> 3561 </table> 3562</div><div class="memdoc"> 3563 3564<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00211">211</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3565 3566</div> 3567</div> 3568<a id="a2e6bd424c90e5734c38eb4f198ed0347"></a> 3569<h2 class="memtitle"><span class="permalink"><a href="#a2e6bd424c90e5734c38eb4f198ed0347">◆ </a></span>RTE_USART1_DMA_RX_PERI_SEL</h2> 3570 3571<div class="memitem"> 3572<div class="memproto"> 3573 <table class="memname"> 3574 <tr> 3575 <td class="memname">#define RTE_USART1_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART1Rx</td> 3576 </tr> 3577 </table> 3578</div><div class="memdoc"> 3579 3580<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00210">210</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3581 3582</div> 3583</div> 3584<a id="a272ab6f694a794b54d6d0bacf4b030c3"></a> 3585<h2 class="memtitle"><span class="permalink"><a href="#a272ab6f694a794b54d6d0bacf4b030c3">◆ </a></span>RTE_USART1_DMA_TX_CH</h2> 3586 3587<div class="memitem"> 3588<div class="memproto"> 3589 <table class="memname"> 3590 <tr> 3591 <td class="memname">#define RTE_USART1_DMA_TX_CH   0</td> 3592 </tr> 3593 </table> 3594</div><div class="memdoc"> 3595 3596<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00205">205</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3597 3598</div> 3599</div> 3600<a id="a7804081da977b330578221c5ce5ba89e"></a> 3601<h2 class="memtitle"><span class="permalink"><a href="#a7804081da977b330578221c5ce5ba89e">◆ </a></span>RTE_USART1_DMA_TX_DMA_BASE</h2> 3602 3603<div class="memitem"> 3604<div class="memproto"> 3605 <table class="memname"> 3606 <tr> 3607 <td class="memname">#define RTE_USART1_DMA_TX_DMA_BASE   DMA0</td> 3608 </tr> 3609 </table> 3610</div><div class="memdoc"> 3611 3612<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00208">208</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3613 3614</div> 3615</div> 3616<a id="a28ef4acc4180de985e24a0bb392e42c8"></a> 3617<h2 class="memtitle"><span class="permalink"><a href="#a28ef4acc4180de985e24a0bb392e42c8">◆ </a></span>RTE_USART1_DMA_TX_DMAMUX_BASE</h2> 3618 3619<div class="memitem"> 3620<div class="memproto"> 3621 <table class="memname"> 3622 <tr> 3623 <td class="memname">#define RTE_USART1_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 3624 </tr> 3625 </table> 3626</div><div class="memdoc"> 3627 3628<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00207">207</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3629 3630</div> 3631</div> 3632<a id="ab360b9072ab5034fe19c591b11ddaa4f"></a> 3633<h2 class="memtitle"><span class="permalink"><a href="#ab360b9072ab5034fe19c591b11ddaa4f">◆ </a></span>RTE_USART1_DMA_TX_PERI_SEL</h2> 3634 3635<div class="memitem"> 3636<div class="memproto"> 3637 <table class="memname"> 3638 <tr> 3639 <td class="memname">#define RTE_USART1_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART1Tx</td> 3640 </tr> 3641 </table> 3642</div><div class="memdoc"> 3643 3644<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00206">206</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3645 3646</div> 3647</div> 3648<a id="af4f4f5e1f698d40d9f7d716257536d42"></a> 3649<h2 class="memtitle"><span class="permalink"><a href="#af4f4f5e1f698d40d9f7d716257536d42">◆ </a></span>RTE_USART2</h2> 3650 3651<div class="memitem"> 3652<div class="memproto"> 3653 <table class="memname"> 3654 <tr> 3655 <td class="memname">#define RTE_USART2   0</td> 3656 </tr> 3657 </table> 3658</div><div class="memdoc"> 3659 3660<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00041">41</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3661 3662</div> 3663</div> 3664<a id="a125adde5b7b5906d3427a57420322722"></a> 3665<h2 class="memtitle"><span class="permalink"><a href="#a125adde5b7b5906d3427a57420322722">◆ </a></span>RTE_USART2_DMA_EN</h2> 3666 3667<div class="memitem"> 3668<div class="memproto"> 3669 <table class="memname"> 3670 <tr> 3671 <td class="memname">#define RTE_USART2_DMA_EN   0</td> 3672 </tr> 3673 </table> 3674</div><div class="memdoc"> 3675 3676<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00042">42</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3677 3678</div> 3679</div> 3680<a id="aaf5d293f3353d103aa7fc672a3cf456d"></a> 3681<h2 class="memtitle"><span class="permalink"><a href="#aaf5d293f3353d103aa7fc672a3cf456d">◆ </a></span>RTE_USART2_DMA_RX_CH</h2> 3682 3683<div class="memitem"> 3684<div class="memproto"> 3685 <table class="memname"> 3686 <tr> 3687 <td class="memname">#define RTE_USART2_DMA_RX_CH   3</td> 3688 </tr> 3689 </table> 3690</div><div class="memdoc"> 3691 3692<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00218">218</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3693 3694</div> 3695</div> 3696<a id="a54af00b2f29f1e9aeb10e1a59a4cde3d"></a> 3697<h2 class="memtitle"><span class="permalink"><a href="#a54af00b2f29f1e9aeb10e1a59a4cde3d">◆ </a></span>RTE_USART2_DMA_RX_DMA_BASE</h2> 3698 3699<div class="memitem"> 3700<div class="memproto"> 3701 <table class="memname"> 3702 <tr> 3703 <td class="memname">#define RTE_USART2_DMA_RX_DMA_BASE   DMA0</td> 3704 </tr> 3705 </table> 3706</div><div class="memdoc"> 3707 3708<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00221">221</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3709 3710</div> 3711</div> 3712<a id="a4e45bca95b4f0c419b7aa5b27655e0f8"></a> 3713<h2 class="memtitle"><span class="permalink"><a href="#a4e45bca95b4f0c419b7aa5b27655e0f8">◆ </a></span>RTE_USART2_DMA_RX_DMAMUX_BASE</h2> 3714 3715<div class="memitem"> 3716<div class="memproto"> 3717 <table class="memname"> 3718 <tr> 3719 <td class="memname">#define RTE_USART2_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 3720 </tr> 3721 </table> 3722</div><div class="memdoc"> 3723 3724<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00220">220</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3725 3726</div> 3727</div> 3728<a id="ad8969d48f9a854dcd661e60ace8f2eac"></a> 3729<h2 class="memtitle"><span class="permalink"><a href="#ad8969d48f9a854dcd661e60ace8f2eac">◆ </a></span>RTE_USART2_DMA_RX_PERI_SEL</h2> 3730 3731<div class="memitem"> 3732<div class="memproto"> 3733 <table class="memname"> 3734 <tr> 3735 <td class="memname">#define RTE_USART2_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART2Rx</td> 3736 </tr> 3737 </table> 3738</div><div class="memdoc"> 3739 3740<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00219">219</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3741 3742</div> 3743</div> 3744<a id="a4da147c7ce755201a079c412c098128f"></a> 3745<h2 class="memtitle"><span class="permalink"><a href="#a4da147c7ce755201a079c412c098128f">◆ </a></span>RTE_USART2_DMA_TX_CH</h2> 3746 3747<div class="memitem"> 3748<div class="memproto"> 3749 <table class="memname"> 3750 <tr> 3751 <td class="memname">#define RTE_USART2_DMA_TX_CH   2</td> 3752 </tr> 3753 </table> 3754</div><div class="memdoc"> 3755 3756<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00214">214</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3757 3758</div> 3759</div> 3760<a id="a667adae4bda8ac302bcc85d4a7a004cd"></a> 3761<h2 class="memtitle"><span class="permalink"><a href="#a667adae4bda8ac302bcc85d4a7a004cd">◆ </a></span>RTE_USART2_DMA_TX_DMA_BASE</h2> 3762 3763<div class="memitem"> 3764<div class="memproto"> 3765 <table class="memname"> 3766 <tr> 3767 <td class="memname">#define RTE_USART2_DMA_TX_DMA_BASE   DMA0</td> 3768 </tr> 3769 </table> 3770</div><div class="memdoc"> 3771 3772<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00217">217</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3773 3774</div> 3775</div> 3776<a id="a35e29209a15939cab26f74b2d1f6daf9"></a> 3777<h2 class="memtitle"><span class="permalink"><a href="#a35e29209a15939cab26f74b2d1f6daf9">◆ </a></span>RTE_USART2_DMA_TX_DMAMUX_BASE</h2> 3778 3779<div class="memitem"> 3780<div class="memproto"> 3781 <table class="memname"> 3782 <tr> 3783 <td class="memname">#define RTE_USART2_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 3784 </tr> 3785 </table> 3786</div><div class="memdoc"> 3787 3788<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00216">216</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3789 3790</div> 3791</div> 3792<a id="a1921b3ed005879e26052e379f23dbcb2"></a> 3793<h2 class="memtitle"><span class="permalink"><a href="#a1921b3ed005879e26052e379f23dbcb2">◆ </a></span>RTE_USART2_DMA_TX_PERI_SEL</h2> 3794 3795<div class="memitem"> 3796<div class="memproto"> 3797 <table class="memname"> 3798 <tr> 3799 <td class="memname">#define RTE_USART2_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART2Tx</td> 3800 </tr> 3801 </table> 3802</div><div class="memdoc"> 3803 3804<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00215">215</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3805 3806</div> 3807</div> 3808<a id="ae6d7bafeb9d5b445ebadbd0f224bf1a5"></a> 3809<h2 class="memtitle"><span class="permalink"><a href="#ae6d7bafeb9d5b445ebadbd0f224bf1a5">◆ </a></span>RTE_USART3</h2> 3810 3811<div class="memitem"> 3812<div class="memproto"> 3813 <table class="memname"> 3814 <tr> 3815 <td class="memname">#define RTE_USART3   0</td> 3816 </tr> 3817 </table> 3818</div><div class="memdoc"> 3819 3820<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00043">43</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3821 3822</div> 3823</div> 3824<a id="a64fade6195385d3c00eeb16517725bb5"></a> 3825<h2 class="memtitle"><span class="permalink"><a href="#a64fade6195385d3c00eeb16517725bb5">◆ </a></span>RTE_USART3_DMA_EN</h2> 3826 3827<div class="memitem"> 3828<div class="memproto"> 3829 <table class="memname"> 3830 <tr> 3831 <td class="memname">#define RTE_USART3_DMA_EN   0</td> 3832 </tr> 3833 </table> 3834</div><div class="memdoc"> 3835 3836<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00044">44</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3837 3838</div> 3839</div> 3840<a id="ab09d3b40ddde8be68179be6d46400d45"></a> 3841<h2 class="memtitle"><span class="permalink"><a href="#ab09d3b40ddde8be68179be6d46400d45">◆ </a></span>RTE_USART3_DMA_RX_CH</h2> 3842 3843<div class="memitem"> 3844<div class="memproto"> 3845 <table class="memname"> 3846 <tr> 3847 <td class="memname">#define RTE_USART3_DMA_RX_CH   5</td> 3848 </tr> 3849 </table> 3850</div><div class="memdoc"> 3851 3852<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00227">227</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3853 3854</div> 3855</div> 3856<a id="ae05b2c8a2baaa32c10d0af3457ce2e28"></a> 3857<h2 class="memtitle"><span class="permalink"><a href="#ae05b2c8a2baaa32c10d0af3457ce2e28">◆ </a></span>RTE_USART3_DMA_RX_DMA_BASE</h2> 3858 3859<div class="memitem"> 3860<div class="memproto"> 3861 <table class="memname"> 3862 <tr> 3863 <td class="memname">#define RTE_USART3_DMA_RX_DMA_BASE   DMA0</td> 3864 </tr> 3865 </table> 3866</div><div class="memdoc"> 3867 3868<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00230">230</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3869 3870</div> 3871</div> 3872<a id="a7ce8b3cab8b376e492e0599890bb4ad0"></a> 3873<h2 class="memtitle"><span class="permalink"><a href="#a7ce8b3cab8b376e492e0599890bb4ad0">◆ </a></span>RTE_USART3_DMA_RX_DMAMUX_BASE</h2> 3874 3875<div class="memitem"> 3876<div class="memproto"> 3877 <table class="memname"> 3878 <tr> 3879 <td class="memname">#define RTE_USART3_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 3880 </tr> 3881 </table> 3882</div><div class="memdoc"> 3883 3884<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00229">229</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3885 3886</div> 3887</div> 3888<a id="ab310379c65913c108e059c4e317ce096"></a> 3889<h2 class="memtitle"><span class="permalink"><a href="#ab310379c65913c108e059c4e317ce096">◆ </a></span>RTE_USART3_DMA_RX_PERI_SEL</h2> 3890 3891<div class="memitem"> 3892<div class="memproto"> 3893 <table class="memname"> 3894 <tr> 3895 <td class="memname">#define RTE_USART3_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART3Rx</td> 3896 </tr> 3897 </table> 3898</div><div class="memdoc"> 3899 3900<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00228">228</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3901 3902</div> 3903</div> 3904<a id="a371552d64a4c36aa553a256ab52c4737"></a> 3905<h2 class="memtitle"><span class="permalink"><a href="#a371552d64a4c36aa553a256ab52c4737">◆ </a></span>RTE_USART3_DMA_TX_CH</h2> 3906 3907<div class="memitem"> 3908<div class="memproto"> 3909 <table class="memname"> 3910 <tr> 3911 <td class="memname">#define RTE_USART3_DMA_TX_CH   4</td> 3912 </tr> 3913 </table> 3914</div><div class="memdoc"> 3915 3916<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00223">223</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3917 3918</div> 3919</div> 3920<a id="a230981b96cecea4add332ecd40533454"></a> 3921<h2 class="memtitle"><span class="permalink"><a href="#a230981b96cecea4add332ecd40533454">◆ </a></span>RTE_USART3_DMA_TX_DMA_BASE</h2> 3922 3923<div class="memitem"> 3924<div class="memproto"> 3925 <table class="memname"> 3926 <tr> 3927 <td class="memname">#define RTE_USART3_DMA_TX_DMA_BASE   DMA0</td> 3928 </tr> 3929 </table> 3930</div><div class="memdoc"> 3931 3932<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00226">226</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3933 3934</div> 3935</div> 3936<a id="a05781de3d61d146f982ffb787d36f3fe"></a> 3937<h2 class="memtitle"><span class="permalink"><a href="#a05781de3d61d146f982ffb787d36f3fe">◆ </a></span>RTE_USART3_DMA_TX_DMAMUX_BASE</h2> 3938 3939<div class="memitem"> 3940<div class="memproto"> 3941 <table class="memname"> 3942 <tr> 3943 <td class="memname">#define RTE_USART3_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 3944 </tr> 3945 </table> 3946</div><div class="memdoc"> 3947 3948<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00225">225</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3949 3950</div> 3951</div> 3952<a id="a298c8ca62c3080284bf1c1ddc9e52c74"></a> 3953<h2 class="memtitle"><span class="permalink"><a href="#a298c8ca62c3080284bf1c1ddc9e52c74">◆ </a></span>RTE_USART3_DMA_TX_PERI_SEL</h2> 3954 3955<div class="memitem"> 3956<div class="memproto"> 3957 <table class="memname"> 3958 <tr> 3959 <td class="memname">#define RTE_USART3_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART3Tx</td> 3960 </tr> 3961 </table> 3962</div><div class="memdoc"> 3963 3964<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00224">224</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3965 3966</div> 3967</div> 3968<a id="a3716b269a4311d87ba183b633ebfad07"></a> 3969<h2 class="memtitle"><span class="permalink"><a href="#a3716b269a4311d87ba183b633ebfad07">◆ </a></span>RTE_USART4</h2> 3970 3971<div class="memitem"> 3972<div class="memproto"> 3973 <table class="memname"> 3974 <tr> 3975 <td class="memname">#define RTE_USART4   0</td> 3976 </tr> 3977 </table> 3978</div><div class="memdoc"> 3979 3980<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00045">45</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3981 3982</div> 3983</div> 3984<a id="abccb132237192d276dec5fd1235d3124"></a> 3985<h2 class="memtitle"><span class="permalink"><a href="#abccb132237192d276dec5fd1235d3124">◆ </a></span>RTE_USART4_DMA_EN</h2> 3986 3987<div class="memitem"> 3988<div class="memproto"> 3989 <table class="memname"> 3990 <tr> 3991 <td class="memname">#define RTE_USART4_DMA_EN   0</td> 3992 </tr> 3993 </table> 3994</div><div class="memdoc"> 3995 3996<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00046">46</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 3997 3998</div> 3999</div> 4000<a id="ae3aa08740bc1278f56cb25413751053b"></a> 4001<h2 class="memtitle"><span class="permalink"><a href="#ae3aa08740bc1278f56cb25413751053b">◆ </a></span>RTE_USART4_DMA_RX_CH</h2> 4002 4003<div class="memitem"> 4004<div class="memproto"> 4005 <table class="memname"> 4006 <tr> 4007 <td class="memname">#define RTE_USART4_DMA_RX_CH   7</td> 4008 </tr> 4009 </table> 4010</div><div class="memdoc"> 4011 4012<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00236">236</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4013 4014</div> 4015</div> 4016<a id="a84ae4f174efa1b7417b5a35d9b9e3de9"></a> 4017<h2 class="memtitle"><span class="permalink"><a href="#a84ae4f174efa1b7417b5a35d9b9e3de9">◆ </a></span>RTE_USART4_DMA_RX_DMA_BASE</h2> 4018 4019<div class="memitem"> 4020<div class="memproto"> 4021 <table class="memname"> 4022 <tr> 4023 <td class="memname">#define RTE_USART4_DMA_RX_DMA_BASE   DMA0</td> 4024 </tr> 4025 </table> 4026</div><div class="memdoc"> 4027 4028<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00239">239</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4029 4030</div> 4031</div> 4032<a id="a0af7a32050ae6ea721dc3bfe51cec886"></a> 4033<h2 class="memtitle"><span class="permalink"><a href="#a0af7a32050ae6ea721dc3bfe51cec886">◆ </a></span>RTE_USART4_DMA_RX_DMAMUX_BASE</h2> 4034 4035<div class="memitem"> 4036<div class="memproto"> 4037 <table class="memname"> 4038 <tr> 4039 <td class="memname">#define RTE_USART4_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 4040 </tr> 4041 </table> 4042</div><div class="memdoc"> 4043 4044<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00238">238</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4045 4046</div> 4047</div> 4048<a id="a2d133b10d9af3b93828d264638c01d69"></a> 4049<h2 class="memtitle"><span class="permalink"><a href="#a2d133b10d9af3b93828d264638c01d69">◆ </a></span>RTE_USART4_DMA_RX_PERI_SEL</h2> 4050 4051<div class="memitem"> 4052<div class="memproto"> 4053 <table class="memname"> 4054 <tr> 4055 <td class="memname">#define RTE_USART4_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART4Rx</td> 4056 </tr> 4057 </table> 4058</div><div class="memdoc"> 4059 4060<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00237">237</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4061 4062</div> 4063</div> 4064<a id="a583406cbb43d2e24e0cf8cafdb45d7d9"></a> 4065<h2 class="memtitle"><span class="permalink"><a href="#a583406cbb43d2e24e0cf8cafdb45d7d9">◆ </a></span>RTE_USART4_DMA_TX_CH</h2> 4066 4067<div class="memitem"> 4068<div class="memproto"> 4069 <table class="memname"> 4070 <tr> 4071 <td class="memname">#define RTE_USART4_DMA_TX_CH   6</td> 4072 </tr> 4073 </table> 4074</div><div class="memdoc"> 4075 4076<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00232">232</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4077 4078</div> 4079</div> 4080<a id="ac4abea21e4bfc3d03539f739892b0e7f"></a> 4081<h2 class="memtitle"><span class="permalink"><a href="#ac4abea21e4bfc3d03539f739892b0e7f">◆ </a></span>RTE_USART4_DMA_TX_DMA_BASE</h2> 4082 4083<div class="memitem"> 4084<div class="memproto"> 4085 <table class="memname"> 4086 <tr> 4087 <td class="memname">#define RTE_USART4_DMA_TX_DMA_BASE   DMA0</td> 4088 </tr> 4089 </table> 4090</div><div class="memdoc"> 4091 4092<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00235">235</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4093 4094</div> 4095</div> 4096<a id="a23d221d38fab3da9b28d9de859af9f48"></a> 4097<h2 class="memtitle"><span class="permalink"><a href="#a23d221d38fab3da9b28d9de859af9f48">◆ </a></span>RTE_USART4_DMA_TX_DMAMUX_BASE</h2> 4098 4099<div class="memitem"> 4100<div class="memproto"> 4101 <table class="memname"> 4102 <tr> 4103 <td class="memname">#define RTE_USART4_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 4104 </tr> 4105 </table> 4106</div><div class="memdoc"> 4107 4108<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00234">234</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4109 4110</div> 4111</div> 4112<a id="a2b6f4b82acc33b81f3637afc63419169"></a> 4113<h2 class="memtitle"><span class="permalink"><a href="#a2b6f4b82acc33b81f3637afc63419169">◆ </a></span>RTE_USART4_DMA_TX_PERI_SEL</h2> 4114 4115<div class="memitem"> 4116<div class="memproto"> 4117 <table class="memname"> 4118 <tr> 4119 <td class="memname">#define RTE_USART4_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART4Tx</td> 4120 </tr> 4121 </table> 4122</div><div class="memdoc"> 4123 4124<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00233">233</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4125 4126</div> 4127</div> 4128<a id="a5c2c625ac67c8f31440a92490b6d767e"></a> 4129<h2 class="memtitle"><span class="permalink"><a href="#a5c2c625ac67c8f31440a92490b6d767e">◆ </a></span>RTE_USART5</h2> 4130 4131<div class="memitem"> 4132<div class="memproto"> 4133 <table class="memname"> 4134 <tr> 4135 <td class="memname">#define RTE_USART5   0</td> 4136 </tr> 4137 </table> 4138</div><div class="memdoc"> 4139 4140<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00047">47</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4141 4142</div> 4143</div> 4144<a id="aaf003f78b5c4c182d687b220e75e1dbb"></a> 4145<h2 class="memtitle"><span class="permalink"><a href="#aaf003f78b5c4c182d687b220e75e1dbb">◆ </a></span>RTE_USART5_DMA_EN</h2> 4146 4147<div class="memitem"> 4148<div class="memproto"> 4149 <table class="memname"> 4150 <tr> 4151 <td class="memname">#define RTE_USART5_DMA_EN   0</td> 4152 </tr> 4153 </table> 4154</div><div class="memdoc"> 4155 4156<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00048">48</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4157 4158</div> 4159</div> 4160<a id="af563379f0b22b56089642e1452293b94"></a> 4161<h2 class="memtitle"><span class="permalink"><a href="#af563379f0b22b56089642e1452293b94">◆ </a></span>RTE_USART5_DMA_RX_CH</h2> 4162 4163<div class="memitem"> 4164<div class="memproto"> 4165 <table class="memname"> 4166 <tr> 4167 <td class="memname">#define RTE_USART5_DMA_RX_CH   9</td> 4168 </tr> 4169 </table> 4170</div><div class="memdoc"> 4171 4172<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00245">245</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4173 4174</div> 4175</div> 4176<a id="a665e630b27a6713ff3055c9893403090"></a> 4177<h2 class="memtitle"><span class="permalink"><a href="#a665e630b27a6713ff3055c9893403090">◆ </a></span>RTE_USART5_DMA_RX_DMA_BASE</h2> 4178 4179<div class="memitem"> 4180<div class="memproto"> 4181 <table class="memname"> 4182 <tr> 4183 <td class="memname">#define RTE_USART5_DMA_RX_DMA_BASE   DMA0</td> 4184 </tr> 4185 </table> 4186</div><div class="memdoc"> 4187 4188<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00248">248</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4189 4190</div> 4191</div> 4192<a id="a7a8f2581e0cbec8210edb6f89f7b187c"></a> 4193<h2 class="memtitle"><span class="permalink"><a href="#a7a8f2581e0cbec8210edb6f89f7b187c">◆ </a></span>RTE_USART5_DMA_RX_DMAMUX_BASE</h2> 4194 4195<div class="memitem"> 4196<div class="memproto"> 4197 <table class="memname"> 4198 <tr> 4199 <td class="memname">#define RTE_USART5_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 4200 </tr> 4201 </table> 4202</div><div class="memdoc"> 4203 4204<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00247">247</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4205 4206</div> 4207</div> 4208<a id="a4dc20b4bfb5766bac0d6de434bda7fd8"></a> 4209<h2 class="memtitle"><span class="permalink"><a href="#a4dc20b4bfb5766bac0d6de434bda7fd8">◆ </a></span>RTE_USART5_DMA_RX_PERI_SEL</h2> 4210 4211<div class="memitem"> 4212<div class="memproto"> 4213 <table class="memname"> 4214 <tr> 4215 <td class="memname">#define RTE_USART5_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART5Rx</td> 4216 </tr> 4217 </table> 4218</div><div class="memdoc"> 4219 4220<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00246">246</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4221 4222</div> 4223</div> 4224<a id="a5fc281007f625bf44a5b16d7f97c9f7b"></a> 4225<h2 class="memtitle"><span class="permalink"><a href="#a5fc281007f625bf44a5b16d7f97c9f7b">◆ </a></span>RTE_USART5_DMA_TX_CH</h2> 4226 4227<div class="memitem"> 4228<div class="memproto"> 4229 <table class="memname"> 4230 <tr> 4231 <td class="memname">#define RTE_USART5_DMA_TX_CH   8</td> 4232 </tr> 4233 </table> 4234</div><div class="memdoc"> 4235 4236<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00241">241</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4237 4238</div> 4239</div> 4240<a id="a530f52cd5d979b98f959163c96e4413b"></a> 4241<h2 class="memtitle"><span class="permalink"><a href="#a530f52cd5d979b98f959163c96e4413b">◆ </a></span>RTE_USART5_DMA_TX_DMA_BASE</h2> 4242 4243<div class="memitem"> 4244<div class="memproto"> 4245 <table class="memname"> 4246 <tr> 4247 <td class="memname">#define RTE_USART5_DMA_TX_DMA_BASE   DMA0</td> 4248 </tr> 4249 </table> 4250</div><div class="memdoc"> 4251 4252<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00244">244</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4253 4254</div> 4255</div> 4256<a id="ae6732d5a38b93890d64314a0837a1d34"></a> 4257<h2 class="memtitle"><span class="permalink"><a href="#ae6732d5a38b93890d64314a0837a1d34">◆ </a></span>RTE_USART5_DMA_TX_DMAMUX_BASE</h2> 4258 4259<div class="memitem"> 4260<div class="memproto"> 4261 <table class="memname"> 4262 <tr> 4263 <td class="memname">#define RTE_USART5_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 4264 </tr> 4265 </table> 4266</div><div class="memdoc"> 4267 4268<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00243">243</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4269 4270</div> 4271</div> 4272<a id="a3f34578afbd133748801bbb852f1cc46"></a> 4273<h2 class="memtitle"><span class="permalink"><a href="#a3f34578afbd133748801bbb852f1cc46">◆ </a></span>RTE_USART5_DMA_TX_PERI_SEL</h2> 4274 4275<div class="memitem"> 4276<div class="memproto"> 4277 <table class="memname"> 4278 <tr> 4279 <td class="memname">#define RTE_USART5_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART5Tx</td> 4280 </tr> 4281 </table> 4282</div><div class="memdoc"> 4283 4284<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00242">242</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4285 4286</div> 4287</div> 4288<a id="af4a7b2970a0f7ac0ee0802298c09848c"></a> 4289<h2 class="memtitle"><span class="permalink"><a href="#af4a7b2970a0f7ac0ee0802298c09848c">◆ </a></span>RTE_USART6</h2> 4290 4291<div class="memitem"> 4292<div class="memproto"> 4293 <table class="memname"> 4294 <tr> 4295 <td class="memname">#define RTE_USART6   0</td> 4296 </tr> 4297 </table> 4298</div><div class="memdoc"> 4299 4300<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00049">49</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4301 4302</div> 4303</div> 4304<a id="a46301a9b2d783e5c629b180d8f2344f6"></a> 4305<h2 class="memtitle"><span class="permalink"><a href="#a46301a9b2d783e5c629b180d8f2344f6">◆ </a></span>RTE_USART6_DMA_EN</h2> 4306 4307<div class="memitem"> 4308<div class="memproto"> 4309 <table class="memname"> 4310 <tr> 4311 <td class="memname">#define RTE_USART6_DMA_EN   0</td> 4312 </tr> 4313 </table> 4314</div><div class="memdoc"> 4315 4316<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00050">50</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4317 4318</div> 4319</div> 4320<a id="a74e96a5225571536daf6ce2058f2ca11"></a> 4321<h2 class="memtitle"><span class="permalink"><a href="#a74e96a5225571536daf6ce2058f2ca11">◆ </a></span>RTE_USART6_DMA_RX_CH</h2> 4322 4323<div class="memitem"> 4324<div class="memproto"> 4325 <table class="memname"> 4326 <tr> 4327 <td class="memname">#define RTE_USART6_DMA_RX_CH   11</td> 4328 </tr> 4329 </table> 4330</div><div class="memdoc"> 4331 4332<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00254">254</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4333 4334</div> 4335</div> 4336<a id="a5937989b65e91558a7ecd473a511e5e6"></a> 4337<h2 class="memtitle"><span class="permalink"><a href="#a5937989b65e91558a7ecd473a511e5e6">◆ </a></span>RTE_USART6_DMA_RX_DMA_BASE</h2> 4338 4339<div class="memitem"> 4340<div class="memproto"> 4341 <table class="memname"> 4342 <tr> 4343 <td class="memname">#define RTE_USART6_DMA_RX_DMA_BASE   DMA0</td> 4344 </tr> 4345 </table> 4346</div><div class="memdoc"> 4347 4348<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00257">257</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4349 4350</div> 4351</div> 4352<a id="aeb3cf21340277e8390db8a14d63ee5d5"></a> 4353<h2 class="memtitle"><span class="permalink"><a href="#aeb3cf21340277e8390db8a14d63ee5d5">◆ </a></span>RTE_USART6_DMA_RX_DMAMUX_BASE</h2> 4354 4355<div class="memitem"> 4356<div class="memproto"> 4357 <table class="memname"> 4358 <tr> 4359 <td class="memname">#define RTE_USART6_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 4360 </tr> 4361 </table> 4362</div><div class="memdoc"> 4363 4364<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00256">256</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4365 4366</div> 4367</div> 4368<a id="ad55c040ec06f230089b7f190f5eb5589"></a> 4369<h2 class="memtitle"><span class="permalink"><a href="#ad55c040ec06f230089b7f190f5eb5589">◆ </a></span>RTE_USART6_DMA_RX_PERI_SEL</h2> 4370 4371<div class="memitem"> 4372<div class="memproto"> 4373 <table class="memname"> 4374 <tr> 4375 <td class="memname">#define RTE_USART6_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART6Rx</td> 4376 </tr> 4377 </table> 4378</div><div class="memdoc"> 4379 4380<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00255">255</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4381 4382</div> 4383</div> 4384<a id="a830ccf4153d422fc98971a8fc2d1ecba"></a> 4385<h2 class="memtitle"><span class="permalink"><a href="#a830ccf4153d422fc98971a8fc2d1ecba">◆ </a></span>RTE_USART6_DMA_TX_CH</h2> 4386 4387<div class="memitem"> 4388<div class="memproto"> 4389 <table class="memname"> 4390 <tr> 4391 <td class="memname">#define RTE_USART6_DMA_TX_CH   10</td> 4392 </tr> 4393 </table> 4394</div><div class="memdoc"> 4395 4396<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00250">250</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4397 4398</div> 4399</div> 4400<a id="aa50f707f6ba72c2c400faa7e2c9b8b5f"></a> 4401<h2 class="memtitle"><span class="permalink"><a href="#aa50f707f6ba72c2c400faa7e2c9b8b5f">◆ </a></span>RTE_USART6_DMA_TX_DMA_BASE</h2> 4402 4403<div class="memitem"> 4404<div class="memproto"> 4405 <table class="memname"> 4406 <tr> 4407 <td class="memname">#define RTE_USART6_DMA_TX_DMA_BASE   DMA0</td> 4408 </tr> 4409 </table> 4410</div><div class="memdoc"> 4411 4412<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00253">253</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4413 4414</div> 4415</div> 4416<a id="af6111a4ca33179e72211e0a267f1b40e"></a> 4417<h2 class="memtitle"><span class="permalink"><a href="#af6111a4ca33179e72211e0a267f1b40e">◆ </a></span>RTE_USART6_DMA_TX_DMAMUX_BASE</h2> 4418 4419<div class="memitem"> 4420<div class="memproto"> 4421 <table class="memname"> 4422 <tr> 4423 <td class="memname">#define RTE_USART6_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 4424 </tr> 4425 </table> 4426</div><div class="memdoc"> 4427 4428<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00252">252</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4429 4430</div> 4431</div> 4432<a id="ac1692d643111d558f2df528205966f28"></a> 4433<h2 class="memtitle"><span class="permalink"><a href="#ac1692d643111d558f2df528205966f28">◆ </a></span>RTE_USART6_DMA_TX_PERI_SEL</h2> 4434 4435<div class="memitem"> 4436<div class="memproto"> 4437 <table class="memname"> 4438 <tr> 4439 <td class="memname">#define RTE_USART6_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART6Tx</td> 4440 </tr> 4441 </table> 4442</div><div class="memdoc"> 4443 4444<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00251">251</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4445 4446</div> 4447</div> 4448<a id="a416995bb1dd6c68b54b5b2dd85f8bc08"></a> 4449<h2 class="memtitle"><span class="permalink"><a href="#a416995bb1dd6c68b54b5b2dd85f8bc08">◆ </a></span>RTE_USART7</h2> 4450 4451<div class="memitem"> 4452<div class="memproto"> 4453 <table class="memname"> 4454 <tr> 4455 <td class="memname">#define RTE_USART7   0</td> 4456 </tr> 4457 </table> 4458</div><div class="memdoc"> 4459 4460<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00051">51</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4461 4462</div> 4463</div> 4464<a id="abde2f17d347b0f02c34cd1875f8bcaba"></a> 4465<h2 class="memtitle"><span class="permalink"><a href="#abde2f17d347b0f02c34cd1875f8bcaba">◆ </a></span>RTE_USART7_DMA_EN</h2> 4466 4467<div class="memitem"> 4468<div class="memproto"> 4469 <table class="memname"> 4470 <tr> 4471 <td class="memname">#define RTE_USART7_DMA_EN   0</td> 4472 </tr> 4473 </table> 4474</div><div class="memdoc"> 4475 4476<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00052">52</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4477 4478</div> 4479</div> 4480<a id="a18ee2a3fba2891c00a7a2d126a81b91f"></a> 4481<h2 class="memtitle"><span class="permalink"><a href="#a18ee2a3fba2891c00a7a2d126a81b91f">◆ </a></span>RTE_USART7_DMA_RX_CH</h2> 4482 4483<div class="memitem"> 4484<div class="memproto"> 4485 <table class="memname"> 4486 <tr> 4487 <td class="memname">#define RTE_USART7_DMA_RX_CH   13</td> 4488 </tr> 4489 </table> 4490</div><div class="memdoc"> 4491 4492<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00263">263</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4493 4494</div> 4495</div> 4496<a id="aff3f3b4435760ac40c7d6a8837642f76"></a> 4497<h2 class="memtitle"><span class="permalink"><a href="#aff3f3b4435760ac40c7d6a8837642f76">◆ </a></span>RTE_USART7_DMA_RX_DMA_BASE</h2> 4498 4499<div class="memitem"> 4500<div class="memproto"> 4501 <table class="memname"> 4502 <tr> 4503 <td class="memname">#define RTE_USART7_DMA_RX_DMA_BASE   DMA0</td> 4504 </tr> 4505 </table> 4506</div><div class="memdoc"> 4507 4508<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00266">266</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4509 4510</div> 4511</div> 4512<a id="a82d952d94e0f421c0928b7bb9271650f"></a> 4513<h2 class="memtitle"><span class="permalink"><a href="#a82d952d94e0f421c0928b7bb9271650f">◆ </a></span>RTE_USART7_DMA_RX_DMAMUX_BASE</h2> 4514 4515<div class="memitem"> 4516<div class="memproto"> 4517 <table class="memname"> 4518 <tr> 4519 <td class="memname">#define RTE_USART7_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 4520 </tr> 4521 </table> 4522</div><div class="memdoc"> 4523 4524<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00265">265</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4525 4526</div> 4527</div> 4528<a id="a5a048d82fae4604ff6183679a90197c3"></a> 4529<h2 class="memtitle"><span class="permalink"><a href="#a5a048d82fae4604ff6183679a90197c3">◆ </a></span>RTE_USART7_DMA_RX_PERI_SEL</h2> 4530 4531<div class="memitem"> 4532<div class="memproto"> 4533 <table class="memname"> 4534 <tr> 4535 <td class="memname">#define RTE_USART7_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART7Rx</td> 4536 </tr> 4537 </table> 4538</div><div class="memdoc"> 4539 4540<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00264">264</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4541 4542</div> 4543</div> 4544<a id="a4f3d104ac7e9a07019d58c26bd53e9a1"></a> 4545<h2 class="memtitle"><span class="permalink"><a href="#a4f3d104ac7e9a07019d58c26bd53e9a1">◆ </a></span>RTE_USART7_DMA_TX_CH</h2> 4546 4547<div class="memitem"> 4548<div class="memproto"> 4549 <table class="memname"> 4550 <tr> 4551 <td class="memname">#define RTE_USART7_DMA_TX_CH   12</td> 4552 </tr> 4553 </table> 4554</div><div class="memdoc"> 4555 4556<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00259">259</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4557 4558</div> 4559</div> 4560<a id="a9417cafd6534bd6b4be87b6bea6ac16c"></a> 4561<h2 class="memtitle"><span class="permalink"><a href="#a9417cafd6534bd6b4be87b6bea6ac16c">◆ </a></span>RTE_USART7_DMA_TX_DMA_BASE</h2> 4562 4563<div class="memitem"> 4564<div class="memproto"> 4565 <table class="memname"> 4566 <tr> 4567 <td class="memname">#define RTE_USART7_DMA_TX_DMA_BASE   DMA0</td> 4568 </tr> 4569 </table> 4570</div><div class="memdoc"> 4571 4572<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00262">262</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4573 4574</div> 4575</div> 4576<a id="a8b9a5d583e90a47e3f535b114da2512f"></a> 4577<h2 class="memtitle"><span class="permalink"><a href="#a8b9a5d583e90a47e3f535b114da2512f">◆ </a></span>RTE_USART7_DMA_TX_DMAMUX_BASE</h2> 4578 4579<div class="memitem"> 4580<div class="memproto"> 4581 <table class="memname"> 4582 <tr> 4583 <td class="memname">#define RTE_USART7_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 4584 </tr> 4585 </table> 4586</div><div class="memdoc"> 4587 4588<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00261">261</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4589 4590</div> 4591</div> 4592<a id="a9105787bef980157f54fc11f21ee84b5"></a> 4593<h2 class="memtitle"><span class="permalink"><a href="#a9105787bef980157f54fc11f21ee84b5">◆ </a></span>RTE_USART7_DMA_TX_PERI_SEL</h2> 4594 4595<div class="memitem"> 4596<div class="memproto"> 4597 <table class="memname"> 4598 <tr> 4599 <td class="memname">#define RTE_USART7_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART7Tx</td> 4600 </tr> 4601 </table> 4602</div><div class="memdoc"> 4603 4604<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00260">260</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4605 4606</div> 4607</div> 4608<a id="a40f133071df7d0c18dd19c6f24e45d7a"></a> 4609<h2 class="memtitle"><span class="permalink"><a href="#a40f133071df7d0c18dd19c6f24e45d7a">◆ </a></span>RTE_USART8</h2> 4610 4611<div class="memitem"> 4612<div class="memproto"> 4613 <table class="memname"> 4614 <tr> 4615 <td class="memname">#define RTE_USART8   0</td> 4616 </tr> 4617 </table> 4618</div><div class="memdoc"> 4619 4620<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00053">53</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4621 4622</div> 4623</div> 4624<a id="a8f35821f094b48ab18d0ee7eb9049686"></a> 4625<h2 class="memtitle"><span class="permalink"><a href="#a8f35821f094b48ab18d0ee7eb9049686">◆ </a></span>RTE_USART8_DMA_EN</h2> 4626 4627<div class="memitem"> 4628<div class="memproto"> 4629 <table class="memname"> 4630 <tr> 4631 <td class="memname">#define RTE_USART8_DMA_EN   0</td> 4632 </tr> 4633 </table> 4634</div><div class="memdoc"> 4635 4636<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00054">54</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4637 4638</div> 4639</div> 4640<a id="a2b464e7a19d4ae0e950dac79aff6adbc"></a> 4641<h2 class="memtitle"><span class="permalink"><a href="#a2b464e7a19d4ae0e950dac79aff6adbc">◆ </a></span>RTE_USART8_DMA_RX_CH</h2> 4642 4643<div class="memitem"> 4644<div class="memproto"> 4645 <table class="memname"> 4646 <tr> 4647 <td class="memname">#define RTE_USART8_DMA_RX_CH   15</td> 4648 </tr> 4649 </table> 4650</div><div class="memdoc"> 4651 4652<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00272">272</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4653 4654</div> 4655</div> 4656<a id="a35b22acc74d0ae6d339a14fdebc5e4d5"></a> 4657<h2 class="memtitle"><span class="permalink"><a href="#a35b22acc74d0ae6d339a14fdebc5e4d5">◆ </a></span>RTE_USART8_DMA_RX_DMA_BASE</h2> 4658 4659<div class="memitem"> 4660<div class="memproto"> 4661 <table class="memname"> 4662 <tr> 4663 <td class="memname">#define RTE_USART8_DMA_RX_DMA_BASE   DMA0</td> 4664 </tr> 4665 </table> 4666</div><div class="memdoc"> 4667 4668<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00275">275</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4669 4670</div> 4671</div> 4672<a id="a155ae73ee7cdaff86bb2ddefa2873dcb"></a> 4673<h2 class="memtitle"><span class="permalink"><a href="#a155ae73ee7cdaff86bb2ddefa2873dcb">◆ </a></span>RTE_USART8_DMA_RX_DMAMUX_BASE</h2> 4674 4675<div class="memitem"> 4676<div class="memproto"> 4677 <table class="memname"> 4678 <tr> 4679 <td class="memname">#define RTE_USART8_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 4680 </tr> 4681 </table> 4682</div><div class="memdoc"> 4683 4684<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00274">274</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4685 4686</div> 4687</div> 4688<a id="a5c16789d134aa6368dbe2d7a7110211c"></a> 4689<h2 class="memtitle"><span class="permalink"><a href="#a5c16789d134aa6368dbe2d7a7110211c">◆ </a></span>RTE_USART8_DMA_RX_PERI_SEL</h2> 4690 4691<div class="memitem"> 4692<div class="memproto"> 4693 <table class="memname"> 4694 <tr> 4695 <td class="memname">#define RTE_USART8_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART8Rx</td> 4696 </tr> 4697 </table> 4698</div><div class="memdoc"> 4699 4700<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00273">273</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4701 4702</div> 4703</div> 4704<a id="abcc6c1f63b1f4885829e6b98f2f99230"></a> 4705<h2 class="memtitle"><span class="permalink"><a href="#abcc6c1f63b1f4885829e6b98f2f99230">◆ </a></span>RTE_USART8_DMA_TX_CH</h2> 4706 4707<div class="memitem"> 4708<div class="memproto"> 4709 <table class="memname"> 4710 <tr> 4711 <td class="memname">#define RTE_USART8_DMA_TX_CH   14</td> 4712 </tr> 4713 </table> 4714</div><div class="memdoc"> 4715 4716<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00268">268</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4717 4718</div> 4719</div> 4720<a id="a0bba1923dd63a116b3c4ef8fcebe26c7"></a> 4721<h2 class="memtitle"><span class="permalink"><a href="#a0bba1923dd63a116b3c4ef8fcebe26c7">◆ </a></span>RTE_USART8_DMA_TX_DMA_BASE</h2> 4722 4723<div class="memitem"> 4724<div class="memproto"> 4725 <table class="memname"> 4726 <tr> 4727 <td class="memname">#define RTE_USART8_DMA_TX_DMA_BASE   DMA0</td> 4728 </tr> 4729 </table> 4730</div><div class="memdoc"> 4731 4732<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00271">271</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4733 4734</div> 4735</div> 4736<a id="a8819d5c827bdd7fbdc30d885547cbf0d"></a> 4737<h2 class="memtitle"><span class="permalink"><a href="#a8819d5c827bdd7fbdc30d885547cbf0d">◆ </a></span>RTE_USART8_DMA_TX_DMAMUX_BASE</h2> 4738 4739<div class="memitem"> 4740<div class="memproto"> 4741 <table class="memname"> 4742 <tr> 4743 <td class="memname">#define RTE_USART8_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 4744 </tr> 4745 </table> 4746</div><div class="memdoc"> 4747 4748<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00270">270</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4749 4750</div> 4751</div> 4752<a id="a32cb9cebe1faa5aaa4103e3bbc5053e8"></a> 4753<h2 class="memtitle"><span class="permalink"><a href="#a32cb9cebe1faa5aaa4103e3bbc5053e8">◆ </a></span>RTE_USART8_DMA_TX_PERI_SEL</h2> 4754 4755<div class="memitem"> 4756<div class="memproto"> 4757 <table class="memname"> 4758 <tr> 4759 <td class="memname">#define RTE_USART8_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART8Tx</td> 4760 </tr> 4761 </table> 4762</div><div class="memdoc"> 4763 4764<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00269">269</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4765 4766</div> 4767</div> 4768<a id="a17247f1beecc5e8c6714787be8ec8949"></a> 4769<h2 class="memtitle"><span class="permalink"><a href="#a17247f1beecc5e8c6714787be8ec8949">◆ </a></span>RTE_USART9</h2> 4770 4771<div class="memitem"> 4772<div class="memproto"> 4773 <table class="memname"> 4774 <tr> 4775 <td class="memname">#define RTE_USART9   0</td> 4776 </tr> 4777 </table> 4778</div><div class="memdoc"> 4779 4780<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00055">55</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4781 4782</div> 4783</div> 4784<a id="a7b2e03393b77773fcaaf18e32eb3104a"></a> 4785<h2 class="memtitle"><span class="permalink"><a href="#a7b2e03393b77773fcaaf18e32eb3104a">◆ </a></span>RTE_USART9_DMA_EN</h2> 4786 4787<div class="memitem"> 4788<div class="memproto"> 4789 <table class="memname"> 4790 <tr> 4791 <td class="memname">#define RTE_USART9_DMA_EN   0</td> 4792 </tr> 4793 </table> 4794</div><div class="memdoc"> 4795 4796<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00056">56</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4797 4798</div> 4799</div> 4800<a id="ac9a2bb67aec256c83d9fe501eb43c43b"></a> 4801<h2 class="memtitle"><span class="permalink"><a href="#ac9a2bb67aec256c83d9fe501eb43c43b">◆ </a></span>RTE_USART9_DMA_RX_CH</h2> 4802 4803<div class="memitem"> 4804<div class="memproto"> 4805 <table class="memname"> 4806 <tr> 4807 <td class="memname">#define RTE_USART9_DMA_RX_CH   17</td> 4808 </tr> 4809 </table> 4810</div><div class="memdoc"> 4811 4812<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00281">281</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4813 4814</div> 4815</div> 4816<a id="a3774cca453a9602c146e45d5f3f15744"></a> 4817<h2 class="memtitle"><span class="permalink"><a href="#a3774cca453a9602c146e45d5f3f15744">◆ </a></span>RTE_USART9_DMA_RX_DMA_BASE</h2> 4818 4819<div class="memitem"> 4820<div class="memproto"> 4821 <table class="memname"> 4822 <tr> 4823 <td class="memname">#define RTE_USART9_DMA_RX_DMA_BASE   DMA0</td> 4824 </tr> 4825 </table> 4826</div><div class="memdoc"> 4827 4828<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00284">284</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4829 4830</div> 4831</div> 4832<a id="a4cf1f6bbfe5beb45a546c685a7832da9"></a> 4833<h2 class="memtitle"><span class="permalink"><a href="#a4cf1f6bbfe5beb45a546c685a7832da9">◆ </a></span>RTE_USART9_DMA_RX_DMAMUX_BASE</h2> 4834 4835<div class="memitem"> 4836<div class="memproto"> 4837 <table class="memname"> 4838 <tr> 4839 <td class="memname">#define RTE_USART9_DMA_RX_DMAMUX_BASE   DMAMUX0</td> 4840 </tr> 4841 </table> 4842</div><div class="memdoc"> 4843 4844<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00283">283</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4845 4846</div> 4847</div> 4848<a id="ad17f943b2877b59baa700768f299ac1f"></a> 4849<h2 class="memtitle"><span class="permalink"><a href="#ad17f943b2877b59baa700768f299ac1f">◆ </a></span>RTE_USART9_DMA_RX_PERI_SEL</h2> 4850 4851<div class="memitem"> 4852<div class="memproto"> 4853 <table class="memname"> 4854 <tr> 4855 <td class="memname">#define RTE_USART9_DMA_RX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART9Rx</td> 4856 </tr> 4857 </table> 4858</div><div class="memdoc"> 4859 4860<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00282">282</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4861 4862</div> 4863</div> 4864<a id="a3fcb81ca746a43a1ca1437f697eb27fc"></a> 4865<h2 class="memtitle"><span class="permalink"><a href="#a3fcb81ca746a43a1ca1437f697eb27fc">◆ </a></span>RTE_USART9_DMA_TX_CH</h2> 4866 4867<div class="memitem"> 4868<div class="memproto"> 4869 <table class="memname"> 4870 <tr> 4871 <td class="memname">#define RTE_USART9_DMA_TX_CH   16</td> 4872 </tr> 4873 </table> 4874</div><div class="memdoc"> 4875 4876<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00277">277</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4877 4878</div> 4879</div> 4880<a id="a2d6c62e2fc4b1e0a71103c653cbd52cd"></a> 4881<h2 class="memtitle"><span class="permalink"><a href="#a2d6c62e2fc4b1e0a71103c653cbd52cd">◆ </a></span>RTE_USART9_DMA_TX_DMA_BASE</h2> 4882 4883<div class="memitem"> 4884<div class="memproto"> 4885 <table class="memname"> 4886 <tr> 4887 <td class="memname">#define RTE_USART9_DMA_TX_DMA_BASE   DMA0</td> 4888 </tr> 4889 </table> 4890</div><div class="memdoc"> 4891 4892<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00280">280</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4893 4894</div> 4895</div> 4896<a id="a9501ce390ace1147e1e2b64f2a7e16c7"></a> 4897<h2 class="memtitle"><span class="permalink"><a href="#a9501ce390ace1147e1e2b64f2a7e16c7">◆ </a></span>RTE_USART9_DMA_TX_DMAMUX_BASE</h2> 4898 4899<div class="memitem"> 4900<div class="memproto"> 4901 <table class="memname"> 4902 <tr> 4903 <td class="memname">#define RTE_USART9_DMA_TX_DMAMUX_BASE   DMAMUX0</td> 4904 </tr> 4905 </table> 4906</div><div class="memdoc"> 4907 4908<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00279">279</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4909 4910</div> 4911</div> 4912<a id="a97dd4ab8c461b660212839a0a83a8854"></a> 4913<h2 class="memtitle"><span class="permalink"><a href="#a97dd4ab8c461b660212839a0a83a8854">◆ </a></span>RTE_USART9_DMA_TX_PERI_SEL</h2> 4914 4915<div class="memitem"> 4916<div class="memproto"> 4917 <table class="memname"> 4918 <tr> 4919 <td class="memname">#define RTE_USART9_DMA_TX_PERI_SEL   (uint8_t) kDmaRequestMuxLPUART9Tx</td> 4920 </tr> 4921 </table> 4922</div><div class="memdoc"> 4923 4924<p class="definition">Definition at line <a class="el" href="a04727_source.html#l00278">278</a> of file <a class="el" href="a04727_source.html">RTE_Device.h</a>.</p> 4925 4926</div> 4927</div> 4928</div><!-- contents --> 4929 4930<hr class="footer"/><address class="footer"><small> 4931© Copyright 2016-2022 NXP. All Rights Reserved. SPDX-License-Identifier: BSD-3-Clause 4932</small></address> 4933</body> 4934</html> 4935
