1<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> 2<html xmlns="http://www.w3.org/1999/xhtml"> 3<head> 4<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> 5<meta http-equiv="X-UA-Compatible" content="IE=9"/> 6<meta name="generator" content="Doxygen 1.8.13"/> 7<meta name="viewport" content="width=device-width, initial-scale=1"/> 8<title>ISSDK: boardkit/frdm-k64f/clock_config.c File Reference</title> 9<link href="tabs.css" rel="stylesheet" type="text/css"/> 10<script type="text/javascript" src="jquery.js"></script> 11<script type="text/javascript" src="dynsections.js"></script> 12<link href="issdk_stylesheet.css" rel="stylesheet" type="text/css" /> 13</head> 14<body> 15<div id="top"><!-- do not remove this div, it is closed by doxygen! --> 16<div id="titlearea"> 17<table cellspacing="0" cellpadding="0"> 18 <tbody> 19 <tr style="height: 56px;"> 20 <td id="projectlogo"><img alt="Logo" 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href="#func-members">Functions</a> | 50<a href="#var-members">Variables</a> </div> 51 <div class="headertitle"> 52<div class="title">clock_config.c File Reference</div> </div> 53</div><!--header--> 54<div class="contents"> 55<div class="textblock"><code>#include "fsl_smc.h"</code><br /> 56<code>#include "<a class="el" href="a04280_source.html">clock_config.h</a>"</code><br /> 57</div><div class="textblock"><div class="dynheader"> 58Include dependency graph for clock_config.c:</div> 59<div class="dyncontent"> 60<div class="center"><img src="a04224.png" border="0" usemap="#boardkit_2frdm-k64f_2clock__config_8c" alt=""/></div> 61<map name="boardkit_2frdm-k64f_2clock__config_8c" id="boardkit_2frdm-k64f_2clock__config_8c"> 62<area shape="rect" id="node3" href="a04280.html" title="clock_config.h" alt="" coords="108,95,213,121"/> 63</map> 64</div> 65</div> 66<p><a href="a04223_source.html">Go to the source code of this file.</a></p> 67<table class="memberdecls"> 68<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> 69Macros</h2></td></tr> 70<tr class="memitem:ab7ada7a74d398bf218d4d25934fce66c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#ab7ada7a74d398bf218d4d25934fce66c">MCG_PLL_DISABLE</a>   0U</td></tr> 71<tr class="separator:ab7ada7a74d398bf218d4d25934fce66c"><td class="memSeparator" colspan="2"> </td></tr> 72<tr class="memitem:a7053135236cea87e9b441946b8e716b9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a7053135236cea87e9b441946b8e716b9">OSC_CAP0P</a>   0U</td></tr> 73<tr class="separator:a7053135236cea87e9b441946b8e716b9"><td class="memSeparator" colspan="2"> </td></tr> 74<tr class="memitem:a24aceb6d1cd39e00a352cdbf31b55e28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a24aceb6d1cd39e00a352cdbf31b55e28">OSC_ER_CLK_DISABLE</a>   0U</td></tr> 75<tr class="separator:a24aceb6d1cd39e00a352cdbf31b55e28"><td class="memSeparator" colspan="2"> </td></tr> 76<tr class="memitem:a7b20ee9fbe65f61be2fb21e18f088bf7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a7b20ee9fbe65f61be2fb21e18f088bf7">SIM_OSC32KSEL_RTC32KCLK_CLK</a>   2U</td></tr> 77<tr class="separator:a7b20ee9fbe65f61be2fb21e18f088bf7"><td class="memSeparator" colspan="2"> </td></tr> 78<tr class="memitem:a3679830dce5c840eb5f96a7644fb6c83"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a3679830dce5c840eb5f96a7644fb6c83">SIM_PLLFLLSEL_IRC48MCLK_CLK</a>   3U</td></tr> 79<tr class="separator:a3679830dce5c840eb5f96a7644fb6c83"><td class="memSeparator" colspan="2"> </td></tr> 80<tr class="memitem:a07e083fe42018c972411cf57fe13278f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a07e083fe42018c972411cf57fe13278f">SIM_PLLFLLSEL_MCGPLLCLK_CLK</a>   1U</td></tr> 81<tr class="separator:a07e083fe42018c972411cf57fe13278f"><td class="memSeparator" colspan="2"> </td></tr> 82</table><table class="memberdecls"> 83<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> 84Functions</h2></td></tr> 85<tr class="memitem:a5e69c4eff0fd5236bbb0ff4e1d5a7a7e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a5e69c4eff0fd5236bbb0ff4e1d5a7a7e">BOARD_BootClockRUN</a> (void)</td></tr> 86<tr class="memdesc:a5e69c4eff0fd5236bbb0ff4e1d5a7a7e"><td class="mdescLeft"> </td><td class="mdescRight">This function executes configuration of clocks. <a href="#a5e69c4eff0fd5236bbb0ff4e1d5a7a7e">More...</a><br /></td></tr> 87<tr class="separator:a5e69c4eff0fd5236bbb0ff4e1d5a7a7e"><td class="memSeparator" colspan="2"> </td></tr> 88<tr class="memitem:aeda06d8bee4b00642713d50a62d8edc9"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#aeda06d8bee4b00642713d50a62d8edc9">BOARD_BootClockVLPR</a> (void)</td></tr> 89<tr class="memdesc:aeda06d8bee4b00642713d50a62d8edc9"><td class="mdescLeft"> </td><td class="mdescRight">This function executes configuration of clocks. <a href="#aeda06d8bee4b00642713d50a62d8edc9">More...</a><br /></td></tr> 90<tr class="separator:aeda06d8bee4b00642713d50a62d8edc9"><td class="memSeparator" colspan="2"> </td></tr> 91</table><table class="memberdecls"> 92<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a> 93Variables</h2></td></tr> 94<tr class="memitem:aa3cd3e43291e81e795d642b79b6088e6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#aa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></td></tr> 95<tr class="separator:aa3cd3e43291e81e795d642b79b6088e6"><td class="memSeparator" colspan="2"> </td></tr> 96<tr class="memitem:a33df7e51829cab27a33a81ab9ecc919f"><td class="memItemLeft" align="right" valign="top">const mcg_config_t </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a33df7e51829cab27a33a81ab9ecc919f">mcgConfig_BOARD_BootClockRUN</a></td></tr> 97<tr class="memdesc:a33df7e51829cab27a33a81ab9ecc919f"><td class="mdescLeft"> </td><td class="mdescRight">MCG set for BOARD_BootClockRUN configuration. <a href="#a33df7e51829cab27a33a81ab9ecc919f">More...</a><br /></td></tr> 98<tr class="separator:a33df7e51829cab27a33a81ab9ecc919f"><td class="memSeparator" colspan="2"> </td></tr> 99<tr class="memitem:a0ce73e827dc487aaac07190a651d9dff"><td class="memItemLeft" align="right" valign="top">const sim_clock_config_t </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a0ce73e827dc487aaac07190a651d9dff">simConfig_BOARD_BootClockRUN</a></td></tr> 100<tr class="memdesc:a0ce73e827dc487aaac07190a651d9dff"><td class="mdescLeft"> </td><td class="mdescRight">SIM module set for BOARD_BootClockRUN configuration. <a href="#a0ce73e827dc487aaac07190a651d9dff">More...</a><br /></td></tr> 101<tr class="separator:a0ce73e827dc487aaac07190a651d9dff"><td class="memSeparator" colspan="2"> </td></tr> 102<tr class="memitem:a8a30f1ebc78e392bb8b05a8fdd7cca15"><td class="memItemLeft" align="right" valign="top">const osc_config_t </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a8a30f1ebc78e392bb8b05a8fdd7cca15">oscConfig_BOARD_BootClockRUN</a></td></tr> 103<tr class="memdesc:a8a30f1ebc78e392bb8b05a8fdd7cca15"><td class="mdescLeft"> </td><td class="mdescRight">OSC set for BOARD_BootClockRUN configuration. <a href="#a8a30f1ebc78e392bb8b05a8fdd7cca15">More...</a><br /></td></tr> 104<tr class="separator:a8a30f1ebc78e392bb8b05a8fdd7cca15"><td class="memSeparator" colspan="2"> </td></tr> 105<tr class="memitem:a57716321a9b9197a8625862f64778b11"><td class="memItemLeft" align="right" valign="top">const mcg_config_t </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a57716321a9b9197a8625862f64778b11">mcgConfig_BOARD_BootClockVLPR</a></td></tr> 106<tr class="memdesc:a57716321a9b9197a8625862f64778b11"><td class="mdescLeft"> </td><td class="mdescRight">MCG set for BOARD_BootClockVLPR configuration. <a href="#a57716321a9b9197a8625862f64778b11">More...</a><br /></td></tr> 107<tr class="separator:a57716321a9b9197a8625862f64778b11"><td class="memSeparator" colspan="2"> </td></tr> 108<tr class="memitem:af1ec80b657d4d5d4e60ab69d71808807"><td class="memItemLeft" align="right" valign="top">const sim_clock_config_t </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#af1ec80b657d4d5d4e60ab69d71808807">simConfig_BOARD_BootClockVLPR</a></td></tr> 109<tr class="memdesc:af1ec80b657d4d5d4e60ab69d71808807"><td class="mdescLeft"> </td><td class="mdescRight">SIM module set for BOARD_BootClockVLPR configuration. <a href="#af1ec80b657d4d5d4e60ab69d71808807">More...</a><br /></td></tr> 110<tr class="separator:af1ec80b657d4d5d4e60ab69d71808807"><td class="memSeparator" colspan="2"> </td></tr> 111<tr class="memitem:a725699f951cc1d3f2007cc96cab2d142"><td class="memItemLeft" align="right" valign="top">const osc_config_t </td><td class="memItemRight" valign="bottom"><a class="el" href="a04223.html#a725699f951cc1d3f2007cc96cab2d142">oscConfig_BOARD_BootClockVLPR</a></td></tr> 112<tr class="memdesc:a725699f951cc1d3f2007cc96cab2d142"><td class="mdescLeft"> </td><td class="mdescRight">OSC set for BOARD_BootClockVLPR configuration. <a href="#a725699f951cc1d3f2007cc96cab2d142">More...</a><br /></td></tr> 113<tr class="separator:a725699f951cc1d3f2007cc96cab2d142"><td class="memSeparator" colspan="2"> </td></tr> 114</table> 115<h2 class="groupheader">Macro Definition Documentation</h2> 116<a id="ab7ada7a74d398bf218d4d25934fce66c"></a> 117<h2 class="memtitle"><span class="permalink"><a href="#ab7ada7a74d398bf218d4d25934fce66c">◆ </a></span>MCG_PLL_DISABLE</h2> 118 119<div class="memitem"> 120<div class="memproto"> 121 <table class="memname"> 122 <tr> 123 <td class="memname">#define MCG_PLL_DISABLE   0U</td> 124 </tr> 125 </table> 126</div><div class="memdoc"> 127<p>MCGPLLCLK disabled </p> 128 129<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00053">53</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 130 131</div> 132</div> 133<a id="a7053135236cea87e9b441946b8e716b9"></a> 134<h2 class="memtitle"><span class="permalink"><a href="#a7053135236cea87e9b441946b8e716b9">◆ </a></span>OSC_CAP0P</h2> 135 136<div class="memitem"> 137<div class="memproto"> 138 <table class="memname"> 139 <tr> 140 <td class="memname">#define OSC_CAP0P   0U</td> 141 </tr> 142 </table> 143</div><div class="memdoc"> 144<p>Oscillator 0pF capacitor load </p> 145 146<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00054">54</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 147 148</div> 149</div> 150<a id="a24aceb6d1cd39e00a352cdbf31b55e28"></a> 151<h2 class="memtitle"><span class="permalink"><a href="#a24aceb6d1cd39e00a352cdbf31b55e28">◆ </a></span>OSC_ER_CLK_DISABLE</h2> 152 153<div class="memitem"> 154<div class="memproto"> 155 <table class="memname"> 156 <tr> 157 <td class="memname">#define OSC_ER_CLK_DISABLE   0U</td> 158 </tr> 159 </table> 160</div><div class="memdoc"> 161<p>Disable external reference clock </p> 162 163<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00055">55</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 164 165</div> 166</div> 167<a id="a7b20ee9fbe65f61be2fb21e18f088bf7"></a> 168<h2 class="memtitle"><span class="permalink"><a href="#a7b20ee9fbe65f61be2fb21e18f088bf7">◆ </a></span>SIM_OSC32KSEL_RTC32KCLK_CLK</h2> 169 170<div class="memitem"> 171<div class="memproto"> 172 <table class="memname"> 173 <tr> 174 <td class="memname">#define SIM_OSC32KSEL_RTC32KCLK_CLK   2U</td> 175 </tr> 176 </table> 177</div><div class="memdoc"> 178<p>OSC32KSEL select: RTC32KCLK clock (32.768kHz) </p> 179 180<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00056">56</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 181 182</div> 183</div> 184<a id="a3679830dce5c840eb5f96a7644fb6c83"></a> 185<h2 class="memtitle"><span class="permalink"><a href="#a3679830dce5c840eb5f96a7644fb6c83">◆ </a></span>SIM_PLLFLLSEL_IRC48MCLK_CLK</h2> 186 187<div class="memitem"> 188<div class="memproto"> 189 <table class="memname"> 190 <tr> 191 <td class="memname">#define SIM_PLLFLLSEL_IRC48MCLK_CLK   3U</td> 192 </tr> 193 </table> 194</div><div class="memdoc"> 195<p>PLLFLL select: IRC48MCLK clock </p> 196 197<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00057">57</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 198 199</div> 200</div> 201<a id="a07e083fe42018c972411cf57fe13278f"></a> 202<h2 class="memtitle"><span class="permalink"><a href="#a07e083fe42018c972411cf57fe13278f">◆ </a></span>SIM_PLLFLLSEL_MCGPLLCLK_CLK</h2> 203 204<div class="memitem"> 205<div class="memproto"> 206 <table class="memname"> 207 <tr> 208 <td class="memname">#define SIM_PLLFLLSEL_MCGPLLCLK_CLK   1U</td> 209 </tr> 210 </table> 211</div><div class="memdoc"> 212<p>PLLFLL select: MCGPLLCLK clock </p> 213 214<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00058">58</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 215 216</div> 217</div> 218<h2 class="groupheader">Function Documentation</h2> 219<a id="a5e69c4eff0fd5236bbb0ff4e1d5a7a7e"></a> 220<h2 class="memtitle"><span class="permalink"><a href="#a5e69c4eff0fd5236bbb0ff4e1d5a7a7e">◆ </a></span>BOARD_BootClockRUN()</h2> 221 222<div class="memitem"> 223<div class="memproto"> 224 <table class="memname"> 225 <tr> 226 <td class="memname">void BOARD_BootClockRUN </td> 227 <td>(</td> 228 <td class="paramtype">void </td> 229 <td class="paramname"></td><td>)</td> 230 <td></td> 231 </tr> 232 </table> 233</div><div class="memdoc"> 234 235<p>This function executes configuration of clocks. </p> 236 237<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00168">168</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 238 239<p class="reference">Referenced by <a class="el" href="a04244_source.html#l00099">BOARD_InitBootClocks()</a>.</p> 240<div class="dynheader"> 241Here is the caller graph for this function:</div> 242<div class="dyncontent"> 243<div class="center"><img src="a04223_a5e69c4eff0fd5236bbb0ff4e1d5a7a7e_icgraph.png" border="0" usemap="#a04223_a5e69c4eff0fd5236bbb0ff4e1d5a7a7e_icgraph" alt=""/></div> 244<map name="a04223_a5e69c4eff0fd5236bbb0ff4e1d5a7a7e_icgraph" id="a04223_a5e69c4eff0fd5236bbb0ff4e1d5a7a7e_icgraph"> 245<area shape="rect" id="node2" href="a04244.html#a09a9a2026d4c394534e528d519370d3e" title="This function executes default configuration of clocks. " alt="" coords="216,5,375,32"/> 246</map> 247</div> 248 249</div> 250</div> 251<a id="aeda06d8bee4b00642713d50a62d8edc9"></a> 252<h2 class="memtitle"><span class="permalink"><a href="#aeda06d8bee4b00642713d50a62d8edc9">◆ </a></span>BOARD_BootClockVLPR()</h2> 253 254<div class="memitem"> 255<div class="memproto"> 256 <table class="memname"> 257 <tr> 258 <td class="memname">void BOARD_BootClockVLPR </td> 259 <td>(</td> 260 <td class="paramtype">void </td> 261 <td class="paramname"></td><td>)</td> 262 <td></td> 263 </tr> 264 </table> 265</div><div class="memdoc"> 266 267<p>This function executes configuration of clocks. </p> 268 269<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00266">266</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 270 271</div> 272</div> 273<h2 class="groupheader">Variable Documentation</h2> 274<a id="a33df7e51829cab27a33a81ab9ecc919f"></a> 275<h2 class="memtitle"><span class="permalink"><a href="#a33df7e51829cab27a33a81ab9ecc919f">◆ </a></span>mcgConfig_BOARD_BootClockRUN</h2> 276 277<div class="memitem"> 278<div class="memproto"> 279 <table class="memname"> 280 <tr> 281 <td class="memname">const mcg_config_t mcgConfig_BOARD_BootClockRUN</td> 282 </tr> 283 </table> 284</div><div class="memdoc"> 285<b>Initial value:</b><div class="fragment"><div class="line">=</div><div class="line"> {</div><div class="line"> .mcgMode = kMCG_ModePEE, </div><div class="line"> .irclkEnableMode = kMCG_IrclkEnable, </div><div class="line"> .ircs = kMCG_IrcSlow, </div><div class="line"> .fcrdiv = 0x0U, </div><div class="line"> .frdiv = 0x0U, </div><div class="line"> .drs = kMCG_DrsLow, </div><div class="line"> .dmx32 = kMCG_Dmx32Default, </div><div class="line"> .oscsel = kMCG_OscselOsc, </div><div class="line"> .pll0Config =</div><div class="line"> {</div><div class="line"> .enableMode = <a class="code" href="a04223.html#ab7ada7a74d398bf218d4d25934fce66c">MCG_PLL_DISABLE</a>, </div><div class="line"> .prdiv = 0x13U, </div><div class="line"> .vdiv = 0x18U, </div><div class="line"> },</div><div class="line"> }</div><div class="ttc" id="a04223_html_ab7ada7a74d398bf218d4d25934fce66c"><div class="ttname"><a href="a04223.html#ab7ada7a74d398bf218d4d25934fce66c">MCG_PLL_DISABLE</a></div><div class="ttdeci">#define MCG_PLL_DISABLE</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00053">clock_config.c:53</a></div></div> 286</div><!-- fragment --> 287<p>MCG set for BOARD_BootClockRUN configuration. </p> 288 289<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00131">131</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 290 291<p class="reference">Referenced by <a class="el" href="a04223_source.html#l00168">BOARD_BootClockRUN()</a>.</p> 292 293</div> 294</div> 295<a id="a57716321a9b9197a8625862f64778b11"></a> 296<h2 class="memtitle"><span class="permalink"><a href="#a57716321a9b9197a8625862f64778b11">◆ </a></span>mcgConfig_BOARD_BootClockVLPR</h2> 297 298<div class="memitem"> 299<div class="memproto"> 300 <table class="memname"> 301 <tr> 302 <td class="memname">const mcg_config_t mcgConfig_BOARD_BootClockVLPR</td> 303 </tr> 304 </table> 305</div><div class="memdoc"> 306<b>Initial value:</b><div class="fragment"><div class="line">=</div><div class="line"> {</div><div class="line"> .mcgMode = kMCG_ModeBLPI, </div><div class="line"> .irclkEnableMode = kMCG_IrclkEnable, </div><div class="line"> .ircs = kMCG_IrcFast, </div><div class="line"> .fcrdiv = 0x0U, </div><div class="line"> .frdiv = 0x0U, </div><div class="line"> .drs = kMCG_DrsLow, </div><div class="line"> .dmx32 = kMCG_Dmx32Default, </div><div class="line"> .oscsel = kMCG_OscselOsc, </div><div class="line"> .pll0Config =</div><div class="line"> {</div><div class="line"> .enableMode = <a class="code" href="a04223.html#ab7ada7a74d398bf218d4d25934fce66c">MCG_PLL_DISABLE</a>, </div><div class="line"> .prdiv = 0x0U, </div><div class="line"> .vdiv = 0x0U, </div><div class="line"> },</div><div class="line"> }</div><div class="ttc" id="a04223_html_ab7ada7a74d398bf218d4d25934fce66c"><div class="ttname"><a href="a04223.html#ab7ada7a74d398bf218d4d25934fce66c">MCG_PLL_DISABLE</a></div><div class="ttdeci">#define MCG_PLL_DISABLE</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00053">clock_config.c:53</a></div></div> 307</div><!-- fragment --> 308<p>MCG set for BOARD_BootClockVLPR configuration. </p> 309 310<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00229">229</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 311 312<p class="reference">Referenced by <a class="el" href="a04223_source.html#l00266">BOARD_BootClockVLPR()</a>.</p> 313 314</div> 315</div> 316<a id="a8a30f1ebc78e392bb8b05a8fdd7cca15"></a> 317<h2 class="memtitle"><span class="permalink"><a href="#a8a30f1ebc78e392bb8b05a8fdd7cca15">◆ </a></span>oscConfig_BOARD_BootClockRUN</h2> 318 319<div class="memitem"> 320<div class="memproto"> 321 <table class="memname"> 322 <tr> 323 <td class="memname">const osc_config_t oscConfig_BOARD_BootClockRUN</td> 324 </tr> 325 </table> 326</div><div class="memdoc"> 327<b>Initial value:</b><div class="fragment"><div class="line">=</div><div class="line"> {</div><div class="line"> .freq = 50000000U, </div><div class="line"> .capLoad = (<a class="code" href="a04223.html#a7053135236cea87e9b441946b8e716b9">OSC_CAP0P</a>), </div><div class="line"> .workMode = kOSC_ModeExt, </div><div class="line"> .oscerConfig =</div><div class="line"> {</div><div class="line"> .enableMode = kOSC_ErClkEnable, </div><div class="line"> }</div><div class="line"> }</div><div class="ttc" id="a04223_html_a7053135236cea87e9b441946b8e716b9"><div class="ttname"><a href="a04223.html#a7053135236cea87e9b441946b8e716b9">OSC_CAP0P</a></div><div class="ttdeci">#define OSC_CAP0P</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00054">clock_config.c:54</a></div></div> 328</div><!-- fragment --> 329<p>OSC set for BOARD_BootClockRUN configuration. </p> 330 331<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00154">154</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 332 333<p class="reference">Referenced by <a class="el" href="a04223_source.html#l00168">BOARD_BootClockRUN()</a>.</p> 334 335</div> 336</div> 337<a id="a725699f951cc1d3f2007cc96cab2d142"></a> 338<h2 class="memtitle"><span class="permalink"><a href="#a725699f951cc1d3f2007cc96cab2d142">◆ </a></span>oscConfig_BOARD_BootClockVLPR</h2> 339 340<div class="memitem"> 341<div class="memproto"> 342 <table class="memname"> 343 <tr> 344 <td class="memname">const osc_config_t oscConfig_BOARD_BootClockVLPR</td> 345 </tr> 346 </table> 347</div><div class="memdoc"> 348<b>Initial value:</b><div class="fragment"><div class="line">=</div><div class="line"> {</div><div class="line"> .freq = 0U, </div><div class="line"> .capLoad = (<a class="code" href="a04223.html#a7053135236cea87e9b441946b8e716b9">OSC_CAP0P</a>), </div><div class="line"> .workMode = kOSC_ModeExt, </div><div class="line"> .oscerConfig =</div><div class="line"> {</div><div class="line"> .enableMode = <a class="code" href="a04223.html#a24aceb6d1cd39e00a352cdbf31b55e28">OSC_ER_CLK_DISABLE</a>, </div><div class="line"> }</div><div class="line"> }</div><div class="ttc" id="a04223_html_a7053135236cea87e9b441946b8e716b9"><div class="ttname"><a href="a04223.html#a7053135236cea87e9b441946b8e716b9">OSC_CAP0P</a></div><div class="ttdeci">#define OSC_CAP0P</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00054">clock_config.c:54</a></div></div> 349<div class="ttc" id="a04223_html_a24aceb6d1cd39e00a352cdbf31b55e28"><div class="ttname"><a href="a04223.html#a24aceb6d1cd39e00a352cdbf31b55e28">OSC_ER_CLK_DISABLE</a></div><div class="ttdeci">#define OSC_ER_CLK_DISABLE</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00055">clock_config.c:55</a></div></div> 350</div><!-- fragment --> 351<p>OSC set for BOARD_BootClockVLPR configuration. </p> 352 353<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00252">252</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 354 355</div> 356</div> 357<a id="a0ce73e827dc487aaac07190a651d9dff"></a> 358<h2 class="memtitle"><span class="permalink"><a href="#a0ce73e827dc487aaac07190a651d9dff">◆ </a></span>simConfig_BOARD_BootClockRUN</h2> 359 360<div class="memitem"> 361<div class="memproto"> 362 <table class="memname"> 363 <tr> 364 <td class="memname">const sim_clock_config_t simConfig_BOARD_BootClockRUN</td> 365 </tr> 366 </table> 367</div><div class="memdoc"> 368<b>Initial value:</b><div class="fragment"><div class="line">=</div><div class="line"> {</div><div class="line"> .pllFllSel = <a class="code" href="a04223.html#a07e083fe42018c972411cf57fe13278f">SIM_PLLFLLSEL_MCGPLLCLK_CLK</a>, </div><div class="line"> .er32kSrc = <a class="code" href="a04223.html#a7b20ee9fbe65f61be2fb21e18f088bf7">SIM_OSC32KSEL_RTC32KCLK_CLK</a>, </div><div class="line"> .clkdiv1 = 0x1240000U, </div><div class="line"> }</div><div class="ttc" id="a04223_html_a7b20ee9fbe65f61be2fb21e18f088bf7"><div class="ttname"><a href="a04223.html#a7b20ee9fbe65f61be2fb21e18f088bf7">SIM_OSC32KSEL_RTC32KCLK_CLK</a></div><div class="ttdeci">#define SIM_OSC32KSEL_RTC32KCLK_CLK</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00056">clock_config.c:56</a></div></div> 369<div class="ttc" id="a04223_html_a07e083fe42018c972411cf57fe13278f"><div class="ttname"><a href="a04223.html#a07e083fe42018c972411cf57fe13278f">SIM_PLLFLLSEL_MCGPLLCLK_CLK</a></div><div class="ttdeci">#define SIM_PLLFLLSEL_MCGPLLCLK_CLK</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00058">clock_config.c:58</a></div></div> 370</div><!-- fragment --> 371<p>SIM module set for BOARD_BootClockRUN configuration. </p> 372 373<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00148">148</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 374 375<p class="reference">Referenced by <a class="el" href="a04232_source.html#l00112">BOARD_BootClockRUN()</a>.</p> 376 377</div> 378</div> 379<a id="af1ec80b657d4d5d4e60ab69d71808807"></a> 380<h2 class="memtitle"><span class="permalink"><a href="#af1ec80b657d4d5d4e60ab69d71808807">◆ </a></span>simConfig_BOARD_BootClockVLPR</h2> 381 382<div class="memitem"> 383<div class="memproto"> 384 <table class="memname"> 385 <tr> 386 <td class="memname">const sim_clock_config_t simConfig_BOARD_BootClockVLPR</td> 387 </tr> 388 </table> 389</div><div class="memdoc"> 390<b>Initial value:</b><div class="fragment"><div class="line">=</div><div class="line"> {</div><div class="line"> .pllFllSel = <a class="code" href="a04223.html#a3679830dce5c840eb5f96a7644fb6c83">SIM_PLLFLLSEL_IRC48MCLK_CLK</a>, </div><div class="line"> .er32kSrc = <a class="code" href="a04223.html#a7b20ee9fbe65f61be2fb21e18f088bf7">SIM_OSC32KSEL_RTC32KCLK_CLK</a>, </div><div class="line"> .clkdiv1 = 0x40000U, </div><div class="line"> }</div><div class="ttc" id="a04223_html_a7b20ee9fbe65f61be2fb21e18f088bf7"><div class="ttname"><a href="a04223.html#a7b20ee9fbe65f61be2fb21e18f088bf7">SIM_OSC32KSEL_RTC32KCLK_CLK</a></div><div class="ttdeci">#define SIM_OSC32KSEL_RTC32KCLK_CLK</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00056">clock_config.c:56</a></div></div> 391<div class="ttc" id="a04223_html_a3679830dce5c840eb5f96a7644fb6c83"><div class="ttname"><a href="a04223.html#a3679830dce5c840eb5f96a7644fb6c83">SIM_PLLFLLSEL_IRC48MCLK_CLK</a></div><div class="ttdeci">#define SIM_PLLFLLSEL_IRC48MCLK_CLK</div><div class="ttdef"><b>Definition:</b> <a href="a04223_source.html#l00057">clock_config.c:57</a></div></div> 392</div><!-- fragment --> 393<p>SIM module set for BOARD_BootClockVLPR configuration. </p> 394 395<p class="definition">Definition at line <a class="el" href="a04223_source.html#l00246">246</a> of file <a class="el" href="a04223_source.html">clock_config.c</a>.</p> 396 397<p class="reference">Referenced by <a class="el" href="a04223_source.html#l00266">BOARD_BootClockVLPR()</a>.</p> 398 399</div> 400</div> 401<a id="aa3cd3e43291e81e795d642b79b6088e6"></a> 402<h2 class="memtitle"><span class="permalink"><a href="#aa3cd3e43291e81e795d642b79b6088e6">◆ </a></span>SystemCoreClock</h2> 403 404<div class="memitem"> 405<div class="memproto"> 406 <table class="memname"> 407 <tr> 408 <td class="memname">uint32_t SystemCoreClock</td> 409 </tr> 410 </table> 411</div><div class="memdoc"> 412 413<p class="reference">Referenced by <a class="el" href="a04823_source.html#l00881">ADS_FlashUpdate()</a>, <a class="el" href="a00671_source.html#l00320">BOARD_ACCEL_Reset()</a>, <a class="el" href="a04235_source.html#l00063">BOARD_BootClockFRO12M()</a>, <a class="el" href="a04235_source.html#l00101">BOARD_BootClockFROHF48M()</a>, <a class="el" href="a04235_source.html#l00142">BOARD_BootClockFROHF96M()</a>, <a class="el" href="a04238_source.html#l00174">BOARD_BootClockPLL100M()</a>, <a class="el" href="a04232_source.html#l00112">BOARD_BootClockRUN()</a>, <a class="el" href="a04223_source.html#l00266">BOARD_BootClockVLPR()</a>, and <a class="el" href="a00815_source.html#l00024">NVM_SetBlockFlash()</a>.</p> 414 415</div> 416</div> 417</div><!-- contents --> 418 419<hr class="footer"/><address class="footer"><small> 420© Copyright 2016-2022 NXP. All Rights Reserved. SPDX-License-Identifier: BSD-3-Clause 421</small></address> 422</body> 423</html> 424
