1 /*
2 * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS-Core(A) Compiler GCC Header File
21 */
22
23 #ifndef __CMSIS_GCC_A_H
24 #define __CMSIS_GCC_A_H
25
26 /* ignore some GCC warnings */
27 #pragma GCC diagnostic push
28 #pragma GCC diagnostic ignored "-Wsign-conversion"
29 #pragma GCC diagnostic ignored "-Wconversion"
30 #pragma GCC diagnostic ignored "-Wunused-parameter"
31
32 /* Fallback for __has_builtin */
33 #ifndef __has_builtin
34 #define __has_builtin(x) (0)
35 #endif
36
37 /* CMSIS compiler specific defines */
38 #ifndef __ASM
39 #define __ASM __asm
40 #endif
41 #ifndef __INLINE
42 #define __INLINE inline
43 #endif
44 #ifndef __FORCEINLINE
45 #define __FORCEINLINE __attribute__((always_inline))
46 #endif
47 #ifndef __STATIC_INLINE
48 #define __STATIC_INLINE static inline
49 #endif
50 #ifndef __STATIC_FORCEINLINE
51 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
52 #endif
53 #ifndef __NO_RETURN
54 #define __NO_RETURN __attribute__((__noreturn__))
55 #endif
56 #ifndef CMSIS_DEPRECATED
57 #define CMSIS_DEPRECATED __attribute__((deprecated))
58 #endif
59 #ifndef __USED
60 #define __USED __attribute__((used))
61 #endif
62 #ifndef __WEAK
63 #define __WEAK __attribute__((weak))
64 #endif
65 #ifndef __PACKED
66 #define __PACKED __attribute__((packed, aligned(1)))
67 #endif
68 #ifndef __PACKED_STRUCT
69 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
70 #endif
71 #ifndef __UNALIGNED_UINT16_WRITE
72 #pragma GCC diagnostic push
73 #pragma GCC diagnostic ignored "-Wpacked"
74 #pragma GCC diagnostic ignored "-Wattributes"
75 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
76 #pragma GCC diagnostic pop
77 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
78 #endif
79 #ifndef __UNALIGNED_UINT16_READ
80 #pragma GCC diagnostic push
81 #pragma GCC diagnostic ignored "-Wpacked"
82 #pragma GCC diagnostic ignored "-Wattributes"
83 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
84 #pragma GCC diagnostic pop
85 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
86 #endif
87 #ifndef __UNALIGNED_UINT32_WRITE
88 #pragma GCC diagnostic push
89 #pragma GCC diagnostic ignored "-Wpacked"
90 #pragma GCC diagnostic ignored "-Wattributes"
91 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
92 #pragma GCC diagnostic pop
93 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
94 #endif
95 #ifndef __UNALIGNED_UINT32_READ
96 #pragma GCC diagnostic push
97 #pragma GCC diagnostic ignored "-Wpacked"
98 #pragma GCC diagnostic ignored "-Wattributes"
99 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
100 #pragma GCC diagnostic pop
101 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
102 #endif
103 #ifndef __ALIGNED
104 #define __ALIGNED(x) __attribute__((aligned(x)))
105 #endif
106 #ifndef __RESTRICT
107 #define __RESTRICT __restrict
108 #endif
109 #ifndef __COMPILER_BARRIER
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
111 #endif
112
113
114 /* ########################## Core Instruction Access ######################### */
115 /**
116 \brief No Operation
117 \details No Operation does nothing. This instruction can be used for code alignment purposes.
118 */
119 #define __NOP() __ASM volatile ("nop")
120
121
122 /**
123 \brief Wait For Interrupt
124 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
125 */
126 #define __WFI() __ASM volatile ("wfi":::"memory")
127
128
129 /**
130 \brief Wait For Event
131 \details Wait For Event is a hint instruction that permits the processor to enter
132 a low-power state until one of a number of events occurs.
133 */
134 #define __WFE() __ASM volatile ("wfe":::"memory")
135
136
137 /**
138 \brief Send Event
139 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
140 */
141 #define __SEV() __ASM volatile ("sev")
142
143
144 /**
145 \brief Instruction Synchronization Barrier
146 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
147 so that all instructions following the ISB are fetched from cache or memory,
148 after the instruction has been completed.
149 */
__ISB(void)150 __STATIC_FORCEINLINE void __ISB(void)
151 {
152 __ASM volatile ("isb 0xF":::"memory");
153 }
154
155
156 /**
157 \brief Data Synchronization Barrier
158 \details Acts as a special kind of Data Memory Barrier.
159 It completes when all explicit memory accesses before this instruction complete.
160 */
__DSB(void)161 __STATIC_FORCEINLINE void __DSB(void)
162 {
163 __ASM volatile ("dsb 0xF":::"memory");
164 }
165
166
167 /**
168 \brief Data Memory Barrier
169 \details Ensures the apparent order of the explicit memory operations before
170 and after the instruction, without ensuring their completion.
171 */
__DMB(void)172 __STATIC_FORCEINLINE void __DMB(void)
173 {
174 __ASM volatile ("dmb 0xF":::"memory");
175 }
176
177
178 /**
179 \brief Reverse byte order (32 bit)
180 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
181 \param [in] value Value to reverse
182 \return Reversed value
183 */
__REV(uint32_t value)184 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
185 {
186 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
187 return __builtin_bswap32(value);
188 #else
189 uint32_t result;
190
191 __ASM ("rev %0, %1" : "=r" (result) : "r" (value) );
192 return result;
193 #endif
194 }
195
196
197 /**
198 \brief Reverse byte order (16 bit)
199 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
200 \param [in] value Value to reverse
201 \return Reversed value
202 */
__REV16(uint32_t value)203 __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
204 {
205 uint32_t result;
206 __ASM ("rev16 %0, %1" : "=r" (result) : "r" (value));
207 return result;
208 }
209
210
211 /**
212 \brief Reverse byte order (16 bit)
213 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
214 \param [in] value Value to reverse
215 \return Reversed value
216 */
__REVSH(int16_t value)217 __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
218 {
219 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
220 return (int16_t)__builtin_bswap16(value);
221 #else
222 int16_t result;
223
224 __ASM ("revsh %0, %1" : "=r" (result) : "r" (value) );
225 return result;
226 #endif
227 }
228
229
230 /**
231 \brief Rotate Right in unsigned value (32 bit)
232 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
233 \param [in] op1 Value to rotate
234 \param [in] op2 Number of Bits to rotate
235 \return Rotated value
236 */
__ROR(uint32_t op1,uint32_t op2)237 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
238 {
239 op2 %= 32U;
240 if (op2 == 0U)
241 {
242 return op1;
243 }
244 return (op1 >> op2) | (op1 << (32U - op2));
245 }
246
247
248 /**
249 \brief Breakpoint
250 \details Causes the processor to enter Debug state.
251 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
252 \param [in] value is ignored by the processor.
253 If required, a debugger can use it to store additional information about the breakpoint.
254 */
255 #define __BKPT(value) __ASM volatile ("bkpt "#value)
256
257
258 /**
259 \brief Reverse bit order of value
260 \details Reverses the bit order of the given value.
261 \param [in] value Value to reverse
262 \return Reversed value
263 */
__RBIT(uint32_t value)264 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
265 {
266 uint32_t result;
267 __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
268 return result;
269 }
270
271
272 /**
273 \brief Count leading zeros
274 \details Counts the number of leading zeros of a data value.
275 \param [in] value Value to count the leading zeros
276 \return number of leading zeros in value
277 */
__CLZ(uint32_t value)278 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
279 {
280 /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
281 __builtin_clz(0) is undefined behaviour, so handle this case specially.
282 This guarantees ARM-compatible results if happening to compile on a non-ARM
283 target, and ensures the compiler doesn't decide to activate any
284 optimisations using the logic "value was passed to __builtin_clz, so it
285 is non-zero".
286 ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
287 single CLZ instruction.
288 */
289 if (value == 0U)
290 {
291 return 32U;
292 }
293 return __builtin_clz(value);
294 }
295
296
297 /**
298 \brief LDR Exclusive (8 bit)
299 \details Executes a exclusive LDR instruction for 8 bit value.
300 \param [in] ptr Pointer to data
301 \return value of type uint8_t at (*ptr)
302 */
__LDREXB(volatile uint8_t * addr)303 __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
304 {
305 uint32_t result;
306
307 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
308 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
309 #else
310 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
311 accepted by assembler. So has to use following less efficient pattern.
312 */
313 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
314 #endif
315 return ((uint8_t) result); /* Add explicit type cast here */
316 }
317
318
319 /**
320 \brief LDR Exclusive (16 bit)
321 \details Executes a exclusive LDR instruction for 16 bit values.
322 \param [in] ptr Pointer to data
323 \return value of type uint16_t at (*ptr)
324 */
__LDREXH(volatile uint16_t * addr)325 __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
326 {
327 uint32_t result;
328
329 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
330 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
331 #else
332 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
333 accepted by assembler. So has to use following less efficient pattern.
334 */
335 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
336 #endif
337 return ((uint16_t) result); /* Add explicit type cast here */
338 }
339
340
341 /**
342 \brief LDR Exclusive (32 bit)
343 \details Executes a exclusive LDR instruction for 32 bit values.
344 \param [in] ptr Pointer to data
345 \return value of type uint32_t at (*ptr)
346 */
__LDREXW(volatile uint32_t * addr)347 __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
348 {
349 uint32_t result;
350
351 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
352 return(result);
353 }
354
355
356 /**
357 \brief STR Exclusive (8 bit)
358 \details Executes a exclusive STR instruction for 8 bit values.
359 \param [in] value Value to store
360 \param [in] ptr Pointer to location
361 \return 0 Function succeeded
362 \return 1 Function failed
363 */
__STREXB(uint8_t value,volatile uint8_t * addr)364 __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
365 {
366 uint32_t result;
367
368 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
369 return(result);
370 }
371
372
373 /**
374 \brief STR Exclusive (16 bit)
375 \details Executes a exclusive STR instruction for 16 bit values.
376 \param [in] value Value to store
377 \param [in] ptr Pointer to location
378 \return 0 Function succeeded
379 \return 1 Function failed
380 */
__STREXH(uint16_t value,volatile uint16_t * addr)381 __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
382 {
383 uint32_t result;
384
385 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
386 return(result);
387 }
388
389
390 /**
391 \brief STR Exclusive (32 bit)
392 \details Executes a exclusive STR instruction for 32 bit values.
393 \param [in] value Value to store
394 \param [in] ptr Pointer to location
395 \return 0 Function succeeded
396 \return 1 Function failed
397 */
__STREXW(uint32_t value,volatile uint32_t * addr)398 __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
399 {
400 uint32_t result;
401
402 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
403 return(result);
404 }
405
406
407 /**
408 \brief Remove the exclusive lock
409 \details Removes the exclusive lock which is created by LDREX.
410 */
__CLREX(void)411 __STATIC_FORCEINLINE void __CLREX(void)
412 {
413 __ASM volatile ("clrex" ::: "memory");
414 }
415
416 /**
417 \brief Signed Saturate
418 \details Saturates a signed value.
419 \param [in] ARG1 Value to be saturated
420 \param [in] ARG2 Bit position to saturate to (1..32)
421 \return Saturated value
422 */
423 #define __SSAT(ARG1, ARG2) \
424 __extension__ \
425 ({ \
426 int32_t __RES, __ARG1 = (ARG1); \
427 __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
428 __RES; \
429 })
430
431
432 /**
433 \brief Unsigned Saturate
434 \details Saturates an unsigned value.
435 \param [in] ARG1 Value to be saturated
436 \param [in] ARG2 Bit position to saturate to (0..31)
437 \return Saturated value
438 */
439 #define __USAT(ARG1, ARG2) \
440 __extension__ \
441 ({ \
442 uint32_t __RES, __ARG1 = (ARG1); \
443 __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
444 __RES; \
445 })
446
447 /**
448 \brief Rotate Right with Extend (32 bit)
449 \details Moves each bit of a bitstring right by one bit.
450 The carry input is shifted in at the left end of the bitstring.
451 \param [in] value Value to rotate
452 \return Rotated value
453 */
__RRX(uint32_t value)454 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
455 {
456 uint32_t result;
457
458 __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
459 return (result);
460 }
461
462
463 /**
464 \brief LDRT Unprivileged (8 bit)
465 \details Executes a Unprivileged LDRT instruction for 8 bit value.
466 \param [in] ptr Pointer to data
467 \return value of type uint8_t at (*ptr)
468 */
__LDRBT(volatile uint8_t * ptr)469 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
470 {
471 uint32_t result;
472
473 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
474 return ((uint8_t)result); /* Add explicit type cast here */
475 }
476
477
478 /**
479 \brief LDRT Unprivileged (16 bit)
480 \details Executes a Unprivileged LDRT instruction for 16 bit values.
481 \param [in] ptr Pointer to data
482 \return value of type uint16_t at (*ptr)
483 */
__LDRHT(volatile uint16_t * ptr)484 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
485 {
486 uint32_t result;
487
488 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
489 return ((uint16_t)result); /* Add explicit type cast here */
490 }
491
492
493 /**
494 \brief LDRT Unprivileged (32 bit)
495 \details Executes a Unprivileged LDRT instruction for 32 bit values.
496 \param [in] ptr Pointer to data
497 \return value of type uint32_t at (*ptr)
498 */
__LDRT(volatile uint32_t * ptr)499 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
500 {
501 uint32_t result;
502
503 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
504 return (result);
505 }
506
507
508 /**
509 \brief STRT Unprivileged (8 bit)
510 \details Executes a Unprivileged STRT instruction for 8 bit values.
511 \param [in] value Value to store
512 \param [in] ptr Pointer to location
513 */
__STRBT(uint8_t value,volatile uint8_t * ptr)514 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
515 {
516 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
517 }
518
519
520 /**
521 \brief STRT Unprivileged (16 bit)
522 \details Executes a Unprivileged STRT instruction for 16 bit values.
523 \param [in] value Value to store
524 \param [in] ptr Pointer to location
525 */
__STRHT(uint16_t value,volatile uint16_t * ptr)526 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
527 {
528 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
529 }
530
531
532 /**
533 \brief STRT Unprivileged (32 bit)
534 \details Executes a Unprivileged STRT instruction for 32 bit values.
535 \param [in] value Value to store
536 \param [in] ptr Pointer to location
537 */
__STRT(uint32_t value,volatile uint32_t * ptr)538 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
539 {
540 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
541 }
542
543 /* ########################### Core Function Access ########################### */
544 /** \ingroup CMSIS_Core_FunctionInterface
545 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
546 @{
547 */
548
549 /**
550 \brief Enable IRQ Interrupts
551 \details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
552 Can only be executed in Privileged modes.
553 */
__enable_irq(void)554 __STATIC_FORCEINLINE void __enable_irq(void)
555 {
556 __ASM volatile ("cpsie i" : : : "memory");
557 }
558
559
560 /**
561 \brief Disable IRQ Interrupts
562 \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
563 Can only be executed in Privileged modes.
564 */
__disable_irq(void)565 __STATIC_FORCEINLINE void __disable_irq(void)
566 {
567 __ASM volatile ("cpsid i" : : : "memory");
568 }
569
570 /**
571 \brief Enable FIQ
572 \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
573 Can only be executed in Privileged modes.
574 */
__enable_fault_irq(void)575 __STATIC_FORCEINLINE void __enable_fault_irq(void)
576 {
577 __ASM volatile ("cpsie f" : : : "memory");
578 }
579
580
581 /**
582 \brief Disable FIQ
583 \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
584 Can only be executed in Privileged modes.
585 */
__disable_fault_irq(void)586 __STATIC_FORCEINLINE void __disable_fault_irq(void)
587 {
588 __ASM volatile ("cpsid f" : : : "memory");
589 }
590
591 /**
592 \brief Get FPSCR
593 \details Returns the current value of the Floating Point Status/Control register.
594 \return Floating Point Status/Control register value
595 */
__get_FPSCR(void)596 __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
597 {
598 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
599 return __builtin_arm_get_fpscr();
600 #else
601 return(0U);
602 #endif
603 }
604
605
606 /**
607 \brief Set FPSCR
608 \details Assigns the given value to the Floating Point Status/Control register.
609 \param [in] fpscr Floating Point Status/Control value to set
610 */
__set_FPSCR(uint32_t fpscr)611 __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
612 {
613 #if (defined(__ARM_FP) && (__ARM_FP >= 1))
614 __builtin_arm_set_fpscr(fpscr);
615 #else
616 (void)fpscr;
617 #endif
618 }
619
620
621 /*@} end of CMSIS_Core_RegAccFunctions */
622
623
624 /* ################### Compiler specific Intrinsics ########################### */
625
626 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
627
628 #define __SADD8 __builtin_arm_sadd8
629 #define __QADD8 __builtin_arm_qadd8
630 #define __SHADD8 __builtin_arm_shadd8
631 #define __UADD8 __builtin_arm_uadd8
632 #define __UQADD8 __builtin_arm_uqadd8
633 #define __UHADD8 __builtin_arm_uhadd8
634 #define __SSUB8 __builtin_arm_ssub8
635 #define __QSUB8 __builtin_arm_qsub8
636 #define __SHSUB8 __builtin_arm_shsub8
637 #define __USUB8 __builtin_arm_usub8
638 #define __UQSUB8 __builtin_arm_uqsub8
639 #define __UHSUB8 __builtin_arm_uhsub8
640 #define __SADD16 __builtin_arm_sadd16
641 #define __QADD16 __builtin_arm_qadd16
642 #define __SHADD16 __builtin_arm_shadd16
643 #define __UADD16 __builtin_arm_uadd16
644 #define __UQADD16 __builtin_arm_uqadd16
645 #define __UHADD16 __builtin_arm_uhadd16
646 #define __SSUB16 __builtin_arm_ssub16
647 #define __QSUB16 __builtin_arm_qsub16
648 #define __SHSUB16 __builtin_arm_shsub16
649 #define __USUB16 __builtin_arm_usub16
650 #define __UQSUB16 __builtin_arm_uqsub16
651 #define __UHSUB16 __builtin_arm_uhsub16
652 #define __SASX __builtin_arm_sasx
653 #define __QASX __builtin_arm_qasx
654 #define __SHASX __builtin_arm_shasx
655 #define __UASX __builtin_arm_uasx
656 #define __UQASX __builtin_arm_uqasx
657 #define __UHASX __builtin_arm_uhasx
658 #define __SSAX __builtin_arm_ssax
659 #define __QSAX __builtin_arm_qsax
660 #define __SHSAX __builtin_arm_shsax
661 #define __USAX __builtin_arm_usax
662 #define __UQSAX __builtin_arm_uqsax
663 #define __UHSAX __builtin_arm_uhsax
664 #define __USAD8 __builtin_arm_usad8
665 #define __USADA8 __builtin_arm_usada8
666 #define __SSAT16 __builtin_arm_ssat16
667 #define __USAT16 __builtin_arm_usat16
668 #define __UXTB16 __builtin_arm_uxtb16
669 #define __UXTAB16 __builtin_arm_uxtab16
670 #define __SXTB16 __builtin_arm_sxtb16
671 #define __SXTAB16 __builtin_arm_sxtab16
672 #define __SMUAD __builtin_arm_smuad
673 #define __SMUADX __builtin_arm_smuadx
674 #define __SMLAD __builtin_arm_smlad
675 #define __SMLADX __builtin_arm_smladx
676 #define __SMLALD __builtin_arm_smlald
677 #define __SMLALDX __builtin_arm_smlaldx
678 #define __SMUSD __builtin_arm_smusd
679 #define __SMUSDX __builtin_arm_smusdx
680 #define __SMLSD __builtin_arm_smlsd
681 #define __SMLSDX __builtin_arm_smlsdx
682 #define __SMLSLD __builtin_arm_smlsld
683 #define __SMLSLDX __builtin_arm_smlsldx
684 #define __SEL __builtin_arm_sel
685 #define __QADD __builtin_arm_qadd
686 #define __QSUB __builtin_arm_qsub
687
688 #define __PKHBT(ARG1,ARG2,ARG3) \
689 __extension__ \
690 ({ \
691 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
692 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
693 __RES; \
694 })
695
696 #define __PKHTB(ARG1,ARG2,ARG3) \
697 __extension__ \
698 ({ \
699 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
700 if (ARG3 == 0) \
701 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
702 else \
703 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
704 __RES; \
705 })
706
__SXTB16_RORn(uint32_t op1,uint32_t rotate)707 __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
708 {
709 uint32_t result;
710 if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
711 {
712 __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
713 }
714 else
715 {
716 result = __SXTB16(__ROR(op1, rotate));
717 }
718 return result;
719 }
720
__SXTAB16_RORn(uint32_t op1,uint32_t op2,uint32_t rotate)721 __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
722 {
723 uint32_t result;
724 if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
725 {
726 __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
727 }
728 else
729 {
730 result = __SXTAB16(op1, __ROR(op2, rotate));
731 }
732 return result;
733 }
734
__SMMLA(int32_t op1,int32_t op2,int32_t op3)735 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
736 {
737 int32_t result;
738
739 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
740 return (result);
741 }
742
743 #endif /* (__ARM_FEATURE_DSP == 1) */
744 /** @} end of group CMSIS_SIMD_intrinsics */
745
746 /** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics
747 Access to dedicated SIMD instructions
748 @{
749 */
750
751 /** \brief Get CPSR Register
752 \return CPSR Register value
753 */
__get_CPSR(void)754 __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
755 {
756 uint32_t result;
757 __ASM volatile("MRS %0, cpsr" : "=r" (result) );
758 return(result);
759 }
760
761 /** \brief Set CPSR Register
762 \param [in] cpsr CPSR value to set
763 */
__set_CPSR(uint32_t cpsr)764 __STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
765 {
766 __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
767 }
768
769 /** \brief Get Mode
770 \return Processor Mode
771 */
__get_mode(void)772 __STATIC_FORCEINLINE uint32_t __get_mode(void)
773 {
774 return (__get_CPSR() & 0x1FU);
775 }
776
777 /** \brief Set Mode
778 \param [in] mode Mode value to set
779 */
__set_mode(uint32_t mode)780 __STATIC_FORCEINLINE void __set_mode(uint32_t mode)
781 {
782 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
783 }
784
785 /** \brief Get Stack Pointer
786 \return Stack Pointer value
787 */
__get_SP(void)788 __STATIC_FORCEINLINE uint32_t __get_SP(void)
789 {
790 uint32_t result;
791 __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
792 return result;
793 }
794
795 /** \brief Set Stack Pointer
796 \param [in] stack Stack Pointer value to set
797 */
__set_SP(uint32_t stack)798 __STATIC_FORCEINLINE void __set_SP(uint32_t stack)
799 {
800 __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
801 }
802
803 /** \brief Get USR/SYS Stack Pointer
804 \return USR/SYS Stack Pointer value
805 */
__get_SP_usr(void)806 __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
807 {
808 uint32_t cpsr = __get_CPSR();
809 uint32_t result;
810 __ASM volatile(
811 "CPS #0x1F \n"
812 "MOV %0, sp " : "=r"(result) : : "memory"
813 );
814 __set_CPSR(cpsr);
815 __ISB();
816 return result;
817 }
818
819 /** \brief Set USR/SYS Stack Pointer
820 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
821 */
__set_SP_usr(uint32_t topOfProcStack)822 __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
823 {
824 uint32_t cpsr = __get_CPSR();
825 __ASM volatile(
826 "CPS #0x1F \n"
827 "MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
828 );
829 __set_CPSR(cpsr);
830 __ISB();
831 }
832
833 /** \brief Get FPEXC
834 \return Floating Point Exception Control register value
835 */
__get_FPEXC(void)836 __STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
837 {
838 #if (__FPU_PRESENT == 1)
839 uint32_t result;
840 __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
841 return(result);
842 #else
843 return(0);
844 #endif
845 }
846
847 /** \brief Set FPEXC
848 \param [in] fpexc Floating Point Exception Control value to set
849 */
__set_FPEXC(uint32_t fpexc)850 __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
851 {
852 #if (__FPU_PRESENT == 1)
853 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
854 #endif
855 }
856
857 /*
858 * Include common core functions to access Coprocessor 15 registers
859 */
860
861 #define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
862 #define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
863 #define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
864 #define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
865
866 #include "cmsis_cp15.h"
867
868 /** \brief Enable Floating Point Unit
869
870 Critical section, called from undef handler, so systick is disabled
871 */
__FPU_Enable(void)872 __STATIC_INLINE void __FPU_Enable(void)
873 {
874 // Permit access to VFP/NEON, registers by modifying CPACR
875 const uint32_t cpacr = __get_CPACR();
876 __set_CPACR(cpacr | 0x00F00000ul);
877 __ISB();
878
879 // Enable VFP/NEON
880 const uint32_t fpexc = __get_FPEXC();
881 __set_FPEXC(fpexc | 0x40000000ul);
882
883 __ASM volatile(
884 // Initialise VFP/NEON registers to 0
885 " MOV R2,#0 \n"
886
887 // Initialise D16 registers to 0
888 " VMOV D0, R2,R2 \n"
889 " VMOV D1, R2,R2 \n"
890 " VMOV D2, R2,R2 \n"
891 " VMOV D3, R2,R2 \n"
892 " VMOV D4, R2,R2 \n"
893 " VMOV D5, R2,R2 \n"
894 " VMOV D6, R2,R2 \n"
895 " VMOV D7, R2,R2 \n"
896 " VMOV D8, R2,R2 \n"
897 " VMOV D9, R2,R2 \n"
898 " VMOV D10,R2,R2 \n"
899 " VMOV D11,R2,R2 \n"
900 " VMOV D12,R2,R2 \n"
901 " VMOV D13,R2,R2 \n"
902 " VMOV D14,R2,R2 \n"
903 " VMOV D15,R2,R2 \n"
904
905 #if (defined(__ARM_NEON) && (__ARM_NEON == 1))
906 // Initialise D32 registers to 0
907 " VMOV D16,R2,R2 \n"
908 " VMOV D17,R2,R2 \n"
909 " VMOV D18,R2,R2 \n"
910 " VMOV D19,R2,R2 \n"
911 " VMOV D20,R2,R2 \n"
912 " VMOV D21,R2,R2 \n"
913 " VMOV D22,R2,R2 \n"
914 " VMOV D23,R2,R2 \n"
915 " VMOV D24,R2,R2 \n"
916 " VMOV D25,R2,R2 \n"
917 " VMOV D26,R2,R2 \n"
918 " VMOV D27,R2,R2 \n"
919 " VMOV D28,R2,R2 \n"
920 " VMOV D29,R2,R2 \n"
921 " VMOV D30,R2,R2 \n"
922 " VMOV D31,R2,R2 \n"
923 #endif
924 : : : "cc", "r2"
925 );
926
927 // Initialise FPSCR to a known state
928 const uint32_t fpscr = __get_FPSCR();
929 __set_FPSCR(fpscr & 0x00086060ul);
930 }
931
932 /*@} end of group CMSIS_Core_intrinsics */
933
934 #pragma GCC diagnostic pop
935
936 #endif /* __CMSIS_GCC_A_H */
937
