1 /**************************************************************************//**
2 * @file system_Device.c
3 * @brief MMU Configuration
4 * Device <DeviceAbbreviation>
5 * @version V1.1.0
6 * @date 23. November 2018
7 ******************************************************************************/
8 /*
9 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 /* Memory map description
27
28 ToDo: add in this file your device memory map description
29 following is an example of a Cortex-A9 Arm FVP device
30
31 Memory Type
32 0xFFFFFFFF |--------------------------| ------------
33 | FLAG SYNC | Device Memory
34 0xFFFFF000 |--------------------------| ------------
35 | Fault | Fault
36 0xFFF00000 |--------------------------| ------------
37 | | Normal
38 | |
39 | Daughterboard |
40 | memory |
41 | |
42 0x80505000 |--------------------------| ------------
43 |TTB (L2 Sync Flags ) 4k | Normal
44 0x80504C00 |--------------------------| ------------
45 |TTB (L2 Peripherals-B) 16k| Normal
46 0x80504800 |--------------------------| ------------
47 |TTB (L2 Peripherals-A) 16k| Normal
48 0x80504400 |--------------------------| ------------
49 |TTB (L2 Priv Periphs) 4k | Normal
50 0x80504000 |--------------------------| ------------
51 | TTB (L1 Descriptors) | Normal
52 0x80500000 |--------------------------| ------------
53 | Heap | Normal
54 |--------------------------| ------------
55 | Stack | Normal
56 0x80400000 |--------------------------| ------------
57 | ZI Data | Normal
58 0x80300000 |--------------------------| ------------
59 | RW Data | Normal
60 0x80200000 |--------------------------| ------------
61 | RO Data | Normal
62 |--------------------------| ------------
63 | RO Code | USH Normal
64 0x80000000 |--------------------------| ------------
65 | Daughterboard | Fault
66 | HSB AXI buses |
67 0x40000000 |--------------------------| ------------
68 | Daughterboard | Fault
69 | test chips peripherals |
70 0x2C002000 |--------------------------| ------------
71 | Private Address | Device Memory
72 0x2C000000 |--------------------------| ------------
73 | Daughterboard | Fault
74 | test chips peripherals |
75 0x20000000 |--------------------------| ------------
76 | Peripherals | Device Memory RW/RO
77 | | & Fault
78 0x00000000 |--------------------------|
79 */
80
81 // L1 Cache info and restrictions about architecture of the caches (CCSIR register):
82 // Write-Through support *not* available
83 // Write-Back support available.
84 // Read allocation support available.
85 // Write allocation support available.
86
87 // Note: You should use the Shareable attribute carefully.
88 // For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
89 // Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
90 // Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
91
92 // Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
93 // When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
94 // When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
95
96 // Following MMU configuration is expected
97 // SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
98 // SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
99 // Domain 0 is always the Client domain
100 // Descriptors should place all memory in domain 0
101
102 #include "<Device>.h" /* ToDo: replace '<Device>' with your device name */
103
104 // L2 table pointers
105 //-----------------------------------------------------
106 #define PRIVATE_TABLE_L2_BASE_4k (0x80504000) //Map 4k Private Address space
107 #define SYNC_FLAGS_TABLE_L2_BASE_4k (0x80504C00) //Map 4k Flag synchronization
108 #define PERIPHERAL_A_TABLE_L2_BASE_64k (0x80504400) //Map 64k Peripheral #1
109 #define PERIPHERAL_B_TABLE_L2_BASE_64k (0x80504800) //Map 64k Peripheral #2
110
111 //--------------------- PERIPHERALS -------------------
112 #define PERIPHERAL_A_FAULT (0x00000000 + 0x1C000000)
113 #define PERIPHERAL_B_FAULT (0x00100000 + 0x1C000000)
114
115 //--------------------- SYNC FLAGS --------------------
116 #define FLAG_SYNC 0xFFFFF000
117 #define F_SYNC_BASE 0xFFF00000 //1M aligned
118
119 //Import symbols from linker
120 extern uint32_t Image$$VECTORS$$Base;
121 extern uint32_t Image$$RW_DATA$$Base;
122 extern uint32_t Image$$ZI_DATA$$Base;
123 extern uint32_t Image$$TTB$$ZI$$Base;
124
125 static uint32_t Sect_Normal; // outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
126 static uint32_t Sect_Normal_Cod; // outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
127 static uint32_t Sect_Normal_RO; // as Sect_Normal_Cod, but not executable
128 static uint32_t Sect_Normal_RW; // as Sect_Normal_Cod, but writeable and not executable
129 static uint32_t Sect_Device_RO; // device, non-shareable, non-executable, ro, domain 0, base addr 0
130 static uint32_t Sect_Device_RW; // as Sect_Device_RO, but writeable
131
132 /* Define global descriptors */
133 static uint32_t Page_L1_4k = 0x0; // generic
134 static uint32_t Page_L1_64k = 0x0; // generic
135 static uint32_t Page_4k_Device_RW; // shared device, not executable, rw, domain 0
136 static uint32_t Page_64k_Device_RW; // shared device, not executable, rw, domain 0
137
MMU_CreateTranslationTable(void)138 void MMU_CreateTranslationTable(void)
139 {
140 mmu_region_attributes_Type region;
141
142 // Create 4GB of faulting entries
143 MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
144
145 /*
146 * Generate descriptors. Refer to core_ca.h to get information about attributes
147 *
148 */
149 // Create descriptors for Vectors, RO, RW, ZI sections
150 section_normal(Sect_Normal, region);
151 section_normal_cod(Sect_Normal_Cod, region);
152 section_normal_ro(Sect_Normal_RO, region);
153 section_normal_rw(Sect_Normal_RW, region);
154 // Create descriptors for peripherals
155 section_Device_ro(Sect_Device_RO, region);
156 section_Device_rw(Sect_Device_RW, region);
157 // Create descriptors for 64k pages
158 page64k_Device_rw(Page_L1_64k, Page_64k_Device_RW, region);
159 // Create descriptors for 4k pages
160 page4k_Device_rw(Page_L1_4k, Page_4k_Device_RW, region);
161
162 /*
163 * Define MMU flat-map regions and attributes
164 *
165 */
166 // Define Image
167 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , 1U, Sect_Normal_Cod);
168 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , 1U, Sect_Normal_RW);
169 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base , 1U, Sect_Normal_RW);
170
171 // All DRAM executable, RW, cacheable - applications may choose to divide memory into RO executable
172 MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$TTB$$ZI$$Base , 2043U, Sect_Normal);
173
174 //--------------------- PERIPHERALS -------------------
175 MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE0 , 64U, Sect_Device_RO);
176 MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_FLASH_BASE1 , 64U, Sect_Device_RO);
177 MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SRAM_BASE , 64U, Sect_Device_RW);
178 MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_VRAM_BASE , 32U, Sect_Device_RW);
179 MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_ETHERNET_BASE , 16U, Sect_Device_RW);
180 MMU_TTSection (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_USB_BASE , 16U, Sect_Device_RW);
181
182 // Create (16 * 64k)=1MB faulting entries to cover peripheral range
183 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_A_FAULT , 16U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
184 // Define peripheral range
185 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DAP_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
186 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SYSTEM_REG_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
187 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_SERIAL_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
188 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_AACI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
189 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_MMCI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
190 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_KMI0_BASE , 2U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
191 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART_BASE , 4U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
192 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_WDT_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
193
194 // Create (16 * 64k)=1MB faulting entries to cover peripheral range
195 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, PERIPHERAL_B_FAULT , 16U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
196 // Define peripheral range
197 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_TIMER_BASE , 2U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
198 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_DVI_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
199 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_RTC_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
200 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_UART4_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
201 MMU_TTPage64k(&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_CLCD_BASE , 1U, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
202
203 // Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
204 MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 256U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
205 // Define private address space entry
206 MMU_TTPage4k (&Image$$TTB$$ZI$$Base, __get_CBAR() , 2U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
207 // Define L2CC entry
208 MMU_TTPage4k (&Image$$TTB$$ZI$$Base, <DeviceAbbreviation>_L2C_BASE , 1U, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
209
210 // Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
211 MMU_TTPage4k (&Image$$TTB$$ZI$$Base, F_SYNC_BASE , 256U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
212 // Define synchronization space entry.
213 MMU_TTPage4k (&Image$$TTB$$ZI$$Base, FLAG_SYNC , 1U, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
214
215 /* Set location of level 1 page table
216 ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
217 ; 13:7 - 0x0
218 ; 6 - IRGN[0] 0x1 (Inner WB WA)
219 ; 5 - NOS 0x0 (Non-shared)
220 ; 4:3 - RGN 0x01 (Outer WB WA)
221 ; 2 - IMP 0x0 (Implementation Defined)
222 ; 1 - S 0x0 (Non-shared)
223 ; 0 - IRGN[1] 0x0 (Inner WB WA) */
224 __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48);
225 __ISB();
226
227 /* Set up domain access control register
228 ; We set domain 0 to Client and all other domains to No Access.
229 ; All translation table entries specify domain 0 */
230 __set_DACR(1);
231 __ISB();
232 }
233
