1 /*
2 * SPDX-FileCopyrightText: Copyright 2010-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_avgpool_s8.c
22 * Description: Pooling function implementations
23 *
24 * $Date: 30 January 2023
25 * $Revision: V.3.2.0
26 *
27 * Target : Arm(R) M-Profile Architecture
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 #if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI)
scale_q31_to_q7_and_clamp(const int32_t * buffer,int8_t * target,int32_t length,const int32_t count,const int act_min,const int act_max)35 static void scale_q31_to_q7_and_clamp(const int32_t *buffer,
36 int8_t *target,
37 int32_t length,
38 const int32_t count,
39 const int act_min,
40 const int act_max)
41 {
42 const int half_count = count / 2;
43
44 for (int i = 0; i < length; i++)
45 {
46 int32_t sum = buffer[i] > 0 ? (buffer[i] + half_count) : (buffer[i] - half_count);
47 sum = sum / count;
48 sum = MAX(sum, act_min);
49 sum = MIN(sum, act_max);
50
51 target[i] = (int8_t)sum;
52 }
53 }
54 #endif
55
56 /**
57 * @ingroup Public
58 */
59
60 /**
61 * @addtogroup Pooling
62 * @{
63 */
64
65 /*
66 * s8 average pooling function
67 *
68 * Refer to header file for details.
69 *
70 */
71
72 #if defined(ARM_MATH_MVEI)
73
arm_avgpool_s8(const cmsis_nn_context * ctx,const cmsis_nn_pool_params * pool_params,const cmsis_nn_dims * input_dims,const int8_t * src,const cmsis_nn_dims * filter_dims,const cmsis_nn_dims * output_dims,int8_t * dst)74 arm_cmsis_nn_status arm_avgpool_s8(const cmsis_nn_context *ctx,
75 const cmsis_nn_pool_params *pool_params,
76 const cmsis_nn_dims *input_dims,
77 const int8_t *src,
78 const cmsis_nn_dims *filter_dims,
79 const cmsis_nn_dims *output_dims,
80 int8_t *dst)
81 {
82 (void)ctx;
83 const int32_t input_y = input_dims->h;
84 const int32_t input_x = input_dims->w;
85 const int32_t output_y = output_dims->h;
86 const int32_t output_x = output_dims->w;
87 const int32_t stride_y = pool_params->stride.h;
88 const int32_t stride_x = pool_params->stride.w;
89 const int32_t kernel_y = filter_dims->h;
90 const int32_t kernel_x = filter_dims->w;
91 const int32_t pad_y = pool_params->padding.h;
92 const int32_t pad_x = pool_params->padding.w;
93 const int32_t act_min = pool_params->activation.min;
94 const int32_t act_max = pool_params->activation.max;
95 const int32_t ch_src = input_dims->c;
96
97 for (int i_y = 0; i_y < output_y; i_y++)
98 {
99 for (int i_x = 0; i_x < output_x; i_x++)
100 {
101 const int32_t k_y_start = MAX(0, i_y * stride_y - pad_y);
102 const int32_t k_y_end = MIN(i_y * stride_y - pad_y + kernel_y, input_y);
103
104 const int32_t k_x_start = MAX(0, i_x * stride_x - pad_x);
105 const int32_t k_x_end = MIN(i_x * stride_x - pad_x + kernel_x, input_x);
106
107 const int8_t *src_base = src;
108 int8_t *out = &dst[ch_src * (i_x + i_y * output_x)];
109
110 int32_t ch_count = (ch_src + 15) / 16;
111 int32_t channels = ch_src;
112
113 while (ch_count > 0)
114 {
115 int8x16_t temp;
116 int16x8_t temp_lo, temp_hi;
117 int32x4_t temp_lo_lo, temp_lo_hi, temp_hi_lo, temp_hi_hi;
118 int32_t count = 0;
119
120 int32x4_t sum_1 = vdupq_n_s32(0);
121 int32x4_t sum_2 = vdupq_n_s32(0);
122 int32x4_t sum_3 = vdupq_n_s32(0);
123 int32x4_t sum_4 = vdupq_n_s32(0);
124 // Load store tail predicate
125 const mve_pred16_t ld_st_p = vctp8q(channels);
126 channels -= 16;
127
128 for (int k_y = k_y_start; k_y < k_y_end; k_y++)
129 {
130 for (int k_x = k_x_start; k_x < k_x_end; k_x++)
131 {
132 const int8_t *src_inner = src_base + (ch_src * (k_x + k_y * input_x));
133 temp = vldrbq_z_s8(src_inner, ld_st_p);
134
135 temp_lo = vmovlbq_s8(temp);
136 temp_hi = vmovltq_s8(temp);
137
138 temp_lo_lo = vmovlbq_s16(temp_lo);
139 temp_lo_hi = vmovltq_s16(temp_lo);
140
141 temp_hi_lo = vmovlbq_s16(temp_hi);
142 temp_hi_hi = vmovltq_s16(temp_hi);
143
144 sum_1 = vaddq_s32(sum_1, temp_lo_lo);
145 sum_2 = vaddq_s32(sum_2, temp_lo_hi);
146 sum_3 = vaddq_s32(sum_3, temp_hi_lo);
147 sum_4 = vaddq_s32(sum_4, temp_hi_hi);
148
149 count++;
150 }
151 }
152
153 // Prevent static code issue DIVIDE_BY_ZERO.
154 if (count == 0)
155 {
156 return ARM_CMSIS_NN_ARG_ERROR;
157 }
158
159 // Perform the following operation
160 // sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count;
161 const int32_t half_count = count / 2;
162 // Predicate for 'sum > 0' operation
163 mve_pred16_t p = vcmpgtq_n_s32(sum_1, 0);
164 sum_1 = vaddq_m_n_s32(sum_1, sum_1, half_count, p);
165 sum_1 = vsubq_m_n_s32(sum_1, sum_1, half_count, ~p);
166
167 p = vcmpgtq_n_s32(sum_2, 0);
168 sum_2 = vaddq_m_n_s32(sum_2, sum_2, half_count, p);
169 sum_2 = vsubq_m_n_s32(sum_2, sum_2, half_count, ~p);
170
171 p = vcmpgtq_n_s32(sum_3, 0);
172 sum_3 = vaddq_m_n_s32(sum_3, sum_3, half_count, p);
173 sum_3 = vsubq_m_n_s32(sum_3, sum_3, half_count, ~p);
174
175 p = vcmpgtq_n_s32(sum_4, 0);
176 sum_4 = vaddq_m_n_s32(sum_4, sum_4, half_count, p);
177 sum_4 = vsubq_m_n_s32(sum_4, sum_4, half_count, ~p);
178
179 for (int i = 0; i < 4; i++)
180 {
181 sum_1[i] = sum_1[i] / count;
182 sum_2[i] = sum_2[i] / count;
183 sum_3[i] = sum_3[i] / count;
184 sum_4[i] = sum_4[i] / count;
185 }
186
187 sum_1 = vmaxq_s32(sum_1, vdupq_n_s32(act_min));
188 sum_1 = vminq_s32(sum_1, vdupq_n_s32(act_max));
189
190 sum_2 = vmaxq_s32(sum_2, vdupq_n_s32(act_min));
191 sum_2 = vminq_s32(sum_2, vdupq_n_s32(act_max));
192
193 sum_3 = vmaxq_s32(sum_3, vdupq_n_s32(act_min));
194 sum_3 = vminq_s32(sum_3, vdupq_n_s32(act_max));
195
196 sum_4 = vmaxq_s32(sum_4, vdupq_n_s32(act_min));
197 sum_4 = vminq_s32(sum_4, vdupq_n_s32(act_max));
198
199 temp_lo = vmovnbq_s32(temp_lo, sum_1);
200 temp_lo = vmovntq_s32(temp_lo, sum_2);
201
202 temp_hi = vmovnbq_s32(temp_hi, sum_3);
203 temp_hi = vmovntq_s32(temp_hi, sum_4);
204
205 temp = vmovnbq_s16(temp, temp_lo);
206 temp = vmovntq_s16(temp, temp_hi);
207
208 vstrbq_p_s8(out, temp, ld_st_p);
209 out += 16;
210
211 ch_count--;
212 src_base += 16;
213 }
214 }
215 }
216 return ARM_CMSIS_NN_SUCCESS;
217 }
218
219 #else
arm_avgpool_s8(const cmsis_nn_context * ctx,const cmsis_nn_pool_params * pool_params,const cmsis_nn_dims * input_dims,const int8_t * src,const cmsis_nn_dims * filter_dims,const cmsis_nn_dims * output_dims,int8_t * dst)220 arm_cmsis_nn_status arm_avgpool_s8(const cmsis_nn_context *ctx,
221 const cmsis_nn_pool_params *pool_params,
222 const cmsis_nn_dims *input_dims,
223 const int8_t *src,
224 const cmsis_nn_dims *filter_dims,
225 const cmsis_nn_dims *output_dims,
226 int8_t *dst)
227 {
228 const int32_t input_y = input_dims->h;
229 const int32_t input_x = input_dims->w;
230 const int32_t output_y = output_dims->h;
231 const int32_t output_x = output_dims->w;
232 const int32_t stride_y = pool_params->stride.h;
233 const int32_t stride_x = pool_params->stride.w;
234 const int32_t kernel_y = filter_dims->h;
235 const int32_t kernel_x = filter_dims->w;
236 const int32_t pad_y = pool_params->padding.h;
237 const int32_t pad_x = pool_params->padding.w;
238 const int32_t act_min = pool_params->activation.min;
239 const int32_t act_max = pool_params->activation.max;
240 const int32_t ch_src = input_dims->c;
241
242 if (ctx->buf == NULL && arm_avgpool_s8_get_buffer_size(output_dims->w, input_dims->c))
243 {
244 return ARM_CMSIS_NN_ARG_ERROR;
245 }
246 int32_t *buffer = (int32_t *)ctx->buf;
247
248 #if defined(ARM_MATH_DSP)
249
250 /* Run the following code for CPU's with DSP extension
251 */
252 for (int i_y = 0, idx_y = -pad_y; i_y < output_y; idx_y += stride_y, i_y++)
253 {
254 for (int i_x = 0, idx_x = -pad_x; i_x < output_x; idx_x += stride_x, i_x++)
255 {
256 /* Condition for kernel start dimension:
257 (base_idx_<x,y> + kernel_<x,y>_start) >= 0 */
258 const int32_t kernel_y_start = MAX(0, -idx_y);
259 const int32_t kernel_x_start = MAX(0, -idx_x);
260
261 /* Condition for kernel end dimension:
262 (base_idx_<x,y> + kernel_<x,y>_end) < dim_src_<width,height> */
263 const int32_t kernel_y_end = MIN(kernel_y, input_y - idx_y);
264 const int32_t kernel_x_end = MIN(kernel_x, input_x - idx_x);
265
266 int count = 0;
267
268 for (int k_y = kernel_y_start; k_y < kernel_y_end; k_y++)
269 {
270 for (int k_x = kernel_x_start; k_x < kernel_x_end; k_x++)
271 {
272 const int8_t *start = src + ch_src * (k_x + idx_x + (k_y + idx_y) * input_x);
273
274 if (count == 0)
275 {
276 for (int i = 0; i < ch_src; i++)
277 {
278 buffer[i] = start[i];
279 }
280 }
281 else
282 {
283 for (int i = 0; i < ch_src; i++)
284 {
285 buffer[i] = QADD(start[i], buffer[i]);
286 }
287 }
288 count++;
289 }
290 }
291
292 // Prevent static code issue DIVIDE_BY_ZERO.
293 if (count == 0)
294 {
295 return ARM_CMSIS_NN_ARG_ERROR;
296 }
297
298 scale_q31_to_q7_and_clamp(buffer, dst, ch_src, count, act_min, act_max);
299 dst += ch_src;
300 }
301 }
302 #else
303
304 /* Reference C code adapted from CMSIS-NN arm_avepool_q7_HWC.
305 */
306 (void)buffer;
307
308 for (int i_y = 0; i_y < output_y; i_y++)
309 {
310 for (int i_x = 0; i_x < output_x; i_x++)
311 {
312 for (int i_ch_in = 0; i_ch_in < ch_src; i_ch_in++)
313 {
314 int sum = 0;
315 int count = 0;
316 for (int k_y = i_y * stride_y - pad_y; k_y < i_y * stride_y - pad_y + kernel_y; k_y++)
317 {
318 for (int k_x = i_x * stride_x - pad_x; k_x < i_x * stride_x - pad_x + kernel_x; k_x++)
319 {
320 if (k_y >= 0 && k_x >= 0 && k_y < input_y && k_x < input_x)
321 {
322 sum += src[i_ch_in + ch_src * (k_x + k_y * input_x)];
323 count++;
324 }
325 }
326 }
327
328 // Prevent static code issue DIVIDE_BY_ZERO.
329 if (count == 0)
330 {
331 return ARM_CMSIS_NN_ARG_ERROR;
332 }
333
334 sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count;
335 sum = MAX(sum, act_min);
336 sum = MIN(sum, act_max);
337
338 dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum;
339 }
340 }
341 }
342
343 #endif
344 return ARM_CMSIS_NN_SUCCESS;
345 }
346
347 #endif /* ARM_MATH_MVEI */
348
349 /**
350 * @} end of Pooling group
351 */
352
