1 /*
2 * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_avgpool_s16.c
22 * Description: Pooling function implementations
23 *
24 * $Date: 30 January 2023
25 * $Revision: V.2.4.0
26 *
27 * Target : Arm(R) M-Profile Architecture
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 #if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI)
35
scale_q31_to_q15_and_clamp(const int32_t * buffer,int16_t * target,int32_t length,const int32_t count,const int act_min,const int act_max)36 static void scale_q31_to_q15_and_clamp(const int32_t *buffer,
37 int16_t *target,
38 int32_t length,
39 const int32_t count,
40 const int act_min,
41 const int act_max)
42 {
43 const int half_count = count / 2;
44
45 for (int i = 0; i < length; i++)
46 {
47 int32_t sum = buffer[i] > 0 ? (buffer[i] + half_count) : (buffer[i] - half_count);
48 sum = sum / count;
49 sum = MAX(sum, act_min);
50 sum = MIN(sum, act_max);
51
52 target[i] = (int16_t)sum;
53 }
54 }
55 #endif
56
57 /**
58 * @ingroup Public
59
60 */
61
62 /**
63 * @addtogroup Pooling
64 * @{
65 */
66
67 /*
68 * s16 average pooling function
69 *
70 * Refer to header file for details.
71 *
72 */
arm_avgpool_s16(const cmsis_nn_context * ctx,const cmsis_nn_pool_params * pool_params,const cmsis_nn_dims * input_dims,const int16_t * src,const cmsis_nn_dims * filter_dims,const cmsis_nn_dims * output_dims,int16_t * dst)73 arm_cmsis_nn_status arm_avgpool_s16(const cmsis_nn_context *ctx,
74 const cmsis_nn_pool_params *pool_params,
75 const cmsis_nn_dims *input_dims,
76 const int16_t *src,
77 const cmsis_nn_dims *filter_dims,
78 const cmsis_nn_dims *output_dims,
79 int16_t *dst)
80 {
81 const int32_t input_y = input_dims->h;
82 const int32_t input_x = input_dims->w;
83 const int32_t output_y = output_dims->h;
84 const int32_t output_x = output_dims->w;
85 const int32_t stride_y = pool_params->stride.h;
86 const int32_t stride_x = pool_params->stride.w;
87 const int32_t kernel_y = filter_dims->h;
88 const int32_t kernel_x = filter_dims->w;
89 const int32_t pad_y = pool_params->padding.h;
90 const int32_t pad_x = pool_params->padding.w;
91 const int32_t act_min = pool_params->activation.min;
92 const int32_t act_max = pool_params->activation.max;
93 const int32_t ch_src = input_dims->c;
94 #if defined(ARM_MATH_MVEI)
95 (void)ctx;
96 for (int i_y = 0; i_y < output_y; i_y++)
97 {
98 for (int i_x = 0; i_x < output_x; i_x++)
99 {
100 const int32_t k_y_start = MAX(0, i_y * stride_y - pad_y);
101 const int32_t k_y_end = MIN(i_y * stride_y - pad_y + kernel_y, input_y);
102
103 const int32_t k_x_start = MAX(0, i_x * stride_x - pad_x);
104 const int32_t k_x_end = MIN(i_x * stride_x - pad_x + kernel_x, input_x);
105
106 const int16_t *src_base = src;
107 int16_t *out = &dst[ch_src * (i_x + i_y * output_x)];
108
109 int32_t ch_count = (ch_src + 7) / 8;
110 int32_t channels = ch_src;
111
112 while (ch_count > 0)
113 {
114 int32_t count = 0;
115
116 int32x4_t sum_1 = vdupq_n_s32(0);
117 int32x4_t sum_2 = vdupq_n_s32(0);
118 // Load store tail predicate
119 const mve_pred16_t ld_st_p = vctp16q(channels);
120 channels -= 8;
121
122 for (int k_y = k_y_start; k_y < k_y_end; k_y++)
123 {
124 for (int k_x = k_x_start; k_x < k_x_end; k_x++)
125 {
126 const int16_t *src_inner = src_base + (ch_src * (k_x + k_y * input_x));
127 const int16x8_t temp = vldrhq_z_s16(src_inner, ld_st_p);
128
129 const int32x4_t temp_lo = vmovlbq_s16(temp);
130 const int32x4_t temp_hi = vmovltq_s16(temp);
131
132 sum_1 = vaddq_s32(sum_1, temp_lo);
133 sum_2 = vaddq_s32(sum_2, temp_hi);
134
135 count++;
136 }
137 }
138
139 // Prevent static code issue DIVIDE_BY_ZERO.
140 if (count == 0)
141 {
142 return ARM_CMSIS_NN_ARG_ERROR;
143 }
144
145 // Perform the following operation
146 // sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count;
147 const int32_t half_count = count / 2;
148 // Predicate for 'sum > 0' operation
149 mve_pred16_t p = vcmpgtq_n_s32(sum_1, 0);
150 sum_1 = vaddq_m_n_s32(sum_1, sum_1, half_count, p);
151 sum_1 = vsubq_m_n_s32(sum_1, sum_1, half_count, ~p);
152
153 p = vcmpgtq_n_s32(sum_2, 0);
154 sum_2 = vaddq_m_n_s32(sum_2, sum_2, half_count, p);
155 sum_2 = vsubq_m_n_s32(sum_2, sum_2, half_count, ~p);
156
157 for (int i = 0; i < 4; i++)
158 {
159 sum_1[i] = sum_1[i] / count;
160 sum_2[i] = sum_2[i] / count;
161 }
162
163 sum_1 = vmaxq_s32(sum_1, vdupq_n_s32(act_min));
164 sum_1 = vminq_s32(sum_1, vdupq_n_s32(act_max));
165
166 sum_2 = vmaxq_s32(sum_2, vdupq_n_s32(act_min));
167 sum_2 = vminq_s32(sum_2, vdupq_n_s32(act_max));
168
169 int16x8_t temp = vdupq_n_s16(0);
170 temp = vmovnbq_s32(temp, sum_1);
171 temp = vmovntq_s32(temp, sum_2);
172
173 vstrhq_p_s16(out, temp, ld_st_p);
174
175 out += 8;
176 ch_count--;
177 src_base += 8;
178 }
179 }
180 }
181 #elif defined(ARM_MATH_DSP)
182
183 int32_t *buffer = (int32_t *)ctx->buf;
184
185 if (buffer == NULL)
186 {
187 return ARM_CMSIS_NN_ARG_ERROR;
188 }
189
190 /* Run the following code for CPU's with DSP extension
191 */
192 for (int i_y = 0, idx_y = -pad_y; i_y < output_y; idx_y += stride_y, i_y++)
193 {
194 for (int i_x = 0, idx_x = -pad_x; i_x < output_x; idx_x += stride_x, i_x++)
195 {
196 /* Condition for kernel start dimension:
197 (base_idx_<x,y> + kernel_<x,y>_start) >= 0 */
198 const int32_t kernel_y_start = MAX(0, -idx_y);
199 const int32_t kernel_x_start = MAX(0, -idx_x);
200
201 /* Condition for kernel end dimension:
202 (base_idx_<x,y> + kernel_<x,y>_end) < dim_src_<width,height> */
203 const int32_t kernel_y_end = MIN(kernel_y, input_y - idx_y);
204 const int32_t kernel_x_end = MIN(kernel_x, input_x - idx_x);
205
206 int count = 0;
207
208 for (int k_y = kernel_y_start; k_y < kernel_y_end; k_y++)
209 {
210 for (int k_x = kernel_x_start; k_x < kernel_x_end; k_x++)
211 {
212 const int16_t *start = src + ch_src * (k_x + idx_x + (k_y + idx_y) * input_x);
213
214 if (count == 0)
215 {
216 for (int i = 0; i < ch_src; i++)
217 {
218 buffer[i] = start[i];
219 }
220 }
221 else
222 {
223 for (int i = 0; i < ch_src; i++)
224 {
225 buffer[i] = QADD(start[i], buffer[i]);
226 }
227 }
228 count++;
229 }
230 }
231
232 // Prevent static code issue DIVIDE_BY_ZERO.
233 if (count == 0)
234 {
235 return ARM_CMSIS_NN_ARG_ERROR;
236 }
237
238 scale_q31_to_q15_and_clamp(buffer, dst, ch_src, count, act_min, act_max);
239 dst += ch_src;
240 }
241 }
242
243 #else
244 /* Reference C code adapted from CMSIS-NN arm_avgpool_s8.c.
245 */
246
247 (void)ctx;
248
249 for (int i_y = 0, base_idx_y = -pad_y; i_y < output_y; base_idx_y += stride_y, i_y++)
250 {
251 for (int i_x = 0, base_idx_x = -pad_x; i_x < output_x; base_idx_x += stride_x, i_x++)
252 {
253 /* Condition for kernel start dimension: (base_idx_<x,y> + kernel_<x,y>_start) >= 0 */
254 const int32_t ker_y_start = MAX(0, -base_idx_y);
255 const int32_t ker_x_start = MAX(0, -base_idx_x);
256
257 /* Condition for kernel end dimension: (base_idx_<x,y> + kernel_<x,y>_end) < dim_src_<width,height> */
258 const int32_t kernel_y_end = MIN(kernel_y, input_y - base_idx_y);
259 const int32_t kernel_x_end = MIN(kernel_x, input_x - base_idx_x);
260
261 for (int i_ch_in = 0; i_ch_in < ch_src; i_ch_in++)
262 {
263 int sum = 0;
264 int count = 0;
265
266 for (int k_y = ker_y_start; k_y < kernel_y_end; k_y++)
267 {
268 for (int k_x = ker_x_start; k_x < kernel_x_end; k_x++)
269 {
270 sum += src[i_ch_in + ch_src * (k_x + base_idx_x + (k_y + base_idx_y) * input_x)];
271 count++;
272 }
273 }
274
275 // Prevent static code issue DIVIDE_BY_ZERO.
276 if (count == 0)
277 {
278 return ARM_CMSIS_NN_ARG_ERROR;
279 }
280
281 sum = sum > 0 ? (sum + count / 2) / count : (sum - count / 2) / count;
282 sum = MAX(sum, act_min);
283 sum = MIN(sum, act_max);
284
285 dst[i_ch_in + ch_src * (i_x + i_y * output_x)] = sum;
286 }
287 }
288 }
289 #endif
290
291 return ARM_CMSIS_NN_SUCCESS;
292 }
293
294 /**
295 * @} end of Pooling group
296 */
297
