1 /*
2 * SPDX-FileCopyrightText: Copyright 2010-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_s16.c
22 * Description: s16 version of convolution using symmetric quantization.
23 *
24 * $Date: 30 January 2023
25 * $Revision: V.2.1.0
26 *
27 * Target : Arm(R) M-Profile Architecture
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 /**
35 * @ingroup Public
36 */
37
38 /**
39 * @addtogroup NNConv
40 * @{
41 */
42
43 /*
44 * Basic s16 convolution function.
45 *
46 * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels
47 * are multiples of 4 or atleast greater than 4.
48 *
49 */
50
arm_convolve_s16(const cmsis_nn_context * ctx,const cmsis_nn_conv_params * conv_params,const cmsis_nn_per_channel_quant_params * quant_params,const cmsis_nn_dims * input_dims,const int16_t * input_data,const cmsis_nn_dims * filter_dims,const int8_t * filter_data,const cmsis_nn_dims * bias_dims,const int64_t * bias_data,const cmsis_nn_dims * output_dims,int16_t * output_data)51 arm_cmsis_nn_status arm_convolve_s16(const cmsis_nn_context *ctx,
52 const cmsis_nn_conv_params *conv_params,
53 const cmsis_nn_per_channel_quant_params *quant_params,
54 const cmsis_nn_dims *input_dims,
55 const int16_t *input_data,
56 const cmsis_nn_dims *filter_dims,
57 const int8_t *filter_data,
58 const cmsis_nn_dims *bias_dims,
59 const int64_t *bias_data,
60 const cmsis_nn_dims *output_dims,
61 int16_t *output_data)
62 {
63 (void)bias_dims;
64 (void)ctx;
65
66 const int32_t input_batches = input_dims->n;
67 const int32_t input_x = input_dims->w;
68 const int32_t input_y = input_dims->h;
69 const int32_t input_ch = input_dims->c;
70 const int32_t kernel_x = filter_dims->w;
71 const int32_t kernel_y = filter_dims->h;
72 const int32_t output_x = output_dims->w;
73 const int32_t output_y = output_dims->h;
74 const int32_t output_ch = output_dims->c;
75
76 const int32_t pad_x = conv_params->padding.w;
77 const int32_t pad_y = conv_params->padding.h;
78 const int32_t stride_x = conv_params->stride.w;
79 const int32_t stride_y = conv_params->stride.h;
80 const int32_t dilation_x = conv_params->dilation.w;
81 const int32_t dilation_y = conv_params->dilation.h;
82
83 const int32_t out_activation_min = conv_params->activation.min;
84 const int32_t out_activation_max = conv_params->activation.max;
85 int32_t *output_mult = quant_params->multiplier;
86 int32_t *output_shift = quant_params->shift;
87
88 for (int i_batch = 0; i_batch < input_batches; i_batch++)
89 {
90 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
91 for (int32_t i_out_ch = 0; i_out_ch < output_ch; i_out_ch++)
92 {
93 const int32_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i_out_ch]);
94
95 for (int32_t base_idx_y = -pad_y, i_out_y = 0; i_out_y < output_y; base_idx_y += stride_y, i_out_y++)
96 {
97 for (int32_t base_idx_x = -pad_x, i_out_x = 0; i_out_x < output_x; base_idx_x += stride_x, i_out_x++)
98 {
99 int64_t conv_out_acc = 0;
100
101 const int32_t start_y_max = (-base_idx_y + dilation_y - 1) / dilation_y;
102 const int32_t ker_y_start = MAX(0, start_y_max);
103 const int32_t start_x_max = (-base_idx_x + dilation_x - 1) / dilation_x;
104 const int32_t ker_x_start = MAX(0, start_x_max);
105 const int32_t end_min_y = (input_y - base_idx_y + dilation_y - 1) / dilation_y;
106 const int32_t ker_y_end = MIN(kernel_y, end_min_y);
107 const int32_t end_min_x = (input_x - base_idx_x + dilation_x - 1) / dilation_x;
108 const int32_t ker_x_end = MIN(kernel_x, end_min_x);
109
110 for (int32_t i_ker_y = ker_y_start; i_ker_y < ker_y_end; i_ker_y++)
111 {
112 for (int32_t i_ker_x = ker_x_start; i_ker_x < ker_x_end; i_ker_x++)
113 {
114 const int32_t in_row = base_idx_y + dilation_y * i_ker_y;
115 const int32_t in_col = base_idx_x + dilation_x * i_ker_x;
116
117 for (int32_t i_input_ch = 0; i_input_ch < input_ch; i_input_ch++)
118 {
119 conv_out_acc += input_data[(in_row * input_x + in_col) * input_ch + i_input_ch] *
120 filter_data[i_out_ch * input_ch * kernel_y * kernel_x +
121 (i_ker_y * kernel_x + i_ker_x) * input_ch + i_input_ch];
122 }
123 }
124 }
125
126 if (bias_data)
127 {
128 conv_out_acc += bias_data[i_out_ch];
129 }
130
131 int32_t conv_out = arm_nn_requantize_s64(conv_out_acc, reduced_multiplier, output_shift[i_out_ch]);
132 conv_out = MAX(conv_out, out_activation_min);
133 conv_out = MIN(conv_out, out_activation_max);
134 output_data[i_out_ch + (i_out_y * output_x + i_out_x) * output_ch] = (int16_t)conv_out;
135 }
136 }
137 }
138 /* Advance to the next batch */
139 input_data += (input_x * input_y * input_ch);
140 output_data += (output_x * output_y * output_ch);
141 }
142
143 /* Return to application */
144 return ARM_CMSIS_NN_SUCCESS;
145 }
146
147 /**
148 * @} end of NNConv group
149 */
150
