1 /*
2 * SPDX-FileCopyrightText: Copyright 2010-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_convolve_fast_s16.c
22 * Description: Optimized s16 version of convolution.
23 *
24 * $Date: 23 March 2023
25 * $Revision: V.2.3.0
26 *
27 * Target : Arm(R) M-Profile Architecture
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnfunctions.h"
32 #include "arm_nnsupportfunctions.h"
33
34 /**
35 * @ingroup Public
36 */
37
38 /**
39 * @addtogroup NNConv
40 * @{
41 */
42
43 /*
44 * Basic s16 convolution function.
45 *
46 * Refer header file for details. Optimal use case for the DSP/MVE implementation is when input and output channels
47 * are multiples of 4 or atleast greater than 4.
48 *
49 */
50
arm_convolve_fast_s16(const cmsis_nn_context * ctx,const cmsis_nn_conv_params * conv_params,const cmsis_nn_per_channel_quant_params * quant_params,const cmsis_nn_dims * input_dims,const int16_t * input_data,const cmsis_nn_dims * filter_dims,const int8_t * filter_data,const cmsis_nn_dims * bias_dims,const int64_t * bias_data,const cmsis_nn_dims * output_dims,int16_t * output_data)51 arm_cmsis_nn_status arm_convolve_fast_s16(const cmsis_nn_context *ctx,
52 const cmsis_nn_conv_params *conv_params,
53 const cmsis_nn_per_channel_quant_params *quant_params,
54 const cmsis_nn_dims *input_dims,
55 const int16_t *input_data,
56 const cmsis_nn_dims *filter_dims,
57 const int8_t *filter_data,
58 const cmsis_nn_dims *bias_dims,
59 const int64_t *bias_data,
60 const cmsis_nn_dims *output_dims,
61 int16_t *output_data)
62 {
63 (void)bias_dims;
64 if (filter_dims->w * filter_dims->h * input_dims->c >= 512)
65 {
66 return ARM_CMSIS_NN_ARG_ERROR;
67 }
68
69 if (ctx->buf == NULL && arm_convolve_s8_get_buffer_size(input_dims, filter_dims) > 0)
70 {
71 return ARM_CMSIS_NN_ARG_ERROR;
72 }
73 int16_t *buffer_a = (int16_t *)ctx->buf;
74
75 const int32_t input_batches = input_dims->n;
76 const int32_t input_x = input_dims->w;
77 const int32_t input_y = input_dims->h;
78 const int32_t input_ch = input_dims->c;
79 const int32_t kernel_x = filter_dims->w;
80 const int32_t kernel_y = filter_dims->h;
81 const int32_t output_x = output_dims->w;
82 const int32_t output_y = output_dims->h;
83 const int32_t output_ch = output_dims->c;
84 const int32_t rhs_cols = input_ch * kernel_y * kernel_x;
85
86 const int32_t pad_x = conv_params->padding.w;
87 const int32_t pad_y = conv_params->padding.h;
88 const int32_t stride_x = conv_params->stride.w;
89 const int32_t stride_y = conv_params->stride.h;
90
91 const int16_t out_activation_min = conv_params->activation.min;
92 const int16_t out_activation_max = conv_params->activation.max;
93 int32_t *output_mult = quant_params->multiplier;
94 int32_t *output_shift = quant_params->shift;
95
96 for (int i_batch = 0; i_batch < input_batches; i_batch++)
97 {
98 #if defined(ARM_MATH_DSP) && !defined(ARM_MATH_MVEI)
99 /* Generate two columns from the input tensor a GEMM computation */
100 int16_t *two_column_buf = buffer_a;
101 int16_t *out = output_data;
102 /* This part implements the im2col function */
103 for (int32_t i_out_y = 0; i_out_y < output_y; i_out_y++)
104 {
105 for (int32_t i_out_x = 0; i_out_x < output_x; i_out_x++)
106 {
107 for (int32_t i_ker_y = i_out_y * stride_y - pad_y; i_ker_y < i_out_y * stride_y - pad_y + kernel_y;
108 i_ker_y++)
109 {
110 for (int32_t i_ker_x = i_out_x * stride_x - pad_x; i_ker_x < i_out_x * stride_x - pad_x + kernel_x;
111 i_ker_x++)
112 {
113 if (i_ker_y < 0 || i_ker_y >= input_y || i_ker_x < 0 || i_ker_x >= input_x)
114 {
115 /* Filling 0 for out-of-bound paddings */
116 arm_memset_s8((int8_t *)two_column_buf, 0, sizeof(int16_t) * input_ch);
117 }
118 else
119 {
120 arm_memcpy_s8((int8_t *)two_column_buf,
121 (const int8_t *)(input_data + (i_ker_y * input_x + i_ker_x) * input_ch),
122 input_ch * sizeof(int16_t));
123 }
124 two_column_buf += input_ch;
125 }
126 }
127 /* Computation is filed for every 2 columns */
128 if (two_column_buf == buffer_a + 2 * rhs_cols)
129 {
130 out = arm_nn_mat_mult_kernel_s16(filter_data,
131 buffer_a,
132 output_ch,
133 output_shift,
134 output_mult,
135 out_activation_min,
136 out_activation_max,
137 rhs_cols,
138 bias_data,
139 out);
140
141 /* Counter reset */
142 two_column_buf = buffer_a;
143 }
144 }
145 }
146
147 /* Left-over because odd number of output pixels */
148 if (two_column_buf != buffer_a)
149 {
150 const int8_t *ker_a = filter_data;
151 int i;
152
153 for (i = 0; i < output_ch; i++)
154 {
155 /* Init the accumulator*/
156 int32_t sum = 0;
157
158 /* Point to the beginning of the im2col buffer where the input is available as a rearranged column */
159 const int16_t *ip_as_col = buffer_a;
160
161 /* 4 multiply and accumulates are done in one loop. */
162 int32_t col_count = rhs_cols >> 2;
163
164 while (col_count)
165 {
166 int32_t ker_a1, ker_a2;
167 int32_t ip_b1, ip_b2;
168
169 ker_a = read_and_pad(ker_a, &ker_a1, &ker_a2);
170
171 ip_b1 = arm_nn_read_q15x2_ia(&ip_as_col);
172 sum = SMLAD(ker_a1, ip_b1, sum);
173 ip_b2 = arm_nn_read_q15x2_ia(&ip_as_col);
174 sum = SMLAD(ker_a2, ip_b2, sum);
175
176 col_count--;
177 }
178 /* Handle left over mac */
179 col_count = rhs_cols & 0x3;
180 while (col_count)
181 {
182 int8_t ker_a1 = *ker_a++;
183 int16_t ip_b1 = *ip_as_col++;
184 sum += ker_a1 * ip_b1;
185 col_count--;
186 }
187 if (bias_data)
188 {
189 int32_t reduced_multiplier = REDUCE_MULTIPLIER(output_mult[i]);
190 int64_t acc_64 = sum + bias_data[i];
191 sum = arm_nn_requantize_s64(acc_64, reduced_multiplier, output_shift[i]);
192 }
193 else
194 {
195 sum = arm_nn_requantize(sum, output_mult[i], output_shift[i]);
196 }
197 sum = MAX(sum, out_activation_min);
198 sum = MIN(sum, out_activation_max);
199 *out++ = (int16_t)sum;
200 }
201 }
202 #else
203 (void)input_data;
204 (void)output_data;
205 (void)bias_data;
206 (void)filter_data;
207 (void)buffer_a;
208 (void)kernel_x;
209 (void)kernel_y;
210 (void)pad_x;
211 (void)pad_y;
212 (void)stride_x;
213 (void)stride_y;
214 (void)out_activation_min;
215 (void)out_activation_max;
216 (void)output_mult;
217 (void)output_shift;
218 (void)rhs_cols;
219 return ARM_CMSIS_NN_ARG_ERROR;
220 #endif
221 /* Advance to the next batch */
222 input_data += (input_x * input_y * input_ch);
223 output_data += (output_x * output_y * output_ch);
224 }
225
226 /* Return to application */
227 return ARM_CMSIS_NN_SUCCESS;
228 }
229
230 /**
231 * @} end of NNConv group
232 */
233
