1 /*
2 * SPDX-FileCopyrightText: Copyright 2022-2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /* ----------------------------------------------------------------------
20 * Project: CMSIS NN Library
21 * Title: arm_elementwise_mul_s16_s8.c
22 * Description: Elementwise multiplication of 16 bit input with 8 bit output
23 *
24 * $Date: 20 January 2023
25 * $Revision: V.1.2.0
26 *
27 * Target : Arm(R) M-Profile Architecture
28 *
29 * -------------------------------------------------------------------- */
30
31 #include "arm_nnsupportfunctions.h"
32
33 /**
34 * @ingroup groupSupport
35 */
36
37 /**
38 * @addtogroup BasicMath
39 * @{
40 */
41
42 /*
43 * s16 elementwise multiplication with s8 output
44 *
45 * Refer header file for details.
46 *
47 */
arm_elementwise_mul_s16_s8(const int16_t * input_1_vect,const int16_t * input_2_vect,int8_t * output,const int32_t out_offset,const int32_t out_mult,const int32_t out_shift,const int32_t block_size)48 arm_cmsis_nn_status arm_elementwise_mul_s16_s8(const int16_t *input_1_vect,
49 const int16_t *input_2_vect,
50 int8_t *output,
51 const int32_t out_offset,
52 const int32_t out_mult,
53 const int32_t out_shift,
54 const int32_t block_size)
55 {
56 int32_t loop_count = block_size;
57
58 #if defined(ARM_MATH_MVEI)
59
60 while (loop_count > 0)
61 {
62 mve_pred16_t pred = vctp32q(loop_count);
63
64 int32x4_t input_1 = vldrhq_z_s32(input_1_vect, pred);
65 int32x4_t input_2 = vldrhq_z_s32(input_2_vect, pred);
66
67 int32x4_t res_0 = vmulq_s32(input_1, input_2);
68
69 res_0 = arm_requantize_mve_32x4(res_0, vdupq_n_s32(out_mult), vdupq_n_s32(out_shift));
70 res_0 = vaddq_n_s32(res_0, out_offset);
71
72 res_0 = vmaxq_s32(res_0, vdupq_n_s32(NN_Q7_MIN));
73 res_0 = vminq_s32(res_0, vdupq_n_s32(NN_Q7_MAX));
74
75 vstrbq_p_s32(output, res_0, pred);
76 input_1_vect += 4;
77 input_2_vect += 4;
78
79 output += 4;
80 loop_count -= 4;
81 }
82
83 #else
84 #if defined(ARM_MATH_DSP)
85
86 while (loop_count > 1)
87 {
88 int32_t input_1 = arm_nn_read_q15x2_ia(&input_1_vect);
89 int32_t input_2 = arm_nn_read_q15x2_ia(&input_2_vect);
90
91 int32_t mul_res = SMULBB(input_1, input_2);
92 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
93 mul_res = CLAMP(mul_res, NN_Q7_MAX, NN_Q7_MIN);
94 int32_t mul = (int16_t)(mul_res & 0xFF);
95
96 mul_res = SMULTT(input_1, input_2);
97 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
98 mul_res = CLAMP(mul_res, NN_Q7_MAX, NN_Q7_MIN);
99 mul |= (int16_t)mul_res << 8;
100
101 arm_nn_write_s8x2_ia(&output, mul);
102 loop_count -= 2;
103 }
104 #endif
105 for (int i = 0; i < loop_count; i++)
106 {
107 /* C = A * B */
108 int32_t mul_res = input_1_vect[i] * input_2_vect[i];
109 mul_res = arm_nn_requantize(mul_res, out_mult, out_shift) + out_offset;
110
111 mul_res = CLAMP(mul_res, NN_Q7_MAX, NN_Q7_MIN);
112
113 output[i] = (int8_t)mul_res;
114 }
115
116 #endif
117
118 return ARM_CMSIS_NN_SUCCESS;
119 }
120 /**
121 * @} end of BasicMath group
122 */
123
