1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Eth_43_NETC.c
9 * @version 2.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Eth_43_NETC.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_ETH_43_NETC_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_ETH_43_NETC_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_ETH_43_NETC_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_ETH_43_NETC_SW_MAJOR_VERSION_C 2
44 #define SCHM_ETH_43_NETC_SW_MINOR_VERSION_C 0
45 #define SCHM_ETH_43_NETC_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_00) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_01) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_02) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_03) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_04) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_05) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_07) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_08) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_09) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_10) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_11) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_12) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_13) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_14) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_15) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_16) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_17) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_18) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_19) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_20) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_21) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_22) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_23) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_24) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_25) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_26) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_27) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_28) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(msr_ETH_EXCLUSIVE_AREA_29) static volatile uint32 msr_ETH_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(reentry_guard_ETH_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_ETH_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
160
161 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
162 #include "Rte_MemMap.h"
163 /*==================================================================================================
164 * GLOBAL CONSTANTS
165 ==================================================================================================*/
166
167
168 /*==================================================================================================
169 * GLOBAL VARIABLES
170 ==================================================================================================*/
171
172 /*==================================================================================================
173 * LOCAL FUNCTION PROTOTYPES
174 ==================================================================================================*/
175
176 #ifndef _COSMIC_C_S32ZE_
177 /*================================================================================================*/
178 /**
179 * @brief This function returns the MSR register value (32 bits).
180 * @details This function returns the MSR register value (32 bits).
181 *
182 * @param[in] void No input parameters
183 * @return uint32 msr This function returns the MSR register value (32 bits).
184 *
185 * @pre None
186 * @post None
187 *
188 */
189 uint32 Eth_43_NETC_schm_read_msr(void);
190 #endif /*ifndef _COSMIC_C_S32ZE_*/
191 /*==================================================================================================
192 * LOCAL FUNCTIONS
193 ==================================================================================================*/
194 #define RTE_START_SEC_CODE
195 #include "Rte_MemMap.h"
196
197 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
198 /*================================================================================================*/
199 /**
200 * @brief This macro returns the MSR register value (32 bits).
201 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
202 *
203 * @pre None
204 * @post None
205 *
206 */
207 #ifdef MCAL_PLATFORM_ARM
208 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Eth_43_NETC_schm_read_msr(void)209 ASM_KEYWORD uint32 Eth_43_NETC_schm_read_msr(void)
210 {
211 mrs x0, S3_3_c4_c2_1
212 }
213 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Eth_43_NETC_schm_read_msr(void)214 ASM_KEYWORD uint32 Eth_43_NETC_schm_read_msr(void)
215 {
216 mrs r0, CPSR
217 }
218 #else
Eth_43_NETC_schm_read_msr(void)219 ASM_KEYWORD uint32 Eth_43_NETC_schm_read_msr(void)
220 {
221 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
222 mrs r0, BASEPRI
223 #else
224 mrs r0, PRIMASK
225 #endif
226 }
227 #endif
228 #else
229 #ifdef MCAL_PLATFORM_S12
Eth_43_NETC_schm_read_msr(void)230 ASM_KEYWORD uint32 Eth_43_NETC_schm_read_msr(void)
231 {
232 tfr ccr, d6
233 }
234 #else
Eth_43_NETC_schm_read_msr(void)235 ASM_KEYWORD uint32 Eth_43_NETC_schm_read_msr(void)
236 {
237 mfmsr r3
238 }
239 #endif
240 #endif
241 #endif /*#ifdef GHS||CW*/
242
243 #ifdef _DIABDATA_C_S32ZE_
244 /**
245 * @brief This function returns the MSR register value (32 bits).
246 * @details This function returns the MSR register value (32 bits).
247 *
248 * @param[in] void No input parameters
249 * @return uint32 msr This function returns the MSR register value (32 bits).
250 *
251 * @pre None
252 * @post None
253 *
254 */
255 #ifdef MCAL_PLATFORM_ARM
Eth_43_NETC_schm_read_msr(void)256 uint32 Eth_43_NETC_schm_read_msr(void)
257 {
258 register uint32 reg_tmp;
259 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
260 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
261 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
262 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
263 #else
264 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
265 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
266 #else
267 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
268 #endif
269 #endif
270 return (uint32)reg_tmp;
271 }
272 #else
Eth_43_NETC_schm_read_msr(void)273 ASM_KEYWORD uint32 Eth_43_NETC_schm_read_msr(void)
274 {
275 mfmsr r3
276 }
277 #endif /* MCAL_PLATFORM_ARM */
278
279 #endif /* _DIABDATA_C_S32ZE_*/
280
281 #ifdef _COSMIC_C_S32ZE_
282 /*================================================================================================*/
283 /**
284 * @brief This function returns the MSR register value (32 bits).
285 * @details This function returns the MSR register value (32 bits).
286 *
287 * @param[in] void No input parameters
288 * @return uint32 msr This function returns the MSR register value (32 bits).
289 *
290 * @pre None
291 * @post None
292 *
293 */
294
295 #ifdef MCAL_PLATFORM_S12
296 #define Eth_43_NETC_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
297 #else
298 #define Eth_43_NETC_schm_read_msr() ASM_KEYWORD("mfmsr r3")
299 #endif
300
301 #endif /*Cosmic compiler only*/
302
303
304 #ifdef _HITECH_C_S32ZE_
305 /*================================================================================================*/
306 /**
307 * @brief This function returns the MSR register value (32 bits).
308 * @details This function returns the MSR register value (32 bits).
309 *
310 * @param[in] void No input parameters
311 * @return uint32 msr This function returns the MSR register value (32 bits).
312 *
313 * @pre None
314 * @post None
315 *
316 */
Eth_43_NETC_schm_read_msr(void)317 uint32 Eth_43_NETC_schm_read_msr(void)
318 {
319 uint32 result;
320 __asm volatile("mfmsr %0" : "=r" (result) :);
321 return result;
322 }
323
324 #endif /*HighTec compiler only*/
325 /*================================================================================================*/
326 #ifdef _GCC_C_S32ZE_
327 /**
328 * @brief This function returns the MSR register value (32 bits).
329 * @details This function returns the MSR register value (32 bits).
330 *
331 * @param[in] void No input parameters
332 * @return uint32 msr This function returns the MSR register value (32 bits).
333 *
334 * @pre None
335 * @post None
336 *
337 */
Eth_43_NETC_schm_read_msr(void)338 uint32 Eth_43_NETC_schm_read_msr(void)
339 {
340 register uint32 reg_tmp;
341 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
342 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
343 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
344 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
345 #else
346 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
347 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
348 #else
349 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
350 #endif
351 #endif
352 return (uint32)reg_tmp;
353 }
354 #endif /* _GCC_C_S32ZE_*/
355 /*================================================================================================*/
356
357 #ifdef _ARM_DS5_C_S32ZE_
358 /**
359 * @brief This function returns the MSR register value (32 bits).
360 * @details This function returns the MSR register value (32 bits).
361 *
362 * @param[in] void No input parameters
363 * @return uint32 msr This function returns the MSR register value (32 bits).
364 *
365 * @pre None
366 * @post None
367 *
368 */
Eth_43_NETC_schm_read_msr(void)369 uint32 Eth_43_NETC_schm_read_msr(void)
370 {
371 register uint32 reg_tmp;
372 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
373 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
374 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
375 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
376 #else
377 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
378 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
379 #else
380 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
381 #endif
382 #endif
383 return (uint32)reg_tmp;
384 }
385 #endif /* _ARM_DS5_C_S32ZE_ */
386
387 #ifdef _IAR_C_S32ZE_
388 /**
389 * @brief This function returns the MSR register value (32 bits).
390 * @details This function returns the MSR register value (32 bits).
391 *
392 * @param[in] void No input parameters
393 * @return uint32 msr This function returns the MSR register value (32 bits).
394 *
395 * @pre None
396 * @post None
397 *
398 */
Eth_43_NETC_schm_read_msr(void)399 uint32 Eth_43_NETC_schm_read_msr(void)
400 {
401 register uint32 reg_tmp;
402
403 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
404 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
405 #else
406 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
407 #endif
408
409 return (uint32)reg_tmp;
410 }
411 #endif /* _IAR_C_S32ZE_ */
412
413 #define RTE_STOP_SEC_CODE
414 #include "Rte_MemMap.h"
415
416 /*==================================================================================================
417 * GLOBAL FUNCTIONS
418 ==================================================================================================*/
419 #define RTE_START_SEC_CODE
420 #include "Rte_MemMap.h"
421
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00(void)422 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00(void)
423 {
424 uint32 msr;
425 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
426
427 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_00[u32CoreId])
428 {
429 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
430 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
431 #else
432 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
433 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
434 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
435 {
436 OsIf_SuspendAllInterrupts();
437 #ifdef _ARM_DS5_C_S32ZE_
438 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
439 #endif
440 }
441 msr_ETH_EXCLUSIVE_AREA_00[u32CoreId] = msr;
442 }
443 reentry_guard_ETH_EXCLUSIVE_AREA_00[u32CoreId]++;
444 }
445
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00(void)446 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_00(void)
447 {
448 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
449
450 reentry_guard_ETH_EXCLUSIVE_AREA_00[u32CoreId]--;
451 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
452 {
453 OsIf_ResumeAllInterrupts();
454 #ifdef _ARM_DS5_C_S32ZE_
455 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
456 #endif
457 }
458 }
459
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01(void)460 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01(void)
461 {
462 uint32 msr;
463 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
464
465 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_01[u32CoreId])
466 {
467 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
468 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
469 #else
470 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
471 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
472 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
473 {
474 OsIf_SuspendAllInterrupts();
475 #ifdef _ARM_DS5_C_S32ZE_
476 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
477 #endif
478 }
479 msr_ETH_EXCLUSIVE_AREA_01[u32CoreId] = msr;
480 }
481 reentry_guard_ETH_EXCLUSIVE_AREA_01[u32CoreId]++;
482 }
483
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01(void)484 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_01(void)
485 {
486 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
487
488 reentry_guard_ETH_EXCLUSIVE_AREA_01[u32CoreId]--;
489 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
490 {
491 OsIf_ResumeAllInterrupts();
492 #ifdef _ARM_DS5_C_S32ZE_
493 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
494 #endif
495 }
496 }
497
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02(void)498 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02(void)
499 {
500 uint32 msr;
501 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
502
503 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_02[u32CoreId])
504 {
505 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
506 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
507 #else
508 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
509 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
510 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
511 {
512 OsIf_SuspendAllInterrupts();
513 #ifdef _ARM_DS5_C_S32ZE_
514 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
515 #endif
516 }
517 msr_ETH_EXCLUSIVE_AREA_02[u32CoreId] = msr;
518 }
519 reentry_guard_ETH_EXCLUSIVE_AREA_02[u32CoreId]++;
520 }
521
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02(void)522 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_02(void)
523 {
524 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
525
526 reentry_guard_ETH_EXCLUSIVE_AREA_02[u32CoreId]--;
527 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
528 {
529 OsIf_ResumeAllInterrupts();
530 #ifdef _ARM_DS5_C_S32ZE_
531 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
532 #endif
533 }
534 }
535
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03(void)536 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03(void)
537 {
538 uint32 msr;
539 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
540
541 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_03[u32CoreId])
542 {
543 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
544 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
545 #else
546 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
547 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
548 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
549 {
550 OsIf_SuspendAllInterrupts();
551 #ifdef _ARM_DS5_C_S32ZE_
552 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
553 #endif
554 }
555 msr_ETH_EXCLUSIVE_AREA_03[u32CoreId] = msr;
556 }
557 reentry_guard_ETH_EXCLUSIVE_AREA_03[u32CoreId]++;
558 }
559
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03(void)560 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_03(void)
561 {
562 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
563
564 reentry_guard_ETH_EXCLUSIVE_AREA_03[u32CoreId]--;
565 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
566 {
567 OsIf_ResumeAllInterrupts();
568 #ifdef _ARM_DS5_C_S32ZE_
569 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
570 #endif
571 }
572 }
573
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04(void)574 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04(void)
575 {
576 uint32 msr;
577 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
578
579 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_04[u32CoreId])
580 {
581 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
582 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
583 #else
584 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
585 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
586 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
587 {
588 OsIf_SuspendAllInterrupts();
589 #ifdef _ARM_DS5_C_S32ZE_
590 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
591 #endif
592 }
593 msr_ETH_EXCLUSIVE_AREA_04[u32CoreId] = msr;
594 }
595 reentry_guard_ETH_EXCLUSIVE_AREA_04[u32CoreId]++;
596 }
597
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04(void)598 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_04(void)
599 {
600 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
601
602 reentry_guard_ETH_EXCLUSIVE_AREA_04[u32CoreId]--;
603 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
604 {
605 OsIf_ResumeAllInterrupts();
606 #ifdef _ARM_DS5_C_S32ZE_
607 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
608 #endif
609 }
610 }
611
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05(void)612 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05(void)
613 {
614 uint32 msr;
615 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
616
617 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_05[u32CoreId])
618 {
619 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
620 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
621 #else
622 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
623 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
624 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
625 {
626 OsIf_SuspendAllInterrupts();
627 #ifdef _ARM_DS5_C_S32ZE_
628 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
629 #endif
630 }
631 msr_ETH_EXCLUSIVE_AREA_05[u32CoreId] = msr;
632 }
633 reentry_guard_ETH_EXCLUSIVE_AREA_05[u32CoreId]++;
634 }
635
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05(void)636 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_05(void)
637 {
638 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
639
640 reentry_guard_ETH_EXCLUSIVE_AREA_05[u32CoreId]--;
641 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
642 {
643 OsIf_ResumeAllInterrupts();
644 #ifdef _ARM_DS5_C_S32ZE_
645 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
646 #endif
647 }
648 }
649
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07(void)650 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07(void)
651 {
652 uint32 msr;
653 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
654
655 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_07[u32CoreId])
656 {
657 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
658 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
659 #else
660 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
661 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
662 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
663 {
664 OsIf_SuspendAllInterrupts();
665 #ifdef _ARM_DS5_C_S32ZE_
666 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
667 #endif
668 }
669 msr_ETH_EXCLUSIVE_AREA_07[u32CoreId] = msr;
670 }
671 reentry_guard_ETH_EXCLUSIVE_AREA_07[u32CoreId]++;
672 }
673
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07(void)674 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_07(void)
675 {
676 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
677
678 reentry_guard_ETH_EXCLUSIVE_AREA_07[u32CoreId]--;
679 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
680 {
681 OsIf_ResumeAllInterrupts();
682 #ifdef _ARM_DS5_C_S32ZE_
683 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
684 #endif
685 }
686 }
687
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08(void)688 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08(void)
689 {
690 uint32 msr;
691 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
692
693 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_08[u32CoreId])
694 {
695 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
696 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
697 #else
698 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
699 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
700 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
701 {
702 OsIf_SuspendAllInterrupts();
703 #ifdef _ARM_DS5_C_S32ZE_
704 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
705 #endif
706 }
707 msr_ETH_EXCLUSIVE_AREA_08[u32CoreId] = msr;
708 }
709 reentry_guard_ETH_EXCLUSIVE_AREA_08[u32CoreId]++;
710 }
711
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08(void)712 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_08(void)
713 {
714 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
715
716 reentry_guard_ETH_EXCLUSIVE_AREA_08[u32CoreId]--;
717 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
718 {
719 OsIf_ResumeAllInterrupts();
720 #ifdef _ARM_DS5_C_S32ZE_
721 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
722 #endif
723 }
724 }
725
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09(void)726 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09(void)
727 {
728 uint32 msr;
729 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
730
731 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_09[u32CoreId])
732 {
733 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
734 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
735 #else
736 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
737 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
738 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
739 {
740 OsIf_SuspendAllInterrupts();
741 #ifdef _ARM_DS5_C_S32ZE_
742 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
743 #endif
744 }
745 msr_ETH_EXCLUSIVE_AREA_09[u32CoreId] = msr;
746 }
747 reentry_guard_ETH_EXCLUSIVE_AREA_09[u32CoreId]++;
748 }
749
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09(void)750 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_09(void)
751 {
752 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
753
754 reentry_guard_ETH_EXCLUSIVE_AREA_09[u32CoreId]--;
755 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
756 {
757 OsIf_ResumeAllInterrupts();
758 #ifdef _ARM_DS5_C_S32ZE_
759 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
760 #endif
761 }
762 }
763
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10(void)764 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10(void)
765 {
766 uint32 msr;
767 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
768
769 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_10[u32CoreId])
770 {
771 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
772 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
773 #else
774 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
775 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
776 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
777 {
778 OsIf_SuspendAllInterrupts();
779 #ifdef _ARM_DS5_C_S32ZE_
780 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
781 #endif
782 }
783 msr_ETH_EXCLUSIVE_AREA_10[u32CoreId] = msr;
784 }
785 reentry_guard_ETH_EXCLUSIVE_AREA_10[u32CoreId]++;
786 }
787
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10(void)788 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_10(void)
789 {
790 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
791
792 reentry_guard_ETH_EXCLUSIVE_AREA_10[u32CoreId]--;
793 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
794 {
795 OsIf_ResumeAllInterrupts();
796 #ifdef _ARM_DS5_C_S32ZE_
797 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
798 #endif
799 }
800 }
801
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11(void)802 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11(void)
803 {
804 uint32 msr;
805 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
806
807 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_11[u32CoreId])
808 {
809 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
810 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
811 #else
812 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
813 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
814 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
815 {
816 OsIf_SuspendAllInterrupts();
817 #ifdef _ARM_DS5_C_S32ZE_
818 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
819 #endif
820 }
821 msr_ETH_EXCLUSIVE_AREA_11[u32CoreId] = msr;
822 }
823 reentry_guard_ETH_EXCLUSIVE_AREA_11[u32CoreId]++;
824 }
825
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11(void)826 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_11(void)
827 {
828 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
829
830 reentry_guard_ETH_EXCLUSIVE_AREA_11[u32CoreId]--;
831 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
832 {
833 OsIf_ResumeAllInterrupts();
834 #ifdef _ARM_DS5_C_S32ZE_
835 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
836 #endif
837 }
838 }
839
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12(void)840 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12(void)
841 {
842 uint32 msr;
843 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
844
845 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_12[u32CoreId])
846 {
847 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
848 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
849 #else
850 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
851 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
852 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
853 {
854 OsIf_SuspendAllInterrupts();
855 #ifdef _ARM_DS5_C_S32ZE_
856 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
857 #endif
858 }
859 msr_ETH_EXCLUSIVE_AREA_12[u32CoreId] = msr;
860 }
861 reentry_guard_ETH_EXCLUSIVE_AREA_12[u32CoreId]++;
862 }
863
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12(void)864 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_12(void)
865 {
866 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
867
868 reentry_guard_ETH_EXCLUSIVE_AREA_12[u32CoreId]--;
869 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
870 {
871 OsIf_ResumeAllInterrupts();
872 #ifdef _ARM_DS5_C_S32ZE_
873 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
874 #endif
875 }
876 }
877
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13(void)878 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13(void)
879 {
880 uint32 msr;
881 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
882
883 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_13[u32CoreId])
884 {
885 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
886 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
887 #else
888 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
889 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
890 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
891 {
892 OsIf_SuspendAllInterrupts();
893 #ifdef _ARM_DS5_C_S32ZE_
894 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
895 #endif
896 }
897 msr_ETH_EXCLUSIVE_AREA_13[u32CoreId] = msr;
898 }
899 reentry_guard_ETH_EXCLUSIVE_AREA_13[u32CoreId]++;
900 }
901
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13(void)902 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_13(void)
903 {
904 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
905
906 reentry_guard_ETH_EXCLUSIVE_AREA_13[u32CoreId]--;
907 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
908 {
909 OsIf_ResumeAllInterrupts();
910 #ifdef _ARM_DS5_C_S32ZE_
911 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
912 #endif
913 }
914 }
915
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14(void)916 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14(void)
917 {
918 uint32 msr;
919 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
920
921 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_14[u32CoreId])
922 {
923 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
924 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
925 #else
926 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
927 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
928 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
929 {
930 OsIf_SuspendAllInterrupts();
931 #ifdef _ARM_DS5_C_S32ZE_
932 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
933 #endif
934 }
935 msr_ETH_EXCLUSIVE_AREA_14[u32CoreId] = msr;
936 }
937 reentry_guard_ETH_EXCLUSIVE_AREA_14[u32CoreId]++;
938 }
939
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14(void)940 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_14(void)
941 {
942 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
943
944 reentry_guard_ETH_EXCLUSIVE_AREA_14[u32CoreId]--;
945 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
946 {
947 OsIf_ResumeAllInterrupts();
948 #ifdef _ARM_DS5_C_S32ZE_
949 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
950 #endif
951 }
952 }
953
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15(void)954 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15(void)
955 {
956 uint32 msr;
957 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
958
959 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_15[u32CoreId])
960 {
961 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
962 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
963 #else
964 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
965 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
966 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
967 {
968 OsIf_SuspendAllInterrupts();
969 #ifdef _ARM_DS5_C_S32ZE_
970 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
971 #endif
972 }
973 msr_ETH_EXCLUSIVE_AREA_15[u32CoreId] = msr;
974 }
975 reentry_guard_ETH_EXCLUSIVE_AREA_15[u32CoreId]++;
976 }
977
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15(void)978 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_15(void)
979 {
980 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
981
982 reentry_guard_ETH_EXCLUSIVE_AREA_15[u32CoreId]--;
983 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
984 {
985 OsIf_ResumeAllInterrupts();
986 #ifdef _ARM_DS5_C_S32ZE_
987 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
988 #endif
989 }
990 }
991
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16(void)992 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16(void)
993 {
994 uint32 msr;
995 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
996
997 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_16[u32CoreId])
998 {
999 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1000 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1001 #else
1002 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1003 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1004 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1005 {
1006 OsIf_SuspendAllInterrupts();
1007 #ifdef _ARM_DS5_C_S32ZE_
1008 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1009 #endif
1010 }
1011 msr_ETH_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1012 }
1013 reentry_guard_ETH_EXCLUSIVE_AREA_16[u32CoreId]++;
1014 }
1015
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16(void)1016 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_16(void)
1017 {
1018 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1019
1020 reentry_guard_ETH_EXCLUSIVE_AREA_16[u32CoreId]--;
1021 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1022 {
1023 OsIf_ResumeAllInterrupts();
1024 #ifdef _ARM_DS5_C_S32ZE_
1025 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1026 #endif
1027 }
1028 }
1029
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17(void)1030 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17(void)
1031 {
1032 uint32 msr;
1033 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1034
1035 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_17[u32CoreId])
1036 {
1037 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1038 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1039 #else
1040 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1041 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1042 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1043 {
1044 OsIf_SuspendAllInterrupts();
1045 #ifdef _ARM_DS5_C_S32ZE_
1046 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1047 #endif
1048 }
1049 msr_ETH_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1050 }
1051 reentry_guard_ETH_EXCLUSIVE_AREA_17[u32CoreId]++;
1052 }
1053
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17(void)1054 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_17(void)
1055 {
1056 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1057
1058 reentry_guard_ETH_EXCLUSIVE_AREA_17[u32CoreId]--;
1059 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1060 {
1061 OsIf_ResumeAllInterrupts();
1062 #ifdef _ARM_DS5_C_S32ZE_
1063 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1064 #endif
1065 }
1066 }
1067
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18(void)1068 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18(void)
1069 {
1070 uint32 msr;
1071 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1072
1073 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_18[u32CoreId])
1074 {
1075 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1076 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1077 #else
1078 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1079 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1080 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1081 {
1082 OsIf_SuspendAllInterrupts();
1083 #ifdef _ARM_DS5_C_S32ZE_
1084 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1085 #endif
1086 }
1087 msr_ETH_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1088 }
1089 reentry_guard_ETH_EXCLUSIVE_AREA_18[u32CoreId]++;
1090 }
1091
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18(void)1092 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_18(void)
1093 {
1094 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1095
1096 reentry_guard_ETH_EXCLUSIVE_AREA_18[u32CoreId]--;
1097 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1098 {
1099 OsIf_ResumeAllInterrupts();
1100 #ifdef _ARM_DS5_C_S32ZE_
1101 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1102 #endif
1103 }
1104 }
1105
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19(void)1106 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19(void)
1107 {
1108 uint32 msr;
1109 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1110
1111 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_19[u32CoreId])
1112 {
1113 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1114 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1115 #else
1116 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1117 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1118 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1119 {
1120 OsIf_SuspendAllInterrupts();
1121 #ifdef _ARM_DS5_C_S32ZE_
1122 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1123 #endif
1124 }
1125 msr_ETH_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1126 }
1127 reentry_guard_ETH_EXCLUSIVE_AREA_19[u32CoreId]++;
1128 }
1129
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19(void)1130 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_19(void)
1131 {
1132 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1133
1134 reentry_guard_ETH_EXCLUSIVE_AREA_19[u32CoreId]--;
1135 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1136 {
1137 OsIf_ResumeAllInterrupts();
1138 #ifdef _ARM_DS5_C_S32ZE_
1139 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1140 #endif
1141 }
1142 }
1143
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20(void)1144 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20(void)
1145 {
1146 uint32 msr;
1147 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1148
1149 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_20[u32CoreId])
1150 {
1151 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1152 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1153 #else
1154 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1155 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1156 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1157 {
1158 OsIf_SuspendAllInterrupts();
1159 #ifdef _ARM_DS5_C_S32ZE_
1160 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1161 #endif
1162 }
1163 msr_ETH_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1164 }
1165 reentry_guard_ETH_EXCLUSIVE_AREA_20[u32CoreId]++;
1166 }
1167
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20(void)1168 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_20(void)
1169 {
1170 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1171
1172 reentry_guard_ETH_EXCLUSIVE_AREA_20[u32CoreId]--;
1173 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1174 {
1175 OsIf_ResumeAllInterrupts();
1176 #ifdef _ARM_DS5_C_S32ZE_
1177 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1178 #endif
1179 }
1180 }
1181
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21(void)1182 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21(void)
1183 {
1184 uint32 msr;
1185 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1186
1187 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_21[u32CoreId])
1188 {
1189 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1190 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1191 #else
1192 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1193 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1194 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1195 {
1196 OsIf_SuspendAllInterrupts();
1197 #ifdef _ARM_DS5_C_S32ZE_
1198 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1199 #endif
1200 }
1201 msr_ETH_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1202 }
1203 reentry_guard_ETH_EXCLUSIVE_AREA_21[u32CoreId]++;
1204 }
1205
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21(void)1206 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_21(void)
1207 {
1208 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1209
1210 reentry_guard_ETH_EXCLUSIVE_AREA_21[u32CoreId]--;
1211 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1212 {
1213 OsIf_ResumeAllInterrupts();
1214 #ifdef _ARM_DS5_C_S32ZE_
1215 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1216 #endif
1217 }
1218 }
1219
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22(void)1220 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22(void)
1221 {
1222 uint32 msr;
1223 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1224
1225 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_22[u32CoreId])
1226 {
1227 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1228 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1229 #else
1230 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1231 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1232 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1233 {
1234 OsIf_SuspendAllInterrupts();
1235 #ifdef _ARM_DS5_C_S32ZE_
1236 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1237 #endif
1238 }
1239 msr_ETH_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1240 }
1241 reentry_guard_ETH_EXCLUSIVE_AREA_22[u32CoreId]++;
1242 }
1243
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22(void)1244 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_22(void)
1245 {
1246 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1247
1248 reentry_guard_ETH_EXCLUSIVE_AREA_22[u32CoreId]--;
1249 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1250 {
1251 OsIf_ResumeAllInterrupts();
1252 #ifdef _ARM_DS5_C_S32ZE_
1253 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1254 #endif
1255 }
1256 }
1257
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23(void)1258 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23(void)
1259 {
1260 uint32 msr;
1261 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1262
1263 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_23[u32CoreId])
1264 {
1265 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1266 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1267 #else
1268 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1269 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1270 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1271 {
1272 OsIf_SuspendAllInterrupts();
1273 #ifdef _ARM_DS5_C_S32ZE_
1274 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1275 #endif
1276 }
1277 msr_ETH_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1278 }
1279 reentry_guard_ETH_EXCLUSIVE_AREA_23[u32CoreId]++;
1280 }
1281
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23(void)1282 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_23(void)
1283 {
1284 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1285
1286 reentry_guard_ETH_EXCLUSIVE_AREA_23[u32CoreId]--;
1287 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1288 {
1289 OsIf_ResumeAllInterrupts();
1290 #ifdef _ARM_DS5_C_S32ZE_
1291 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1292 #endif
1293 }
1294 }
1295
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24(void)1296 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24(void)
1297 {
1298 uint32 msr;
1299 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1300
1301 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_24[u32CoreId])
1302 {
1303 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1304 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1305 #else
1306 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1307 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1308 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1309 {
1310 OsIf_SuspendAllInterrupts();
1311 #ifdef _ARM_DS5_C_S32ZE_
1312 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1313 #endif
1314 }
1315 msr_ETH_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1316 }
1317 reentry_guard_ETH_EXCLUSIVE_AREA_24[u32CoreId]++;
1318 }
1319
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24(void)1320 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_24(void)
1321 {
1322 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1323
1324 reentry_guard_ETH_EXCLUSIVE_AREA_24[u32CoreId]--;
1325 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1326 {
1327 OsIf_ResumeAllInterrupts();
1328 #ifdef _ARM_DS5_C_S32ZE_
1329 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1330 #endif
1331 }
1332 }
1333
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25(void)1334 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25(void)
1335 {
1336 uint32 msr;
1337 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1338
1339 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_25[u32CoreId])
1340 {
1341 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1342 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1343 #else
1344 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1345 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1346 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1347 {
1348 OsIf_SuspendAllInterrupts();
1349 #ifdef _ARM_DS5_C_S32ZE_
1350 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1351 #endif
1352 }
1353 msr_ETH_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1354 }
1355 reentry_guard_ETH_EXCLUSIVE_AREA_25[u32CoreId]++;
1356 }
1357
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25(void)1358 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_25(void)
1359 {
1360 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1361
1362 reentry_guard_ETH_EXCLUSIVE_AREA_25[u32CoreId]--;
1363 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1364 {
1365 OsIf_ResumeAllInterrupts();
1366 #ifdef _ARM_DS5_C_S32ZE_
1367 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1368 #endif
1369 }
1370 }
1371
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26(void)1372 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26(void)
1373 {
1374 uint32 msr;
1375 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1376
1377 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_26[u32CoreId])
1378 {
1379 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1380 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1381 #else
1382 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1383 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1384 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1385 {
1386 OsIf_SuspendAllInterrupts();
1387 #ifdef _ARM_DS5_C_S32ZE_
1388 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1389 #endif
1390 }
1391 msr_ETH_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1392 }
1393 reentry_guard_ETH_EXCLUSIVE_AREA_26[u32CoreId]++;
1394 }
1395
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26(void)1396 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_26(void)
1397 {
1398 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1399
1400 reentry_guard_ETH_EXCLUSIVE_AREA_26[u32CoreId]--;
1401 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1402 {
1403 OsIf_ResumeAllInterrupts();
1404 #ifdef _ARM_DS5_C_S32ZE_
1405 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1406 #endif
1407 }
1408 }
1409
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27(void)1410 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27(void)
1411 {
1412 uint32 msr;
1413 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1414
1415 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_27[u32CoreId])
1416 {
1417 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1418 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1419 #else
1420 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1421 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1422 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1423 {
1424 OsIf_SuspendAllInterrupts();
1425 #ifdef _ARM_DS5_C_S32ZE_
1426 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1427 #endif
1428 }
1429 msr_ETH_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1430 }
1431 reentry_guard_ETH_EXCLUSIVE_AREA_27[u32CoreId]++;
1432 }
1433
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27(void)1434 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_27(void)
1435 {
1436 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1437
1438 reentry_guard_ETH_EXCLUSIVE_AREA_27[u32CoreId]--;
1439 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1440 {
1441 OsIf_ResumeAllInterrupts();
1442 #ifdef _ARM_DS5_C_S32ZE_
1443 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1444 #endif
1445 }
1446 }
1447
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28(void)1448 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28(void)
1449 {
1450 uint32 msr;
1451 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1452
1453 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_28[u32CoreId])
1454 {
1455 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1456 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1457 #else
1458 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1459 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1460 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1461 {
1462 OsIf_SuspendAllInterrupts();
1463 #ifdef _ARM_DS5_C_S32ZE_
1464 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1465 #endif
1466 }
1467 msr_ETH_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1468 }
1469 reentry_guard_ETH_EXCLUSIVE_AREA_28[u32CoreId]++;
1470 }
1471
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28(void)1472 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_28(void)
1473 {
1474 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1475
1476 reentry_guard_ETH_EXCLUSIVE_AREA_28[u32CoreId]--;
1477 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1478 {
1479 OsIf_ResumeAllInterrupts();
1480 #ifdef _ARM_DS5_C_S32ZE_
1481 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1482 #endif
1483 }
1484 }
1485
SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29(void)1486 void SchM_Enter_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29(void)
1487 {
1488 uint32 msr;
1489 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1490
1491 if(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_29[u32CoreId])
1492 {
1493 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1494 msr = OsIf_Trusted_Call_Return(Eth_43_NETC_schm_read_msr);
1495 #else
1496 msr = Eth_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1497 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1498 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1499 {
1500 OsIf_SuspendAllInterrupts();
1501 #ifdef _ARM_DS5_C_S32ZE_
1502 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1503 #endif
1504 }
1505 msr_ETH_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1506 }
1507 reentry_guard_ETH_EXCLUSIVE_AREA_29[u32CoreId]++;
1508 }
1509
SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29(void)1510 void SchM_Exit_Eth_43_NETC_ETH_EXCLUSIVE_AREA_29(void)
1511 {
1512 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1513
1514 reentry_guard_ETH_EXCLUSIVE_AREA_29[u32CoreId]--;
1515 if ((ISR_ON(msr_ETH_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1516 {
1517 OsIf_ResumeAllInterrupts();
1518 #ifdef _ARM_DS5_C_S32ZE_
1519 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1520 #endif
1521 }
1522 }
1523
1524
1525 #ifdef MCAL_TESTING_ENVIRONMENT
1526 /**
1527 @brief This function checks that all entered exclusive areas were also exited.
1528 @details This function checks that all entered exclusive areas were also exited. The check
1529 is done by verifying that all reentry_guard_* static variables are back to the
1530 zero value.
1531
1532 @param[in] void No input parameters
1533 @return void This function does not return a value. Test asserts are used instead.
1534
1535 @pre None
1536 @post None
1537
1538 @remarks Covers
1539 @remarks Implements
1540 */
SchM_Check_eth_43_netc(void)1541 void SchM_Check_eth_43_netc(void)
1542 {
1543 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1544
1545 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_00[u32CoreId]);
1546 reentry_guard_ETH_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_00 for the next test in the suite*/
1547
1548 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_01[u32CoreId]);
1549 reentry_guard_ETH_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_01 for the next test in the suite*/
1550
1551 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_02[u32CoreId]);
1552 reentry_guard_ETH_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_02 for the next test in the suite*/
1553
1554 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_03[u32CoreId]);
1555 reentry_guard_ETH_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_03 for the next test in the suite*/
1556
1557 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_04[u32CoreId]);
1558 reentry_guard_ETH_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_04 for the next test in the suite*/
1559
1560 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_05[u32CoreId]);
1561 reentry_guard_ETH_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_05 for the next test in the suite*/
1562
1563 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_07[u32CoreId]);
1564 reentry_guard_ETH_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_07 for the next test in the suite*/
1565
1566 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_08[u32CoreId]);
1567 reentry_guard_ETH_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_08 for the next test in the suite*/
1568
1569 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_09[u32CoreId]);
1570 reentry_guard_ETH_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_09 for the next test in the suite*/
1571
1572 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_10[u32CoreId]);
1573 reentry_guard_ETH_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_10 for the next test in the suite*/
1574
1575 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_11[u32CoreId]);
1576 reentry_guard_ETH_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_11 for the next test in the suite*/
1577
1578 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_12[u32CoreId]);
1579 reentry_guard_ETH_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_12 for the next test in the suite*/
1580
1581 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_13[u32CoreId]);
1582 reentry_guard_ETH_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_13 for the next test in the suite*/
1583
1584 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_14[u32CoreId]);
1585 reentry_guard_ETH_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_14 for the next test in the suite*/
1586
1587 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_15[u32CoreId]);
1588 reentry_guard_ETH_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_15 for the next test in the suite*/
1589
1590 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_16[u32CoreId]);
1591 reentry_guard_ETH_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_16 for the next test in the suite*/
1592
1593 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_17[u32CoreId]);
1594 reentry_guard_ETH_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_17 for the next test in the suite*/
1595
1596 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_18[u32CoreId]);
1597 reentry_guard_ETH_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_18 for the next test in the suite*/
1598
1599 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_19[u32CoreId]);
1600 reentry_guard_ETH_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_19 for the next test in the suite*/
1601
1602 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_20[u32CoreId]);
1603 reentry_guard_ETH_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_20 for the next test in the suite*/
1604
1605 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_21[u32CoreId]);
1606 reentry_guard_ETH_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_21 for the next test in the suite*/
1607
1608 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_22[u32CoreId]);
1609 reentry_guard_ETH_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_22 for the next test in the suite*/
1610
1611 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_23[u32CoreId]);
1612 reentry_guard_ETH_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_23 for the next test in the suite*/
1613
1614 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_24[u32CoreId]);
1615 reentry_guard_ETH_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_24 for the next test in the suite*/
1616
1617 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_25[u32CoreId]);
1618 reentry_guard_ETH_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_25 for the next test in the suite*/
1619
1620 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_26[u32CoreId]);
1621 reentry_guard_ETH_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_26 for the next test in the suite*/
1622
1623 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_27[u32CoreId]);
1624 reentry_guard_ETH_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_27 for the next test in the suite*/
1625
1626 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_28[u32CoreId]);
1627 reentry_guard_ETH_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_28 for the next test in the suite*/
1628
1629 EU_ASSERT(0UL == reentry_guard_ETH_EXCLUSIVE_AREA_29[u32CoreId]);
1630 reentry_guard_ETH_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_ETH_EXCLUSIVE_AREA_29 for the next test in the suite*/
1631
1632
1633 }
1634 #endif /*MCAL_TESTING_ENVIRONMENT*/
1635
1636 #define RTE_STOP_SEC_CODE
1637 #include "Rte_MemMap.h"
1638
1639 #ifdef __cplusplus
1640 }
1641 #endif
1642
1643 /** @} */
1644
