1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_EthSwt_43_NETC.c
9 * @version 2.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_EthSwt_43_NETC.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_ETHSWT_43_NETC_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_ETHSWT_43_NETC_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_ETHSWT_43_NETC_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_ETHSWT_43_NETC_SW_MAJOR_VERSION_C 2
44 #define SCHM_ETHSWT_43_NETC_SW_MINOR_VERSION_C 0
45 #define SCHM_ETHSWT_43_NETC_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_00) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_01) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_02) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_03) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_04) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_05) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_06) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_07) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_08) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_09) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_10) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_10) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_10[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_11) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_12) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_12) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_12[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_13) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_13) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_13[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_14) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_14) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_14[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_15) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_16) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_17) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_18) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_19) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_20) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_21) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_22) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_23) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_24) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_25) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_26) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_27) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_28) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_29) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_30) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_31) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_32) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_32) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_33) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_33) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_34) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_34) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_34[NUMBER_OF_CORES];
172 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_35) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
173 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_35) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_35[NUMBER_OF_CORES];
174 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_36) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
175 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_36) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_36[NUMBER_OF_CORES];
176 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_37) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
177 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_37) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_37[NUMBER_OF_CORES];
178 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_38) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
179 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_38) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_38[NUMBER_OF_CORES];
180 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_39) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
181 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_39) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_39[NUMBER_OF_CORES];
182 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_40) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
183 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_40) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_40[NUMBER_OF_CORES];
184 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_41) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
185 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_41) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_41[NUMBER_OF_CORES];
186 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_42) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
187 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_42) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_42[NUMBER_OF_CORES];
188 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_43) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
189 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_43) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_43[NUMBER_OF_CORES];
190 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_44) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
191 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_44) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
192 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_45) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
193 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_45) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
194 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_46) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
195 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_46) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
196 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_47) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
197 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_47) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
198 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_48) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
199 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_48) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
200 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_49) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
201 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_49) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
202 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_50) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
203 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_50) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
204 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_51) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
205 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_51) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
206 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_52) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
207 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_52) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
208 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_53) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
209 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_53) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
210 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_54) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
211 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_54) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_54[NUMBER_OF_CORES];
212 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_55) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
213 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_55) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_55[NUMBER_OF_CORES];
214 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_56) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
215 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_56) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_56[NUMBER_OF_CORES];
216 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_57) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
217 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_57) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
218 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_58) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
219 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_58) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
220 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_59) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
221 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_59) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
222 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_60) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
223 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_60) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_60[NUMBER_OF_CORES];
224 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_61) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
225 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_61) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_61[NUMBER_OF_CORES];
226 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_62) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
227 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_62) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_62[NUMBER_OF_CORES];
228 VAR_SEC_NOCACHE(msr_ETHSWT_EXCLUSIVE_AREA_63) static volatile uint32 msr_ETHSWT_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
229 VAR_SEC_NOCACHE(reentry_guard_ETHSWT_EXCLUSIVE_AREA_63) static volatile uint32 reentry_guard_ETHSWT_EXCLUSIVE_AREA_63[NUMBER_OF_CORES];
230
231 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
232 #include "Rte_MemMap.h"
233 /*==================================================================================================
234 * GLOBAL CONSTANTS
235 ==================================================================================================*/
236
237
238 /*==================================================================================================
239 * GLOBAL VARIABLES
240 ==================================================================================================*/
241
242 /*==================================================================================================
243 * LOCAL FUNCTION PROTOTYPES
244 ==================================================================================================*/
245
246 #ifndef _COSMIC_C_S32ZE_
247 /*================================================================================================*/
248 /**
249 * @brief This function returns the MSR register value (32 bits).
250 * @details This function returns the MSR register value (32 bits).
251 *
252 * @param[in] void No input parameters
253 * @return uint32 msr This function returns the MSR register value (32 bits).
254 *
255 * @pre None
256 * @post None
257 *
258 */
259 uint32 EthSwt_43_NETC_schm_read_msr(void);
260 #endif /*ifndef _COSMIC_C_S32ZE_*/
261 /*==================================================================================================
262 * LOCAL FUNCTIONS
263 ==================================================================================================*/
264 #define RTE_START_SEC_CODE
265 #include "Rte_MemMap.h"
266
267 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
268 /*================================================================================================*/
269 /**
270 * @brief This macro returns the MSR register value (32 bits).
271 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
272 *
273 * @pre None
274 * @post None
275 *
276 */
277 #ifdef MCAL_PLATFORM_ARM
278 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
EthSwt_43_NETC_schm_read_msr(void)279 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
280 {
281 mrs x0, S3_3_c4_c2_1
282 }
283 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
EthSwt_43_NETC_schm_read_msr(void)284 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
285 {
286 mrs r0, CPSR
287 }
288 #else
EthSwt_43_NETC_schm_read_msr(void)289 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
290 {
291 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
292 mrs r0, BASEPRI
293 #else
294 mrs r0, PRIMASK
295 #endif
296 }
297 #endif
298 #else
299 #ifdef MCAL_PLATFORM_S12
EthSwt_43_NETC_schm_read_msr(void)300 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
301 {
302 tfr ccr, d6
303 }
304 #else
EthSwt_43_NETC_schm_read_msr(void)305 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
306 {
307 mfmsr r3
308 }
309 #endif
310 #endif
311 #endif /*#ifdef GHS||CW*/
312
313 #ifdef _DIABDATA_C_S32ZE_
314 /**
315 * @brief This function returns the MSR register value (32 bits).
316 * @details This function returns the MSR register value (32 bits).
317 *
318 * @param[in] void No input parameters
319 * @return uint32 msr This function returns the MSR register value (32 bits).
320 *
321 * @pre None
322 * @post None
323 *
324 */
325 #ifdef MCAL_PLATFORM_ARM
EthSwt_43_NETC_schm_read_msr(void)326 uint32 EthSwt_43_NETC_schm_read_msr(void)
327 {
328 register uint32 reg_tmp;
329 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
330 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
331 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
332 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
333 #else
334 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
335 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
336 #else
337 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
338 #endif
339 #endif
340 return (uint32)reg_tmp;
341 }
342 #else
EthSwt_43_NETC_schm_read_msr(void)343 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
344 {
345 mfmsr r3
346 }
347 #endif /* MCAL_PLATFORM_ARM */
348
349 #endif /* _DIABDATA_C_S32ZE_*/
350
351 #ifdef _COSMIC_C_S32ZE_
352 /*================================================================================================*/
353 /**
354 * @brief This function returns the MSR register value (32 bits).
355 * @details This function returns the MSR register value (32 bits).
356 *
357 * @param[in] void No input parameters
358 * @return uint32 msr This function returns the MSR register value (32 bits).
359 *
360 * @pre None
361 * @post None
362 *
363 */
364
365 #ifdef MCAL_PLATFORM_S12
366 #define EthSwt_43_NETC_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
367 #else
368 #define EthSwt_43_NETC_schm_read_msr() ASM_KEYWORD("mfmsr r3")
369 #endif
370
371 #endif /*Cosmic compiler only*/
372
373
374 #ifdef _HITECH_C_S32ZE_
375 /*================================================================================================*/
376 /**
377 * @brief This function returns the MSR register value (32 bits).
378 * @details This function returns the MSR register value (32 bits).
379 *
380 * @param[in] void No input parameters
381 * @return uint32 msr This function returns the MSR register value (32 bits).
382 *
383 * @pre None
384 * @post None
385 *
386 */
EthSwt_43_NETC_schm_read_msr(void)387 uint32 EthSwt_43_NETC_schm_read_msr(void)
388 {
389 uint32 result;
390 __asm volatile("mfmsr %0" : "=r" (result) :);
391 return result;
392 }
393
394 #endif /*HighTec compiler only*/
395 /*================================================================================================*/
396 #ifdef _GCC_C_S32ZE_
397 /**
398 * @brief This function returns the MSR register value (32 bits).
399 * @details This function returns the MSR register value (32 bits).
400 *
401 * @param[in] void No input parameters
402 * @return uint32 msr This function returns the MSR register value (32 bits).
403 *
404 * @pre None
405 * @post None
406 *
407 */
EthSwt_43_NETC_schm_read_msr(void)408 uint32 EthSwt_43_NETC_schm_read_msr(void)
409 {
410 register uint32 reg_tmp;
411 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
412 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
413 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
414 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
415 #else
416 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
417 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
418 #else
419 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
420 #endif
421 #endif
422 return (uint32)reg_tmp;
423 }
424 #endif /* _GCC_C_S32ZE_*/
425 /*================================================================================================*/
426
427 #ifdef _ARM_DS5_C_S32ZE_
428 /**
429 * @brief This function returns the MSR register value (32 bits).
430 * @details This function returns the MSR register value (32 bits).
431 *
432 * @param[in] void No input parameters
433 * @return uint32 msr This function returns the MSR register value (32 bits).
434 *
435 * @pre None
436 * @post None
437 *
438 */
EthSwt_43_NETC_schm_read_msr(void)439 uint32 EthSwt_43_NETC_schm_read_msr(void)
440 {
441 register uint32 reg_tmp;
442 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
443 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
444 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
445 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
446 #else
447 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
448 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
449 #else
450 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
451 #endif
452 #endif
453 return (uint32)reg_tmp;
454 }
455 #endif /* _ARM_DS5_C_S32ZE_ */
456
457 #ifdef _IAR_C_S32ZE_
458 /**
459 * @brief This function returns the MSR register value (32 bits).
460 * @details This function returns the MSR register value (32 bits).
461 *
462 * @param[in] void No input parameters
463 * @return uint32 msr This function returns the MSR register value (32 bits).
464 *
465 * @pre None
466 * @post None
467 *
468 */
EthSwt_43_NETC_schm_read_msr(void)469 uint32 EthSwt_43_NETC_schm_read_msr(void)
470 {
471 register uint32 reg_tmp;
472
473 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
474 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
475 #else
476 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
477 #endif
478
479 return (uint32)reg_tmp;
480 }
481 #endif /* _IAR_C_S32ZE_ */
482
483 #define RTE_STOP_SEC_CODE
484 #include "Rte_MemMap.h"
485
486 /*==================================================================================================
487 * GLOBAL FUNCTIONS
488 ==================================================================================================*/
489 #define RTE_START_SEC_CODE
490 #include "Rte_MemMap.h"
491
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_00(void)492 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_00(void)
493 {
494 uint32 msr;
495 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
496
497 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId])
498 {
499 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
500 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
501 #else
502 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
503 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
504 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
505 {
506 OsIf_SuspendAllInterrupts();
507 #ifdef _ARM_DS5_C_S32ZE_
508 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
509 #endif
510 }
511 msr_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId] = msr;
512 }
513 reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId]++;
514 }
515
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_00(void)516 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_00(void)
517 {
518 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
519
520 reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId]--;
521 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
522 {
523 OsIf_ResumeAllInterrupts();
524 #ifdef _ARM_DS5_C_S32ZE_
525 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
526 #endif
527 }
528 }
529
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_01(void)530 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_01(void)
531 {
532 uint32 msr;
533 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
534
535 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId])
536 {
537 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
538 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
539 #else
540 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
541 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
542 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
543 {
544 OsIf_SuspendAllInterrupts();
545 #ifdef _ARM_DS5_C_S32ZE_
546 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
547 #endif
548 }
549 msr_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId] = msr;
550 }
551 reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId]++;
552 }
553
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_01(void)554 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_01(void)
555 {
556 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
557
558 reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId]--;
559 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
560 {
561 OsIf_ResumeAllInterrupts();
562 #ifdef _ARM_DS5_C_S32ZE_
563 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
564 #endif
565 }
566 }
567
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_02(void)568 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_02(void)
569 {
570 uint32 msr;
571 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
572
573 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId])
574 {
575 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
576 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
577 #else
578 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
579 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
580 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
581 {
582 OsIf_SuspendAllInterrupts();
583 #ifdef _ARM_DS5_C_S32ZE_
584 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
585 #endif
586 }
587 msr_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId] = msr;
588 }
589 reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId]++;
590 }
591
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_02(void)592 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_02(void)
593 {
594 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
595
596 reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId]--;
597 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
598 {
599 OsIf_ResumeAllInterrupts();
600 #ifdef _ARM_DS5_C_S32ZE_
601 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
602 #endif
603 }
604 }
605
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_03(void)606 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_03(void)
607 {
608 uint32 msr;
609 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
610
611 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId])
612 {
613 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
614 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
615 #else
616 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
617 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
618 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
619 {
620 OsIf_SuspendAllInterrupts();
621 #ifdef _ARM_DS5_C_S32ZE_
622 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
623 #endif
624 }
625 msr_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId] = msr;
626 }
627 reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId]++;
628 }
629
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_03(void)630 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_03(void)
631 {
632 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
633
634 reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId]--;
635 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
636 {
637 OsIf_ResumeAllInterrupts();
638 #ifdef _ARM_DS5_C_S32ZE_
639 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
640 #endif
641 }
642 }
643
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_04(void)644 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_04(void)
645 {
646 uint32 msr;
647 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
648
649 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId])
650 {
651 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
652 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
653 #else
654 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
655 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
656 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
657 {
658 OsIf_SuspendAllInterrupts();
659 #ifdef _ARM_DS5_C_S32ZE_
660 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
661 #endif
662 }
663 msr_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId] = msr;
664 }
665 reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId]++;
666 }
667
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_04(void)668 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_04(void)
669 {
670 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
671
672 reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId]--;
673 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
674 {
675 OsIf_ResumeAllInterrupts();
676 #ifdef _ARM_DS5_C_S32ZE_
677 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
678 #endif
679 }
680 }
681
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_05(void)682 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_05(void)
683 {
684 uint32 msr;
685 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
686
687 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId])
688 {
689 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
690 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
691 #else
692 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
693 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
694 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
695 {
696 OsIf_SuspendAllInterrupts();
697 #ifdef _ARM_DS5_C_S32ZE_
698 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
699 #endif
700 }
701 msr_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId] = msr;
702 }
703 reentry_guard_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId]++;
704 }
705
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_05(void)706 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_05(void)
707 {
708 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
709
710 reentry_guard_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId]--;
711 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
712 {
713 OsIf_ResumeAllInterrupts();
714 #ifdef _ARM_DS5_C_S32ZE_
715 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
716 #endif
717 }
718 }
719
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_06(void)720 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_06(void)
721 {
722 uint32 msr;
723 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
724
725 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId])
726 {
727 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
728 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
729 #else
730 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
731 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
732 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
733 {
734 OsIf_SuspendAllInterrupts();
735 #ifdef _ARM_DS5_C_S32ZE_
736 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
737 #endif
738 }
739 msr_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId] = msr;
740 }
741 reentry_guard_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId]++;
742 }
743
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_06(void)744 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_06(void)
745 {
746 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
747
748 reentry_guard_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId]--;
749 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
750 {
751 OsIf_ResumeAllInterrupts();
752 #ifdef _ARM_DS5_C_S32ZE_
753 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
754 #endif
755 }
756 }
757
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_07(void)758 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_07(void)
759 {
760 uint32 msr;
761 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
762
763 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId])
764 {
765 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
766 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
767 #else
768 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
769 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
770 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
771 {
772 OsIf_SuspendAllInterrupts();
773 #ifdef _ARM_DS5_C_S32ZE_
774 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
775 #endif
776 }
777 msr_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId] = msr;
778 }
779 reentry_guard_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId]++;
780 }
781
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_07(void)782 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_07(void)
783 {
784 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
785
786 reentry_guard_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId]--;
787 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
788 {
789 OsIf_ResumeAllInterrupts();
790 #ifdef _ARM_DS5_C_S32ZE_
791 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
792 #endif
793 }
794 }
795
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_08(void)796 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_08(void)
797 {
798 uint32 msr;
799 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
800
801 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId])
802 {
803 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
804 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
805 #else
806 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
807 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
808 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
809 {
810 OsIf_SuspendAllInterrupts();
811 #ifdef _ARM_DS5_C_S32ZE_
812 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
813 #endif
814 }
815 msr_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId] = msr;
816 }
817 reentry_guard_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId]++;
818 }
819
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_08(void)820 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_08(void)
821 {
822 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
823
824 reentry_guard_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId]--;
825 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
826 {
827 OsIf_ResumeAllInterrupts();
828 #ifdef _ARM_DS5_C_S32ZE_
829 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
830 #endif
831 }
832 }
833
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_09(void)834 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_09(void)
835 {
836 uint32 msr;
837 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
838
839 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId])
840 {
841 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
842 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
843 #else
844 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
845 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
846 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
847 {
848 OsIf_SuspendAllInterrupts();
849 #ifdef _ARM_DS5_C_S32ZE_
850 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
851 #endif
852 }
853 msr_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId] = msr;
854 }
855 reentry_guard_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId]++;
856 }
857
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_09(void)858 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_09(void)
859 {
860 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
861
862 reentry_guard_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId]--;
863 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
864 {
865 OsIf_ResumeAllInterrupts();
866 #ifdef _ARM_DS5_C_S32ZE_
867 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
868 #endif
869 }
870 }
871
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_10(void)872 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_10(void)
873 {
874 uint32 msr;
875 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
876
877 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId])
878 {
879 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
880 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
881 #else
882 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
883 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
884 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
885 {
886 OsIf_SuspendAllInterrupts();
887 #ifdef _ARM_DS5_C_S32ZE_
888 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
889 #endif
890 }
891 msr_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId] = msr;
892 }
893 reentry_guard_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId]++;
894 }
895
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_10(void)896 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_10(void)
897 {
898 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
899
900 reentry_guard_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId]--;
901 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId])) /*if interrupts were enabled*/
902 {
903 OsIf_ResumeAllInterrupts();
904 #ifdef _ARM_DS5_C_S32ZE_
905 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
906 #endif
907 }
908 }
909
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_11(void)910 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_11(void)
911 {
912 uint32 msr;
913 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
914
915 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId])
916 {
917 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
918 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
919 #else
920 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
921 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
922 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
923 {
924 OsIf_SuspendAllInterrupts();
925 #ifdef _ARM_DS5_C_S32ZE_
926 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
927 #endif
928 }
929 msr_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId] = msr;
930 }
931 reentry_guard_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId]++;
932 }
933
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_11(void)934 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_11(void)
935 {
936 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
937
938 reentry_guard_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId]--;
939 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
940 {
941 OsIf_ResumeAllInterrupts();
942 #ifdef _ARM_DS5_C_S32ZE_
943 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
944 #endif
945 }
946 }
947
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_12(void)948 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_12(void)
949 {
950 uint32 msr;
951 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
952
953 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId])
954 {
955 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
956 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
957 #else
958 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
959 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
960 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
961 {
962 OsIf_SuspendAllInterrupts();
963 #ifdef _ARM_DS5_C_S32ZE_
964 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
965 #endif
966 }
967 msr_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId] = msr;
968 }
969 reentry_guard_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId]++;
970 }
971
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_12(void)972 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_12(void)
973 {
974 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
975
976 reentry_guard_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId]--;
977 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId])) /*if interrupts were enabled*/
978 {
979 OsIf_ResumeAllInterrupts();
980 #ifdef _ARM_DS5_C_S32ZE_
981 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
982 #endif
983 }
984 }
985
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_13(void)986 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_13(void)
987 {
988 uint32 msr;
989 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
990
991 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId])
992 {
993 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
994 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
995 #else
996 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
997 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
998 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
999 {
1000 OsIf_SuspendAllInterrupts();
1001 #ifdef _ARM_DS5_C_S32ZE_
1002 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1003 #endif
1004 }
1005 msr_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId] = msr;
1006 }
1007 reentry_guard_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId]++;
1008 }
1009
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_13(void)1010 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_13(void)
1011 {
1012 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1013
1014 reentry_guard_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId]--;
1015 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId])) /*if interrupts were enabled*/
1016 {
1017 OsIf_ResumeAllInterrupts();
1018 #ifdef _ARM_DS5_C_S32ZE_
1019 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1020 #endif
1021 }
1022 }
1023
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_14(void)1024 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_14(void)
1025 {
1026 uint32 msr;
1027 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1028
1029 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId])
1030 {
1031 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1032 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1033 #else
1034 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1035 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1036 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1037 {
1038 OsIf_SuspendAllInterrupts();
1039 #ifdef _ARM_DS5_C_S32ZE_
1040 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1041 #endif
1042 }
1043 msr_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId] = msr;
1044 }
1045 reentry_guard_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId]++;
1046 }
1047
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_14(void)1048 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_14(void)
1049 {
1050 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1051
1052 reentry_guard_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId]--;
1053 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId])) /*if interrupts were enabled*/
1054 {
1055 OsIf_ResumeAllInterrupts();
1056 #ifdef _ARM_DS5_C_S32ZE_
1057 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1058 #endif
1059 }
1060 }
1061
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_15(void)1062 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_15(void)
1063 {
1064 uint32 msr;
1065 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1066
1067 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId])
1068 {
1069 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1070 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1071 #else
1072 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1073 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1074 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1075 {
1076 OsIf_SuspendAllInterrupts();
1077 #ifdef _ARM_DS5_C_S32ZE_
1078 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1079 #endif
1080 }
1081 msr_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId] = msr;
1082 }
1083 reentry_guard_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId]++;
1084 }
1085
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_15(void)1086 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_15(void)
1087 {
1088 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1089
1090 reentry_guard_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId]--;
1091 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
1092 {
1093 OsIf_ResumeAllInterrupts();
1094 #ifdef _ARM_DS5_C_S32ZE_
1095 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1096 #endif
1097 }
1098 }
1099
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_16(void)1100 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_16(void)
1101 {
1102 uint32 msr;
1103 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1104
1105 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId])
1106 {
1107 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1108 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1109 #else
1110 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1111 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1112 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1113 {
1114 OsIf_SuspendAllInterrupts();
1115 #ifdef _ARM_DS5_C_S32ZE_
1116 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1117 #endif
1118 }
1119 msr_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId] = msr;
1120 }
1121 reentry_guard_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId]++;
1122 }
1123
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_16(void)1124 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_16(void)
1125 {
1126 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1127
1128 reentry_guard_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId]--;
1129 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
1130 {
1131 OsIf_ResumeAllInterrupts();
1132 #ifdef _ARM_DS5_C_S32ZE_
1133 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1134 #endif
1135 }
1136 }
1137
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_17(void)1138 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_17(void)
1139 {
1140 uint32 msr;
1141 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1142
1143 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId])
1144 {
1145 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1146 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1147 #else
1148 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1149 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1150 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1151 {
1152 OsIf_SuspendAllInterrupts();
1153 #ifdef _ARM_DS5_C_S32ZE_
1154 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1155 #endif
1156 }
1157 msr_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId] = msr;
1158 }
1159 reentry_guard_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId]++;
1160 }
1161
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_17(void)1162 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_17(void)
1163 {
1164 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1165
1166 reentry_guard_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId]--;
1167 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
1168 {
1169 OsIf_ResumeAllInterrupts();
1170 #ifdef _ARM_DS5_C_S32ZE_
1171 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1172 #endif
1173 }
1174 }
1175
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_18(void)1176 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_18(void)
1177 {
1178 uint32 msr;
1179 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1180
1181 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId])
1182 {
1183 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1184 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1185 #else
1186 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1187 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1188 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1189 {
1190 OsIf_SuspendAllInterrupts();
1191 #ifdef _ARM_DS5_C_S32ZE_
1192 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1193 #endif
1194 }
1195 msr_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1196 }
1197 reentry_guard_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId]++;
1198 }
1199
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_18(void)1200 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_18(void)
1201 {
1202 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1203
1204 reentry_guard_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId]--;
1205 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1206 {
1207 OsIf_ResumeAllInterrupts();
1208 #ifdef _ARM_DS5_C_S32ZE_
1209 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1210 #endif
1211 }
1212 }
1213
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_19(void)1214 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_19(void)
1215 {
1216 uint32 msr;
1217 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1218
1219 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId])
1220 {
1221 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1222 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1223 #else
1224 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1225 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1226 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1227 {
1228 OsIf_SuspendAllInterrupts();
1229 #ifdef _ARM_DS5_C_S32ZE_
1230 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1231 #endif
1232 }
1233 msr_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1234 }
1235 reentry_guard_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId]++;
1236 }
1237
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_19(void)1238 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_19(void)
1239 {
1240 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1241
1242 reentry_guard_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId]--;
1243 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1244 {
1245 OsIf_ResumeAllInterrupts();
1246 #ifdef _ARM_DS5_C_S32ZE_
1247 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1248 #endif
1249 }
1250 }
1251
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_20(void)1252 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_20(void)
1253 {
1254 uint32 msr;
1255 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1256
1257 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId])
1258 {
1259 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1260 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1261 #else
1262 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1263 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1264 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1265 {
1266 OsIf_SuspendAllInterrupts();
1267 #ifdef _ARM_DS5_C_S32ZE_
1268 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1269 #endif
1270 }
1271 msr_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1272 }
1273 reentry_guard_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId]++;
1274 }
1275
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_20(void)1276 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_20(void)
1277 {
1278 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1279
1280 reentry_guard_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId]--;
1281 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1282 {
1283 OsIf_ResumeAllInterrupts();
1284 #ifdef _ARM_DS5_C_S32ZE_
1285 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1286 #endif
1287 }
1288 }
1289
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_21(void)1290 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_21(void)
1291 {
1292 uint32 msr;
1293 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1294
1295 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId])
1296 {
1297 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1298 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1299 #else
1300 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1301 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1302 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1303 {
1304 OsIf_SuspendAllInterrupts();
1305 #ifdef _ARM_DS5_C_S32ZE_
1306 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1307 #endif
1308 }
1309 msr_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1310 }
1311 reentry_guard_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId]++;
1312 }
1313
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_21(void)1314 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_21(void)
1315 {
1316 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1317
1318 reentry_guard_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId]--;
1319 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1320 {
1321 OsIf_ResumeAllInterrupts();
1322 #ifdef _ARM_DS5_C_S32ZE_
1323 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1324 #endif
1325 }
1326 }
1327
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_22(void)1328 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_22(void)
1329 {
1330 uint32 msr;
1331 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1332
1333 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId])
1334 {
1335 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1336 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1337 #else
1338 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1339 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1340 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1341 {
1342 OsIf_SuspendAllInterrupts();
1343 #ifdef _ARM_DS5_C_S32ZE_
1344 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1345 #endif
1346 }
1347 msr_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1348 }
1349 reentry_guard_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId]++;
1350 }
1351
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_22(void)1352 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_22(void)
1353 {
1354 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1355
1356 reentry_guard_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId]--;
1357 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1358 {
1359 OsIf_ResumeAllInterrupts();
1360 #ifdef _ARM_DS5_C_S32ZE_
1361 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1362 #endif
1363 }
1364 }
1365
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_23(void)1366 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_23(void)
1367 {
1368 uint32 msr;
1369 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1370
1371 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId])
1372 {
1373 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1374 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1375 #else
1376 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1377 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1378 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1379 {
1380 OsIf_SuspendAllInterrupts();
1381 #ifdef _ARM_DS5_C_S32ZE_
1382 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1383 #endif
1384 }
1385 msr_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1386 }
1387 reentry_guard_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId]++;
1388 }
1389
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_23(void)1390 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_23(void)
1391 {
1392 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1393
1394 reentry_guard_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId]--;
1395 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1396 {
1397 OsIf_ResumeAllInterrupts();
1398 #ifdef _ARM_DS5_C_S32ZE_
1399 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1400 #endif
1401 }
1402 }
1403
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_24(void)1404 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_24(void)
1405 {
1406 uint32 msr;
1407 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1408
1409 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId])
1410 {
1411 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1412 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1413 #else
1414 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1415 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1416 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1417 {
1418 OsIf_SuspendAllInterrupts();
1419 #ifdef _ARM_DS5_C_S32ZE_
1420 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1421 #endif
1422 }
1423 msr_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1424 }
1425 reentry_guard_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId]++;
1426 }
1427
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_24(void)1428 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_24(void)
1429 {
1430 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1431
1432 reentry_guard_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId]--;
1433 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1434 {
1435 OsIf_ResumeAllInterrupts();
1436 #ifdef _ARM_DS5_C_S32ZE_
1437 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1438 #endif
1439 }
1440 }
1441
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_25(void)1442 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_25(void)
1443 {
1444 uint32 msr;
1445 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1446
1447 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId])
1448 {
1449 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1450 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1451 #else
1452 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1453 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1454 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1455 {
1456 OsIf_SuspendAllInterrupts();
1457 #ifdef _ARM_DS5_C_S32ZE_
1458 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1459 #endif
1460 }
1461 msr_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1462 }
1463 reentry_guard_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId]++;
1464 }
1465
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_25(void)1466 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_25(void)
1467 {
1468 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1469
1470 reentry_guard_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId]--;
1471 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1472 {
1473 OsIf_ResumeAllInterrupts();
1474 #ifdef _ARM_DS5_C_S32ZE_
1475 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1476 #endif
1477 }
1478 }
1479
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_26(void)1480 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_26(void)
1481 {
1482 uint32 msr;
1483 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1484
1485 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId])
1486 {
1487 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1488 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1489 #else
1490 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1491 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1492 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1493 {
1494 OsIf_SuspendAllInterrupts();
1495 #ifdef _ARM_DS5_C_S32ZE_
1496 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1497 #endif
1498 }
1499 msr_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1500 }
1501 reentry_guard_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId]++;
1502 }
1503
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_26(void)1504 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_26(void)
1505 {
1506 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1507
1508 reentry_guard_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId]--;
1509 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1510 {
1511 OsIf_ResumeAllInterrupts();
1512 #ifdef _ARM_DS5_C_S32ZE_
1513 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1514 #endif
1515 }
1516 }
1517
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_27(void)1518 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_27(void)
1519 {
1520 uint32 msr;
1521 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1522
1523 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId])
1524 {
1525 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1526 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1527 #else
1528 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1529 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1530 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1531 {
1532 OsIf_SuspendAllInterrupts();
1533 #ifdef _ARM_DS5_C_S32ZE_
1534 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1535 #endif
1536 }
1537 msr_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1538 }
1539 reentry_guard_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId]++;
1540 }
1541
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_27(void)1542 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_27(void)
1543 {
1544 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1545
1546 reentry_guard_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId]--;
1547 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1548 {
1549 OsIf_ResumeAllInterrupts();
1550 #ifdef _ARM_DS5_C_S32ZE_
1551 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1552 #endif
1553 }
1554 }
1555
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_28(void)1556 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_28(void)
1557 {
1558 uint32 msr;
1559 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1560
1561 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId])
1562 {
1563 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1564 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1565 #else
1566 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1567 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1568 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1569 {
1570 OsIf_SuspendAllInterrupts();
1571 #ifdef _ARM_DS5_C_S32ZE_
1572 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1573 #endif
1574 }
1575 msr_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1576 }
1577 reentry_guard_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId]++;
1578 }
1579
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_28(void)1580 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_28(void)
1581 {
1582 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1583
1584 reentry_guard_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId]--;
1585 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1586 {
1587 OsIf_ResumeAllInterrupts();
1588 #ifdef _ARM_DS5_C_S32ZE_
1589 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1590 #endif
1591 }
1592 }
1593
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_29(void)1594 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_29(void)
1595 {
1596 uint32 msr;
1597 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1598
1599 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId])
1600 {
1601 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1602 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1603 #else
1604 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1605 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1606 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1607 {
1608 OsIf_SuspendAllInterrupts();
1609 #ifdef _ARM_DS5_C_S32ZE_
1610 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1611 #endif
1612 }
1613 msr_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1614 }
1615 reentry_guard_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId]++;
1616 }
1617
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_29(void)1618 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_29(void)
1619 {
1620 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1621
1622 reentry_guard_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId]--;
1623 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1624 {
1625 OsIf_ResumeAllInterrupts();
1626 #ifdef _ARM_DS5_C_S32ZE_
1627 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1628 #endif
1629 }
1630 }
1631
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_30(void)1632 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_30(void)
1633 {
1634 uint32 msr;
1635 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1636
1637 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId])
1638 {
1639 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1640 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1641 #else
1642 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1643 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1644 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1645 {
1646 OsIf_SuspendAllInterrupts();
1647 #ifdef _ARM_DS5_C_S32ZE_
1648 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1649 #endif
1650 }
1651 msr_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1652 }
1653 reentry_guard_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId]++;
1654 }
1655
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_30(void)1656 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_30(void)
1657 {
1658 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1659
1660 reentry_guard_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId]--;
1661 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1662 {
1663 OsIf_ResumeAllInterrupts();
1664 #ifdef _ARM_DS5_C_S32ZE_
1665 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1666 #endif
1667 }
1668 }
1669
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_31(void)1670 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_31(void)
1671 {
1672 uint32 msr;
1673 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1674
1675 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId])
1676 {
1677 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1678 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1679 #else
1680 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1681 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1682 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1683 {
1684 OsIf_SuspendAllInterrupts();
1685 #ifdef _ARM_DS5_C_S32ZE_
1686 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1687 #endif
1688 }
1689 msr_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1690 }
1691 reentry_guard_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId]++;
1692 }
1693
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_31(void)1694 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_31(void)
1695 {
1696 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1697
1698 reentry_guard_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId]--;
1699 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1700 {
1701 OsIf_ResumeAllInterrupts();
1702 #ifdef _ARM_DS5_C_S32ZE_
1703 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1704 #endif
1705 }
1706 }
1707
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_32(void)1708 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_32(void)
1709 {
1710 uint32 msr;
1711 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1712
1713 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId])
1714 {
1715 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1716 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1717 #else
1718 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1719 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1720 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1721 {
1722 OsIf_SuspendAllInterrupts();
1723 #ifdef _ARM_DS5_C_S32ZE_
1724 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1725 #endif
1726 }
1727 msr_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId] = msr;
1728 }
1729 reentry_guard_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId]++;
1730 }
1731
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_32(void)1732 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_32(void)
1733 {
1734 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1735
1736 reentry_guard_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId]--;
1737 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId])) /*if interrupts were enabled*/
1738 {
1739 OsIf_ResumeAllInterrupts();
1740 #ifdef _ARM_DS5_C_S32ZE_
1741 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1742 #endif
1743 }
1744 }
1745
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_33(void)1746 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_33(void)
1747 {
1748 uint32 msr;
1749 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1750
1751 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId])
1752 {
1753 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1754 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1755 #else
1756 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1757 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1758 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1759 {
1760 OsIf_SuspendAllInterrupts();
1761 #ifdef _ARM_DS5_C_S32ZE_
1762 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1763 #endif
1764 }
1765 msr_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId] = msr;
1766 }
1767 reentry_guard_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId]++;
1768 }
1769
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_33(void)1770 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_33(void)
1771 {
1772 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1773
1774 reentry_guard_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId]--;
1775 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId])) /*if interrupts were enabled*/
1776 {
1777 OsIf_ResumeAllInterrupts();
1778 #ifdef _ARM_DS5_C_S32ZE_
1779 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1780 #endif
1781 }
1782 }
1783
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_34(void)1784 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_34(void)
1785 {
1786 uint32 msr;
1787 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1788
1789 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId])
1790 {
1791 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1792 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1793 #else
1794 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1795 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1796 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1797 {
1798 OsIf_SuspendAllInterrupts();
1799 #ifdef _ARM_DS5_C_S32ZE_
1800 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1801 #endif
1802 }
1803 msr_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId] = msr;
1804 }
1805 reentry_guard_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId]++;
1806 }
1807
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_34(void)1808 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_34(void)
1809 {
1810 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1811
1812 reentry_guard_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId]--;
1813 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId])) /*if interrupts were enabled*/
1814 {
1815 OsIf_ResumeAllInterrupts();
1816 #ifdef _ARM_DS5_C_S32ZE_
1817 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1818 #endif
1819 }
1820 }
1821
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_35(void)1822 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_35(void)
1823 {
1824 uint32 msr;
1825 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1826
1827 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId])
1828 {
1829 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1830 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1831 #else
1832 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1833 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1834 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1835 {
1836 OsIf_SuspendAllInterrupts();
1837 #ifdef _ARM_DS5_C_S32ZE_
1838 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1839 #endif
1840 }
1841 msr_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId] = msr;
1842 }
1843 reentry_guard_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId]++;
1844 }
1845
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_35(void)1846 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_35(void)
1847 {
1848 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1849
1850 reentry_guard_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId]--;
1851 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId])) /*if interrupts were enabled*/
1852 {
1853 OsIf_ResumeAllInterrupts();
1854 #ifdef _ARM_DS5_C_S32ZE_
1855 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1856 #endif
1857 }
1858 }
1859
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_36(void)1860 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_36(void)
1861 {
1862 uint32 msr;
1863 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1864
1865 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId])
1866 {
1867 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1868 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1869 #else
1870 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1871 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1872 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1873 {
1874 OsIf_SuspendAllInterrupts();
1875 #ifdef _ARM_DS5_C_S32ZE_
1876 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1877 #endif
1878 }
1879 msr_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId] = msr;
1880 }
1881 reentry_guard_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId]++;
1882 }
1883
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_36(void)1884 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_36(void)
1885 {
1886 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1887
1888 reentry_guard_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId]--;
1889 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId])) /*if interrupts were enabled*/
1890 {
1891 OsIf_ResumeAllInterrupts();
1892 #ifdef _ARM_DS5_C_S32ZE_
1893 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1894 #endif
1895 }
1896 }
1897
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_37(void)1898 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_37(void)
1899 {
1900 uint32 msr;
1901 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1902
1903 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId])
1904 {
1905 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1906 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1907 #else
1908 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1909 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1910 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1911 {
1912 OsIf_SuspendAllInterrupts();
1913 #ifdef _ARM_DS5_C_S32ZE_
1914 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1915 #endif
1916 }
1917 msr_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId] = msr;
1918 }
1919 reentry_guard_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId]++;
1920 }
1921
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_37(void)1922 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_37(void)
1923 {
1924 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1925
1926 reentry_guard_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId]--;
1927 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId])) /*if interrupts were enabled*/
1928 {
1929 OsIf_ResumeAllInterrupts();
1930 #ifdef _ARM_DS5_C_S32ZE_
1931 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1932 #endif
1933 }
1934 }
1935
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_38(void)1936 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_38(void)
1937 {
1938 uint32 msr;
1939 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1940
1941 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId])
1942 {
1943 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1944 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1945 #else
1946 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1947 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1948 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1949 {
1950 OsIf_SuspendAllInterrupts();
1951 #ifdef _ARM_DS5_C_S32ZE_
1952 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1953 #endif
1954 }
1955 msr_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId] = msr;
1956 }
1957 reentry_guard_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId]++;
1958 }
1959
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_38(void)1960 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_38(void)
1961 {
1962 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1963
1964 reentry_guard_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId]--;
1965 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId])) /*if interrupts were enabled*/
1966 {
1967 OsIf_ResumeAllInterrupts();
1968 #ifdef _ARM_DS5_C_S32ZE_
1969 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1970 #endif
1971 }
1972 }
1973
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_39(void)1974 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_39(void)
1975 {
1976 uint32 msr;
1977 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1978
1979 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId])
1980 {
1981 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1982 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
1983 #else
1984 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
1985 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1986 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1987 {
1988 OsIf_SuspendAllInterrupts();
1989 #ifdef _ARM_DS5_C_S32ZE_
1990 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1991 #endif
1992 }
1993 msr_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId] = msr;
1994 }
1995 reentry_guard_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId]++;
1996 }
1997
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_39(void)1998 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_39(void)
1999 {
2000 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2001
2002 reentry_guard_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId]--;
2003 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId])) /*if interrupts were enabled*/
2004 {
2005 OsIf_ResumeAllInterrupts();
2006 #ifdef _ARM_DS5_C_S32ZE_
2007 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2008 #endif
2009 }
2010 }
2011
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_40(void)2012 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_40(void)
2013 {
2014 uint32 msr;
2015 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2016
2017 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId])
2018 {
2019 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2020 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2021 #else
2022 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2023 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2024 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2025 {
2026 OsIf_SuspendAllInterrupts();
2027 #ifdef _ARM_DS5_C_S32ZE_
2028 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2029 #endif
2030 }
2031 msr_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId] = msr;
2032 }
2033 reentry_guard_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId]++;
2034 }
2035
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_40(void)2036 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_40(void)
2037 {
2038 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2039
2040 reentry_guard_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId]--;
2041 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId])) /*if interrupts were enabled*/
2042 {
2043 OsIf_ResumeAllInterrupts();
2044 #ifdef _ARM_DS5_C_S32ZE_
2045 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2046 #endif
2047 }
2048 }
2049
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_41(void)2050 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_41(void)
2051 {
2052 uint32 msr;
2053 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2054
2055 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId])
2056 {
2057 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2058 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2059 #else
2060 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2061 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2062 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2063 {
2064 OsIf_SuspendAllInterrupts();
2065 #ifdef _ARM_DS5_C_S32ZE_
2066 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2067 #endif
2068 }
2069 msr_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId] = msr;
2070 }
2071 reentry_guard_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId]++;
2072 }
2073
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_41(void)2074 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_41(void)
2075 {
2076 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2077
2078 reentry_guard_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId]--;
2079 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId])) /*if interrupts were enabled*/
2080 {
2081 OsIf_ResumeAllInterrupts();
2082 #ifdef _ARM_DS5_C_S32ZE_
2083 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2084 #endif
2085 }
2086 }
2087
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_42(void)2088 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_42(void)
2089 {
2090 uint32 msr;
2091 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2092
2093 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId])
2094 {
2095 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2096 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2097 #else
2098 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2099 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2100 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2101 {
2102 OsIf_SuspendAllInterrupts();
2103 #ifdef _ARM_DS5_C_S32ZE_
2104 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2105 #endif
2106 }
2107 msr_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId] = msr;
2108 }
2109 reentry_guard_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId]++;
2110 }
2111
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_42(void)2112 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_42(void)
2113 {
2114 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2115
2116 reentry_guard_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId]--;
2117 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId])) /*if interrupts were enabled*/
2118 {
2119 OsIf_ResumeAllInterrupts();
2120 #ifdef _ARM_DS5_C_S32ZE_
2121 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2122 #endif
2123 }
2124 }
2125
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_43(void)2126 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_43(void)
2127 {
2128 uint32 msr;
2129 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2130
2131 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId])
2132 {
2133 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2134 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2135 #else
2136 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2137 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2138 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2139 {
2140 OsIf_SuspendAllInterrupts();
2141 #ifdef _ARM_DS5_C_S32ZE_
2142 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2143 #endif
2144 }
2145 msr_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId] = msr;
2146 }
2147 reentry_guard_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId]++;
2148 }
2149
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_43(void)2150 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_43(void)
2151 {
2152 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2153
2154 reentry_guard_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId]--;
2155 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId])) /*if interrupts were enabled*/
2156 {
2157 OsIf_ResumeAllInterrupts();
2158 #ifdef _ARM_DS5_C_S32ZE_
2159 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2160 #endif
2161 }
2162 }
2163
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_44(void)2164 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_44(void)
2165 {
2166 uint32 msr;
2167 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2168
2169 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId])
2170 {
2171 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2172 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2173 #else
2174 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2175 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2176 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2177 {
2178 OsIf_SuspendAllInterrupts();
2179 #ifdef _ARM_DS5_C_S32ZE_
2180 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2181 #endif
2182 }
2183 msr_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId] = msr;
2184 }
2185 reentry_guard_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId]++;
2186 }
2187
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_44(void)2188 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_44(void)
2189 {
2190 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2191
2192 reentry_guard_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId]--;
2193 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId])) /*if interrupts were enabled*/
2194 {
2195 OsIf_ResumeAllInterrupts();
2196 #ifdef _ARM_DS5_C_S32ZE_
2197 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2198 #endif
2199 }
2200 }
2201
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_45(void)2202 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_45(void)
2203 {
2204 uint32 msr;
2205 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2206
2207 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId])
2208 {
2209 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2210 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2211 #else
2212 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2213 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2214 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2215 {
2216 OsIf_SuspendAllInterrupts();
2217 #ifdef _ARM_DS5_C_S32ZE_
2218 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2219 #endif
2220 }
2221 msr_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId] = msr;
2222 }
2223 reentry_guard_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId]++;
2224 }
2225
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_45(void)2226 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_45(void)
2227 {
2228 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2229
2230 reentry_guard_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId]--;
2231 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId])) /*if interrupts were enabled*/
2232 {
2233 OsIf_ResumeAllInterrupts();
2234 #ifdef _ARM_DS5_C_S32ZE_
2235 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2236 #endif
2237 }
2238 }
2239
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_46(void)2240 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_46(void)
2241 {
2242 uint32 msr;
2243 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2244
2245 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId])
2246 {
2247 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2248 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2249 #else
2250 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2251 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2252 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2253 {
2254 OsIf_SuspendAllInterrupts();
2255 #ifdef _ARM_DS5_C_S32ZE_
2256 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2257 #endif
2258 }
2259 msr_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId] = msr;
2260 }
2261 reentry_guard_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId]++;
2262 }
2263
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_46(void)2264 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_46(void)
2265 {
2266 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2267
2268 reentry_guard_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId]--;
2269 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId])) /*if interrupts were enabled*/
2270 {
2271 OsIf_ResumeAllInterrupts();
2272 #ifdef _ARM_DS5_C_S32ZE_
2273 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2274 #endif
2275 }
2276 }
2277
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_47(void)2278 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_47(void)
2279 {
2280 uint32 msr;
2281 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2282
2283 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId])
2284 {
2285 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2286 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2287 #else
2288 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2289 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2290 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2291 {
2292 OsIf_SuspendAllInterrupts();
2293 #ifdef _ARM_DS5_C_S32ZE_
2294 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2295 #endif
2296 }
2297 msr_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId] = msr;
2298 }
2299 reentry_guard_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId]++;
2300 }
2301
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_47(void)2302 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_47(void)
2303 {
2304 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2305
2306 reentry_guard_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId]--;
2307 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId])) /*if interrupts were enabled*/
2308 {
2309 OsIf_ResumeAllInterrupts();
2310 #ifdef _ARM_DS5_C_S32ZE_
2311 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2312 #endif
2313 }
2314 }
2315
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_48(void)2316 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_48(void)
2317 {
2318 uint32 msr;
2319 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2320
2321 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId])
2322 {
2323 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2324 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2325 #else
2326 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2327 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2328 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2329 {
2330 OsIf_SuspendAllInterrupts();
2331 #ifdef _ARM_DS5_C_S32ZE_
2332 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2333 #endif
2334 }
2335 msr_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId] = msr;
2336 }
2337 reentry_guard_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId]++;
2338 }
2339
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_48(void)2340 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_48(void)
2341 {
2342 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2343
2344 reentry_guard_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId]--;
2345 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId])) /*if interrupts were enabled*/
2346 {
2347 OsIf_ResumeAllInterrupts();
2348 #ifdef _ARM_DS5_C_S32ZE_
2349 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2350 #endif
2351 }
2352 }
2353
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_49(void)2354 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_49(void)
2355 {
2356 uint32 msr;
2357 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2358
2359 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId])
2360 {
2361 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2362 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2363 #else
2364 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2365 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2366 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2367 {
2368 OsIf_SuspendAllInterrupts();
2369 #ifdef _ARM_DS5_C_S32ZE_
2370 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2371 #endif
2372 }
2373 msr_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId] = msr;
2374 }
2375 reentry_guard_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId]++;
2376 }
2377
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_49(void)2378 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_49(void)
2379 {
2380 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2381
2382 reentry_guard_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId]--;
2383 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId])) /*if interrupts were enabled*/
2384 {
2385 OsIf_ResumeAllInterrupts();
2386 #ifdef _ARM_DS5_C_S32ZE_
2387 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2388 #endif
2389 }
2390 }
2391
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_50(void)2392 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_50(void)
2393 {
2394 uint32 msr;
2395 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2396
2397 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId])
2398 {
2399 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2400 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2401 #else
2402 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2403 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2404 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2405 {
2406 OsIf_SuspendAllInterrupts();
2407 #ifdef _ARM_DS5_C_S32ZE_
2408 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2409 #endif
2410 }
2411 msr_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId] = msr;
2412 }
2413 reentry_guard_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId]++;
2414 }
2415
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_50(void)2416 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_50(void)
2417 {
2418 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2419
2420 reentry_guard_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId]--;
2421 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId])) /*if interrupts were enabled*/
2422 {
2423 OsIf_ResumeAllInterrupts();
2424 #ifdef _ARM_DS5_C_S32ZE_
2425 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2426 #endif
2427 }
2428 }
2429
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_51(void)2430 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_51(void)
2431 {
2432 uint32 msr;
2433 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2434
2435 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId])
2436 {
2437 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2438 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2439 #else
2440 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2441 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2442 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2443 {
2444 OsIf_SuspendAllInterrupts();
2445 #ifdef _ARM_DS5_C_S32ZE_
2446 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2447 #endif
2448 }
2449 msr_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId] = msr;
2450 }
2451 reentry_guard_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId]++;
2452 }
2453
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_51(void)2454 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_51(void)
2455 {
2456 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2457
2458 reentry_guard_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId]--;
2459 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId])) /*if interrupts were enabled*/
2460 {
2461 OsIf_ResumeAllInterrupts();
2462 #ifdef _ARM_DS5_C_S32ZE_
2463 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2464 #endif
2465 }
2466 }
2467
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_52(void)2468 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_52(void)
2469 {
2470 uint32 msr;
2471 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2472
2473 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId])
2474 {
2475 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2476 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2477 #else
2478 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2479 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2480 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2481 {
2482 OsIf_SuspendAllInterrupts();
2483 #ifdef _ARM_DS5_C_S32ZE_
2484 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2485 #endif
2486 }
2487 msr_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId] = msr;
2488 }
2489 reentry_guard_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId]++;
2490 }
2491
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_52(void)2492 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_52(void)
2493 {
2494 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2495
2496 reentry_guard_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId]--;
2497 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId])) /*if interrupts were enabled*/
2498 {
2499 OsIf_ResumeAllInterrupts();
2500 #ifdef _ARM_DS5_C_S32ZE_
2501 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2502 #endif
2503 }
2504 }
2505
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_53(void)2506 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_53(void)
2507 {
2508 uint32 msr;
2509 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2510
2511 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId])
2512 {
2513 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2514 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2515 #else
2516 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2517 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2518 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2519 {
2520 OsIf_SuspendAllInterrupts();
2521 #ifdef _ARM_DS5_C_S32ZE_
2522 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2523 #endif
2524 }
2525 msr_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId] = msr;
2526 }
2527 reentry_guard_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId]++;
2528 }
2529
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_53(void)2530 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_53(void)
2531 {
2532 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2533
2534 reentry_guard_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId]--;
2535 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId])) /*if interrupts were enabled*/
2536 {
2537 OsIf_ResumeAllInterrupts();
2538 #ifdef _ARM_DS5_C_S32ZE_
2539 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2540 #endif
2541 }
2542 }
2543
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_54(void)2544 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_54(void)
2545 {
2546 uint32 msr;
2547 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2548
2549 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId])
2550 {
2551 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2552 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2553 #else
2554 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2555 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2556 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2557 {
2558 OsIf_SuspendAllInterrupts();
2559 #ifdef _ARM_DS5_C_S32ZE_
2560 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2561 #endif
2562 }
2563 msr_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId] = msr;
2564 }
2565 reentry_guard_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId]++;
2566 }
2567
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_54(void)2568 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_54(void)
2569 {
2570 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2571
2572 reentry_guard_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId]--;
2573 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId])) /*if interrupts were enabled*/
2574 {
2575 OsIf_ResumeAllInterrupts();
2576 #ifdef _ARM_DS5_C_S32ZE_
2577 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2578 #endif
2579 }
2580 }
2581
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_55(void)2582 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_55(void)
2583 {
2584 uint32 msr;
2585 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2586
2587 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId])
2588 {
2589 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2590 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2591 #else
2592 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2593 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2594 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2595 {
2596 OsIf_SuspendAllInterrupts();
2597 #ifdef _ARM_DS5_C_S32ZE_
2598 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2599 #endif
2600 }
2601 msr_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId] = msr;
2602 }
2603 reentry_guard_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId]++;
2604 }
2605
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_55(void)2606 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_55(void)
2607 {
2608 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2609
2610 reentry_guard_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId]--;
2611 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId])) /*if interrupts were enabled*/
2612 {
2613 OsIf_ResumeAllInterrupts();
2614 #ifdef _ARM_DS5_C_S32ZE_
2615 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2616 #endif
2617 }
2618 }
2619
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_56(void)2620 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_56(void)
2621 {
2622 uint32 msr;
2623 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2624
2625 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId])
2626 {
2627 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2628 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2629 #else
2630 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2631 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2632 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2633 {
2634 OsIf_SuspendAllInterrupts();
2635 #ifdef _ARM_DS5_C_S32ZE_
2636 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2637 #endif
2638 }
2639 msr_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId] = msr;
2640 }
2641 reentry_guard_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId]++;
2642 }
2643
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_56(void)2644 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_56(void)
2645 {
2646 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2647
2648 reentry_guard_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId]--;
2649 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId])) /*if interrupts were enabled*/
2650 {
2651 OsIf_ResumeAllInterrupts();
2652 #ifdef _ARM_DS5_C_S32ZE_
2653 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2654 #endif
2655 }
2656 }
2657
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_57(void)2658 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_57(void)
2659 {
2660 uint32 msr;
2661 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2662
2663 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId])
2664 {
2665 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2666 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2667 #else
2668 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2669 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2670 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2671 {
2672 OsIf_SuspendAllInterrupts();
2673 #ifdef _ARM_DS5_C_S32ZE_
2674 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2675 #endif
2676 }
2677 msr_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId] = msr;
2678 }
2679 reentry_guard_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId]++;
2680 }
2681
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_57(void)2682 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_57(void)
2683 {
2684 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2685
2686 reentry_guard_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId]--;
2687 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId])) /*if interrupts were enabled*/
2688 {
2689 OsIf_ResumeAllInterrupts();
2690 #ifdef _ARM_DS5_C_S32ZE_
2691 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2692 #endif
2693 }
2694 }
2695
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_58(void)2696 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_58(void)
2697 {
2698 uint32 msr;
2699 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2700
2701 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId])
2702 {
2703 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2704 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2705 #else
2706 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2707 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2708 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2709 {
2710 OsIf_SuspendAllInterrupts();
2711 #ifdef _ARM_DS5_C_S32ZE_
2712 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2713 #endif
2714 }
2715 msr_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId] = msr;
2716 }
2717 reentry_guard_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId]++;
2718 }
2719
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_58(void)2720 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_58(void)
2721 {
2722 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2723
2724 reentry_guard_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId]--;
2725 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId])) /*if interrupts were enabled*/
2726 {
2727 OsIf_ResumeAllInterrupts();
2728 #ifdef _ARM_DS5_C_S32ZE_
2729 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2730 #endif
2731 }
2732 }
2733
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_59(void)2734 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_59(void)
2735 {
2736 uint32 msr;
2737 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2738
2739 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId])
2740 {
2741 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2742 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2743 #else
2744 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2745 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2746 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2747 {
2748 OsIf_SuspendAllInterrupts();
2749 #ifdef _ARM_DS5_C_S32ZE_
2750 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2751 #endif
2752 }
2753 msr_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId] = msr;
2754 }
2755 reentry_guard_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId]++;
2756 }
2757
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_59(void)2758 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_59(void)
2759 {
2760 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2761
2762 reentry_guard_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId]--;
2763 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId])) /*if interrupts were enabled*/
2764 {
2765 OsIf_ResumeAllInterrupts();
2766 #ifdef _ARM_DS5_C_S32ZE_
2767 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2768 #endif
2769 }
2770 }
2771
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_60(void)2772 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_60(void)
2773 {
2774 uint32 msr;
2775 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2776
2777 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId])
2778 {
2779 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2780 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2781 #else
2782 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2783 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2784 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2785 {
2786 OsIf_SuspendAllInterrupts();
2787 #ifdef _ARM_DS5_C_S32ZE_
2788 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2789 #endif
2790 }
2791 msr_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId] = msr;
2792 }
2793 reentry_guard_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId]++;
2794 }
2795
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_60(void)2796 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_60(void)
2797 {
2798 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2799
2800 reentry_guard_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId]--;
2801 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId])) /*if interrupts were enabled*/
2802 {
2803 OsIf_ResumeAllInterrupts();
2804 #ifdef _ARM_DS5_C_S32ZE_
2805 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2806 #endif
2807 }
2808 }
2809
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_61(void)2810 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_61(void)
2811 {
2812 uint32 msr;
2813 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2814
2815 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId])
2816 {
2817 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2818 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2819 #else
2820 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2821 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2822 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2823 {
2824 OsIf_SuspendAllInterrupts();
2825 #ifdef _ARM_DS5_C_S32ZE_
2826 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2827 #endif
2828 }
2829 msr_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId] = msr;
2830 }
2831 reentry_guard_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId]++;
2832 }
2833
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_61(void)2834 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_61(void)
2835 {
2836 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2837
2838 reentry_guard_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId]--;
2839 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId])) /*if interrupts were enabled*/
2840 {
2841 OsIf_ResumeAllInterrupts();
2842 #ifdef _ARM_DS5_C_S32ZE_
2843 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2844 #endif
2845 }
2846 }
2847
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_62(void)2848 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_62(void)
2849 {
2850 uint32 msr;
2851 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2852
2853 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId])
2854 {
2855 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2856 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2857 #else
2858 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2859 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2860 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2861 {
2862 OsIf_SuspendAllInterrupts();
2863 #ifdef _ARM_DS5_C_S32ZE_
2864 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2865 #endif
2866 }
2867 msr_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId] = msr;
2868 }
2869 reentry_guard_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId]++;
2870 }
2871
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_62(void)2872 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_62(void)
2873 {
2874 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2875
2876 reentry_guard_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId]--;
2877 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId])) /*if interrupts were enabled*/
2878 {
2879 OsIf_ResumeAllInterrupts();
2880 #ifdef _ARM_DS5_C_S32ZE_
2881 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2882 #endif
2883 }
2884 }
2885
SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_63(void)2886 void SchM_Enter_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_63(void)
2887 {
2888 uint32 msr;
2889 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2890
2891 if(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId])
2892 {
2893 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2894 msr = OsIf_Trusted_Call_Return(EthSwt_43_NETC_schm_read_msr);
2895 #else
2896 msr = EthSwt_43_NETC_schm_read_msr(); /*read MSR (to store interrupts state)*/
2897 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2898 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2899 {
2900 OsIf_SuspendAllInterrupts();
2901 #ifdef _ARM_DS5_C_S32ZE_
2902 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2903 #endif
2904 }
2905 msr_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId] = msr;
2906 }
2907 reentry_guard_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId]++;
2908 }
2909
SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_63(void)2910 void SchM_Exit_EthSwt_43_NETC_ETHSWT_EXCLUSIVE_AREA_63(void)
2911 {
2912 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2913
2914 reentry_guard_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId]--;
2915 if ((ISR_ON(msr_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId]))&&(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId])) /*if interrupts were enabled*/
2916 {
2917 OsIf_ResumeAllInterrupts();
2918 #ifdef _ARM_DS5_C_S32ZE_
2919 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2920 #endif
2921 }
2922 }
2923
2924 #ifdef MCAL_TESTING_ENVIRONMENT
2925 /**
2926 @brief This function checks that all entered exclusive areas were also exited.
2927 @details This function checks that all entered exclusive areas were also exited. The check
2928 is done by verifying that all reentry_guard_* static variables are back to the
2929 zero value.
2930
2931 @param[in] void No input parameters
2932 @return void This function does not return a value. Test asserts are used instead.
2933
2934 @pre None
2935 @post None
2936
2937 @remarks Covers
2938 @remarks Implements
2939 */
SchM_Check_ethswt_43_netc(void)2940 void SchM_Check_ethswt_43_netc(void)
2941 {
2942 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2943
2944 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId]);
2945 reentry_guard_ETHSWT_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_00 for the next test in the suite*/
2946
2947 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId]);
2948 reentry_guard_ETHSWT_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_01 for the next test in the suite*/
2949
2950 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId]);
2951 reentry_guard_ETHSWT_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_02 for the next test in the suite*/
2952
2953 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId]);
2954 reentry_guard_ETHSWT_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_03 for the next test in the suite*/
2955
2956 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId]);
2957 reentry_guard_ETHSWT_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_04 for the next test in the suite*/
2958
2959 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId]);
2960 reentry_guard_ETHSWT_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_05 for the next test in the suite*/
2961
2962 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId]);
2963 reentry_guard_ETHSWT_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_06 for the next test in the suite*/
2964
2965 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId]);
2966 reentry_guard_ETHSWT_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_07 for the next test in the suite*/
2967
2968 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId]);
2969 reentry_guard_ETHSWT_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_08 for the next test in the suite*/
2970
2971 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId]);
2972 reentry_guard_ETHSWT_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_09 for the next test in the suite*/
2973
2974 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId]);
2975 reentry_guard_ETHSWT_EXCLUSIVE_AREA_10[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_10 for the next test in the suite*/
2976
2977 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId]);
2978 reentry_guard_ETHSWT_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_11 for the next test in the suite*/
2979
2980 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId]);
2981 reentry_guard_ETHSWT_EXCLUSIVE_AREA_12[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_12 for the next test in the suite*/
2982
2983 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId]);
2984 reentry_guard_ETHSWT_EXCLUSIVE_AREA_13[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_13 for the next test in the suite*/
2985
2986 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId]);
2987 reentry_guard_ETHSWT_EXCLUSIVE_AREA_14[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_14 for the next test in the suite*/
2988
2989 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId]);
2990 reentry_guard_ETHSWT_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_15 for the next test in the suite*/
2991
2992 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId]);
2993 reentry_guard_ETHSWT_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_16 for the next test in the suite*/
2994
2995 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId]);
2996 reentry_guard_ETHSWT_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_17 for the next test in the suite*/
2997
2998 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId]);
2999 reentry_guard_ETHSWT_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_18 for the next test in the suite*/
3000
3001 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId]);
3002 reentry_guard_ETHSWT_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_19 for the next test in the suite*/
3003
3004 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId]);
3005 reentry_guard_ETHSWT_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_20 for the next test in the suite*/
3006
3007 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId]);
3008 reentry_guard_ETHSWT_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_21 for the next test in the suite*/
3009
3010 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId]);
3011 reentry_guard_ETHSWT_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_22 for the next test in the suite*/
3012
3013 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId]);
3014 reentry_guard_ETHSWT_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_23 for the next test in the suite*/
3015
3016 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId]);
3017 reentry_guard_ETHSWT_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_24 for the next test in the suite*/
3018
3019 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId]);
3020 reentry_guard_ETHSWT_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_25 for the next test in the suite*/
3021
3022 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId]);
3023 reentry_guard_ETHSWT_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_26 for the next test in the suite*/
3024
3025 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId]);
3026 reentry_guard_ETHSWT_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_27 for the next test in the suite*/
3027
3028 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId]);
3029 reentry_guard_ETHSWT_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_28 for the next test in the suite*/
3030
3031 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId]);
3032 reentry_guard_ETHSWT_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_29 for the next test in the suite*/
3033
3034 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId]);
3035 reentry_guard_ETHSWT_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_30 for the next test in the suite*/
3036
3037 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId]);
3038 reentry_guard_ETHSWT_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_31 for the next test in the suite*/
3039
3040 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId]);
3041 reentry_guard_ETHSWT_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_32 for the next test in the suite*/
3042
3043 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId]);
3044 reentry_guard_ETHSWT_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_33 for the next test in the suite*/
3045
3046 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId]);
3047 reentry_guard_ETHSWT_EXCLUSIVE_AREA_34[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_34 for the next test in the suite*/
3048
3049 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId]);
3050 reentry_guard_ETHSWT_EXCLUSIVE_AREA_35[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_35 for the next test in the suite*/
3051
3052 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId]);
3053 reentry_guard_ETHSWT_EXCLUSIVE_AREA_36[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_36 for the next test in the suite*/
3054
3055 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId]);
3056 reentry_guard_ETHSWT_EXCLUSIVE_AREA_37[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_37 for the next test in the suite*/
3057
3058 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId]);
3059 reentry_guard_ETHSWT_EXCLUSIVE_AREA_38[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_38 for the next test in the suite*/
3060
3061 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId]);
3062 reentry_guard_ETHSWT_EXCLUSIVE_AREA_39[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_39 for the next test in the suite*/
3063
3064 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId]);
3065 reentry_guard_ETHSWT_EXCLUSIVE_AREA_40[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_40 for the next test in the suite*/
3066
3067 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId]);
3068 reentry_guard_ETHSWT_EXCLUSIVE_AREA_41[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_41 for the next test in the suite*/
3069
3070 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId]);
3071 reentry_guard_ETHSWT_EXCLUSIVE_AREA_42[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_42 for the next test in the suite*/
3072
3073 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId]);
3074 reentry_guard_ETHSWT_EXCLUSIVE_AREA_43[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_43 for the next test in the suite*/
3075
3076 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId]);
3077 reentry_guard_ETHSWT_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_44 for the next test in the suite*/
3078
3079 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId]);
3080 reentry_guard_ETHSWT_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_45 for the next test in the suite*/
3081
3082 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId]);
3083 reentry_guard_ETHSWT_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_46 for the next test in the suite*/
3084
3085 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId]);
3086 reentry_guard_ETHSWT_EXCLUSIVE_AREA_47[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_47 for the next test in the suite*/
3087
3088 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId]);
3089 reentry_guard_ETHSWT_EXCLUSIVE_AREA_48[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_48 for the next test in the suite*/
3090
3091 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId]);
3092 reentry_guard_ETHSWT_EXCLUSIVE_AREA_49[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_49 for the next test in the suite*/
3093
3094 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId]);
3095 reentry_guard_ETHSWT_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_50 for the next test in the suite*/
3096
3097 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId]);
3098 reentry_guard_ETHSWT_EXCLUSIVE_AREA_51[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_51 for the next test in the suite*/
3099
3100 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId]);
3101 reentry_guard_ETHSWT_EXCLUSIVE_AREA_52[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_52 for the next test in the suite*/
3102
3103 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId]);
3104 reentry_guard_ETHSWT_EXCLUSIVE_AREA_53[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_53 for the next test in the suite*/
3105
3106 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId]);
3107 reentry_guard_ETHSWT_EXCLUSIVE_AREA_54[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_54 for the next test in the suite*/
3108
3109 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId]);
3110 reentry_guard_ETHSWT_EXCLUSIVE_AREA_55[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_55 for the next test in the suite*/
3111
3112 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId]);
3113 reentry_guard_ETHSWT_EXCLUSIVE_AREA_56[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_56 for the next test in the suite*/
3114
3115 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId]);
3116 reentry_guard_ETHSWT_EXCLUSIVE_AREA_57[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_57 for the next test in the suite*/
3117
3118 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId]);
3119 reentry_guard_ETHSWT_EXCLUSIVE_AREA_58[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_58 for the next test in the suite*/
3120
3121 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId]);
3122 reentry_guard_ETHSWT_EXCLUSIVE_AREA_59[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_59 for the next test in the suite*/
3123
3124 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId]);
3125 reentry_guard_ETHSWT_EXCLUSIVE_AREA_60[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_60 for the next test in the suite*/
3126
3127 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId]);
3128 reentry_guard_ETHSWT_EXCLUSIVE_AREA_61[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_61 for the next test in the suite*/
3129
3130 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId]);
3131 reentry_guard_ETHSWT_EXCLUSIVE_AREA_62[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_62 for the next test in the suite*/
3132
3133 EU_ASSERT(0UL == reentry_guard_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId]);
3134 reentry_guard_ETHSWT_EXCLUSIVE_AREA_63[u32CoreId] = 0UL; /*reset reentry_guard_ETHSWT_EXCLUSIVE_AREA_62 for the next test in the suite*/
3135
3136 }
3137 #endif /*MCAL_TESTING_ENVIRONMENT*/
3138
3139 #define RTE_STOP_SEC_CODE
3140 #include "Rte_MemMap.h"
3141
3142 #ifdef __cplusplus
3143 }
3144 #endif
3145
3146 /** @} */
3147
