1 /**
2   ******************************************************************************
3   * @file    stm32g041xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for stm32g041xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2018-2021 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 /** @addtogroup CMSIS_Device
28   * @{
29   */
30 
31 /** @addtogroup stm32g041xx
32   * @{
33   */
34 
35 #ifndef STM32G041xx_H
36 #define STM32G041xx_H
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif /* __cplusplus */
41 
42 /** @addtogroup Configuration_section_for_CMSIS
43   * @{
44   */
45 
46 /**
47   * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
48    */
49 #define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
50 #define __MPU_PRESENT             1U /*!< STM32G0xx  provides an MPU                    */
51 #define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
52 #define __NVIC_PRIO_BITS          2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */
53 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
54 
55 /**
56   * @}
57   */
58 
59 /** @addtogroup Peripheral_interrupt_number_definition
60   * @{
61   */
62 
63 /**
64  * @brief stm32g041xx Interrupt Number Definition, according to the selected device
65  *        in @ref Library_configuration_section
66  */
67 
68 /*!< Interrupt Number Definition */
69 typedef enum
70 {
71 /******  Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
72   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
73   HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
74   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
77 /******  STM32G0xxxx specific Interrupt Numbers ****************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_IRQn                    = 1,      /*!< PVD through EXTI line 16                                          */
80   RTC_TAMP_IRQn               = 2,      /*!< RTC interrupt through the EXTI line 19 & 21                       */
81   FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                            */
82   RCC_IRQn                    = 4,      /*!< RCC global Interrupt                                              */
83   EXTI0_1_IRQn                = 5,      /*!< EXTI 0 and 1 Interrupts                                           */
84   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                      */
85   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                      */
86   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                          */
87   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                           */
88   DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11,     /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interrupts        */
89   ADC1_IRQn                   = 12,     /*!< ADC1 Interrupts                                                   */
90   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts            */
91   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                    */
92   TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                                    */
93   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                             */
94   LPTIM1_IRQn                 = 17,     /*!< LPTIM1 global Interrupts                                          */
95   LPTIM2_IRQn                 = 18,     /*!< LPTIM2 global Interrupt                                           */
96   TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                            */
97   TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                            */
98   TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                            */
99   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt  (combined with EXTI 23)                           */
100   I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                    */
101   SPI1_IRQn                   = 25,     /*!< SPI1/I2S1 Interrupt                                               */
102   SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                    */
103   USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                                  */
104   USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                                  */
105   LPUART1_IRQn                = 29,     /*!< LPUART1 globlal Interrupts (combined with EXTI 28)                 */
106   AES_RNG_IRQn                = 31,     /*!< AES & RNG Interrupt                                                */
107 } IRQn_Type;
108 
109 /**
110   * @}
111   */
112 
113 #include "core_cm0plus.h"               /* Cortex-M0+ processor and core peripherals */
114 #include "system_stm32g0xx.h"
115 #include <stdint.h>
116 
117 /** @addtogroup Peripheral_registers_structures
118   * @{
119   */
120 
121 /**
122   * @brief Analog to Digital Converter
123   */
124 typedef struct
125 {
126   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
127   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
128   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
129   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
130   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
131   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
132        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
133        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
134   __IO uint32_t AWD1TR;       /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
135   __IO uint32_t AWD2TR;       /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
136   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
137   __IO uint32_t AWD3TR;       /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
138        uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
139   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
140        uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
141   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
142   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
143        uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
144   __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
145 } ADC_TypeDef;
146 
147 typedef struct
148 {
149   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
150 } ADC_Common_TypeDef;
151 
152 /* Legacy registers naming */
153 #define TR1     AWD1TR
154 #define TR2     AWD2TR
155 #define TR3     AWD3TR
156 
157 
158 
159 
160 /**
161   * @brief CRC calculation unit
162   */
163 typedef struct
164 {
165   __IO uint32_t DR;             /*!< CRC Data register,                         Address offset: 0x00 */
166   __IO uint32_t IDR;            /*!< CRC Independent data register,             Address offset: 0x04 */
167   __IO uint32_t CR;             /*!< CRC Control register,                      Address offset: 0x08 */
168        uint32_t RESERVED1;      /*!< Reserved,                                                  0x0C */
169   __IO uint32_t INIT;           /*!< Initial CRC value register,                Address offset: 0x10 */
170   __IO uint32_t POL;            /*!< CRC polynomial register,                   Address offset: 0x14 */
171 } CRC_TypeDef;
172 
173 
174 /**
175   * @brief Debug MCU
176   */
177 typedef struct
178 {
179   __IO uint32_t IDCODE;      /*!< MCU device ID code,              Address offset: 0x00 */
180   __IO uint32_t CR;          /*!< Debug configuration register,    Address offset: 0x04 */
181   __IO uint32_t APBFZ1;      /*!< Debug APB freeze register 1,     Address offset: 0x08 */
182   __IO uint32_t APBFZ2;      /*!< Debug APB freeze register 2,     Address offset: 0x0C */
183 } DBG_TypeDef;
184 
185 /**
186   * @brief DMA Controller
187   */
188 typedef struct
189 {
190   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
191   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
192   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
193   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
194 } DMA_Channel_TypeDef;
195 
196 typedef struct
197 {
198   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
199   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
200 } DMA_TypeDef;
201 
202 /**
203   * @brief DMA Multiplexer
204   */
205 typedef struct
206 {
207   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
208 }DMAMUX_Channel_TypeDef;
209 
210 typedef struct
211 {
212   __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
213   __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
214 }DMAMUX_ChannelStatus_TypeDef;
215 
216 typedef struct
217 {
218   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
219 }DMAMUX_RequestGen_TypeDef;
220 
221 typedef struct
222 {
223   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
224   __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
225 }DMAMUX_RequestGenStatus_TypeDef;
226 
227 /**
228   * @brief Asynch Interrupt/Event Controller (EXTI)
229   */
230 typedef struct
231 {
232   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
233   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
234   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
235   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
236   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
237        uint32_t RESERVED1[3];   /*!< Reserved 1,                                                0x14 -- 0x1C */
238        uint32_t RESERVED2[5];   /*!< Reserved 2,                                                0x20 -- 0x30 */
239        uint32_t RESERVED3[11];  /*!< Reserved 3,                                                0x34 -- 0x5C */
240   __IO uint32_t EXTICR[4];      /*!< EXTI External Interrupt Configuration Register,            0x60 -- 0x6C */
241        uint32_t RESERVED4[4];   /*!< Reserved 4,                                                0x70 -- 0x7C */
242   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
243   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
244 } EXTI_TypeDef;
245 
246 /**
247   * @brief FLASH Registers
248   */
249 typedef struct
250 {
251   __IO uint32_t ACR;          /*!< FLASH Access Control register,                     Address offset: 0x00 */
252        uint32_t RESERVED1;    /*!< Reserved1,                                         Address offset: 0x04 */
253   __IO uint32_t KEYR;         /*!< FLASH Key register,                                Address offset: 0x08 */
254   __IO uint32_t OPTKEYR;      /*!< FLASH Option Key register,                         Address offset: 0x0C */
255   __IO uint32_t SR;           /*!< FLASH Status register,                             Address offset: 0x10 */
256   __IO uint32_t CR;           /*!< FLASH Control register,                            Address offset: 0x14 */
257   __IO uint32_t ECCR;         /*!< FLASH ECC register,                                Address offset: 0x18 */
258        uint32_t RESERVED2;    /*!< Reserved2,                                         Address offset: 0x1C */
259   __IO uint32_t OPTR;         /*!< FLASH Option register,                             Address offset: 0x20 */
260   __IO uint32_t PCROP1ASR;    /*!< FLASH Bank PCROP area A Start address register,    Address offset: 0x24 */
261   __IO uint32_t PCROP1AER;    /*!< FLASH Bank PCROP area A End address register,      Address offset: 0x28 */
262   __IO uint32_t WRP1AR;       /*!< FLASH Bank WRP area A address register,            Address offset: 0x2C */
263   __IO uint32_t WRP1BR;       /*!< FLASH Bank WRP area B address register,            Address offset: 0x30 */
264   __IO uint32_t PCROP1BSR;    /*!< FLASH Bank PCROP area B Start address register,    Address offset: 0x34 */
265   __IO uint32_t PCROP1BER;    /*!< FLASH Bank PCROP area B End address register,      Address offset: 0x38 */
266        uint32_t RESERVED8[17];/*!< Reserved8,                                         Address offset: 0x3C--0x7C */
267   __IO uint32_t SECR;         /*!< FLASH security register ,                          Address offset: 0x80 */
268 } FLASH_TypeDef;
269 
270 /**
271   * @brief General Purpose I/O
272   */
273 typedef struct
274 {
275   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
276   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
277   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
278   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
279   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
280   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
281   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
282   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
283   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
284   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
285 } GPIO_TypeDef;
286 
287 
288 /**
289   * @brief Inter-integrated Circuit Interface
290   */
291 typedef struct
292 {
293   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
294   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
295   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
296   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
297   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
298   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
299   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
300   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
301   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
302   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
303   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
304 } I2C_TypeDef;
305 
306 /**
307   * @brief Independent WATCHDOG
308   */
309 typedef struct
310 {
311   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
312   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
313   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
314   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
315   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
316 } IWDG_TypeDef;
317 
318 /**
319   * @brief LPTIMER
320   */
321 typedef struct
322 {
323   __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
324   __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
325   __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
326   __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
327   __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
328   __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
329   __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
330   __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
331   __IO uint32_t RESERVED1;        /*!< Reserved1,                                          Address offset: 0x20 */
332   __IO uint32_t CFGR2;            /*!< LPTIM Option register,                              Address offset: 0x24 */
333 } LPTIM_TypeDef;
334 
335 
336 /**
337   * @brief Power Control
338   */
339 typedef struct
340 {
341   __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
342   __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
343   __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
344   __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
345   __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
346   __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
347   __IO uint32_t SCR;          /*!< PWR Power Status Clear Register,                  Address offset: 0x18 */
348        uint32_t RESERVED1;    /*!< Reserved,                                         Address offset: 0x1C */
349   __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
350   __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
351   __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
352   __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
353   __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
354   __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
355   __IO uint32_t PUCRD;        /*!< PWR Pull-Up Control Register of port D,           Address offset: 0x38 */
356   __IO uint32_t PDCRD;        /*!< PWR Pull-Down Control Register of port D,         Address offset: 0x3C */
357        uint32_t RESERVED2;    /*!< Reserved,                                         Address offset: 0x40 */
358        uint32_t RESERVED3;    /*!< Reserved,                                         Address offset: 0x44 */
359   __IO uint32_t PUCRF;        /*!< PWR Pull-Up Control Register of port F,           Address offset: 0x48 */
360   __IO uint32_t PDCRF;        /*!< PWR Pull-Down Control Register of port F,         Address offset: 0x4C */
361 } PWR_TypeDef;
362 
363 /**
364   * @brief Reset and Clock Control
365   */
366 typedef struct
367 {
368   __IO uint32_t CR;          /*!< RCC Clock Sources Control Register,                                     Address offset: 0x00 */
369   __IO uint32_t ICSCR;       /*!< RCC Internal Clock Sources Calibration Register,                        Address offset: 0x04 */
370   __IO uint32_t CFGR;        /*!< RCC Regulated Domain Clocks Configuration Register,                     Address offset: 0x08 */
371   __IO uint32_t PLLCFGR;     /*!< RCC System PLL configuration Register,                                  Address offset: 0x0C */
372   __IO uint32_t RESERVED0;   /*!< Reserved,                                                               Address offset: 0x10 */
373   __IO uint32_t RESERVED1;   /*!< Reserved,                                                               Address offset: 0x14 */
374   __IO uint32_t CIER;        /*!< RCC Clock Interrupt Enable Register,                                    Address offset: 0x18 */
375   __IO uint32_t CIFR;        /*!< RCC Clock Interrupt Flag Register,                                      Address offset: 0x1C */
376   __IO uint32_t CICR;        /*!< RCC Clock Interrupt Clear Register,                                     Address offset: 0x20 */
377   __IO uint32_t IOPRSTR;     /*!< RCC IO port reset register,                                             Address offset: 0x24 */
378   __IO uint32_t AHBRSTR;     /*!< RCC AHB peripherals reset register,                                     Address offset: 0x28 */
379   __IO uint32_t APBRSTR1;    /*!< RCC APB peripherals reset register 1,                                   Address offset: 0x2C */
380   __IO uint32_t APBRSTR2;    /*!< RCC APB peripherals reset register 2,                                   Address offset: 0x30 */
381   __IO uint32_t IOPENR;      /*!< RCC IO port enable register,                                            Address offset: 0x34 */
382   __IO uint32_t AHBENR;      /*!< RCC AHB peripherals clock enable register,                              Address offset: 0x38 */
383   __IO uint32_t APBENR1;     /*!< RCC APB peripherals clock enable register1,                             Address offset: 0x3C */
384   __IO uint32_t APBENR2;     /*!< RCC APB peripherals clock enable register2,                             Address offset: 0x40 */
385   __IO uint32_t IOPSMENR;    /*!< RCC IO port clocks enable in sleep mode register,                       Address offset: 0x44 */
386   __IO uint32_t AHBSMENR;    /*!< RCC AHB peripheral clocks enable in sleep mode register,                Address offset: 0x48 */
387   __IO uint32_t APBSMENR1;   /*!< RCC APB peripheral clocks enable in sleep mode register1,               Address offset: 0x4C */
388   __IO uint32_t APBSMENR2;   /*!< RCC APB peripheral clocks enable in sleep mode register2,               Address offset: 0x50 */
389   __IO uint32_t CCIPR;       /*!< RCC Peripherals Independent Clocks Configuration Register,              Address offset: 0x54 */
390   __IO uint32_t RESERVED2;   /*!< Reserved,                                                               Address offset: 0x58 */
391   __IO uint32_t BDCR;        /*!< RCC Backup Domain Control Register,                                     Address offset: 0x5C */
392   __IO uint32_t CSR;         /*!< RCC Unregulated Domain Clock Control and Status Register,               Address offset: 0x60 */
393 } RCC_TypeDef;
394 
395 /**
396   * @brief Real-Time Clock
397   */
398 typedef struct
399 {
400   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
401   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
402   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
403   __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
404   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
405   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
406   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
407        uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
408        uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
409   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
410   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
411   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
412   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
413   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
414   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
415        uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x1C */
416   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
417   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
418   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
419   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
420   __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
421   __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
422        uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
423   __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
424   __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x60 */
425 } RTC_TypeDef;
426 
427 /**
428   * @brief Tamper and backup registers
429   */
430 typedef struct
431 {
432   __IO uint32_t CR1;            /*!< TAMP configuration register 1,                             Address offset: 0x00 */
433   __IO uint32_t CR2;            /*!< TAMP configuration register 2,                             Address offset: 0x04 */
434        uint32_t RESERVED0;      /*!< Reserved                                                   Address offset: 0x08 */
435   __IO uint32_t FLTCR;          /*!< Reserved                                                   Address offset: 0x0C */
436        uint32_t RESERVED1[7];   /*!< Reserved                                                   Address offset: 0x10 -- 0x28 */
437   __IO uint32_t IER;            /*!< TAMP Interrupt enable register,                            Address offset: 0x2C */
438   __IO uint32_t SR;             /*!< TAMP Status register,                                      Address offset: 0x30 */
439   __IO uint32_t MISR;           /*!< TAMP Masked Interrupt Status register,                     Address offset: 0x34 */
440        uint32_t RESERVED2;      /*!< Reserved                                                   Address offset: 0x38 */
441   __IO uint32_t SCR;            /*!< TAMP Status clear register,                                Address offset: 0x3C */
442        uint32_t RESERVED3[48];  /*!< Reserved                                                   Address offset: 0x54 -- 0xFC */
443   __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                                    Address offset: 0x100 */
444   __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                                    Address offset: 0x104 */
445   __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                                    Address offset: 0x108 */
446   __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                                    Address offset: 0x10C */
447   __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                                    Address offset: 0x110 */
448 } TAMP_TypeDef;
449 
450   /**
451   * @brief Serial Peripheral Interface
452   */
453 typedef struct
454 {
455   __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
456   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
457   __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
458   __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
459   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
460   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
461   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
462   __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
463   __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
464 } SPI_TypeDef;
465 
466 /**
467   * @brief System configuration controller
468   */
469 typedef struct
470 {
471   __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                   Address offset: 0x00 */
472        uint32_t RESERVED0[5];   /*!< Reserved,                                                   0x04 --0x14 */
473   __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                   Address offset: 0x18 */
474        uint32_t RESERVED1[25];  /*!< Reserved                                                           0x1C */
475   __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,             Address offset: 0x80 */
476 } SYSCFG_TypeDef;
477 
478 /**
479   * @brief TIM
480   */
481 typedef struct
482 {
483   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
484   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
485   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
486   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
487   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
488   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
489   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
490   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
491   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
492   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
493   __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
494   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
495   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
496   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
497   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
498   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
499   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
500   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
501   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
502   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
503   __IO uint32_t OR1;         /*!< TIM option register,                      Address offset: 0x50 */
504   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
505   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
506   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
507   __IO uint32_t AF1;         /*!< TIM alternate function register 1,        Address offset: 0x60 */
508   __IO uint32_t AF2;         /*!< TIM alternate function register 2,        Address offset: 0x64 */
509   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
510 } TIM_TypeDef;
511 
512 /**
513   * @brief Universal Synchronous Asynchronous Receiver Transmitter
514   */
515 typedef struct
516 {
517   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
518   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
519   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
520   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
521   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
522   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */
523   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
524   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
525   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
526   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
527   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
528   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
529 } USART_TypeDef;
530 
531 /**
532   * @brief VREFBUF
533   */
534 typedef struct
535 {
536   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
537   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
538 } VREFBUF_TypeDef;
539 
540 /**
541   * @brief Window WATCHDOG
542   */
543 typedef struct
544 {
545   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
546   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
547   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
548 } WWDG_TypeDef;
549 
550 /**
551   * @brief AES hardware accelerator
552   */
553 typedef struct
554 {
555   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
556   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
557   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
558   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
559   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
560   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
561   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
562   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
563   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
564   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
565   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
566   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
567   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
568   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
569   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
570   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
571   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
572   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
573   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
574   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
575   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
576   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
577   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
578   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x5C */
579 } AES_TypeDef;
580 
581 /**
582   * @brief RNG
583   */
584 typedef struct
585 {
586   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
587   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
588   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
589 } RNG_TypeDef;
590 
591 
592 /**
593   * @}
594   */
595 
596 /** @addtogroup Peripheral_memory_map
597   * @{
598   */
599 #define FLASH_BASE            (0x08000000UL)  /*!< FLASH base address */
600 #define SRAM_BASE             (0x20000000UL)  /*!< SRAM base address */
601 #define PERIPH_BASE           (0x40000000UL)  /*!< Peripheral base address */
602 #define IOPORT_BASE           (0x50000000UL)  /*!< IOPORT base address */
603 #define SRAM_SIZE_MAX         (0x00002000UL)  /*!< maximum SRAM size (up to 8 KBytes) */
604 
605 #define FLASH_SIZE            (((*((uint32_t *)FLASHSIZE_BASE)) & (0x007FU)) << 10U)
606 
607 /*!< Peripheral memory map */
608 #define APBPERIPH_BASE        (PERIPH_BASE)
609 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
610 
611 /*!< APB peripherals */
612 
613 #define TIM2_BASE             (APBPERIPH_BASE + 0UL)
614 #define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
615 #define TIM14_BASE            (APBPERIPH_BASE + 0x00002000UL)
616 #define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
617 #define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
618 #define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
619 #define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
620 #define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
621 #define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
622 #define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
623 #define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
624 #define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
625 #define LPUART1_BASE          (APBPERIPH_BASE + 0x00008000UL)
626 #define LPTIM2_BASE           (APBPERIPH_BASE + 0x00009400UL)
627 #define TAMP_BASE             (APBPERIPH_BASE + 0x0000B000UL)
628 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
629 #define VREFBUF_BASE          (APBPERIPH_BASE + 0x00010030UL)
630 #define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
631 #define ADC1_COMMON_BASE      (APBPERIPH_BASE + 0x00012708UL)
632 #define ADC_BASE              (ADC1_COMMON_BASE) /* Kept for legacy purpose */
633 #define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00UL)
634 #define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
635 #define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
636 #define TIM16_BASE            (APBPERIPH_BASE + 0x00014400UL)
637 #define TIM17_BASE            (APBPERIPH_BASE + 0x00014800UL)
638 #define DBG_BASE              (APBPERIPH_BASE + 0x00015800UL)
639 
640 
641 /*!< AHB peripherals */
642 #define DMA1_BASE             (AHBPERIPH_BASE)
643 #define DMAMUX1_BASE          (AHBPERIPH_BASE + 0x00000800UL)
644 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
645 #define EXTI_BASE             (AHBPERIPH_BASE + 0x00001800UL)
646 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL)
647 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
648 
649 #define RNG_BASE              (AHBPERIPH_BASE + 0x00005000UL)
650 #define AES_BASE              (AHBPERIPH_BASE + 0x00006000UL)
651 
652 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
653 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
654 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
655 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
656 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
657 
658 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
659 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)
660 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)
661 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x0000000CUL)
662 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x00000010UL)
663 
664 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)
665 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)
666 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)
667 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x0000010CUL)
668 
669 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)
670 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)
671 
672 /*!< IOPORT */
673 #define GPIOA_BASE            (IOPORT_BASE + 0x00000000UL)
674 #define GPIOB_BASE            (IOPORT_BASE + 0x00000400UL)
675 #define GPIOC_BASE            (IOPORT_BASE + 0x00000800UL)
676 #define GPIOD_BASE            (IOPORT_BASE + 0x00000C00UL)
677 #define GPIOF_BASE            (IOPORT_BASE + 0x00001400UL)
678 
679 /*!< Device Electronic Signature */
680 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
681 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
682 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
683 
684 /**
685   * @}
686   */
687 
688 /** @addtogroup Peripheral_declaration
689   * @{
690   */
691 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
692 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
693 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
694 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
695 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
696 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
697 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
698 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
699 #define USART2              ((USART_TypeDef *) USART2_BASE)
700 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
701 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
702 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
703 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
704 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
705 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
706 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
707 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
708 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
709 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
710 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
711 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
712 #define USART1              ((USART_TypeDef *) USART1_BASE)
713 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
714 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
715 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
716 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
717 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
718 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
719 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
720 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
721 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
722 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
723 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
724 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
725 #define ADC                 (ADC1_COMMON) /* Kept for legacy purpose */
726 
727 #define AES                 ((AES_TypeDef *) AES_BASE)
728 #define AES1                ((AES_TypeDef *) AES_BASE)
729 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
730 
731 
732 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
733 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
734 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
735 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
736 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
737 #define DMAMUX1                ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
738 #define DMAMUX1_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
739 #define DMAMUX1_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
740 #define DMAMUX1_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
741 #define DMAMUX1_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
742 #define DMAMUX1_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
743 
744 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
745 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
746 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
747 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
748 
749 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
750 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
751 
752 #define DBG              ((DBG_TypeDef *) DBG_BASE)
753 
754 /**
755   * @}
756   */
757 
758 /** @addtogroup Exported_constants
759   * @{
760   */
761 
762   /** @addtogroup Hardware_Constant_Definition
763     * @{
764     */
765 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
766 
767   /**
768     * @}
769     */
770 
771   /** @addtogroup Peripheral_Registers_Bits_Definition
772   * @{
773   */
774 
775 /******************************************************************************/
776 /*                         Peripheral Registers Bits Definition               */
777 /******************************************************************************/
778 
779 /******************************************************************************/
780 /*                                                                            */
781 /*                      Analog to Digital Converter (ADC)                     */
782 /*                                                                            */
783 /******************************************************************************/
784 /********************  Bit definition for ADC_ISR register  *******************/
785 #define ADC_ISR_ADRDY_Pos              (0U)
786 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
787 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
788 #define ADC_ISR_EOSMP_Pos              (1U)
789 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
790 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
791 #define ADC_ISR_EOC_Pos                (2U)
792 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
793 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
794 #define ADC_ISR_EOS_Pos                (3U)
795 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
796 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
797 #define ADC_ISR_OVR_Pos                (4U)
798 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
799 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
800 #define ADC_ISR_AWD1_Pos               (7U)
801 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
802 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
803 #define ADC_ISR_AWD2_Pos               (8U)
804 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
805 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
806 #define ADC_ISR_AWD3_Pos               (9U)
807 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
808 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
809 #define ADC_ISR_EOCAL_Pos              (11U)
810 #define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
811 #define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
812 #define ADC_ISR_CCRDY_Pos              (13U)
813 #define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
814 #define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
815 
816 /* Legacy defines */
817 #define ADC_ISR_EOSEQ           (ADC_ISR_EOS)
818 
819 /********************  Bit definition for ADC_IER register  *******************/
820 #define ADC_IER_ADRDYIE_Pos            (0U)
821 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
822 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
823 #define ADC_IER_EOSMPIE_Pos            (1U)
824 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
825 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
826 #define ADC_IER_EOCIE_Pos              (2U)
827 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
828 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
829 #define ADC_IER_EOSIE_Pos              (3U)
830 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
831 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
832 #define ADC_IER_OVRIE_Pos              (4U)
833 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
834 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
835 #define ADC_IER_AWD1IE_Pos             (7U)
836 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
837 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
838 #define ADC_IER_AWD2IE_Pos             (8U)
839 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
840 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
841 #define ADC_IER_AWD3IE_Pos             (9U)
842 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
843 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
844 #define ADC_IER_EOCALIE_Pos            (11U)
845 #define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
846 #define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
847 #define ADC_IER_CCRDYIE_Pos            (13U)
848 #define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
849 #define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
850 
851 /* Legacy defines */
852 #define ADC_IER_EOSEQIE           (ADC_IER_EOSIE)
853 
854 /********************  Bit definition for ADC_CR register  ********************/
855 #define ADC_CR_ADEN_Pos                (0U)
856 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
857 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
858 #define ADC_CR_ADDIS_Pos               (1U)
859 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
860 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
861 #define ADC_CR_ADSTART_Pos             (2U)
862 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
863 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
864 #define ADC_CR_ADSTP_Pos               (4U)
865 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
866 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
867 #define ADC_CR_ADVREGEN_Pos            (28U)
868 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
869 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
870 #define ADC_CR_ADCAL_Pos               (31U)
871 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
872 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
873 
874 /********************  Bit definition for ADC_CFGR1 register  *****************/
875 #define ADC_CFGR1_DMAEN_Pos            (0U)
876 #define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
877 #define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
878 #define ADC_CFGR1_DMACFG_Pos           (1U)
879 #define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
880 #define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
881 
882 #define ADC_CFGR1_SCANDIR_Pos          (2U)
883 #define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
884 #define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
885 
886 #define ADC_CFGR1_RES_Pos              (3U)
887 #define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
888 #define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
889 #define ADC_CFGR1_RES_0                (0x1U << ADC_CFGR1_RES_Pos)             /*!< 0x00000008 */
890 #define ADC_CFGR1_RES_1                (0x2U << ADC_CFGR1_RES_Pos)             /*!< 0x00000010 */
891 
892 #define ADC_CFGR1_ALIGN_Pos            (5U)
893 #define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
894 #define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignment */
895 
896 #define ADC_CFGR1_EXTSEL_Pos           (6U)
897 #define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
898 #define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
899 #define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
900 #define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
901 #define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
902 
903 #define ADC_CFGR1_EXTEN_Pos            (10U)
904 #define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
905 #define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
906 #define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
907 #define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
908 
909 #define ADC_CFGR1_OVRMOD_Pos           (12U)
910 #define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
911 #define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
912 #define ADC_CFGR1_CONT_Pos             (13U)
913 #define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
914 #define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
915 #define ADC_CFGR1_WAIT_Pos             (14U)
916 #define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
917 #define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
918 #define ADC_CFGR1_AUTOFF_Pos           (15U)
919 #define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
920 #define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
921 #define ADC_CFGR1_DISCEN_Pos           (16U)
922 #define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
923 #define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
924 #define ADC_CFGR1_CHSELRMOD_Pos        (21U)
925 #define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
926 #define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
927 
928 #define ADC_CFGR1_AWD1SGL_Pos          (22U)
929 #define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
930 #define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
931 #define ADC_CFGR1_AWD1EN_Pos           (23U)
932 #define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
933 #define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
934 
935 #define ADC_CFGR1_AWD1CH_Pos           (26U)
936 #define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
937 #define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
938 #define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
939 #define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
940 #define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
941 #define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
942 #define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
943 
944 /* Legacy defines */
945 #define ADC_CFGR1_AUTDLY          (ADC_CFGR1_WAIT)
946 
947 /********************  Bit definition for ADC_CFGR2 register  *****************/
948 #define ADC_CFGR2_OVSE_Pos             (0U)
949 #define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
950 #define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
951 
952 #define ADC_CFGR2_OVSR_Pos             (2U)
953 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
954 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
955 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
956 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
957 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
958 
959 #define ADC_CFGR2_OVSS_Pos             (5U)
960 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
961 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
962 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
963 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
964 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
965 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
966 
967 #define ADC_CFGR2_TOVS_Pos             (9U)
968 #define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
969 #define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
970 
971 #define ADC_CFGR2_LFTRIG_Pos           (29U)
972 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
973 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
974 
975 #define ADC_CFGR2_CKMODE_Pos           (30U)
976 #define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
977 #define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
978 #define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
979 #define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
980 
981 /********************  Bit definition for ADC_SMPR register  ******************/
982 #define ADC_SMPR_SMP1_Pos              (0U)
983 #define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
984 #define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
985 #define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
986 #define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
987 #define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
988 
989 #define ADC_SMPR_SMP2_Pos              (4U)
990 #define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
991 #define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
992 #define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
993 #define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
994 #define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
995 
996 #define ADC_SMPR_SMPSEL_Pos            (8U)
997 #define ADC_SMPR_SMPSEL_Msk            (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x07FFFF00 */
998 #define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
999 #define ADC_SMPR_SMPSEL0_Pos           (8U)
1000 #define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
1001 #define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
1002 #define ADC_SMPR_SMPSEL1_Pos           (9U)
1003 #define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
1004 #define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
1005 #define ADC_SMPR_SMPSEL2_Pos           (10U)
1006 #define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
1007 #define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
1008 #define ADC_SMPR_SMPSEL3_Pos           (11U)
1009 #define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
1010 #define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
1011 #define ADC_SMPR_SMPSEL4_Pos           (12U)
1012 #define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
1013 #define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
1014 #define ADC_SMPR_SMPSEL5_Pos           (13U)
1015 #define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
1016 #define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
1017 #define ADC_SMPR_SMPSEL6_Pos           (14U)
1018 #define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
1019 #define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
1020 #define ADC_SMPR_SMPSEL7_Pos           (15U)
1021 #define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
1022 #define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
1023 #define ADC_SMPR_SMPSEL8_Pos           (16U)
1024 #define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
1025 #define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
1026 #define ADC_SMPR_SMPSEL9_Pos           (17U)
1027 #define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
1028 #define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
1029 #define ADC_SMPR_SMPSEL10_Pos          (18U)
1030 #define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
1031 #define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
1032 #define ADC_SMPR_SMPSEL11_Pos          (19U)
1033 #define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
1034 #define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
1035 #define ADC_SMPR_SMPSEL12_Pos          (20U)
1036 #define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
1037 #define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
1038 #define ADC_SMPR_SMPSEL13_Pos          (21U)
1039 #define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
1040 #define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
1041 #define ADC_SMPR_SMPSEL14_Pos          (22U)
1042 #define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
1043 #define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
1044 #define ADC_SMPR_SMPSEL15_Pos          (23U)
1045 #define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
1046 #define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
1047 #define ADC_SMPR_SMPSEL16_Pos          (24U)
1048 #define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
1049 #define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
1050 #define ADC_SMPR_SMPSEL17_Pos          (25U)
1051 #define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
1052 #define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
1053 #define ADC_SMPR_SMPSEL18_Pos          (26U)
1054 #define ADC_SMPR_SMPSEL18_Msk          (0x1UL << ADC_SMPR_SMPSEL18_Pos)        /*!< 0x04000000 */
1055 #define ADC_SMPR_SMPSEL18              ADC_SMPR_SMPSEL18_Msk                   /*!< ADC channel 18 sampling time selection */
1056 
1057 /********************  Bit definition for ADC_AWD1TR register  *******************/
1058 #define ADC_AWD1TR_LT1_Pos                (0U)
1059 #define ADC_AWD1TR_LT1_Msk             (0xFFFUL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000FFF */
1060 #define ADC_AWD1TR_LT1                 ADC_AWD1TR_LT1_Msk                      /*!< ADC analog watchdog 1 threshold low */
1061 #define ADC_AWD1TR_LT1_0               (0x001UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000001 */
1062 #define ADC_AWD1TR_LT1_1               (0x002UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000002 */
1063 #define ADC_AWD1TR_LT1_2               (0x004UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000004 */
1064 #define ADC_AWD1TR_LT1_3               (0x008UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000008 */
1065 #define ADC_AWD1TR_LT1_4               (0x010UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000010 */
1066 #define ADC_AWD1TR_LT1_5               (0x020UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000020 */
1067 #define ADC_AWD1TR_LT1_6               (0x040UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000040 */
1068 #define ADC_AWD1TR_LT1_7               (0x080UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000080 */
1069 #define ADC_AWD1TR_LT1_8               (0x100UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000100 */
1070 #define ADC_AWD1TR_LT1_9               (0x200UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000200 */
1071 #define ADC_AWD1TR_LT1_10              (0x400UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000400 */
1072 #define ADC_AWD1TR_LT1_11              (0x800UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000800 */
1073 
1074 #define ADC_AWD1TR_HT1_Pos             (16U)
1075 #define ADC_AWD1TR_HT1_Msk             (0xFFFUL << ADC_AWD1TR_HT1_Pos)         /*!< 0x0FFF0000 */
1076 #define ADC_AWD1TR_HT1                 ADC_AWD1TR_HT1_Msk                      /*!< ADC Analog watchdog 1 threshold high */
1077 #define ADC_AWD1TR_HT1_0               (0x001UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00010000 */
1078 #define ADC_AWD1TR_HT1_1               (0x002UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00020000 */
1079 #define ADC_AWD1TR_HT1_2               (0x004UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00040000 */
1080 #define ADC_AWD1TR_HT1_3               (0x008UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00080000 */
1081 #define ADC_AWD1TR_HT1_4               (0x010UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00100000 */
1082 #define ADC_AWD1TR_HT1_5               (0x020UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00200000 */
1083 #define ADC_AWD1TR_HT1_6               (0x040UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00400000 */
1084 #define ADC_AWD1TR_HT1_7               (0x080UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00800000 */
1085 #define ADC_AWD1TR_HT1_8               (0x100UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x01000000 */
1086 #define ADC_AWD1TR_HT1_9               (0x200UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x02000000 */
1087 #define ADC_AWD1TR_HT1_10              (0x400UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x04000000 */
1088 #define ADC_AWD1TR_HT1_11              (0x800UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x08000000 */
1089 
1090 /* Legacy definitions */
1091 #define ADC_TR1_LT1             ADC_AWD1TR_LT1
1092 #define ADC_TR1_LT1_0           ADC_AWD1TR_LT1_0
1093 #define ADC_TR1_LT1_1           ADC_AWD1TR_LT1_1
1094 #define ADC_TR1_LT1_2           ADC_AWD1TR_LT1_2
1095 #define ADC_TR1_LT1_3           ADC_AWD1TR_LT1_3
1096 #define ADC_TR1_LT1_4           ADC_AWD1TR_LT1_4
1097 #define ADC_TR1_LT1_5           ADC_AWD1TR_LT1_5
1098 #define ADC_TR1_LT1_6           ADC_AWD1TR_LT1_6
1099 #define ADC_TR1_LT1_7           ADC_AWD1TR_LT1_7
1100 #define ADC_TR1_LT1_8           ADC_AWD1TR_LT1_8
1101 #define ADC_TR1_LT1_9           ADC_AWD1TR_LT1_9
1102 #define ADC_TR1_LT1_10          ADC_AWD1TR_LT1_10
1103 #define ADC_TR1_LT1_11          ADC_AWD1TR_LT1_11
1104 
1105 #define ADC_TR1_HT1             ADC_AWD1TR_HT1
1106 #define ADC_TR1_HT1_0           ADC_AWD1TR_HT1_0
1107 #define ADC_TR1_HT1_1           ADC_AWD1TR_HT1_1
1108 #define ADC_TR1_HT1_2           ADC_AWD1TR_HT1_2
1109 #define ADC_TR1_HT1_3           ADC_AWD1TR_HT1_3
1110 #define ADC_TR1_HT1_4           ADC_AWD1TR_HT1_4
1111 #define ADC_TR1_HT1_5           ADC_AWD1TR_HT1_5
1112 #define ADC_TR1_HT1_6           ADC_AWD1TR_HT1_6
1113 #define ADC_TR1_HT1_7           ADC_AWD1TR_HT1_7
1114 #define ADC_TR1_HT1_8           ADC_AWD1TR_HT1_8
1115 #define ADC_TR1_HT1_9           ADC_AWD1TR_HT1_9
1116 #define ADC_TR1_HT1_10          ADC_AWD1TR_HT1_10
1117 #define ADC_TR1_HT1_11          ADC_AWD1TR_HT1_11
1118 
1119 /********************  Bit definition for ADC_AWD2TR register  *******************/
1120 #define ADC_AWD2TR_LT2_Pos             (0U)
1121 #define ADC_AWD2TR_LT2_Msk             (0xFFFUL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000FFF */
1122 #define ADC_AWD2TR_LT2                 ADC_AWD2TR_LT2_Msk                      /*!< ADC analog watchdog 2 threshold low */
1123 #define ADC_AWD2TR_LT2_0               (0x001UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000001 */
1124 #define ADC_AWD2TR_LT2_1               (0x002UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000002 */
1125 #define ADC_AWD2TR_LT2_2               (0x004UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000004 */
1126 #define ADC_AWD2TR_LT2_3               (0x008UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000008 */
1127 #define ADC_AWD2TR_LT2_4               (0x010UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000010 */
1128 #define ADC_AWD2TR_LT2_5               (0x020UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000020 */
1129 #define ADC_AWD2TR_LT2_6               (0x040UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000040 */
1130 #define ADC_AWD2TR_LT2_7               (0x080UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000080 */
1131 #define ADC_AWD2TR_LT2_8               (0x100UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000100 */
1132 #define ADC_AWD2TR_LT2_9               (0x200UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000200 */
1133 #define ADC_AWD2TR_LT2_10              (0x400UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000400 */
1134 #define ADC_AWD2TR_LT2_11              (0x800UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000800 */
1135 
1136 #define ADC_AWD2TR_HT2_Pos             (16U)
1137 #define ADC_AWD2TR_HT2_Msk             (0xFFFUL << ADC_AWD2TR_HT2_Pos)         /*!< 0x0FFF0000 */
1138 #define ADC_AWD2TR_HT2                 ADC_AWD2TR_HT2_Msk                      /*!< ADC analog watchdog 2 threshold high */
1139 #define ADC_AWD2TR_HT2_0               (0x001UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00010000 */
1140 #define ADC_AWD2TR_HT2_1               (0x002UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00020000 */
1141 #define ADC_AWD2TR_HT2_2               (0x004UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00040000 */
1142 #define ADC_AWD2TR_HT2_3               (0x008UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00080000 */
1143 #define ADC_AWD2TR_HT2_4               (0x010UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00100000 */
1144 #define ADC_AWD2TR_HT2_5               (0x020UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00200000 */
1145 #define ADC_AWD2TR_HT2_6               (0x040UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00400000 */
1146 #define ADC_AWD2TR_HT2_7               (0x080UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00800000 */
1147 #define ADC_AWD2TR_HT2_8               (0x100UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x01000000 */
1148 #define ADC_AWD2TR_HT2_9               (0x200UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x02000000 */
1149 #define ADC_AWD2TR_HT2_10              (0x400UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x04000000 */
1150 #define ADC_AWD2TR_HT2_11              (0x800UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x08000000 */
1151 
1152 /* Legacy definitions */
1153 #define ADC_TR2_LT2             ADC_AWD2TR_LT2
1154 #define ADC_TR2_LT2_0           ADC_AWD2TR_LT2_0
1155 #define ADC_TR2_LT2_1           ADC_AWD2TR_LT2_1
1156 #define ADC_TR2_LT2_2           ADC_AWD2TR_LT2_2
1157 #define ADC_TR2_LT2_3           ADC_AWD2TR_LT2_3
1158 #define ADC_TR2_LT2_4           ADC_AWD2TR_LT2_4
1159 #define ADC_TR2_LT2_5           ADC_AWD2TR_LT2_5
1160 #define ADC_TR2_LT2_6           ADC_AWD2TR_LT2_6
1161 #define ADC_TR2_LT2_7           ADC_AWD2TR_LT2_7
1162 #define ADC_TR2_LT2_8           ADC_AWD2TR_LT2_8
1163 #define ADC_TR2_LT2_9           ADC_AWD2TR_LT2_9
1164 #define ADC_TR2_LT2_10          ADC_AWD2TR_LT2_10
1165 #define ADC_TR2_LT2_11          ADC_AWD2TR_LT2_11
1166 
1167 #define ADC_TR2_HT2             ADC_AWD2TR_HT2
1168 #define ADC_TR2_HT2_0           ADC_AWD2TR_HT2_0
1169 #define ADC_TR2_HT2_1           ADC_AWD2TR_HT2_1
1170 #define ADC_TR2_HT2_2           ADC_AWD2TR_HT2_2
1171 #define ADC_TR2_HT2_3           ADC_AWD2TR_HT2_3
1172 #define ADC_TR2_HT2_4           ADC_AWD2TR_HT2_4
1173 #define ADC_TR2_HT2_5           ADC_AWD2TR_HT2_5
1174 #define ADC_TR2_HT2_6           ADC_AWD2TR_HT2_6
1175 #define ADC_TR2_HT2_7           ADC_AWD2TR_HT2_7
1176 #define ADC_TR2_HT2_8           ADC_AWD2TR_HT2_8
1177 #define ADC_TR2_HT2_9           ADC_AWD2TR_HT2_9
1178 #define ADC_TR2_HT2_10          ADC_AWD2TR_HT2_10
1179 #define ADC_TR2_HT2_11          ADC_AWD2TR_HT2_11
1180 
1181 /********************  Bit definition for ADC_CHSELR register  ****************/
1182 #define ADC_CHSELR_CHSEL_Pos           (0U)
1183 #define ADC_CHSELR_CHSEL_Msk           (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)     /*!< 0x0007FFFF */
1184 #define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1185 #define ADC_CHSELR_CHSEL18_Pos         (18U)
1186 #define ADC_CHSELR_CHSEL18_Msk         (0x1UL << ADC_CHSELR_CHSEL18_Pos)       /*!< 0x00040000 */
1187 #define ADC_CHSELR_CHSEL18             ADC_CHSELR_CHSEL18_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1188 #define ADC_CHSELR_CHSEL17_Pos         (17U)
1189 #define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
1190 #define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1191 #define ADC_CHSELR_CHSEL16_Pos         (16U)
1192 #define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
1193 #define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1194 #define ADC_CHSELR_CHSEL15_Pos         (15U)
1195 #define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
1196 #define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1197 #define ADC_CHSELR_CHSEL14_Pos         (14U)
1198 #define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
1199 #define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1200 #define ADC_CHSELR_CHSEL13_Pos         (13U)
1201 #define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
1202 #define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1203 #define ADC_CHSELR_CHSEL12_Pos         (12U)
1204 #define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
1205 #define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1206 #define ADC_CHSELR_CHSEL11_Pos         (11U)
1207 #define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
1208 #define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1209 #define ADC_CHSELR_CHSEL10_Pos         (10U)
1210 #define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
1211 #define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1212 #define ADC_CHSELR_CHSEL9_Pos          (9U)
1213 #define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
1214 #define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1215 #define ADC_CHSELR_CHSEL8_Pos          (8U)
1216 #define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
1217 #define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1218 #define ADC_CHSELR_CHSEL7_Pos          (7U)
1219 #define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
1220 #define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1221 #define ADC_CHSELR_CHSEL6_Pos          (6U)
1222 #define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
1223 #define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1224 #define ADC_CHSELR_CHSEL5_Pos          (5U)
1225 #define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
1226 #define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1227 #define ADC_CHSELR_CHSEL4_Pos          (4U)
1228 #define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
1229 #define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1230 #define ADC_CHSELR_CHSEL3_Pos          (3U)
1231 #define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
1232 #define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1233 #define ADC_CHSELR_CHSEL2_Pos          (2U)
1234 #define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
1235 #define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1236 #define ADC_CHSELR_CHSEL1_Pos          (1U)
1237 #define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
1238 #define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1239 #define ADC_CHSELR_CHSEL0_Pos          (0U)
1240 #define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
1241 #define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1242 
1243 #define ADC_CHSELR_SQ_ALL_Pos          (0U)
1244 #define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1245 #define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1246 
1247 #define ADC_CHSELR_SQ8_Pos             (28U)
1248 #define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
1249 #define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1250 #define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
1251 #define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
1252 #define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
1253 #define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
1254 
1255 #define ADC_CHSELR_SQ7_Pos             (24U)
1256 #define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
1257 #define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1258 #define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
1259 #define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
1260 #define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
1261 #define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
1262 
1263 #define ADC_CHSELR_SQ6_Pos             (20U)
1264 #define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
1265 #define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1266 #define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
1267 #define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
1268 #define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
1269 #define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
1270 
1271 #define ADC_CHSELR_SQ5_Pos             (16U)
1272 #define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
1273 #define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1274 #define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
1275 #define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
1276 #define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
1277 #define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
1278 
1279 #define ADC_CHSELR_SQ4_Pos             (12U)
1280 #define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
1281 #define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1282 #define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
1283 #define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
1284 #define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
1285 #define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
1286 
1287 #define ADC_CHSELR_SQ3_Pos             (8U)
1288 #define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
1289 #define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1290 #define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
1291 #define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
1292 #define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
1293 #define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
1294 
1295 #define ADC_CHSELR_SQ2_Pos             (4U)
1296 #define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
1297 #define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1298 #define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
1299 #define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
1300 #define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
1301 #define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
1302 
1303 #define ADC_CHSELR_SQ1_Pos             (0U)
1304 #define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
1305 #define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1306 #define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
1307 #define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
1308 #define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
1309 #define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
1310 
1311 /********************  Bit definition for ADC_AWD3TR register  *******************/
1312 #define ADC_AWD3TR_LT3_Pos             (0U)
1313 #define ADC_AWD3TR_LT3_Msk             (0xFFFUL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000FFF */
1314 #define ADC_AWD3TR_LT3                 ADC_AWD3TR_LT3_Msk                      /*!< ADC analog watchdog 3 threshold low */
1315 #define ADC_AWD3TR_LT3_0               (0x001UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000001 */
1316 #define ADC_AWD3TR_LT3_1               (0x002UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000002 */
1317 #define ADC_AWD3TR_LT3_2               (0x004UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000004 */
1318 #define ADC_AWD3TR_LT3_3               (0x008UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000008 */
1319 #define ADC_AWD3TR_LT3_4               (0x010UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000010 */
1320 #define ADC_AWD3TR_LT3_5               (0x020UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000020 */
1321 #define ADC_AWD3TR_LT3_6               (0x040UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000040 */
1322 #define ADC_AWD3TR_LT3_7               (0x080UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000080 */
1323 #define ADC_AWD3TR_LT3_8               (0x100UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000100 */
1324 #define ADC_AWD3TR_LT3_9               (0x200UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000200 */
1325 #define ADC_AWD3TR_LT3_10              (0x400UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000400 */
1326 #define ADC_AWD3TR_LT3_11              (0x800UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000800 */
1327 
1328 #define ADC_AWD3TR_HT3_Pos             (16U)
1329 #define ADC_AWD3TR_HT3_Msk             (0xFFFUL << ADC_AWD3TR_HT3_Pos)         /*!< 0x0FFF0000 */
1330 #define ADC_AWD3TR_HT3                 ADC_AWD3TR_HT3_Msk                      /*!< ADC analog watchdog 3 threshold high */
1331 #define ADC_AWD3TR_HT3_0               (0x001UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00010000 */
1332 #define ADC_AWD3TR_HT3_1               (0x002UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00020000 */
1333 #define ADC_AWD3TR_HT3_2               (0x004UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00040000 */
1334 #define ADC_AWD3TR_HT3_3               (0x008UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00080000 */
1335 #define ADC_AWD3TR_HT3_4               (0x010UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00100000 */
1336 #define ADC_AWD3TR_HT3_5               (0x020UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00200000 */
1337 #define ADC_AWD3TR_HT3_6               (0x040UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00400000 */
1338 #define ADC_AWD3TR_HT3_7               (0x080UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00800000 */
1339 #define ADC_AWD3TR_HT3_8               (0x100UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x01000000 */
1340 #define ADC_AWD3TR_HT3_9               (0x200UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x02000000 */
1341 #define ADC_AWD3TR_HT3_10              (0x400UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x04000000 */
1342 #define ADC_AWD3TR_HT3_11              (0x800UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x08000000 */
1343 
1344 /* Legacy definitions */
1345 #define ADC_TR3_LT3             ADC_AWD3TR_LT3
1346 #define ADC_TR3_LT3_0           ADC_AWD3TR_LT3_0
1347 #define ADC_TR3_LT3_1           ADC_AWD3TR_LT3_1
1348 #define ADC_TR3_LT3_2           ADC_AWD3TR_LT3_2
1349 #define ADC_TR3_LT3_3           ADC_AWD3TR_LT3_3
1350 #define ADC_TR3_LT3_4           ADC_AWD3TR_LT3_4
1351 #define ADC_TR3_LT3_5           ADC_AWD3TR_LT3_5
1352 #define ADC_TR3_LT3_6           ADC_AWD3TR_LT3_6
1353 #define ADC_TR3_LT3_7           ADC_AWD3TR_LT3_7
1354 #define ADC_TR3_LT3_8           ADC_AWD3TR_LT3_8
1355 #define ADC_TR3_LT3_9           ADC_AWD3TR_LT3_9
1356 #define ADC_TR3_LT3_10          ADC_AWD3TR_LT3_10
1357 #define ADC_TR3_LT3_11          ADC_AWD3TR_LT3_11
1358 
1359 #define ADC_TR3_HT3             ADC_AWD3TR_HT3
1360 #define ADC_TR3_HT3_0           ADC_AWD3TR_HT3_0
1361 #define ADC_TR3_HT3_1           ADC_AWD3TR_HT3_1
1362 #define ADC_TR3_HT3_2           ADC_AWD3TR_HT3_2
1363 #define ADC_TR3_HT3_3           ADC_AWD3TR_HT3_3
1364 #define ADC_TR3_HT3_4           ADC_AWD3TR_HT3_4
1365 #define ADC_TR3_HT3_5           ADC_AWD3TR_HT3_5
1366 #define ADC_TR3_HT3_6           ADC_AWD3TR_HT3_6
1367 #define ADC_TR3_HT3_7           ADC_AWD3TR_HT3_7
1368 #define ADC_TR3_HT3_8           ADC_AWD3TR_HT3_8
1369 #define ADC_TR3_HT3_9           ADC_AWD3TR_HT3_9
1370 #define ADC_TR3_HT3_10          ADC_AWD3TR_HT3_10
1371 #define ADC_TR3_HT3_11          ADC_AWD3TR_HT3_11
1372 
1373 /********************  Bit definition for ADC_DR register  ********************/
1374 #define ADC_DR_DATA_Pos                (0U)
1375 #define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
1376 #define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
1377 #define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
1378 #define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
1379 #define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
1380 #define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
1381 #define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
1382 #define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
1383 #define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
1384 #define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
1385 #define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
1386 #define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
1387 #define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
1388 #define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
1389 #define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
1390 #define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
1391 #define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
1392 #define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
1393 
1394 /********************  Bit definition for ADC_AWD2CR register  ****************/
1395 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
1396 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
1397 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1398 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
1399 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
1400 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
1401 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
1402 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
1403 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
1404 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
1405 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
1406 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
1407 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
1408 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
1409 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
1410 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
1411 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
1412 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
1413 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
1414 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
1415 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
1416 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
1417 
1418 /********************  Bit definition for ADC_AWD3CR register  ****************/
1419 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
1420 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
1421 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1422 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
1423 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
1424 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
1425 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
1426 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
1427 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
1428 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
1429 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
1430 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
1431 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
1432 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
1433 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
1434 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
1435 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
1436 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
1437 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
1438 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
1439 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
1440 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
1441 
1442 /********************  Bit definition for ADC_CALFACT register  ***************/
1443 #define ADC_CALFACT_CALFACT_Pos        (0U)
1444 #define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
1445 #define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
1446 #define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
1447 #define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
1448 #define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
1449 #define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
1450 #define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
1451 #define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
1452 #define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
1453 
1454 /*************************  ADC Common registers  *****************************/
1455 /********************  Bit definition for ADC_CCR register  *******************/
1456 #define ADC_CCR_PRESC_Pos              (18U)
1457 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
1458 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
1459 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
1460 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
1461 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
1462 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
1463 
1464 #define ADC_CCR_VREFEN_Pos             (22U)
1465 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
1466 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
1467 #define ADC_CCR_TSEN_Pos               (23U)
1468 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
1469 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
1470 #define ADC_CCR_VBATEN_Pos             (24U)
1471 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
1472 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
1473 
1474 /* Legacy */
1475 #define ADC_CCR_LFMEN_Pos              (25U)
1476 #define ADC_CCR_LFMEN_Msk              (0x1UL << ADC_CCR_LFMEN_Pos)            /*!< 0x02000000 */
1477 #define ADC_CCR_LFMEN                  ADC_CCR_LFMEN_Msk                       /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
1478 
1479 
1480 /******************************************************************************/
1481 /*                                                                            */
1482 /*                          CRC calculation unit                              */
1483 /*                                                                            */
1484 /******************************************************************************/
1485 /*******************  Bit definition for CRC_DR register  *********************/
1486 #define CRC_DR_DR_Pos            (0U)
1487 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
1488 #define CRC_DR_DR                CRC_DR_DR_Msk                                  /*!< Data register bits */
1489 
1490 /*******************  Bit definition for CRC_IDR register  ********************/
1491 #define CRC_IDR_IDR_Pos          (0U)
1492 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)              /*!< 0xFFFFFFFF */
1493 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                                /*!< General-purpose 32-bits data register bits */
1494 
1495 /********************  Bit definition for CRC_CR register  ********************/
1496 #define CRC_CR_RESET_Pos         (0U)
1497 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
1498 #define CRC_CR_RESET             CRC_CR_RESET_Msk                               /*!< RESET the CRC computation unit bit */
1499 #define CRC_CR_POLYSIZE_Pos      (3U)
1500 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
1501 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                            /*!< Polynomial size bits */
1502 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
1503 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
1504 #define CRC_CR_REV_IN_Pos        (5U)
1505 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
1506 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                              /*!< REV_IN Reverse Input Data bits */
1507 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
1508 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
1509 #define CRC_CR_REV_OUT_Pos       (7U)
1510 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
1511 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                             /*!< REV_OUT Reverse Output Data bits */
1512 
1513 /*******************  Bit definition for CRC_INIT register  *******************/
1514 #define CRC_INIT_INIT_Pos        (0U)
1515 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
1516 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                              /*!< Initial CRC value bits */
1517 
1518 /*******************  Bit definition for CRC_POL register  ********************/
1519 #define CRC_POL_POL_Pos          (0U)
1520 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
1521 #define CRC_POL_POL              CRC_POL_POL_Msk                                /*!< Coefficients of the polynomial */
1522 
1523 /******************************************************************************/
1524 /*                                                                            */
1525 /*                       Advanced Encryption Standard (AES)                   */
1526 /*                                                                            */
1527 /******************************************************************************/
1528 /*******************  Bit definition for AES_CR register  *********************/
1529 #define AES_CR_EN_Pos            (0U)
1530 #define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                       /*!< 0x00000001 */
1531 #define AES_CR_EN                AES_CR_EN_Msk                                  /*!< AES Enable */
1532 #define AES_CR_DATATYPE_Pos      (1U)
1533 #define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
1534 #define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                            /*!< Data type selection */
1535 #define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
1536 #define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
1537 
1538 #define AES_CR_MODE_Pos          (3U)
1539 #define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
1540 #define AES_CR_MODE              AES_CR_MODE_Msk                                /*!< AES Mode Of Operation */
1541 #define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
1542 #define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
1543 
1544 #define AES_CR_CHMOD_Pos         (5U)
1545 #define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                  /*!< 0x00010060 */
1546 #define AES_CR_CHMOD             AES_CR_CHMOD_Msk                               /*!< AES Chaining Mode */
1547 #define AES_CR_CHMOD_0           (0x001UL << AES_CR_CHMOD_Pos)                  /*!< 0x00000020 */
1548 #define AES_CR_CHMOD_1           (0x002UL << AES_CR_CHMOD_Pos)                  /*!< 0x00000040 */
1549 #define AES_CR_CHMOD_2           (0x800UL << AES_CR_CHMOD_Pos)                  /*!< 0x00010000 */
1550 
1551 #define AES_CR_CCFC_Pos          (7U)
1552 #define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
1553 #define AES_CR_CCFC              AES_CR_CCFC_Msk                                /*!< Computation Complete Flag Clear */
1554 #define AES_CR_ERRC_Pos          (8U)
1555 #define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
1556 #define AES_CR_ERRC              AES_CR_ERRC_Msk                                /*!< Error Clear */
1557 #define AES_CR_CCFIE_Pos         (9U)
1558 #define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                    /*!< 0x00000200 */
1559 #define AES_CR_CCFIE             AES_CR_CCFIE_Msk                               /*!< Computation Complete Flag Interrupt Enable */
1560 #define AES_CR_ERRIE_Pos         (10U)
1561 #define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
1562 #define AES_CR_ERRIE             AES_CR_ERRIE_Msk                               /*!< Error Interrupt Enable */
1563 #define AES_CR_DMAINEN_Pos       (11U)
1564 #define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
1565 #define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                             /*!< Enable data input phase DMA management  */
1566 #define AES_CR_DMAOUTEN_Pos      (12U)
1567 #define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
1568 #define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                            /*!< Enable data output phase DMA management */
1569 
1570 #define AES_CR_NPBLB_Pos         (20U)
1571 #define AES_CR_NPBLB_Msk         (0xFUL << AES_CR_NPBLB_Pos)                    /*!< 0x00F00000 */
1572 #define AES_CR_NPBLB             AES_CR_NPBLB_Msk                               /*!< Number of padding bytes in last block of payload. */
1573 #define AES_CR_NPBLB_0           (0x1UL << AES_CR_NPBLB_Pos)                    /*!< 0x00100000 */
1574 #define AES_CR_NPBLB_1           (0x2UL << AES_CR_NPBLB_Pos)                    /*!< 0x00200000 */
1575 #define AES_CR_NPBLB_2           (0x4UL << AES_CR_NPBLB_Pos)                    /*!< 0x00400000 */
1576 #define AES_CR_NPBLB_3           (0x8UL << AES_CR_NPBLB_Pos)                    /*!< 0x00800000 */
1577 
1578 #define AES_CR_GCMPH_Pos         (13U)
1579 #define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                    /*!< 0x00006000 */
1580 #define AES_CR_GCMPH             AES_CR_GCMPH_Msk                               /*!< GCM Phase */
1581 #define AES_CR_GCMPH_0           (0x1UL << AES_CR_GCMPH_Pos)                    /*!< 0x00002000 */
1582 #define AES_CR_GCMPH_1           (0x2UL << AES_CR_GCMPH_Pos)                    /*!< 0x00004000 */
1583 
1584 #define AES_CR_KEYSIZE_Pos       (18U)
1585 #define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                  /*!< 0x00040000 */
1586 #define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                             /*!< Key size selection */
1587 
1588 /*******************  Bit definition for AES_SR register  *********************/
1589 #define AES_SR_CCF_Pos           (0U)
1590 #define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
1591 #define AES_SR_CCF               AES_SR_CCF_Msk                                 /*!< Computation Complete Flag */
1592 #define AES_SR_RDERR_Pos         (1U)
1593 #define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
1594 #define AES_SR_RDERR             AES_SR_RDERR_Msk                               /*!< Read Error Flag */
1595 #define AES_SR_WRERR_Pos         (2U)
1596 #define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
1597 #define AES_SR_WRERR             AES_SR_WRERR_Msk                               /*!< Write Error Flag */
1598 #define AES_SR_BUSY_Pos          (3U)
1599 #define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                     /*!< 0x00000008 */
1600 #define AES_SR_BUSY              AES_SR_BUSY_Msk                                /*!< Busy Flag */
1601 
1602 /*******************  Bit definition for AES_DINR register  *******************/
1603 #define AES_DINR_Pos             (0U)
1604 #define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                 /*!< 0xFFFFFFFF */
1605 #define AES_DINR                 AES_DINR_Msk                                   /*!< AES Data Input Register */
1606 
1607 /*******************  Bit definition for AES_DOUTR register  ******************/
1608 #define AES_DOUTR_Pos            (0U)
1609 #define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)                /*!< 0xFFFFFFFF */
1610 #define AES_DOUTR                AES_DOUTR_Msk                                  /*!< AES Data Output Register */
1611 
1612 /*******************  Bit definition for AES_KEYR0 register  ******************/
1613 #define AES_KEYR0_Pos            (0U)
1614 #define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)                /*!< 0xFFFFFFFF */
1615 #define AES_KEYR0                AES_KEYR0_Msk                                  /*!< AES Key Register 0 */
1616 
1617 /*******************  Bit definition for AES_KEYR1 register  ******************/
1618 #define AES_KEYR1_Pos            (0U)
1619 #define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)                /*!< 0xFFFFFFFF */
1620 #define AES_KEYR1                AES_KEYR1_Msk                                  /*!< AES Key Register 1 */
1621 
1622 /*******************  Bit definition for AES_KEYR2 register  ******************/
1623 #define AES_KEYR2_Pos            (0U)
1624 #define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)                /*!< 0xFFFFFFFF */
1625 #define AES_KEYR2                AES_KEYR2_Msk                                  /*!< AES Key Register 2 */
1626 
1627 /*******************  Bit definition for AES_KEYR3 register  ******************/
1628 #define AES_KEYR3_Pos            (0U)
1629 #define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)                /*!< 0xFFFFFFFF */
1630 #define AES_KEYR3                AES_KEYR3_Msk                                  /*!< AES Key Register 3 */
1631 
1632 /*******************  Bit definition for AES_KEYR4 register  ******************/
1633 #define AES_KEYR4_Pos            (0U)
1634 #define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)                /*!< 0xFFFFFFFF */
1635 #define AES_KEYR4                AES_KEYR4_Msk                                  /*!< AES Key Register 4 */
1636 
1637 /*******************  Bit definition for AES_KEYR5 register  ******************/
1638 #define AES_KEYR5_Pos            (0U)
1639 #define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)                /*!< 0xFFFFFFFF */
1640 #define AES_KEYR5                AES_KEYR5_Msk                                  /*!< AES Key Register 5 */
1641 
1642 /*******************  Bit definition for AES_KEYR6 register  ******************/
1643 #define AES_KEYR6_Pos            (0U)
1644 #define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)                /*!< 0xFFFFFFFF */
1645 #define AES_KEYR6                AES_KEYR6_Msk                                  /*!< AES Key Register 6 */
1646 
1647 /*******************  Bit definition for AES_KEYR7 register  ******************/
1648 #define AES_KEYR7_Pos            (0U)
1649 #define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)                /*!< 0xFFFFFFFF */
1650 #define AES_KEYR7                AES_KEYR7_Msk                                  /*!< AES Key Register 7 */
1651 
1652 /*******************  Bit definition for AES_IVR0 register   ******************/
1653 #define AES_IVR0_Pos             (0U)
1654 #define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                 /*!< 0xFFFFFFFF */
1655 #define AES_IVR0                 AES_IVR0_Msk                                   /*!< AES Initialization Vector Register 0 */
1656 
1657 /*******************  Bit definition for AES_IVR1 register   ******************/
1658 #define AES_IVR1_Pos             (0U)
1659 #define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                 /*!< 0xFFFFFFFF */
1660 #define AES_IVR1                 AES_IVR1_Msk                                   /*!< AES Initialization Vector Register 1 */
1661 
1662 /*******************  Bit definition for AES_IVR2 register   ******************/
1663 #define AES_IVR2_Pos             (0U)
1664 #define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
1665 #define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
1666 
1667 /*******************  Bit definition for AES_IVR3 register   ******************/
1668 #define AES_IVR3_Pos             (0U)
1669 #define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
1670 #define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
1671 
1672 /*******************  Bit definition for AES_SUSP0R register  ******************/
1673 #define AES_SUSP0R_Pos           (0U)
1674 #define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
1675 #define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
1676 
1677 /*******************  Bit definition for AES_SUSP1R register  ******************/
1678 #define AES_SUSP1R_Pos           (0U)
1679 #define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
1680 #define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
1681 
1682 /*******************  Bit definition for AES_SUSP2R register  ******************/
1683 #define AES_SUSP2R_Pos           (0U)
1684 #define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
1685 #define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
1686 
1687 /*******************  Bit definition for AES_SUSP3R register  ******************/
1688 #define AES_SUSP3R_Pos           (0U)
1689 #define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
1690 #define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
1691 
1692 /*******************  Bit definition for AES_SUSP4R register  ******************/
1693 #define AES_SUSP4R_Pos           (0U)
1694 #define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
1695 #define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
1696 
1697 /*******************  Bit definition for AES_SUSP5R register  ******************/
1698 #define AES_SUSP5R_Pos           (0U)
1699 #define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
1700 #define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
1701 
1702 /*******************  Bit definition for AES_SUSP6R register  ******************/
1703 #define AES_SUSP6R_Pos           (0U)
1704 #define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
1705 #define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
1706 
1707 /*******************  Bit definition for AES_SUSP7R register  ******************/
1708 #define AES_SUSP7R_Pos           (0U)
1709 #define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
1710 #define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
1711 
1712 
1713 
1714 /******************************************************************************/
1715 /*                                                                            */
1716 /*                                 Debug MCU                                  */
1717 /*                                                                            */
1718 /******************************************************************************/
1719 
1720 /******************************************************************************/
1721 /*                                                                            */
1722 /*                           DMA Controller (DMA)                             */
1723 /*                                                                            */
1724 /******************************************************************************/
1725 
1726 /*******************  Bit definition for DMA_ISR register  ********************/
1727 #define DMA_ISR_GIF1_Pos       (0U)
1728 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
1729 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
1730 #define DMA_ISR_TCIF1_Pos      (1U)
1731 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
1732 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
1733 #define DMA_ISR_HTIF1_Pos      (2U)
1734 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
1735 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
1736 #define DMA_ISR_TEIF1_Pos      (3U)
1737 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
1738 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
1739 #define DMA_ISR_GIF2_Pos       (4U)
1740 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
1741 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
1742 #define DMA_ISR_TCIF2_Pos      (5U)
1743 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
1744 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
1745 #define DMA_ISR_HTIF2_Pos      (6U)
1746 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
1747 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
1748 #define DMA_ISR_TEIF2_Pos      (7U)
1749 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
1750 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
1751 #define DMA_ISR_GIF3_Pos       (8U)
1752 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
1753 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
1754 #define DMA_ISR_TCIF3_Pos      (9U)
1755 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
1756 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
1757 #define DMA_ISR_HTIF3_Pos      (10U)
1758 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
1759 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
1760 #define DMA_ISR_TEIF3_Pos      (11U)
1761 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
1762 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
1763 #define DMA_ISR_GIF4_Pos       (12U)
1764 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
1765 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
1766 #define DMA_ISR_TCIF4_Pos      (13U)
1767 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
1768 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
1769 #define DMA_ISR_HTIF4_Pos      (14U)
1770 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
1771 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
1772 #define DMA_ISR_TEIF4_Pos      (15U)
1773 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
1774 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
1775 #define DMA_ISR_GIF5_Pos       (16U)
1776 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
1777 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
1778 #define DMA_ISR_TCIF5_Pos      (17U)
1779 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
1780 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
1781 #define DMA_ISR_HTIF5_Pos      (18U)
1782 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
1783 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
1784 #define DMA_ISR_TEIF5_Pos      (19U)
1785 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
1786 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
1787 #define DMA_ISR_GIF6_Pos       (20U)
1788 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
1789 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
1790 #define DMA_ISR_TCIF6_Pos      (21U)
1791 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
1792 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
1793 #define DMA_ISR_HTIF6_Pos      (22U)
1794 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
1795 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
1796 #define DMA_ISR_TEIF6_Pos      (23U)
1797 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
1798 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
1799 #define DMA_ISR_GIF7_Pos       (24U)
1800 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
1801 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
1802 #define DMA_ISR_TCIF7_Pos      (25U)
1803 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
1804 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
1805 #define DMA_ISR_HTIF7_Pos      (26U)
1806 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
1807 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
1808 #define DMA_ISR_TEIF7_Pos      (27U)
1809 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
1810 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
1811 
1812 /*******************  Bit definition for DMA_IFCR register  *******************/
1813 #define DMA_IFCR_CGIF1_Pos     (0U)
1814 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
1815 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
1816 #define DMA_IFCR_CTCIF1_Pos    (1U)
1817 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
1818 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
1819 #define DMA_IFCR_CHTIF1_Pos    (2U)
1820 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
1821 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
1822 #define DMA_IFCR_CTEIF1_Pos    (3U)
1823 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
1824 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
1825 #define DMA_IFCR_CGIF2_Pos     (4U)
1826 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
1827 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
1828 #define DMA_IFCR_CTCIF2_Pos    (5U)
1829 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
1830 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
1831 #define DMA_IFCR_CHTIF2_Pos    (6U)
1832 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
1833 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
1834 #define DMA_IFCR_CTEIF2_Pos    (7U)
1835 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
1836 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
1837 #define DMA_IFCR_CGIF3_Pos     (8U)
1838 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
1839 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
1840 #define DMA_IFCR_CTCIF3_Pos    (9U)
1841 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
1842 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
1843 #define DMA_IFCR_CHTIF3_Pos    (10U)
1844 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
1845 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
1846 #define DMA_IFCR_CTEIF3_Pos    (11U)
1847 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
1848 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
1849 #define DMA_IFCR_CGIF4_Pos     (12U)
1850 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
1851 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
1852 #define DMA_IFCR_CTCIF4_Pos    (13U)
1853 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
1854 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
1855 #define DMA_IFCR_CHTIF4_Pos    (14U)
1856 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
1857 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
1858 #define DMA_IFCR_CTEIF4_Pos    (15U)
1859 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
1860 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
1861 #define DMA_IFCR_CGIF5_Pos     (16U)
1862 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
1863 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
1864 #define DMA_IFCR_CTCIF5_Pos    (17U)
1865 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
1866 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
1867 #define DMA_IFCR_CHTIF5_Pos    (18U)
1868 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
1869 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
1870 #define DMA_IFCR_CTEIF5_Pos    (19U)
1871 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
1872 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
1873 #define DMA_IFCR_CGIF6_Pos     (20U)
1874 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
1875 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
1876 #define DMA_IFCR_CTCIF6_Pos    (21U)
1877 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
1878 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
1879 #define DMA_IFCR_CHTIF6_Pos    (22U)
1880 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
1881 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
1882 #define DMA_IFCR_CTEIF6_Pos    (23U)
1883 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
1884 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
1885 #define DMA_IFCR_CGIF7_Pos     (24U)
1886 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
1887 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
1888 #define DMA_IFCR_CTCIF7_Pos    (25U)
1889 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
1890 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
1891 #define DMA_IFCR_CHTIF7_Pos    (26U)
1892 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
1893 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
1894 #define DMA_IFCR_CTEIF7_Pos    (27U)
1895 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
1896 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
1897 
1898 /*******************  Bit definition for DMA_CCR register  ********************/
1899 #define DMA_CCR_EN_Pos         (0U)
1900 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
1901 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
1902 #define DMA_CCR_TCIE_Pos       (1U)
1903 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
1904 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
1905 #define DMA_CCR_HTIE_Pos       (2U)
1906 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
1907 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
1908 #define DMA_CCR_TEIE_Pos       (3U)
1909 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
1910 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
1911 #define DMA_CCR_DIR_Pos        (4U)
1912 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
1913 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
1914 #define DMA_CCR_CIRC_Pos       (5U)
1915 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
1916 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
1917 #define DMA_CCR_PINC_Pos       (6U)
1918 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
1919 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
1920 #define DMA_CCR_MINC_Pos       (7U)
1921 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
1922 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
1923 
1924 #define DMA_CCR_PSIZE_Pos      (8U)
1925 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
1926 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
1927 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
1928 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
1929 
1930 #define DMA_CCR_MSIZE_Pos      (10U)
1931 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
1932 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
1933 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
1934 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
1935 
1936 #define DMA_CCR_PL_Pos         (12U)
1937 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
1938 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
1939 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
1940 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
1941 
1942 #define DMA_CCR_MEM2MEM_Pos    (14U)
1943 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
1944 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
1945 
1946 /******************  Bit definition for DMA_CNDTR register  *******************/
1947 #define DMA_CNDTR_NDT_Pos      (0U)
1948 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
1949 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
1950 
1951 /******************  Bit definition for DMA_CPAR register  ********************/
1952 #define DMA_CPAR_PA_Pos        (0U)
1953 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
1954 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
1955 
1956 /******************  Bit definition for DMA_CMAR register  ********************/
1957 #define DMA_CMAR_MA_Pos        (0U)
1958 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
1959 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
1960 
1961 /******************************************************************************/
1962 /*                                                                            */
1963 /*                             DMAMUX Controller                              */
1964 /*                                                                            */
1965 /******************************************************************************/
1966 /********************  Bits definition for DMAMUX_CxCR register  **************/
1967 #define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
1968 #define DMAMUX_CxCR_DMAREQ_ID_Msk              (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
1969 #define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk             /*!< DMA Request ID   */
1970 #define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
1971 #define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
1972 #define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
1973 #define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
1974 #define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
1975 #define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
1976 #define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
1977 #define DMAMUX_CxCR_SOIE_Pos                   (8U)
1978 #define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos)  /*!< 0x00000100 */
1979 #define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk             /*!< Synchro overrun interrupt enable     */
1980 #define DMAMUX_CxCR_EGE_Pos                    (9U)
1981 #define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)   /*!< 0x00000200 */
1982 #define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk              /*!< Event generation interrupt enable    */
1983 #define DMAMUX_CxCR_SE_Pos                     (16U)
1984 #define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)    /*!< 0x00010000 */
1985 #define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk               /*!< Synchronization enable               */
1986 #define DMAMUX_CxCR_SPOL_Pos                   (17U)
1987 #define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00060000 */
1988 #define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk             /*!< Synchronization polarity             */
1989 #define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00020000 */
1990 #define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00040000 */
1991 #define DMAMUX_CxCR_NBREQ_Pos                  (19U)
1992 #define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
1993 #define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk             /*!< Number of request                    */
1994 #define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
1995 #define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
1996 #define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
1997 #define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
1998 #define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
1999 #define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
2000 #define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2001 #define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk             /*!< Synchronization ID                   */
2002 #define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2003 #define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2004 #define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2005 #define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2006 #define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2007 
2008 /*******************  Bits definition for DMAMUX_CSR register  **************/
2009 #define DMAMUX_CSR_SOF0_Pos                    (0U)
2010 #define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */
2011 #define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */
2012 #define DMAMUX_CSR_SOF1_Pos                    (1U)
2013 #define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */
2014 #define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */
2015 #define DMAMUX_CSR_SOF2_Pos                    (2U)
2016 #define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */
2017 #define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */
2018 #define DMAMUX_CSR_SOF3_Pos                    (3U)
2019 #define DMAMUX_CSR_SOF3_Msk                    (0x1UL << DMAMUX_CSR_SOF3_Pos)  /*!< 0x00000008 */
2020 #define DMAMUX_CSR_SOF3                        DMAMUX_CSR_SOF3_Msk             /*!< Synchronization Overrun Flag 3       */
2021 #define DMAMUX_CSR_SOF4_Pos                    (4U)
2022 #define DMAMUX_CSR_SOF4_Msk                    (0x1UL << DMAMUX_CSR_SOF4_Pos)  /*!< 0x00000010 */
2023 #define DMAMUX_CSR_SOF4                        DMAMUX_CSR_SOF4_Msk             /*!< Synchronization Overrun Flag 4       */
2024 #define DMAMUX_CSR_SOF5_Pos                    (5U)
2025 #define DMAMUX_CSR_SOF5_Msk                    (0x1UL << DMAMUX_CSR_SOF5_Pos)  /*!< 0x00000020 */
2026 #define DMAMUX_CSR_SOF5                        DMAMUX_CSR_SOF5_Msk             /*!< Synchronization Overrun Flag 5       */
2027 #define DMAMUX_CSR_SOF6_Pos                    (6U)
2028 #define DMAMUX_CSR_SOF6_Msk                    (0x1UL << DMAMUX_CSR_SOF6_Pos)  /*!< 0x00000040 */
2029 #define DMAMUX_CSR_SOF6                        DMAMUX_CSR_SOF6_Msk             /*!< Synchronization Overrun Flag 6       */
2030 
2031 /********************  Bits definition for DMAMUX_CFR register  **************/
2032 #define DMAMUX_CFR_CSOF0_Pos                   (0U)
2033 #define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos)  /*!< 0x00000001 */
2034 #define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk             /*!< Clear Overrun Flag 0                 */
2035 #define DMAMUX_CFR_CSOF1_Pos                   (1U)
2036 #define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos)  /*!< 0x00000002 */
2037 #define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk             /*!< Clear Overrun Flag 1                 */
2038 #define DMAMUX_CFR_CSOF2_Pos                   (2U)
2039 #define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos)  /*!< 0x00000004 */
2040 #define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk             /*!< Clear Overrun Flag 2                 */
2041 #define DMAMUX_CFR_CSOF3_Pos                   (3U)
2042 #define DMAMUX_CFR_CSOF3_Msk                   (0x1UL << DMAMUX_CFR_CSOF3_Pos)  /*!< 0x00000008 */
2043 #define DMAMUX_CFR_CSOF3                       DMAMUX_CFR_CSOF3_Msk             /*!< Clear Overrun Flag 3                 */
2044 #define DMAMUX_CFR_CSOF4_Pos                   (4U)
2045 #define DMAMUX_CFR_CSOF4_Msk                   (0x1UL << DMAMUX_CFR_CSOF4_Pos)  /*!< 0x00000010 */
2046 #define DMAMUX_CFR_CSOF4                       DMAMUX_CFR_CSOF4_Msk             /*!< Clear Overrun Flag 4                 */
2047 #define DMAMUX_CFR_CSOF5_Pos                   (5U)
2048 #define DMAMUX_CFR_CSOF5_Msk                   (0x1UL << DMAMUX_CFR_CSOF5_Pos)  /*!< 0x00000020 */
2049 #define DMAMUX_CFR_CSOF5                       DMAMUX_CFR_CSOF5_Msk             /*!< Clear Overrun Flag 5                 */
2050 #define DMAMUX_CFR_CSOF6_Pos                   (6U)
2051 #define DMAMUX_CFR_CSOF6_Msk                   (0x1UL << DMAMUX_CFR_CSOF6_Pos)  /*!< 0x00000040 */
2052 #define DMAMUX_CFR_CSOF6                       DMAMUX_CFR_CSOF6_Msk             /*!< Clear Overrun Flag 6                 */
2053 
2054 /********************  Bits definition for DMAMUX_RGxCR register  ************/
2055 #define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
2056 #define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2057 #define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk             /*!< Signal ID                         */
2058 #define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2059 #define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2060 #define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2061 #define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2062 #define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2063 #define DMAMUX_RGxCR_OIE_Pos                   (8U)
2064 #define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos)  /*!< 0x00000100 */
2065 #define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk             /*!< Overrun interrupt enable             */
2066 #define DMAMUX_RGxCR_GE_Pos                    (16U)
2067 #define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)   /*!< 0x00010000 */
2068 #define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk              /*!< Generation enable                    */
2069 #define DMAMUX_RGxCR_GPOL_Pos                  (17U)
2070 #define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2071 #define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk            /*!< Generation polarity                  */
2072 #define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2073 #define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2074 #define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
2075 #define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2076 #define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk             /*!< Number of request                 */
2077 #define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2078 #define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2079 #define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2080 #define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2081 #define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2082 
2083 /********************  Bits definition for DMAMUX_RGSR register  **************/
2084 #define DMAMUX_RGSR_OF0_Pos                    (0U)
2085 #define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)   /*!< 0x00000001 */
2086 #define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk              /*!< Overrun flag 0                       */
2087 #define DMAMUX_RGSR_OF1_Pos                    (1U)
2088 #define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)   /*!< 0x00000002 */
2089 #define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk              /*!< Overrun flag 1                       */
2090 #define DMAMUX_RGSR_OF2_Pos                    (2U)
2091 #define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)   /*!< 0x00000004 */
2092 #define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk              /*!< Overrun flag 2                       */
2093 #define DMAMUX_RGSR_OF3_Pos                    (3U)
2094 #define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)   /*!< 0x00000008 */
2095 #define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk              /*!< Overrun flag 3                       */
2096 
2097 /********************  Bits definition for DMAMUX_RGCFR register  **************/
2098 #define DMAMUX_RGCFR_COF0_Pos                  (0U)
2099 #define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2100 #define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk            /*!< Clear Overrun flag 0                 */
2101 #define DMAMUX_RGCFR_COF1_Pos                  (1U)
2102 #define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2103 #define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk            /*!< Clear Overrun flag 1                 */
2104 #define DMAMUX_RGCFR_COF2_Pos                  (2U)
2105 #define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2106 #define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk            /*!< Clear Overrun flag 2                 */
2107 #define DMAMUX_RGCFR_COF3_Pos                  (3U)
2108 #define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2109 #define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk            /*!< Clear Overrun flag 3                 */
2110 
2111 /******************************************************************************/
2112 /*                                                                            */
2113 /*                    External Interrupt/Event Controller                     */
2114 /*                                                                            */
2115 /******************************************************************************/
2116 /******************  Bit definition for EXTI_RTSR1 register  ******************/
2117 #define EXTI_RTSR1_RT0_Pos           (0U)
2118 #define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
2119 #define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
2120 #define EXTI_RTSR1_RT1_Pos           (1U)
2121 #define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
2122 #define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
2123 #define EXTI_RTSR1_RT2_Pos           (2U)
2124 #define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
2125 #define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
2126 #define EXTI_RTSR1_RT3_Pos           (3U)
2127 #define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
2128 #define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
2129 #define EXTI_RTSR1_RT4_Pos           (4U)
2130 #define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
2131 #define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
2132 #define EXTI_RTSR1_RT5_Pos           (5U)
2133 #define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
2134 #define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
2135 #define EXTI_RTSR1_RT6_Pos           (6U)
2136 #define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
2137 #define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
2138 #define EXTI_RTSR1_RT7_Pos           (7U)
2139 #define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
2140 #define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
2141 #define EXTI_RTSR1_RT8_Pos           (8U)
2142 #define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
2143 #define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
2144 #define EXTI_RTSR1_RT9_Pos           (9U)
2145 #define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
2146 #define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
2147 #define EXTI_RTSR1_RT10_Pos          (10U)
2148 #define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
2149 #define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
2150 #define EXTI_RTSR1_RT11_Pos          (11U)
2151 #define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
2152 #define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
2153 #define EXTI_RTSR1_RT12_Pos          (12U)
2154 #define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
2155 #define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
2156 #define EXTI_RTSR1_RT13_Pos          (13U)
2157 #define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
2158 #define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
2159 #define EXTI_RTSR1_RT14_Pos          (14U)
2160 #define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
2161 #define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
2162 #define EXTI_RTSR1_RT15_Pos          (15U)
2163 #define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
2164 #define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
2165 #define EXTI_RTSR1_RT16_Pos          (16U)
2166 #define EXTI_RTSR1_RT16_Msk          (0x1UL << EXTI_RTSR1_RT16_Pos)            /*!< 0x00010000 */
2167 #define EXTI_RTSR1_RT16              EXTI_RTSR1_RT16_Msk                       /*!< Rising trigger configuration for input line 16 */
2168 
2169 /******************  Bit definition for EXTI_FTSR1 register  ******************/
2170 #define EXTI_FTSR1_FT0_Pos           (0U)
2171 #define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
2172 #define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
2173 #define EXTI_FTSR1_FT1_Pos           (1U)
2174 #define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
2175 #define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
2176 #define EXTI_FTSR1_FT2_Pos           (2U)
2177 #define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
2178 #define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
2179 #define EXTI_FTSR1_FT3_Pos           (3U)
2180 #define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
2181 #define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
2182 #define EXTI_FTSR1_FT4_Pos           (4U)
2183 #define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
2184 #define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
2185 #define EXTI_FTSR1_FT5_Pos           (5U)
2186 #define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
2187 #define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
2188 #define EXTI_FTSR1_FT6_Pos           (6U)
2189 #define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
2190 #define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
2191 #define EXTI_FTSR1_FT7_Pos           (7U)
2192 #define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
2193 #define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
2194 #define EXTI_FTSR1_FT8_Pos           (8U)
2195 #define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
2196 #define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
2197 #define EXTI_FTSR1_FT9_Pos           (9U)
2198 #define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
2199 #define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
2200 #define EXTI_FTSR1_FT10_Pos          (10U)
2201 #define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
2202 #define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
2203 #define EXTI_FTSR1_FT11_Pos          (11U)
2204 #define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
2205 #define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
2206 #define EXTI_FTSR1_FT12_Pos          (12U)
2207 #define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
2208 #define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
2209 #define EXTI_FTSR1_FT13_Pos          (13U)
2210 #define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
2211 #define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
2212 #define EXTI_FTSR1_FT14_Pos          (14U)
2213 #define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
2214 #define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
2215 #define EXTI_FTSR1_FT15_Pos          (15U)
2216 #define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
2217 #define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
2218 #define EXTI_FTSR1_FT16_Pos          (16U)
2219 #define EXTI_FTSR1_FT16_Msk          (0x1UL << EXTI_FTSR1_FT16_Pos)            /*!< 0x00010000 */
2220 #define EXTI_FTSR1_FT16              EXTI_FTSR1_FT16_Msk                       /*!< Falling trigger configuration for input line 16 */
2221 
2222 /******************  Bit definition for EXTI_SWIER1 register  *****************/
2223 #define EXTI_SWIER1_SWI0_Pos         (0U)
2224 #define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
2225 #define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
2226 #define EXTI_SWIER1_SWI1_Pos         (1U)
2227 #define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
2228 #define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
2229 #define EXTI_SWIER1_SWI2_Pos         (2U)
2230 #define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
2231 #define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
2232 #define EXTI_SWIER1_SWI3_Pos         (3U)
2233 #define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
2234 #define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
2235 #define EXTI_SWIER1_SWI4_Pos         (4U)
2236 #define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
2237 #define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
2238 #define EXTI_SWIER1_SWI5_Pos         (5U)
2239 #define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
2240 #define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
2241 #define EXTI_SWIER1_SWI6_Pos         (6U)
2242 #define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
2243 #define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
2244 #define EXTI_SWIER1_SWI7_Pos         (7U)
2245 #define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
2246 #define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
2247 #define EXTI_SWIER1_SWI8_Pos         (8U)
2248 #define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
2249 #define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
2250 #define EXTI_SWIER1_SWI9_Pos         (9U)
2251 #define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
2252 #define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
2253 #define EXTI_SWIER1_SWI10_Pos        (10U)
2254 #define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
2255 #define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
2256 #define EXTI_SWIER1_SWI11_Pos        (11U)
2257 #define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
2258 #define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
2259 #define EXTI_SWIER1_SWI12_Pos        (12U)
2260 #define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
2261 #define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
2262 #define EXTI_SWIER1_SWI13_Pos        (13U)
2263 #define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
2264 #define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
2265 #define EXTI_SWIER1_SWI14_Pos        (14U)
2266 #define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
2267 #define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
2268 #define EXTI_SWIER1_SWI15_Pos        (15U)
2269 #define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
2270 #define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
2271 #define EXTI_SWIER1_SWI16_Pos        (16U)
2272 #define EXTI_SWIER1_SWI16_Msk        (0x1UL << EXTI_SWIER1_SWI16_Pos)          /*!< 0x00010000 */
2273 #define EXTI_SWIER1_SWI16            EXTI_SWIER1_SWI16_Msk                     /*!< Software Interrupt on line 16 */
2274 
2275 /*******************  Bit definition for EXTI_RPR1 register  ******************/
2276 #define EXTI_RPR1_RPIF0_Pos          (0U)
2277 #define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
2278 #define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
2279 #define EXTI_RPR1_RPIF1_Pos          (1U)
2280 #define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
2281 #define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
2282 #define EXTI_RPR1_RPIF2_Pos          (2U)
2283 #define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
2284 #define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
2285 #define EXTI_RPR1_RPIF3_Pos          (3U)
2286 #define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
2287 #define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
2288 #define EXTI_RPR1_RPIF4_Pos          (4U)
2289 #define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
2290 #define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
2291 #define EXTI_RPR1_RPIF5_Pos          (5U)
2292 #define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
2293 #define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
2294 #define EXTI_RPR1_RPIF6_Pos          (6U)
2295 #define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
2296 #define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
2297 #define EXTI_RPR1_RPIF7_Pos          (7U)
2298 #define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
2299 #define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
2300 #define EXTI_RPR1_RPIF8_Pos          (8U)
2301 #define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
2302 #define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
2303 #define EXTI_RPR1_RPIF9_Pos          (9U)
2304 #define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
2305 #define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
2306 #define EXTI_RPR1_RPIF10_Pos         (10U)
2307 #define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
2308 #define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
2309 #define EXTI_RPR1_RPIF11_Pos         (11U)
2310 #define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
2311 #define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
2312 #define EXTI_RPR1_RPIF12_Pos         (12U)
2313 #define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
2314 #define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
2315 #define EXTI_RPR1_RPIF13_Pos         (13U)
2316 #define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
2317 #define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
2318 #define EXTI_RPR1_RPIF14_Pos         (14U)
2319 #define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
2320 #define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
2321 #define EXTI_RPR1_RPIF15_Pos         (15U)
2322 #define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
2323 #define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
2324 #define EXTI_RPR1_RPIF16_Pos         (16U)
2325 #define EXTI_RPR1_RPIF16_Msk         (0x1UL << EXTI_RPR1_RPIF16_Pos)           /*!< 0x00010000 */
2326 #define EXTI_RPR1_RPIF16             EXTI_RPR1_RPIF16_Msk                      /*!< Rising Pending Interrupt Flag on line 16 */
2327 
2328 /*******************  Bit definition for EXTI_FPR1 register  ******************/
2329 #define EXTI_FPR1_FPIF0_Pos          (0U)
2330 #define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
2331 #define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
2332 #define EXTI_FPR1_FPIF1_Pos          (1U)
2333 #define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
2334 #define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
2335 #define EXTI_FPR1_FPIF2_Pos          (2U)
2336 #define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
2337 #define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
2338 #define EXTI_FPR1_FPIF3_Pos          (3U)
2339 #define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
2340 #define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
2341 #define EXTI_FPR1_FPIF4_Pos          (4U)
2342 #define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
2343 #define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
2344 #define EXTI_FPR1_FPIF5_Pos          (5U)
2345 #define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
2346 #define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
2347 #define EXTI_FPR1_FPIF6_Pos          (6U)
2348 #define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
2349 #define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
2350 #define EXTI_FPR1_FPIF7_Pos          (7U)
2351 #define EXTI_FPR1_FPIF7_Msk          (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
2352 #define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
2353 #define EXTI_FPR1_FPIF8_Pos          (8U)
2354 #define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
2355 #define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
2356 #define EXTI_FPR1_FPIF9_Pos          (9U)
2357 #define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
2358 #define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
2359 #define EXTI_FPR1_FPIF10_Pos         (10U)
2360 #define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
2361 #define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
2362 #define EXTI_FPR1_FPIF11_Pos         (11U)
2363 #define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
2364 #define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
2365 #define EXTI_FPR1_FPIF12_Pos         (12U)
2366 #define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
2367 #define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
2368 #define EXTI_FPR1_FPIF13_Pos         (13U)
2369 #define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */
2370 #define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
2371 #define EXTI_FPR1_FPIF14_Pos         (14U)
2372 #define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */
2373 #define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
2374 #define EXTI_FPR1_FPIF15_Pos         (15U)
2375 #define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */
2376 #define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
2377 #define EXTI_FPR1_FPIF16_Pos         (16U)
2378 #define EXTI_FPR1_FPIF16_Msk         (0x1UL << EXTI_FPR1_FPIF16_Pos)           /*!< 0x00010000 */
2379 #define EXTI_FPR1_FPIF16             EXTI_FPR1_FPIF16_Msk                      /*!< Falling Pending Interrupt Flag on line 16 */
2380 
2381 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
2382 #define EXTI_EXTICR1_EXTI0_Pos       (0U)
2383 #define EXTI_EXTICR1_EXTI0_Msk       (0x7UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000007 */
2384 #define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
2385 #define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
2386 #define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
2387 #define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
2388 #define EXTI_EXTICR1_EXTI1_Pos       (8U)
2389 #define EXTI_EXTICR1_EXTI1_Msk       (0x7UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000700 */
2390 #define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
2391 #define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
2392 #define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
2393 #define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
2394 #define EXTI_EXTICR1_EXTI2_Pos       (16U)
2395 #define EXTI_EXTICR1_EXTI2_Msk       (0x7UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00070000 */
2396 #define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
2397 #define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
2398 #define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
2399 #define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
2400 #define EXTI_EXTICR1_EXTI3_Pos       (24U)
2401 #define EXTI_EXTICR1_EXTI3_Msk       (0x7UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x07000000 */
2402 #define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
2403 #define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
2404 #define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
2405 #define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
2406 
2407 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
2408 #define EXTI_EXTICR2_EXTI4_Pos       (0U)
2409 #define EXTI_EXTICR2_EXTI4_Msk       (0x7UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000007 */
2410 #define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
2411 #define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
2412 #define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
2413 #define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
2414 #define EXTI_EXTICR2_EXTI5_Pos       (8U)
2415 #define EXTI_EXTICR2_EXTI5_Msk       (0x7UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000700 */
2416 #define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
2417 #define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
2418 #define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
2419 #define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
2420 #define EXTI_EXTICR2_EXTI6_Pos       (16U)
2421 #define EXTI_EXTICR2_EXTI6_Msk       (0x7UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00070000 */
2422 #define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
2423 #define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
2424 #define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
2425 #define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
2426 #define EXTI_EXTICR2_EXTI7_Pos       (24U)
2427 #define EXTI_EXTICR2_EXTI7_Msk       (0x7UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x07000000 */
2428 #define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
2429 #define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
2430 #define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
2431 #define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
2432 
2433 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
2434 #define EXTI_EXTICR3_EXTI8_Pos       (0U)
2435 #define EXTI_EXTICR3_EXTI8_Msk       (0x7UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000007 */
2436 #define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
2437 #define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
2438 #define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
2439 #define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
2440 #define EXTI_EXTICR3_EXTI9_Pos       (8U)
2441 #define EXTI_EXTICR3_EXTI9_Msk       (0x7UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000700 */
2442 #define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
2443 #define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
2444 #define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
2445 #define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
2446 #define EXTI_EXTICR3_EXTI10_Pos      (16U)
2447 #define EXTI_EXTICR3_EXTI10_Msk      (0x7UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00070000 */
2448 #define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
2449 #define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
2450 #define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
2451 #define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
2452 #define EXTI_EXTICR3_EXTI11_Pos      (24U)
2453 #define EXTI_EXTICR3_EXTI11_Msk      (0x7UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x07000000 */
2454 #define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
2455 #define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
2456 #define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
2457 #define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
2458 
2459 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
2460 #define EXTI_EXTICR4_EXTI12_Pos      (0U)
2461 #define EXTI_EXTICR4_EXTI12_Msk      (0x7UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000007 */
2462 #define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
2463 #define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
2464 #define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
2465 #define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
2466 #define EXTI_EXTICR4_EXTI13_Pos      (8U)
2467 #define EXTI_EXTICR4_EXTI13_Msk      (0x7UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000700 */
2468 #define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
2469 #define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
2470 #define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00000200 */
2471 #define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)         /*!< 0x00000400 */
2472 #define EXTI_EXTICR4_EXTI14_Pos      (16U)
2473 #define EXTI_EXTICR4_EXTI14_Msk      (0x7UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00070000 */
2474 #define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
2475 #define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
2476 #define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
2477 #define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
2478 #define EXTI_EXTICR4_EXTI15_Pos      (24U)
2479 #define EXTI_EXTICR4_EXTI15_Msk      (0x7UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x07000000 */
2480 #define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
2481 #define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
2482 #define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
2483 #define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
2484 
2485 /*******************  Bit definition for EXTI_IMR1 register  ******************/
2486 #define EXTI_IMR1_IM0_Pos            (0U)
2487 #define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
2488 #define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
2489 #define EXTI_IMR1_IM1_Pos            (1U)
2490 #define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
2491 #define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
2492 #define EXTI_IMR1_IM2_Pos            (2U)
2493 #define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
2494 #define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
2495 #define EXTI_IMR1_IM3_Pos            (3U)
2496 #define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
2497 #define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
2498 #define EXTI_IMR1_IM4_Pos            (4U)
2499 #define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
2500 #define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
2501 #define EXTI_IMR1_IM5_Pos            (5U)
2502 #define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
2503 #define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
2504 #define EXTI_IMR1_IM6_Pos            (6U)
2505 #define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
2506 #define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
2507 #define EXTI_IMR1_IM7_Pos            (7U)
2508 #define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
2509 #define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
2510 #define EXTI_IMR1_IM8_Pos            (8U)
2511 #define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
2512 #define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
2513 #define EXTI_IMR1_IM9_Pos            (9U)
2514 #define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
2515 #define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
2516 #define EXTI_IMR1_IM10_Pos           (10U)
2517 #define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
2518 #define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
2519 #define EXTI_IMR1_IM11_Pos           (11U)
2520 #define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
2521 #define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
2522 #define EXTI_IMR1_IM12_Pos           (12U)
2523 #define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
2524 #define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
2525 #define EXTI_IMR1_IM13_Pos           (13U)
2526 #define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
2527 #define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
2528 #define EXTI_IMR1_IM14_Pos           (14U)
2529 #define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
2530 #define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
2531 #define EXTI_IMR1_IM15_Pos           (15U)
2532 #define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
2533 #define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
2534 #define EXTI_IMR1_IM16_Pos           (16U)
2535 #define EXTI_IMR1_IM16_Msk           (0x1UL << EXTI_IMR1_IM16_Pos)             /*!< 0x00010000 */
2536 #define EXTI_IMR1_IM16               EXTI_IMR1_IM16_Msk                        /*!< Interrupt Mask on line 16 */
2537 #define EXTI_IMR1_IM19_Pos           (19U)
2538 #define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
2539 #define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
2540 #define EXTI_IMR1_IM21_Pos           (21U)
2541 #define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
2542 #define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
2543 #define EXTI_IMR1_IM23_Pos           (23U)
2544 #define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
2545 #define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
2546 #define EXTI_IMR1_IM25_Pos           (25U)
2547 #define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
2548 #define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
2549 #define EXTI_IMR1_IM28_Pos           (28U)
2550 #define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
2551 #define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
2552 #define EXTI_IMR1_IM29_Pos           (29U)
2553 #define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
2554 #define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
2555 #define EXTI_IMR1_IM30_Pos           (30U)
2556 #define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
2557 #define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
2558 #define EXTI_IMR1_IM31_Pos           (31U)
2559 #define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)              /*!< 0x80000000 */
2560 #define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */
2561 #define EXTI_IMR1_IM_Pos             (0U)
2562 #define EXTI_IMR1_IM_Msk             (0xF2A9FFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xF2A9FFFF */
2563 #define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */
2564 
2565 
2566 /*******************  Bit definition for EXTI_EMR1 register  ******************/
2567 #define EXTI_EMR1_EM0_Pos            (0U)
2568 #define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
2569 #define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
2570 #define EXTI_EMR1_EM1_Pos            (1U)
2571 #define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
2572 #define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
2573 #define EXTI_EMR1_EM2_Pos            (2U)
2574 #define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
2575 #define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
2576 #define EXTI_EMR1_EM3_Pos            (3U)
2577 #define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
2578 #define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
2579 #define EXTI_EMR1_EM4_Pos            (4U)
2580 #define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
2581 #define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
2582 #define EXTI_EMR1_EM5_Pos            (5U)
2583 #define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
2584 #define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
2585 #define EXTI_EMR1_EM6_Pos            (6U)
2586 #define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
2587 #define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
2588 #define EXTI_EMR1_EM7_Pos            (7U)
2589 #define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
2590 #define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
2591 #define EXTI_EMR1_EM8_Pos            (8U)
2592 #define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
2593 #define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
2594 #define EXTI_EMR1_EM9_Pos            (9U)
2595 #define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
2596 #define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
2597 #define EXTI_EMR1_EM10_Pos           (10U)
2598 #define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
2599 #define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
2600 #define EXTI_EMR1_EM11_Pos           (11U)
2601 #define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
2602 #define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
2603 #define EXTI_EMR1_EM12_Pos           (12U)
2604 #define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
2605 #define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
2606 #define EXTI_EMR1_EM13_Pos           (13U)
2607 #define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
2608 #define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
2609 #define EXTI_EMR1_EM14_Pos           (14U)
2610 #define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
2611 #define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
2612 #define EXTI_EMR1_EM15_Pos           (15U)
2613 #define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
2614 #define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
2615 #define EXTI_EMR1_EM16_Pos           (16U)
2616 #define EXTI_EMR1_EM16_Msk           (0x1UL << EXTI_EMR1_EM16_Pos)             /*!< 0x00010000 */
2617 #define EXTI_EMR1_EM16               EXTI_EMR1_EM16_Msk                        /*!< Event Mask on line 16 */
2618 #define EXTI_EMR1_EM19_Pos           (19U)
2619 #define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
2620 #define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
2621 #define EXTI_EMR1_EM21_Pos           (21U)
2622 #define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
2623 #define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
2624 #define EXTI_EMR1_EM23_Pos           (23U)
2625 #define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
2626 #define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
2627 #define EXTI_EMR1_EM25_Pos           (25U)
2628 #define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
2629 #define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
2630 #define EXTI_EMR1_EM28_Pos           (28U)
2631 #define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
2632 #define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
2633 #define EXTI_EMR1_EM29_Pos           (29U)
2634 #define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */
2635 #define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */
2636 #define EXTI_EMR1_EM30_Pos           (30U)
2637 #define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
2638 #define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
2639 #define EXTI_EMR1_EM31_Pos           (31U)
2640 #define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
2641 #define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */
2642 
2643 
2644 /******************************************************************************/
2645 /*                                                                            */
2646 /*                                    FLASH                                   */
2647 /*                                                                            */
2648 /******************************************************************************/
2649 #define GPIO_NRST_CONFIG_SUPPORT         /*!< GPIO feature available only on specific devices: Configure NRST pin */
2650 #define FLASH_SECURABLE_MEMORY_SUPPORT   /*!< Flash feature available only on specific devices: allow to secure memory */
2651 #define FLASH_PCROP_SUPPORT              /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */
2652 
2653 /*******************  Bits definition for FLASH_ACR register  *****************/
2654 #define FLASH_ACR_LATENCY_Pos                  (0U)
2655 #define FLASH_ACR_LATENCY_Msk                  (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
2656 #define FLASH_ACR_LATENCY                      FLASH_ACR_LATENCY_Msk
2657 #define FLASH_ACR_LATENCY_0                    (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2658 #define FLASH_ACR_LATENCY_1                    (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
2659 #define FLASH_ACR_LATENCY_2                    (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
2660 #define FLASH_ACR_PRFTEN_Pos                   (8U)
2661 #define FLASH_ACR_PRFTEN_Msk                   (0x1UL << FLASH_ACR_PRFTEN_Pos)  /*!< 0x00000100 */
2662 #define FLASH_ACR_PRFTEN                       FLASH_ACR_PRFTEN_Msk
2663 #define FLASH_ACR_ICEN_Pos                     (9U)
2664 #define FLASH_ACR_ICEN_Msk                     (0x1UL << FLASH_ACR_ICEN_Pos)    /*!< 0x00000200 */
2665 #define FLASH_ACR_ICEN                         FLASH_ACR_ICEN_Msk
2666 #define FLASH_ACR_ICRST_Pos                    (11U)
2667 #define FLASH_ACR_ICRST_Msk                    (0x1UL << FLASH_ACR_ICRST_Pos)   /*!< 0x00000800 */
2668 #define FLASH_ACR_ICRST                        FLASH_ACR_ICRST_Msk
2669 #define FLASH_ACR_PROGEMPTY_Pos                (16U)
2670 #define FLASH_ACR_PROGEMPTY_Msk                (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
2671 #define FLASH_ACR_PROGEMPTY                    FLASH_ACR_PROGEMPTY_Msk
2672 #define FLASH_ACR_DBG_SWEN_Pos                 (18U)
2673 #define FLASH_ACR_DBG_SWEN_Msk                 (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
2674 #define FLASH_ACR_DBG_SWEN                     FLASH_ACR_DBG_SWEN_Msk
2675 
2676 /*******************  Bits definition for FLASH_SR register  ******************/
2677 #define FLASH_SR_EOP_Pos                       (0U)
2678 #define FLASH_SR_EOP_Msk                       (0x1UL << FLASH_SR_EOP_Pos)      /*!< 0x00000001 */
2679 #define FLASH_SR_EOP                           FLASH_SR_EOP_Msk
2680 #define FLASH_SR_OPERR_Pos                     (1U)
2681 #define FLASH_SR_OPERR_Msk                     (0x1UL << FLASH_SR_OPERR_Pos)    /*!< 0x00000002 */
2682 #define FLASH_SR_OPERR                         FLASH_SR_OPERR_Msk
2683 #define FLASH_SR_PROGERR_Pos                   (3U)
2684 #define FLASH_SR_PROGERR_Msk                   (0x1UL << FLASH_SR_PROGERR_Pos)  /*!< 0x00000008 */
2685 #define FLASH_SR_PROGERR                       FLASH_SR_PROGERR_Msk
2686 #define FLASH_SR_WRPERR_Pos                    (4U)
2687 #define FLASH_SR_WRPERR_Msk                    (0x1UL << FLASH_SR_WRPERR_Pos)   /*!< 0x00000010 */
2688 #define FLASH_SR_WRPERR                        FLASH_SR_WRPERR_Msk
2689 #define FLASH_SR_PGAERR_Pos                    (5U)
2690 #define FLASH_SR_PGAERR_Msk                    (0x1UL << FLASH_SR_PGAERR_Pos)   /*!< 0x00000020 */
2691 #define FLASH_SR_PGAERR                        FLASH_SR_PGAERR_Msk
2692 #define FLASH_SR_SIZERR_Pos                    (6U)
2693 #define FLASH_SR_SIZERR_Msk                    (0x1UL << FLASH_SR_SIZERR_Pos)   /*!< 0x00000040 */
2694 #define FLASH_SR_SIZERR                        FLASH_SR_SIZERR_Msk
2695 #define FLASH_SR_PGSERR_Pos                    (7U)
2696 #define FLASH_SR_PGSERR_Msk                    (0x1UL << FLASH_SR_PGSERR_Pos)   /*!< 0x00000080 */
2697 #define FLASH_SR_PGSERR                        FLASH_SR_PGSERR_Msk
2698 #define FLASH_SR_MISERR_Pos                    (8U)
2699 #define FLASH_SR_MISERR_Msk                    (0x1UL << FLASH_SR_MISERR_Pos)   /*!< 0x00000100 */
2700 #define FLASH_SR_MISERR                        FLASH_SR_MISERR_Msk
2701 #define FLASH_SR_FASTERR_Pos                   (9U)
2702 #define FLASH_SR_FASTERR_Msk                   (0x1UL << FLASH_SR_FASTERR_Pos)  /*!< 0x00000200 */
2703 #define FLASH_SR_FASTERR                       FLASH_SR_FASTERR_Msk
2704 #define FLASH_SR_RDERR_Pos                     (14U)
2705 #define FLASH_SR_RDERR_Msk                     (0x1UL << FLASH_SR_RDERR_Pos)    /*!< 0x00004000 */
2706 #define FLASH_SR_RDERR                         FLASH_SR_RDERR_Msk
2707 #define FLASH_SR_OPTVERR_Pos                   (15U)
2708 #define FLASH_SR_OPTVERR_Msk                   (0x1UL << FLASH_SR_OPTVERR_Pos)  /*!< 0x00008000 */
2709 #define FLASH_SR_OPTVERR                       FLASH_SR_OPTVERR_Msk
2710 #define FLASH_SR_BSY1_Pos                      (16U)
2711 #define FLASH_SR_BSY1_Msk                      (0x1UL << FLASH_SR_BSY1_Pos)     /*!< 0x00010000 */
2712 #define FLASH_SR_BSY1                          FLASH_SR_BSY1_Msk
2713 #define FLASH_SR_CFGBSY_Pos                    (18U)
2714 #define FLASH_SR_CFGBSY_Msk                    (0x1UL << FLASH_SR_CFGBSY_Pos)   /*!< 0x00040000 */
2715 #define FLASH_SR_CFGBSY                        FLASH_SR_CFGBSY_Msk
2716 
2717 /*******************  Bits definition for FLASH_CR register  ******************/
2718 #define FLASH_CR_PG_Pos                        (0U)
2719 #define FLASH_CR_PG_Msk                        (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
2720 #define FLASH_CR_PG                            FLASH_CR_PG_Msk
2721 #define FLASH_CR_PER_Pos                       (1U)
2722 #define FLASH_CR_PER_Msk                       (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
2723 #define FLASH_CR_PER                           FLASH_CR_PER_Msk
2724 #define FLASH_CR_MER1_Pos                      (2U)
2725 #define FLASH_CR_MER1_Msk                      (0x1UL << FLASH_CR_MER1_Pos)       /*!< 0x00000004 */
2726 #define FLASH_CR_MER1                          FLASH_CR_MER1_Msk
2727 #define FLASH_CR_PNB_Pos                       (3U)
2728 #define FLASH_CR_PNB_Msk                       (0x3FFUL << FLASH_CR_PNB_Pos)       /*!< 0x00001FF8 */
2729 #define FLASH_CR_PNB                           FLASH_CR_PNB_Msk
2730 #define FLASH_CR_STRT_Pos                      (16U)
2731 #define FLASH_CR_STRT_Msk                      (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
2732 #define FLASH_CR_STRT                          FLASH_CR_STRT_Msk
2733 #define FLASH_CR_OPTSTRT_Pos                   (17U)
2734 #define FLASH_CR_OPTSTRT_Msk                   (0x1UL << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
2735 #define FLASH_CR_OPTSTRT                       FLASH_CR_OPTSTRT_Msk
2736 #define FLASH_CR_FSTPG_Pos                     (18U)
2737 #define FLASH_CR_FSTPG_Msk                     (0x1UL << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
2738 #define FLASH_CR_FSTPG                         FLASH_CR_FSTPG_Msk
2739 #define FLASH_CR_EOPIE_Pos                     (24U)
2740 #define FLASH_CR_EOPIE_Msk                     (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
2741 #define FLASH_CR_EOPIE                         FLASH_CR_EOPIE_Msk
2742 #define FLASH_CR_ERRIE_Pos                     (25U)
2743 #define FLASH_CR_ERRIE_Msk                     (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
2744 #define FLASH_CR_ERRIE                         FLASH_CR_ERRIE_Msk
2745 #define FLASH_CR_RDERRIE_Pos                   (26U)
2746 #define FLASH_CR_RDERRIE_Msk                   (0x1UL << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
2747 #define FLASH_CR_RDERRIE                       FLASH_CR_RDERRIE_Msk
2748 #define FLASH_CR_OBL_LAUNCH_Pos                (27U)
2749 #define FLASH_CR_OBL_LAUNCH_Msk                (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
2750 #define FLASH_CR_OBL_LAUNCH                    FLASH_CR_OBL_LAUNCH_Msk
2751 #define FLASH_CR_SEC_PROT_Pos                  (28U)
2752 #define FLASH_CR_SEC_PROT_Msk                  (0x1UL << FLASH_CR_SEC_PROT_Pos)   /*!< 0x10000000 */
2753 #define FLASH_CR_SEC_PROT                      FLASH_CR_SEC_PROT_Msk
2754 #define FLASH_CR_OPTLOCK_Pos                   (30U)
2755 #define FLASH_CR_OPTLOCK_Msk                   (0x1UL << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
2756 #define FLASH_CR_OPTLOCK                       FLASH_CR_OPTLOCK_Msk
2757 #define FLASH_CR_LOCK_Pos                      (31U)
2758 #define FLASH_CR_LOCK_Msk                      (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
2759 #define FLASH_CR_LOCK                          FLASH_CR_LOCK_Msk
2760 
2761 /*******************  Bits definition for FLASH_ECCR register  ****************/
2762 #define FLASH_ECCR_ADDR_ECC_Pos                (0U)
2763 #define FLASH_ECCR_ADDR_ECC_Msk                (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos)  /*!< 0x00003FFF */
2764 #define FLASH_ECCR_ADDR_ECC                    FLASH_ECCR_ADDR_ECC_Msk
2765 #define FLASH_ECCR_SYSF_ECC_Pos                (20U)
2766 #define FLASH_ECCR_SYSF_ECC_Msk                (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)     /*!< 0x00100000 */
2767 #define FLASH_ECCR_SYSF_ECC                    FLASH_ECCR_SYSF_ECC_Msk
2768 #define FLASH_ECCR_ECCCIE_Pos                  (24U)
2769 #define FLASH_ECCR_ECCCIE_Msk                  (0x1UL << FLASH_ECCR_ECCCIE_Pos)       /*!< 0x01000000 */
2770 #define FLASH_ECCR_ECCCIE                      FLASH_ECCR_ECCCIE_Msk
2771 #define FLASH_ECCR_ECCC_Pos                    (30U)
2772 #define FLASH_ECCR_ECCC_Msk                    (0x1UL << FLASH_ECCR_ECCC_Pos)         /*!< 0x40000000 */
2773 #define FLASH_ECCR_ECCC                        FLASH_ECCR_ECCC_Msk
2774 #define FLASH_ECCR_ECCD_Pos                    (31U)
2775 #define FLASH_ECCR_ECCD_Msk                    (0x1UL << FLASH_ECCR_ECCD_Pos)         /*!< 0x80000000 */
2776 #define FLASH_ECCR_ECCD                        FLASH_ECCR_ECCD_Msk
2777 
2778 /*******************  Bits definition for FLASH_OPTR register  ****************/
2779 #define FLASH_OPTR_RDP_Pos                     (0U)
2780 #define FLASH_OPTR_RDP_Msk                     (0xFFUL << FLASH_OPTR_RDP_Pos)             /*!< 0x000000FF */
2781 #define FLASH_OPTR_RDP                         FLASH_OPTR_RDP_Msk
2782 #define FLASH_OPTR_BOR_EN_Pos                  (8U)
2783 #define FLASH_OPTR_BOR_EN_Msk                  (0x1UL << FLASH_OPTR_BOR_EN_Pos)           /*!< 0x00000100 */
2784 #define FLASH_OPTR_BOR_EN                      FLASH_OPTR_BOR_EN_Msk
2785 #define FLASH_OPTR_BORR_LEV_Pos                (9U)
2786 #define FLASH_OPTR_BORR_LEV_Msk                (0x3UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000600 */
2787 #define FLASH_OPTR_BORR_LEV                    FLASH_OPTR_BORR_LEV_Msk
2788 #define FLASH_OPTR_BORR_LEV_0                  (0x1UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000200 */
2789 #define FLASH_OPTR_BORR_LEV_1                  (0x2UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000400 */
2790 #define FLASH_OPTR_BORF_LEV_Pos                (11U)
2791 #define FLASH_OPTR_BORF_LEV_Msk                (0x3UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001800 */
2792 #define FLASH_OPTR_BORF_LEV                    FLASH_OPTR_BORF_LEV_Msk
2793 #define FLASH_OPTR_BORF_LEV_0                  (0x1UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00000800 */
2794 #define FLASH_OPTR_BORF_LEV_1                  (0x2UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001000 */
2795 #define FLASH_OPTR_nRST_STOP_Pos               (13U)
2796 #define FLASH_OPTR_nRST_STOP_Msk               (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00002000 */
2797 #define FLASH_OPTR_nRST_STOP                   FLASH_OPTR_nRST_STOP_Msk
2798 #define FLASH_OPTR_nRST_STDBY_Pos              (14U)
2799 #define FLASH_OPTR_nRST_STDBY_Msk              (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00004000 */
2800 #define FLASH_OPTR_nRST_STDBY                  FLASH_OPTR_nRST_STDBY_Msk
2801 #define FLASH_OPTR_nRST_SHDW_Pos               (15U)
2802 #define FLASH_OPTR_nRST_SHDW_Msk               (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)        /*!< 0x00008000 */
2803 #define FLASH_OPTR_nRST_SHDW                   FLASH_OPTR_nRST_SHDW_Msk
2804 #define FLASH_OPTR_IWDG_SW_Pos                 (16U)
2805 #define FLASH_OPTR_IWDG_SW_Msk                 (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00010000 */
2806 #define FLASH_OPTR_IWDG_SW                     FLASH_OPTR_IWDG_SW_Msk
2807 #define FLASH_OPTR_IWDG_STOP_Pos               (17U)
2808 #define FLASH_OPTR_IWDG_STOP_Msk               (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)        /*!< 0x00020000 */
2809 #define FLASH_OPTR_IWDG_STOP                   FLASH_OPTR_IWDG_STOP_Msk
2810 #define FLASH_OPTR_IWDG_STDBY_Pos              (18U)
2811 #define FLASH_OPTR_IWDG_STDBY_Msk              (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)       /*!< 0x00040000 */
2812 #define FLASH_OPTR_IWDG_STDBY                  FLASH_OPTR_IWDG_STDBY_Msk
2813 #define FLASH_OPTR_WWDG_SW_Pos                 (19U)
2814 #define FLASH_OPTR_WWDG_SW_Msk                 (0x1UL << FLASH_OPTR_WWDG_SW_Pos)          /*!< 0x00080000 */
2815 #define FLASH_OPTR_WWDG_SW                     FLASH_OPTR_WWDG_SW_Msk
2816 #define FLASH_OPTR_RAM_PARITY_CHECK_Pos        (22U)
2817 #define FLASH_OPTR_RAM_PARITY_CHECK_Msk        (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
2818 #define FLASH_OPTR_RAM_PARITY_CHECK            FLASH_OPTR_RAM_PARITY_CHECK_Msk
2819 #define FLASH_OPTR_nBOOT_SEL_Pos               (24U)
2820 #define FLASH_OPTR_nBOOT_SEL_Msk               (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos)        /*!< 0x01000000 */
2821 #define FLASH_OPTR_nBOOT_SEL                   FLASH_OPTR_nBOOT_SEL_Msk
2822 #define FLASH_OPTR_nBOOT1_Pos                  (25U)
2823 #define FLASH_OPTR_nBOOT1_Msk                  (0x1UL << FLASH_OPTR_nBOOT1_Pos)           /*!< 0x02000000 */
2824 #define FLASH_OPTR_nBOOT1                      FLASH_OPTR_nBOOT1_Msk
2825 #define FLASH_OPTR_nBOOT0_Pos                  (26U)
2826 #define FLASH_OPTR_nBOOT0_Msk                  (0x1UL << FLASH_OPTR_nBOOT0_Pos)           /*!< 0x04000000 */
2827 #define FLASH_OPTR_nBOOT0                      FLASH_OPTR_nBOOT0_Msk
2828 #define FLASH_OPTR_NRST_MODE_Pos               (27U)
2829 #define FLASH_OPTR_NRST_MODE_Msk               (0x3UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x18000000 */
2830 #define FLASH_OPTR_NRST_MODE                   FLASH_OPTR_NRST_MODE_Msk
2831 #define FLASH_OPTR_NRST_MODE_0                 (0x1UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x08000000 */
2832 #define FLASH_OPTR_NRST_MODE_1                 (0x2UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x10000000 */
2833 #define FLASH_OPTR_IRHEN_Pos                   (29U)
2834 #define FLASH_OPTR_IRHEN_Msk                   (0x1UL << FLASH_OPTR_IRHEN_Pos)            /*!< 0x20000000 */
2835 #define FLASH_OPTR_IRHEN                       FLASH_OPTR_IRHEN_Msk
2836 
2837 /******************  Bits definition for FLASH_PCROP1ASR register  ************/
2838 #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos       (0U)
2839 #define FLASH_PCROP1ASR_PCROP1A_STRT_Msk       (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)   /*!< 0x0000007F */
2840 #define FLASH_PCROP1ASR_PCROP1A_STRT           FLASH_PCROP1ASR_PCROP1A_STRT_Msk
2841 
2842 /******************  Bits definition for FLASH_PCROP1AER register  ************/
2843 #define FLASH_PCROP1AER_PCROP1A_END_Pos        (0U)
2844 #define FLASH_PCROP1AER_PCROP1A_END_Msk        (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos)    /*!< 0x0000007F */
2845 #define FLASH_PCROP1AER_PCROP1A_END            FLASH_PCROP1AER_PCROP1A_END_Msk
2846 #define FLASH_PCROP1AER_PCROP_RDP_Pos          (31U)
2847 #define FLASH_PCROP1AER_PCROP_RDP_Msk          (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)       /*!< 0x80000000 */
2848 #define FLASH_PCROP1AER_PCROP_RDP              FLASH_PCROP1AER_PCROP_RDP_Msk
2849 
2850 /******************  Bits definition for FLASH_WRP1AR register  ***************/
2851 #define FLASH_WRP1AR_WRP1A_STRT_Pos            (0U)
2852 #define FLASH_WRP1AR_WRP1A_STRT_Msk            (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */
2853 #define FLASH_WRP1AR_WRP1A_STRT                FLASH_WRP1AR_WRP1A_STRT_Msk
2854 #define FLASH_WRP1AR_WRP1A_END_Pos             (16U)
2855 #define FLASH_WRP1AR_WRP1A_END_Msk             (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */
2856 #define FLASH_WRP1AR_WRP1A_END                 FLASH_WRP1AR_WRP1A_END_Msk
2857 
2858 /******************  Bits definition for FLASH_WRP1BR register  ***************/
2859 #define FLASH_WRP1BR_WRP1B_STRT_Pos            (0U)
2860 #define FLASH_WRP1BR_WRP1B_STRT_Msk            (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */
2861 #define FLASH_WRP1BR_WRP1B_STRT                FLASH_WRP1BR_WRP1B_STRT_Msk
2862 #define FLASH_WRP1BR_WRP1B_END_Pos             (16U)
2863 #define FLASH_WRP1BR_WRP1B_END_Msk             (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */
2864 #define FLASH_WRP1BR_WRP1B_END                 FLASH_WRP1BR_WRP1B_END_Msk
2865 
2866 /******************  Bits definition for FLASH_PCROP1BSR register  ************/
2867 #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos       (0U)
2868 #define FLASH_PCROP1BSR_PCROP1B_STRT_Msk       (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)   /*!< 0x0000007F */
2869 #define FLASH_PCROP1BSR_PCROP1B_STRT           FLASH_PCROP1BSR_PCROP1B_STRT_Msk
2870 
2871 /******************  Bits definition for FLASH_PCROP1BER register  ************/
2872 #define FLASH_PCROP1BER_PCROP1B_END_Pos        (0U)
2873 #define FLASH_PCROP1BER_PCROP1B_END_Msk        (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos)    /*!< 0x0000007F */
2874 #define FLASH_PCROP1BER_PCROP1B_END            FLASH_PCROP1BER_PCROP1B_END_Msk
2875 
2876 
2877 /******************  Bits definition for FLASH_SECR register  *****************/
2878 #define FLASH_SECR_SEC_SIZE_Pos                (0U)
2879 #define FLASH_SECR_SEC_SIZE_Msk                (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */
2880 #define FLASH_SECR_SEC_SIZE                    FLASH_SECR_SEC_SIZE_Msk
2881 #define FLASH_SECR_BOOT_LOCK_Pos               (16U)
2882 #define FLASH_SECR_BOOT_LOCK_Msk               (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */
2883 #define FLASH_SECR_BOOT_LOCK                   FLASH_SECR_BOOT_LOCK_Msk
2884 
2885 /******************************************************************************/
2886 /*                                                                            */
2887 /*                            General Purpose I/O                             */
2888 /*                                                                            */
2889 /******************************************************************************/
2890 /******************  Bits definition for GPIO_MODER register  *****************/
2891 #define GPIO_MODER_MODE0_Pos           (0U)
2892 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
2893 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
2894 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
2895 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
2896 #define GPIO_MODER_MODE1_Pos           (2U)
2897 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
2898 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
2899 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
2900 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
2901 #define GPIO_MODER_MODE2_Pos           (4U)
2902 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
2903 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
2904 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
2905 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
2906 #define GPIO_MODER_MODE3_Pos           (6U)
2907 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
2908 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
2909 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
2910 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
2911 #define GPIO_MODER_MODE4_Pos           (8U)
2912 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
2913 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
2914 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
2915 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
2916 #define GPIO_MODER_MODE5_Pos           (10U)
2917 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
2918 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
2919 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
2920 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
2921 #define GPIO_MODER_MODE6_Pos           (12U)
2922 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
2923 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
2924 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
2925 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
2926 #define GPIO_MODER_MODE7_Pos           (14U)
2927 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
2928 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
2929 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
2930 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
2931 #define GPIO_MODER_MODE8_Pos           (16U)
2932 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
2933 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
2934 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
2935 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
2936 #define GPIO_MODER_MODE9_Pos           (18U)
2937 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
2938 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
2939 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
2940 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
2941 #define GPIO_MODER_MODE10_Pos          (20U)
2942 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
2943 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
2944 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
2945 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
2946 #define GPIO_MODER_MODE11_Pos          (22U)
2947 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
2948 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
2949 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
2950 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
2951 #define GPIO_MODER_MODE12_Pos          (24U)
2952 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
2953 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
2954 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
2955 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
2956 #define GPIO_MODER_MODE13_Pos          (26U)
2957 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
2958 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
2959 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
2960 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
2961 #define GPIO_MODER_MODE14_Pos          (28U)
2962 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
2963 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
2964 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
2965 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
2966 #define GPIO_MODER_MODE15_Pos          (30U)
2967 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
2968 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
2969 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
2970 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
2971 
2972 /******************  Bits definition for GPIO_OTYPER register  ****************/
2973 #define GPIO_OTYPER_OT0_Pos            (0U)
2974 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
2975 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
2976 #define GPIO_OTYPER_OT1_Pos            (1U)
2977 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
2978 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
2979 #define GPIO_OTYPER_OT2_Pos            (2U)
2980 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
2981 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
2982 #define GPIO_OTYPER_OT3_Pos            (3U)
2983 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
2984 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
2985 #define GPIO_OTYPER_OT4_Pos            (4U)
2986 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
2987 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
2988 #define GPIO_OTYPER_OT5_Pos            (5U)
2989 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
2990 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
2991 #define GPIO_OTYPER_OT6_Pos            (6U)
2992 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
2993 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
2994 #define GPIO_OTYPER_OT7_Pos            (7U)
2995 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
2996 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
2997 #define GPIO_OTYPER_OT8_Pos            (8U)
2998 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
2999 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
3000 #define GPIO_OTYPER_OT9_Pos            (9U)
3001 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
3002 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
3003 #define GPIO_OTYPER_OT10_Pos           (10U)
3004 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
3005 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
3006 #define GPIO_OTYPER_OT11_Pos           (11U)
3007 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
3008 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
3009 #define GPIO_OTYPER_OT12_Pos           (12U)
3010 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
3011 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
3012 #define GPIO_OTYPER_OT13_Pos           (13U)
3013 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
3014 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
3015 #define GPIO_OTYPER_OT14_Pos           (14U)
3016 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
3017 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
3018 #define GPIO_OTYPER_OT15_Pos           (15U)
3019 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
3020 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
3021 
3022 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3023 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
3024 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
3025 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
3026 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
3027 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
3028 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
3029 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
3030 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
3031 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
3032 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
3033 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
3034 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
3035 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
3036 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
3037 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
3038 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
3039 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
3040 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
3041 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
3042 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
3043 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
3044 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
3045 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
3046 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
3047 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
3048 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
3049 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
3050 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
3051 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
3052 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
3053 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
3054 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
3055 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
3056 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
3057 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
3058 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
3059 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
3060 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
3061 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
3062 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
3063 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
3064 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
3065 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
3066 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
3067 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
3068 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
3069 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
3070 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
3071 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
3072 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
3073 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
3074 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
3075 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
3076 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
3077 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
3078 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
3079 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
3080 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
3081 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
3082 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
3083 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
3084 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
3085 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
3086 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
3087 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
3088 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
3089 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
3090 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
3091 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
3092 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
3093 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
3094 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
3095 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
3096 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
3097 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
3098 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
3099 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
3100 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
3101 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
3102 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
3103 
3104 /******************  Bits definition for GPIO_PUPDR register  *****************/
3105 #define GPIO_PUPDR_PUPD0_Pos           (0U)
3106 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
3107 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
3108 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
3109 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
3110 #define GPIO_PUPDR_PUPD1_Pos           (2U)
3111 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
3112 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
3113 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
3114 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
3115 #define GPIO_PUPDR_PUPD2_Pos           (4U)
3116 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
3117 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
3118 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
3119 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
3120 #define GPIO_PUPDR_PUPD3_Pos           (6U)
3121 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
3122 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
3123 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
3124 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
3125 #define GPIO_PUPDR_PUPD4_Pos           (8U)
3126 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
3127 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
3128 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
3129 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
3130 #define GPIO_PUPDR_PUPD5_Pos           (10U)
3131 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
3132 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
3133 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
3134 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
3135 #define GPIO_PUPDR_PUPD6_Pos           (12U)
3136 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
3137 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
3138 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
3139 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
3140 #define GPIO_PUPDR_PUPD7_Pos           (14U)
3141 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
3142 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
3143 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
3144 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
3145 #define GPIO_PUPDR_PUPD8_Pos           (16U)
3146 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
3147 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
3148 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
3149 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
3150 #define GPIO_PUPDR_PUPD9_Pos           (18U)
3151 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
3152 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
3153 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
3154 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
3155 #define GPIO_PUPDR_PUPD10_Pos          (20U)
3156 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
3157 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
3158 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
3159 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
3160 #define GPIO_PUPDR_PUPD11_Pos          (22U)
3161 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
3162 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
3163 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
3164 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
3165 #define GPIO_PUPDR_PUPD12_Pos          (24U)
3166 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
3167 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
3168 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
3169 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
3170 #define GPIO_PUPDR_PUPD13_Pos          (26U)
3171 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
3172 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
3173 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
3174 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
3175 #define GPIO_PUPDR_PUPD14_Pos          (28U)
3176 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
3177 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
3178 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
3179 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
3180 #define GPIO_PUPDR_PUPD15_Pos          (30U)
3181 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
3182 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
3183 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
3184 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
3185 
3186 /******************  Bits definition for GPIO_IDR register  *******************/
3187 #define GPIO_IDR_ID0_Pos               (0U)
3188 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
3189 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
3190 #define GPIO_IDR_ID1_Pos               (1U)
3191 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
3192 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
3193 #define GPIO_IDR_ID2_Pos               (2U)
3194 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
3195 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
3196 #define GPIO_IDR_ID3_Pos               (3U)
3197 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
3198 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
3199 #define GPIO_IDR_ID4_Pos               (4U)
3200 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
3201 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
3202 #define GPIO_IDR_ID5_Pos               (5U)
3203 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
3204 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
3205 #define GPIO_IDR_ID6_Pos               (6U)
3206 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
3207 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
3208 #define GPIO_IDR_ID7_Pos               (7U)
3209 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
3210 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
3211 #define GPIO_IDR_ID8_Pos               (8U)
3212 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
3213 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
3214 #define GPIO_IDR_ID9_Pos               (9U)
3215 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
3216 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
3217 #define GPIO_IDR_ID10_Pos              (10U)
3218 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
3219 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
3220 #define GPIO_IDR_ID11_Pos              (11U)
3221 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
3222 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
3223 #define GPIO_IDR_ID12_Pos              (12U)
3224 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
3225 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
3226 #define GPIO_IDR_ID13_Pos              (13U)
3227 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
3228 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
3229 #define GPIO_IDR_ID14_Pos              (14U)
3230 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
3231 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
3232 #define GPIO_IDR_ID15_Pos              (15U)
3233 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
3234 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
3235 
3236 /******************  Bits definition for GPIO_ODR register  *******************/
3237 #define GPIO_ODR_OD0_Pos               (0U)
3238 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
3239 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
3240 #define GPIO_ODR_OD1_Pos               (1U)
3241 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
3242 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
3243 #define GPIO_ODR_OD2_Pos               (2U)
3244 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
3245 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
3246 #define GPIO_ODR_OD3_Pos               (3U)
3247 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
3248 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
3249 #define GPIO_ODR_OD4_Pos               (4U)
3250 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
3251 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
3252 #define GPIO_ODR_OD5_Pos               (5U)
3253 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
3254 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
3255 #define GPIO_ODR_OD6_Pos               (6U)
3256 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
3257 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
3258 #define GPIO_ODR_OD7_Pos               (7U)
3259 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
3260 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
3261 #define GPIO_ODR_OD8_Pos               (8U)
3262 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
3263 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
3264 #define GPIO_ODR_OD9_Pos               (9U)
3265 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
3266 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
3267 #define GPIO_ODR_OD10_Pos              (10U)
3268 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
3269 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
3270 #define GPIO_ODR_OD11_Pos              (11U)
3271 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
3272 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
3273 #define GPIO_ODR_OD12_Pos              (12U)
3274 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
3275 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
3276 #define GPIO_ODR_OD13_Pos              (13U)
3277 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
3278 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
3279 #define GPIO_ODR_OD14_Pos              (14U)
3280 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
3281 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
3282 #define GPIO_ODR_OD15_Pos              (15U)
3283 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
3284 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
3285 
3286 /******************  Bits definition for GPIO_BSRR register  ******************/
3287 #define GPIO_BSRR_BS0_Pos              (0U)
3288 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
3289 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
3290 #define GPIO_BSRR_BS1_Pos              (1U)
3291 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
3292 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
3293 #define GPIO_BSRR_BS2_Pos              (2U)
3294 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
3295 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
3296 #define GPIO_BSRR_BS3_Pos              (3U)
3297 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
3298 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
3299 #define GPIO_BSRR_BS4_Pos              (4U)
3300 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
3301 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
3302 #define GPIO_BSRR_BS5_Pos              (5U)
3303 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
3304 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
3305 #define GPIO_BSRR_BS6_Pos              (6U)
3306 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
3307 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
3308 #define GPIO_BSRR_BS7_Pos              (7U)
3309 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
3310 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
3311 #define GPIO_BSRR_BS8_Pos              (8U)
3312 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
3313 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
3314 #define GPIO_BSRR_BS9_Pos              (9U)
3315 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
3316 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
3317 #define GPIO_BSRR_BS10_Pos             (10U)
3318 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
3319 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
3320 #define GPIO_BSRR_BS11_Pos             (11U)
3321 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
3322 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
3323 #define GPIO_BSRR_BS12_Pos             (12U)
3324 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
3325 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
3326 #define GPIO_BSRR_BS13_Pos             (13U)
3327 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
3328 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
3329 #define GPIO_BSRR_BS14_Pos             (14U)
3330 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
3331 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
3332 #define GPIO_BSRR_BS15_Pos             (15U)
3333 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
3334 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
3335 #define GPIO_BSRR_BR0_Pos              (16U)
3336 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
3337 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
3338 #define GPIO_BSRR_BR1_Pos              (17U)
3339 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
3340 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
3341 #define GPIO_BSRR_BR2_Pos              (18U)
3342 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
3343 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
3344 #define GPIO_BSRR_BR3_Pos              (19U)
3345 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
3346 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
3347 #define GPIO_BSRR_BR4_Pos              (20U)
3348 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
3349 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
3350 #define GPIO_BSRR_BR5_Pos              (21U)
3351 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
3352 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
3353 #define GPIO_BSRR_BR6_Pos              (22U)
3354 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
3355 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
3356 #define GPIO_BSRR_BR7_Pos              (23U)
3357 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
3358 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
3359 #define GPIO_BSRR_BR8_Pos              (24U)
3360 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
3361 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
3362 #define GPIO_BSRR_BR9_Pos              (25U)
3363 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
3364 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
3365 #define GPIO_BSRR_BR10_Pos             (26U)
3366 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
3367 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
3368 #define GPIO_BSRR_BR11_Pos             (27U)
3369 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
3370 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
3371 #define GPIO_BSRR_BR12_Pos             (28U)
3372 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
3373 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
3374 #define GPIO_BSRR_BR13_Pos             (29U)
3375 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
3376 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
3377 #define GPIO_BSRR_BR14_Pos             (30U)
3378 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
3379 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
3380 #define GPIO_BSRR_BR15_Pos             (31U)
3381 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
3382 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
3383 
3384 /****************** Bit definition for GPIO_LCKR register *********************/
3385 #define GPIO_LCKR_LCK0_Pos             (0U)
3386 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
3387 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
3388 #define GPIO_LCKR_LCK1_Pos             (1U)
3389 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
3390 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
3391 #define GPIO_LCKR_LCK2_Pos             (2U)
3392 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
3393 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
3394 #define GPIO_LCKR_LCK3_Pos             (3U)
3395 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
3396 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
3397 #define GPIO_LCKR_LCK4_Pos             (4U)
3398 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
3399 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
3400 #define GPIO_LCKR_LCK5_Pos             (5U)
3401 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
3402 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
3403 #define GPIO_LCKR_LCK6_Pos             (6U)
3404 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
3405 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
3406 #define GPIO_LCKR_LCK7_Pos             (7U)
3407 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
3408 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
3409 #define GPIO_LCKR_LCK8_Pos             (8U)
3410 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
3411 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
3412 #define GPIO_LCKR_LCK9_Pos             (9U)
3413 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
3414 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
3415 #define GPIO_LCKR_LCK10_Pos            (10U)
3416 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
3417 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
3418 #define GPIO_LCKR_LCK11_Pos            (11U)
3419 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
3420 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
3421 #define GPIO_LCKR_LCK12_Pos            (12U)
3422 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
3423 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
3424 #define GPIO_LCKR_LCK13_Pos            (13U)
3425 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
3426 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
3427 #define GPIO_LCKR_LCK14_Pos            (14U)
3428 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
3429 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
3430 #define GPIO_LCKR_LCK15_Pos            (15U)
3431 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
3432 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
3433 #define GPIO_LCKR_LCKK_Pos             (16U)
3434 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
3435 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
3436 
3437 /****************** Bit definition for GPIO_AFRL register *********************/
3438 #define GPIO_AFRL_AFSEL0_Pos           (0U)
3439 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
3440 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
3441 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
3442 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
3443 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
3444 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
3445 #define GPIO_AFRL_AFSEL1_Pos           (4U)
3446 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
3447 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
3448 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
3449 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
3450 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
3451 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
3452 #define GPIO_AFRL_AFSEL2_Pos           (8U)
3453 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
3454 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
3455 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
3456 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
3457 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
3458 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
3459 #define GPIO_AFRL_AFSEL3_Pos           (12U)
3460 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
3461 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
3462 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
3463 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
3464 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
3465 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
3466 #define GPIO_AFRL_AFSEL4_Pos           (16U)
3467 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
3468 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
3469 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
3470 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
3471 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
3472 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
3473 #define GPIO_AFRL_AFSEL5_Pos           (20U)
3474 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
3475 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
3476 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
3477 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
3478 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
3479 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
3480 #define GPIO_AFRL_AFSEL6_Pos           (24U)
3481 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
3482 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
3483 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
3484 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
3485 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
3486 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
3487 #define GPIO_AFRL_AFSEL7_Pos           (28U)
3488 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
3489 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
3490 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
3491 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
3492 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
3493 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
3494 
3495 /****************** Bit definition for GPIO_AFRH register *********************/
3496 #define GPIO_AFRH_AFSEL8_Pos           (0U)
3497 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
3498 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
3499 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
3500 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
3501 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
3502 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
3503 #define GPIO_AFRH_AFSEL9_Pos           (4U)
3504 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
3505 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
3506 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
3507 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
3508 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
3509 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
3510 #define GPIO_AFRH_AFSEL10_Pos          (8U)
3511 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
3512 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
3513 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
3514 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
3515 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
3516 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
3517 #define GPIO_AFRH_AFSEL11_Pos          (12U)
3518 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
3519 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
3520 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
3521 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
3522 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
3523 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
3524 #define GPIO_AFRH_AFSEL12_Pos          (16U)
3525 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
3526 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
3527 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
3528 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
3529 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
3530 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
3531 #define GPIO_AFRH_AFSEL13_Pos          (20U)
3532 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
3533 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
3534 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
3535 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
3536 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
3537 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
3538 #define GPIO_AFRH_AFSEL14_Pos          (24U)
3539 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
3540 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
3541 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
3542 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
3543 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
3544 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
3545 #define GPIO_AFRH_AFSEL15_Pos          (28U)
3546 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
3547 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
3548 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
3549 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
3550 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
3551 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
3552 
3553 /******************  Bits definition for GPIO_BRR register  ******************/
3554 #define GPIO_BRR_BR0_Pos               (0U)
3555 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
3556 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
3557 #define GPIO_BRR_BR1_Pos               (1U)
3558 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
3559 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
3560 #define GPIO_BRR_BR2_Pos               (2U)
3561 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
3562 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
3563 #define GPIO_BRR_BR3_Pos               (3U)
3564 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
3565 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
3566 #define GPIO_BRR_BR4_Pos               (4U)
3567 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
3568 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
3569 #define GPIO_BRR_BR5_Pos               (5U)
3570 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
3571 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
3572 #define GPIO_BRR_BR6_Pos               (6U)
3573 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
3574 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
3575 #define GPIO_BRR_BR7_Pos               (7U)
3576 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
3577 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
3578 #define GPIO_BRR_BR8_Pos               (8U)
3579 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
3580 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
3581 #define GPIO_BRR_BR9_Pos               (9U)
3582 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
3583 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
3584 #define GPIO_BRR_BR10_Pos              (10U)
3585 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
3586 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
3587 #define GPIO_BRR_BR11_Pos              (11U)
3588 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
3589 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
3590 #define GPIO_BRR_BR12_Pos              (12U)
3591 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
3592 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
3593 #define GPIO_BRR_BR13_Pos              (13U)
3594 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
3595 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
3596 #define GPIO_BRR_BR14_Pos              (14U)
3597 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
3598 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
3599 #define GPIO_BRR_BR15_Pos              (15U)
3600 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
3601 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
3602 
3603 
3604 /******************************************************************************/
3605 /*                                                                            */
3606 /*                      Inter-integrated Circuit Interface (I2C)              */
3607 /*                                                                            */
3608 /******************************************************************************/
3609 /*******************  Bit definition for I2C_CR1 register  *******************/
3610 #define I2C_CR1_PE_Pos               (0U)
3611 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
3612 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
3613 #define I2C_CR1_TXIE_Pos             (1U)
3614 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
3615 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
3616 #define I2C_CR1_RXIE_Pos             (2U)
3617 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
3618 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
3619 #define I2C_CR1_ADDRIE_Pos           (3U)
3620 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
3621 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
3622 #define I2C_CR1_NACKIE_Pos           (4U)
3623 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
3624 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
3625 #define I2C_CR1_STOPIE_Pos           (5U)
3626 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
3627 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
3628 #define I2C_CR1_TCIE_Pos             (6U)
3629 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
3630 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
3631 #define I2C_CR1_ERRIE_Pos            (7U)
3632 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
3633 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
3634 #define I2C_CR1_DNF_Pos              (8U)
3635 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
3636 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
3637 #define I2C_CR1_ANFOFF_Pos           (12U)
3638 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
3639 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
3640 #define I2C_CR1_SWRST_Pos            (13U)
3641 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
3642 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
3643 #define I2C_CR1_TXDMAEN_Pos          (14U)
3644 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
3645 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
3646 #define I2C_CR1_RXDMAEN_Pos          (15U)
3647 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
3648 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
3649 #define I2C_CR1_SBC_Pos              (16U)
3650 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
3651 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
3652 #define I2C_CR1_NOSTRETCH_Pos        (17U)
3653 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
3654 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
3655 #define I2C_CR1_WUPEN_Pos            (18U)
3656 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
3657 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
3658 #define I2C_CR1_GCEN_Pos             (19U)
3659 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
3660 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
3661 #define I2C_CR1_SMBHEN_Pos           (20U)
3662 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
3663 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
3664 #define I2C_CR1_SMBDEN_Pos           (21U)
3665 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
3666 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
3667 #define I2C_CR1_ALERTEN_Pos          (22U)
3668 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
3669 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
3670 #define I2C_CR1_PECEN_Pos            (23U)
3671 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
3672 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
3673 
3674 /******************  Bit definition for I2C_CR2 register  ********************/
3675 #define I2C_CR2_SADD_Pos             (0U)
3676 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
3677 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
3678 #define I2C_CR2_RD_WRN_Pos           (10U)
3679 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
3680 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
3681 #define I2C_CR2_ADD10_Pos            (11U)
3682 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
3683 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
3684 #define I2C_CR2_HEAD10R_Pos          (12U)
3685 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
3686 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
3687 #define I2C_CR2_START_Pos            (13U)
3688 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
3689 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
3690 #define I2C_CR2_STOP_Pos             (14U)
3691 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
3692 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
3693 #define I2C_CR2_NACK_Pos             (15U)
3694 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
3695 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
3696 #define I2C_CR2_NBYTES_Pos           (16U)
3697 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
3698 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
3699 #define I2C_CR2_RELOAD_Pos           (24U)
3700 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
3701 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
3702 #define I2C_CR2_AUTOEND_Pos          (25U)
3703 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
3704 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
3705 #define I2C_CR2_PECBYTE_Pos          (26U)
3706 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
3707 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
3708 
3709 /*******************  Bit definition for I2C_OAR1 register  ******************/
3710 #define I2C_OAR1_OA1_Pos             (0U)
3711 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
3712 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
3713 #define I2C_OAR1_OA1MODE_Pos         (10U)
3714 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
3715 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
3716 #define I2C_OAR1_OA1EN_Pos           (15U)
3717 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
3718 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
3719 
3720 /*******************  Bit definition for I2C_OAR2 register  ******************/
3721 #define I2C_OAR2_OA2_Pos             (1U)
3722 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
3723 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
3724 #define I2C_OAR2_OA2MSK_Pos          (8U)
3725 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
3726 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
3727 #define I2C_OAR2_OA2NOMASK           (0U)                                      /*!< No mask                                        */
3728 #define I2C_OAR2_OA2MASK01_Pos       (8U)
3729 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
3730 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
3731 #define I2C_OAR2_OA2MASK02_Pos       (9U)
3732 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
3733 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
3734 #define I2C_OAR2_OA2MASK03_Pos       (8U)
3735 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
3736 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
3737 #define I2C_OAR2_OA2MASK04_Pos       (10U)
3738 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
3739 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
3740 #define I2C_OAR2_OA2MASK05_Pos       (8U)
3741 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
3742 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
3743 #define I2C_OAR2_OA2MASK06_Pos       (9U)
3744 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
3745 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
3746 #define I2C_OAR2_OA2MASK07_Pos       (8U)
3747 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
3748 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
3749 #define I2C_OAR2_OA2EN_Pos           (15U)
3750 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
3751 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
3752 
3753 /*******************  Bit definition for I2C_TIMINGR register *******************/
3754 #define I2C_TIMINGR_SCLL_Pos         (0U)
3755 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
3756 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
3757 #define I2C_TIMINGR_SCLH_Pos         (8U)
3758 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
3759 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
3760 #define I2C_TIMINGR_SDADEL_Pos       (16U)
3761 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
3762 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
3763 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
3764 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
3765 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
3766 #define I2C_TIMINGR_PRESC_Pos        (28U)
3767 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
3768 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
3769 
3770 /******************* Bit definition for I2C_TIMEOUTR register *******************/
3771 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
3772 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
3773 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
3774 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
3775 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
3776 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
3777 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
3778 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
3779 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
3780 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
3781 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
3782 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
3783 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
3784 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
3785 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
3786 
3787 /******************  Bit definition for I2C_ISR register  *********************/
3788 #define I2C_ISR_TXE_Pos              (0U)
3789 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
3790 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
3791 #define I2C_ISR_TXIS_Pos             (1U)
3792 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
3793 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
3794 #define I2C_ISR_RXNE_Pos             (2U)
3795 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
3796 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
3797 #define I2C_ISR_ADDR_Pos             (3U)
3798 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
3799 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
3800 #define I2C_ISR_NACKF_Pos            (4U)
3801 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
3802 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
3803 #define I2C_ISR_STOPF_Pos            (5U)
3804 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
3805 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
3806 #define I2C_ISR_TC_Pos               (6U)
3807 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
3808 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
3809 #define I2C_ISR_TCR_Pos              (7U)
3810 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
3811 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
3812 #define I2C_ISR_BERR_Pos             (8U)
3813 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
3814 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
3815 #define I2C_ISR_ARLO_Pos             (9U)
3816 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
3817 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
3818 #define I2C_ISR_OVR_Pos              (10U)
3819 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
3820 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
3821 #define I2C_ISR_PECERR_Pos           (11U)
3822 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
3823 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
3824 #define I2C_ISR_TIMEOUT_Pos          (12U)
3825 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
3826 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
3827 #define I2C_ISR_ALERT_Pos            (13U)
3828 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
3829 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
3830 #define I2C_ISR_BUSY_Pos             (15U)
3831 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
3832 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
3833 #define I2C_ISR_DIR_Pos              (16U)
3834 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
3835 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
3836 #define I2C_ISR_ADDCODE_Pos          (17U)
3837 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
3838 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
3839 
3840 /******************  Bit definition for I2C_ICR register  *********************/
3841 #define I2C_ICR_ADDRCF_Pos           (3U)
3842 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
3843 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
3844 #define I2C_ICR_NACKCF_Pos           (4U)
3845 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
3846 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
3847 #define I2C_ICR_STOPCF_Pos           (5U)
3848 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
3849 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
3850 #define I2C_ICR_BERRCF_Pos           (8U)
3851 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
3852 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
3853 #define I2C_ICR_ARLOCF_Pos           (9U)
3854 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
3855 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
3856 #define I2C_ICR_OVRCF_Pos            (10U)
3857 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
3858 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
3859 #define I2C_ICR_PECCF_Pos            (11U)
3860 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
3861 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
3862 #define I2C_ICR_TIMOUTCF_Pos         (12U)
3863 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
3864 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
3865 #define I2C_ICR_ALERTCF_Pos          (13U)
3866 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
3867 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
3868 
3869 /******************  Bit definition for I2C_PECR register  *********************/
3870 #define I2C_PECR_PEC_Pos             (0U)
3871 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
3872 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
3873 
3874 /******************  Bit definition for I2C_RXDR register  *********************/
3875 #define I2C_RXDR_RXDATA_Pos          (0U)
3876 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
3877 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
3878 
3879 /******************  Bit definition for I2C_TXDR register  *********************/
3880 #define I2C_TXDR_TXDATA_Pos          (0U)
3881 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
3882 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
3883 
3884 
3885 /******************************************************************************/
3886 /*                                                                            */
3887 /*                        Independent WATCHDOG (IWDG)                         */
3888 /*                                                                            */
3889 /******************************************************************************/
3890 /*******************  Bit definition for IWDG_KR register  ********************/
3891 #define IWDG_KR_KEY_Pos      (0U)
3892 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
3893 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
3894 
3895 /*******************  Bit definition for IWDG_PR register  ********************/
3896 #define IWDG_PR_PR_Pos       (0U)
3897 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
3898 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
3899 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
3900 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
3901 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
3902 
3903 /*******************  Bit definition for IWDG_RLR register  *******************/
3904 #define IWDG_RLR_RL_Pos      (0U)
3905 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
3906 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
3907 
3908 /*******************  Bit definition for IWDG_SR register  ********************/
3909 #define IWDG_SR_PVU_Pos      (0U)
3910 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
3911 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
3912 #define IWDG_SR_RVU_Pos      (1U)
3913 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
3914 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
3915 #define IWDG_SR_WVU_Pos      (2U)
3916 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
3917 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
3918 
3919 /*******************  Bit definition for IWDG_KR register  ********************/
3920 #define IWDG_WINR_WIN_Pos    (0U)
3921 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
3922 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
3923 
3924 
3925 /******************************************************************************/
3926 /*                                                                            */
3927 /*                        Power Control                                       */
3928 /*                                                                            */
3929 /******************************************************************************/
3930 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
3931 #define PWR_BOR_SUPPORT                       /*!< PWR feature available only on specific devices: Brown-Out Reset feature         */
3932 #define PWR_SHDW_SUPPORT                      /*!< PWR feature available only on specific devices: Shutdown mode */
3933 
3934 /********************  Bit definition for PWR_CR1 register  ********************/
3935 #define PWR_CR1_LPMS_Pos          (0U)
3936 #define PWR_CR1_LPMS_Msk          (0x7UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000007 */
3937 #define PWR_CR1_LPMS              PWR_CR1_LPMS_Msk                             /*!< Low Power Mode Selection */
3938 #define PWR_CR1_LPMS_0            (0x1UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000001 */
3939 #define PWR_CR1_LPMS_1            (0x2UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000002 */
3940 #define PWR_CR1_LPMS_2            (0x4UL << PWR_CR1_LPMS_Pos)                   /*!< 0x00000004 */
3941 #define PWR_CR1_FPD_STOP_Pos      (3U)
3942 #define PWR_CR1_FPD_STOP_Msk      (0x1UL << PWR_CR1_FPD_STOP_Pos)              /*!< 0x00000008 */
3943 #define PWR_CR1_FPD_STOP          PWR_CR1_FPD_STOP_Msk                         /*!< Flash power down mode during stop */
3944 #define PWR_CR1_FPD_LPRUN_Pos     (4U)
3945 #define PWR_CR1_FPD_LPRUN_Msk     (0x1UL << PWR_CR1_FPD_LPRUN_Pos)             /*!< 0x00000010 */
3946 #define PWR_CR1_FPD_LPRUN         PWR_CR1_FPD_LPRUN_Msk                        /*!< Flash power down mode during run */
3947 #define PWR_CR1_FPD_LPSLP_Pos     (5U)
3948 #define PWR_CR1_FPD_LPSLP_Msk     (0x1UL << PWR_CR1_FPD_LPSLP_Pos)             /*!< 0x00000020 */
3949 #define PWR_CR1_FPD_LPSLP         PWR_CR1_FPD_LPSLP_Msk                        /*!< Flash power down mode during sleep */
3950 #define PWR_CR1_DBP_Pos           (8U)
3951 #define PWR_CR1_DBP_Msk           (0x1UL << PWR_CR1_DBP_Pos)                   /*!< 0x00000100 */
3952 #define PWR_CR1_DBP               PWR_CR1_DBP_Msk                              /*!< Disable Backup Domain write protection */
3953 #define PWR_CR1_VOS_Pos           (9U)
3954 #define PWR_CR1_VOS_Msk           (0x3UL << PWR_CR1_VOS_Pos)                   /*!< 0x00000600 */
3955 #define PWR_CR1_VOS               PWR_CR1_VOS_Msk                              /*!< Voltage scaling */
3956 #define PWR_CR1_VOS_0             (0x1UL << PWR_CR1_VOS_Pos)                   /*!< Voltage scaling bit 0 */
3957 #define PWR_CR1_VOS_1             (0x2UL << PWR_CR1_VOS_Pos)                   /*!< Voltage scaling bit 1 */
3958 #define PWR_CR1_LPR_Pos           (14U)
3959 #define PWR_CR1_LPR_Msk           (0x1UL << PWR_CR1_LPR_Pos)                   /*!< 0x00004000 */
3960 #define PWR_CR1_LPR               PWR_CR1_LPR_Msk                              /*!< Regulator Low-Power Run mode */
3961 
3962 /********************  Bit definition for PWR_CR2 register  ********************/
3963 #define PWR_CR2_PVDE_Pos          (0U)
3964 #define PWR_CR2_PVDE_Msk          (0x1UL << PWR_CR2_PVDE_Pos)                  /*!< 0x00000001 */
3965 #define PWR_CR2_PVDE              PWR_CR2_PVDE_Msk                             /*!< Programmable Voltage Detector Enable */
3966 #define PWR_CR2_PVDFT_Pos         (1U)
3967 #define PWR_CR2_PVDFT_Msk         (0x7UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x0000000E */
3968 #define PWR_CR2_PVDFT             PWR_CR2_PVDFT_Msk                            /*!< PVD Falling Threshold Selection bit field */
3969 #define PWR_CR2_PVDFT_0           (0x1UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x00000002 */
3970 #define PWR_CR2_PVDFT_1           (0x2UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x00000004 */
3971 #define PWR_CR2_PVDFT_2           (0x4UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x00000008 */
3972 #define PWR_CR2_PVDRT_Pos         (4U)
3973 #define PWR_CR2_PVDRT_Msk         (0x7UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000070 */
3974 #define PWR_CR2_PVDRT             PWR_CR2_PVDRT_Msk                            /*!< PVD Rising Threshold Selection bit field */
3975 #define PWR_CR2_PVDRT_0           (0x1UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000010 */
3976 #define PWR_CR2_PVDRT_1           (0x2UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000020 */
3977 #define PWR_CR2_PVDRT_2           (0x4UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000040 */
3978 
3979 /********************  Bit definition for PWR_CR3 register  ********************/
3980 #define PWR_CR3_EWUP_Pos          (0U)
3981 #define PWR_CR3_EWUP_Msk          (0x2BUL << PWR_CR3_EWUP_Pos)                 /*!< 0x0000002B */
3982 #define PWR_CR3_EWUP              PWR_CR3_EWUP_Msk                             /*!< Enable all Wake-Up Pins  */
3983 #define PWR_CR3_EWUP1_Pos         (0U)
3984 #define PWR_CR3_EWUP1_Msk         (0x1UL << PWR_CR3_EWUP1_Pos)                 /*!< 0x00000001 */
3985 #define PWR_CR3_EWUP1             PWR_CR3_EWUP1_Msk                            /*!< Enable WKUP pin 1 */
3986 #define PWR_CR3_EWUP2_Pos         (1U)
3987 #define PWR_CR3_EWUP2_Msk         (0x1UL << PWR_CR3_EWUP2_Pos)                 /*!< 0x00000002 */
3988 #define PWR_CR3_EWUP2             PWR_CR3_EWUP2_Msk                            /*!< Enable WKUP pin 2 */
3989 #define PWR_CR3_EWUP4_Pos         (3U)
3990 #define PWR_CR3_EWUP4_Msk         (0x1UL << PWR_CR3_EWUP4_Pos)                 /*!< 0x00000008 */
3991 #define PWR_CR3_EWUP4             PWR_CR3_EWUP4_Msk                            /*!< Enable WKUP pin 4 */
3992 #define PWR_CR3_EWUP6_Pos         (5U)
3993 #define PWR_CR3_EWUP6_Msk         (0x1UL << PWR_CR3_EWUP6_Pos)                 /*!< 0x00000020 */
3994 #define PWR_CR3_EWUP6             PWR_CR3_EWUP6_Msk                            /*!< Enable WKUP pin 6 */
3995 #define PWR_CR3_RRS_Pos           (8U)
3996 #define PWR_CR3_RRS_Msk           (0x1UL << PWR_CR3_RRS_Pos)                   /*!< 0x00000100 */
3997 #define PWR_CR3_RRS               PWR_CR3_RRS_Msk                              /*!< RAM retention in Standby mode */
3998 #define PWR_CR3_ENB_ULP_Pos       (9U)
3999 #define PWR_CR3_ENB_ULP_Msk       (0x1UL << PWR_CR3_ENB_ULP_Pos)               /*!< 0x00000200 */
4000 #define PWR_CR3_ENB_ULP           PWR_CR3_ENB_ULP_Msk                          /*!< Enable sampling resistor bridge in the LPMU_RESET block */
4001 #define PWR_CR3_APC_Pos           (10U)
4002 #define PWR_CR3_APC_Msk           (0x1UL << PWR_CR3_APC_Pos)                   /*!< 0x00000400 */
4003 #define PWR_CR3_APC               PWR_CR3_APC_Msk                              /*!< Apply pull-up and pull-down configuration */
4004 #define PWR_CR3_EIWUL_Pos         (15U)
4005 #define PWR_CR3_EIWUL_Msk         (0x1UL << PWR_CR3_EIWUL_Pos)                 /*!< 0x00008000 */
4006 #define PWR_CR3_EIWUL             PWR_CR3_EIWUL_Msk                            /*!< Enable Internal Wake-up line */
4007 
4008 /********************  Bit definition for PWR_CR4 register  ********************/
4009 #define PWR_CR4_WP_Pos            (0U)
4010 #define PWR_CR4_WP_Msk            (0x2BUL << PWR_CR4_WP_Pos)                   /*!< 0x0000002B */
4011 #define PWR_CR4_WP                PWR_CR4_WP_Msk                               /*!< all Wake-Up Pin polarity */
4012 #define PWR_CR4_WP1_Pos           (0U)
4013 #define PWR_CR4_WP1_Msk           (0x1UL << PWR_CR4_WP1_Pos)                   /*!< 0x00000001 */
4014 #define PWR_CR4_WP1               PWR_CR4_WP1_Msk                              /*!< Wake-Up Pin 1 polarity */
4015 #define PWR_CR4_WP2_Pos           (1U)
4016 #define PWR_CR4_WP2_Msk           (0x1UL << PWR_CR4_WP2_Pos)                   /*!< 0x00000002 */
4017 #define PWR_CR4_WP2               PWR_CR4_WP2_Msk                              /*!< Wake-Up Pin 2 polarity */
4018 #define PWR_CR4_WP4_Pos           (3U)
4019 #define PWR_CR4_WP4_Msk           (0x1UL << PWR_CR4_WP4_Pos)                   /*!< 0x00000008 */
4020 #define PWR_CR4_WP4               PWR_CR4_WP4_Msk                              /*!< Wake-Up Pin 4 polarity */
4021 #define PWR_CR4_WP6_Pos           (5U)
4022 #define PWR_CR4_WP6_Msk           (0x1UL << PWR_CR4_WP6_Pos)                   /*!< 0x00000020 */
4023 #define PWR_CR4_WP6               PWR_CR4_WP6_Msk                              /*!< Wake-Up Pin 6 polarity */
4024 #define PWR_CR4_VBE_Pos           (8U)
4025 #define PWR_CR4_VBE_Msk           (0x1UL << PWR_CR4_VBE_Pos)                   /*!< 0x00000100 */
4026 #define PWR_CR4_VBE               PWR_CR4_VBE_Msk                              /*!< VBAT Battery charging Enable  */
4027 #define PWR_CR4_VBRS_Pos          (9U)
4028 #define PWR_CR4_VBRS_Msk          (0x1UL << PWR_CR4_VBRS_Pos)                  /*!< 0x00000200 */
4029 #define PWR_CR4_VBRS              PWR_CR4_VBRS_Msk                             /*!< VBAT Battery charging Resistor Selection */
4030 
4031 /********************  Bit definition for PWR_SR1 register  ********************/
4032 #define PWR_SR1_WUF_Pos           (0U)
4033 #define PWR_SR1_WUF_Msk           (0x2BUL << PWR_SR1_WUF_Pos)                  /*!< 0x0000002B */
4034 #define PWR_SR1_WUF               PWR_SR1_WUF_Msk                              /*!< Wakeup Flags  */
4035 #define PWR_SR1_WUF1_Pos          (0U)
4036 #define PWR_SR1_WUF1_Msk          (0x1UL << PWR_SR1_WUF1_Pos)                  /*!< 0x00000001 */
4037 #define PWR_SR1_WUF1              PWR_SR1_WUF1_Msk                             /*!< Wakeup Flag 1 */
4038 #define PWR_SR1_WUF2_Pos          (1U)
4039 #define PWR_SR1_WUF2_Msk          (0x1UL << PWR_SR1_WUF2_Pos)                  /*!< 0x00000002 */
4040 #define PWR_SR1_WUF2              PWR_SR1_WUF2_Msk                             /*!< Wakeup Flag 2 */
4041 #define PWR_SR1_WUF4_Pos          (3U)
4042 #define PWR_SR1_WUF4_Msk          (0x1UL << PWR_SR1_WUF4_Pos)                  /*!< 0x00000008 */
4043 #define PWR_SR1_WUF4              PWR_SR1_WUF4_Msk                             /*!< Wakeup Flag 4 */
4044 #define PWR_SR1_WUF6_Pos          (5U)
4045 #define PWR_SR1_WUF6_Msk          (0x1UL << PWR_SR1_WUF6_Pos)                  /*!< 0x00000020 */
4046 #define PWR_SR1_WUF6              PWR_SR1_WUF6_Msk                             /*!< Wakeup Flag 6 */
4047 #define PWR_SR1_SBF_Pos           (8U)
4048 #define PWR_SR1_SBF_Msk           (0x1UL << PWR_SR1_SBF_Pos)                   /*!< 0x00000100 */
4049 #define PWR_SR1_SBF               PWR_SR1_SBF_Msk                              /*!< Standby Flag  */
4050 #define PWR_SR1_WUFI_Pos          (15U)
4051 #define PWR_SR1_WUFI_Msk          (0x1UL << PWR_SR1_WUFI_Pos)                  /*!< 0x00008000 */
4052 #define PWR_SR1_WUFI              PWR_SR1_WUFI_Msk                             /*!< Wakeup Flag Internal */
4053 
4054 /********************  Bit definition for PWR_SR2 register  ********************/
4055 #define PWR_SR2_FLASH_RDY_Pos     (7U)
4056 #define PWR_SR2_FLASH_RDY_Msk     (0x1UL << PWR_SR2_FLASH_RDY_Pos)             /*!< 0x00000080 */
4057 #define PWR_SR2_FLASH_RDY         PWR_SR2_FLASH_RDY_Msk                        /*!< Flash Ready */
4058 #define PWR_SR2_REGLPS_Pos        (8U)
4059 #define PWR_SR2_REGLPS_Msk        (0x1UL << PWR_SR2_REGLPS_Pos)                /*!< 0x00000100 */
4060 #define PWR_SR2_REGLPS            PWR_SR2_REGLPS_Msk                           /*!< Regulator Low Power started */
4061 #define PWR_SR2_REGLPF_Pos        (9U)
4062 #define PWR_SR2_REGLPF_Msk        (0x1UL << PWR_SR2_REGLPF_Pos)                /*!< 0x00000200 */
4063 #define PWR_SR2_REGLPF            PWR_SR2_REGLPF_Msk                           /*!< Regulator Low Power flag    */
4064 #define PWR_SR2_VOSF_Pos          (10U)
4065 #define PWR_SR2_VOSF_Msk          (0x1UL << PWR_SR2_VOSF_Pos)                  /*!< 0x00000400 */
4066 #define PWR_SR2_VOSF              PWR_SR2_VOSF_Msk                             /*!< Voltage Scaling Flag */
4067 #define PWR_SR2_PVDO_Pos          (11U)
4068 #define PWR_SR2_PVDO_Msk          (0x1UL << PWR_SR2_PVDO_Pos)                  /*!< 0x00000800 */
4069 #define PWR_SR2_PVDO              PWR_SR2_PVDO_Msk                             /*!< Power voltage detector output */
4070 
4071 /********************  Bit definition for PWR_SCR register  ********************/
4072 #define PWR_SCR_CWUF_Pos          (0U)
4073 #define PWR_SCR_CWUF_Msk          (0x2BUL << PWR_SCR_CWUF_Pos)                 /*!< 0x0000002B */
4074 #define PWR_SCR_CWUF              PWR_SCR_CWUF_Msk                             /*!< Clear Wake-up Flags  */
4075 #define PWR_SCR_CWUF1_Pos         (0U)
4076 #define PWR_SCR_CWUF1_Msk         (0x1UL << PWR_SCR_CWUF1_Pos)                 /*!< 0x00000001 */
4077 #define PWR_SCR_CWUF1             PWR_SCR_CWUF1_Msk                            /*!< Clear Wake-up Flag 1 */
4078 #define PWR_SCR_CWUF2_Pos         (1U)
4079 #define PWR_SCR_CWUF2_Msk         (0x1UL << PWR_SCR_CWUF2_Pos)                 /*!< 0x00000002 */
4080 #define PWR_SCR_CWUF2             PWR_SCR_CWUF2_Msk                            /*!< Clear Wake-up Flag 2 */
4081 #define PWR_SCR_CWUF4_Pos         (3U)
4082 #define PWR_SCR_CWUF4_Msk         (0x1UL << PWR_SCR_CWUF4_Pos)                 /*!< 0x00000008 */
4083 #define PWR_SCR_CWUF4             PWR_SCR_CWUF4_Msk                            /*!< Clear Wake-up Flag 4 */
4084 #define PWR_SCR_CWUF6_Pos         (5U)
4085 #define PWR_SCR_CWUF6_Msk         (0x1UL << PWR_SCR_CWUF6_Pos)                 /*!< 0x00000020 */
4086 #define PWR_SCR_CWUF6             PWR_SCR_CWUF6_Msk                            /*!< Clear Wake-up Flag 6 */
4087 #define PWR_SCR_CSBF_Pos          (8U)
4088 #define PWR_SCR_CSBF_Msk          (0x1UL << PWR_SCR_CSBF_Pos)                  /*!< 0x00000100 */
4089 #define PWR_SCR_CSBF              PWR_SCR_CSBF_Msk                             /*!< Clear Standby Flag  */
4090 
4091 /********************  Bit definition for PWR_PUCRA register  *****************/
4092 #define PWR_PUCRA_PU0_Pos         (0U)
4093 #define PWR_PUCRA_PU0_Msk         (0x1UL << PWR_PUCRA_PU0_Pos)                 /*!< 0x00000001 */
4094 #define PWR_PUCRA_PU0             PWR_PUCRA_PU0_Msk                            /*!< Pin PA0 Pull-Up set */
4095 #define PWR_PUCRA_PU1_Pos         (1U)
4096 #define PWR_PUCRA_PU1_Msk         (0x1UL << PWR_PUCRA_PU1_Pos)                 /*!< 0x00000002 */
4097 #define PWR_PUCRA_PU1             PWR_PUCRA_PU1_Msk                            /*!< Pin PA1 Pull-Up set */
4098 #define PWR_PUCRA_PU2_Pos         (2U)
4099 #define PWR_PUCRA_PU2_Msk         (0x1UL << PWR_PUCRA_PU2_Pos)                 /*!< 0x00000004 */
4100 #define PWR_PUCRA_PU2             PWR_PUCRA_PU2_Msk                            /*!< Pin PA2 Pull-Up set */
4101 #define PWR_PUCRA_PU3_Pos         (3U)
4102 #define PWR_PUCRA_PU3_Msk         (0x1UL << PWR_PUCRA_PU3_Pos)                 /*!< 0x00000008 */
4103 #define PWR_PUCRA_PU3             PWR_PUCRA_PU3_Msk                            /*!< Pin PA3 Pull-Up set */
4104 #define PWR_PUCRA_PU4_Pos         (4U)
4105 #define PWR_PUCRA_PU4_Msk         (0x1UL << PWR_PUCRA_PU4_Pos)                 /*!< 0x00000010 */
4106 #define PWR_PUCRA_PU4             PWR_PUCRA_PU4_Msk                            /*!< Pin PA4 Pull-Up set */
4107 #define PWR_PUCRA_PU5_Pos         (5U)
4108 #define PWR_PUCRA_PU5_Msk         (0x1UL << PWR_PUCRA_PU5_Pos)                 /*!< 0x00000020 */
4109 #define PWR_PUCRA_PU5             PWR_PUCRA_PU5_Msk                            /*!< Pin PA5 Pull-Up set */
4110 #define PWR_PUCRA_PU6_Pos         (6U)
4111 #define PWR_PUCRA_PU6_Msk         (0x1UL << PWR_PUCRA_PU6_Pos)                 /*!< 0x00000040 */
4112 #define PWR_PUCRA_PU6             PWR_PUCRA_PU6_Msk                            /*!< Pin PA6 Pull-Up set */
4113 #define PWR_PUCRA_PU7_Pos         (7U)
4114 #define PWR_PUCRA_PU7_Msk         (0x1UL << PWR_PUCRA_PU7_Pos)                 /*!< 0x00000080 */
4115 #define PWR_PUCRA_PU7             PWR_PUCRA_PU7_Msk                            /*!< Pin PA7 Pull-Up set */
4116 #define PWR_PUCRA_PU8_Pos         (8U)
4117 #define PWR_PUCRA_PU8_Msk         (0x1UL << PWR_PUCRA_PU8_Pos)                 /*!< 0x00000100 */
4118 #define PWR_PUCRA_PU8             PWR_PUCRA_PU8_Msk                            /*!< Pin PA8 Pull-Up set */
4119 #define PWR_PUCRA_PU9_Pos         (9U)
4120 #define PWR_PUCRA_PU9_Msk         (0x1UL << PWR_PUCRA_PU9_Pos)                 /*!< 0x00000200 */
4121 #define PWR_PUCRA_PU9             PWR_PUCRA_PU9_Msk                            /*!< Pin PA9 Pull-Up set */
4122 #define PWR_PUCRA_PU10_Pos        (10U)
4123 #define PWR_PUCRA_PU10_Msk        (0x1UL << PWR_PUCRA_PU10_Pos)                /*!< 0x00000400 */
4124 #define PWR_PUCRA_PU10            PWR_PUCRA_PU10_Msk                           /*!< Pin PA10 Pull-Up set */
4125 #define PWR_PUCRA_PU11_Pos        (11U)
4126 #define PWR_PUCRA_PU11_Msk        (0x1UL << PWR_PUCRA_PU11_Pos)                /*!< 0x00000800 */
4127 #define PWR_PUCRA_PU11            PWR_PUCRA_PU11_Msk                           /*!< Pin PA11 Pull-Up set */
4128 #define PWR_PUCRA_PU12_Pos        (12U)
4129 #define PWR_PUCRA_PU12_Msk        (0x1UL << PWR_PUCRA_PU12_Pos)                /*!< 0x00001000 */
4130 #define PWR_PUCRA_PU12            PWR_PUCRA_PU12_Msk                           /*!< Pin PA12 Pull-Up set */
4131 #define PWR_PUCRA_PU13_Pos        (13U)
4132 #define PWR_PUCRA_PU13_Msk        (0x1UL << PWR_PUCRA_PU13_Pos)                /*!< 0x00002000 */
4133 #define PWR_PUCRA_PU13            PWR_PUCRA_PU13_Msk                           /*!< Pin PA13 Pull-Up set */
4134 #define PWR_PUCRA_PU14_Pos        (14U)
4135 #define PWR_PUCRA_PU14_Msk        (0x1UL << PWR_PUCRA_PU14_Pos)                /*!< 0x00004000 */
4136 #define PWR_PUCRA_PU14            PWR_PUCRA_PU14_Msk                           /*!< Pin PA14 Pull-Up set */
4137 #define PWR_PUCRA_PU15_Pos        (15U)
4138 #define PWR_PUCRA_PU15_Msk        (0x1UL << PWR_PUCRA_PU15_Pos)                /*!< 0x00008000 */
4139 #define PWR_PUCRA_PU15            PWR_PUCRA_PU15_Msk                           /*!< Pin PA15 Pull-Up set */
4140 
4141 /********************  Bit definition for PWR_PDCRA register  *****************/
4142 #define PWR_PDCRA_PD0_Pos         (0U)
4143 #define PWR_PDCRA_PD0_Msk         (0x1UL << PWR_PDCRA_PD0_Pos)                 /*!< 0x00000001 */
4144 #define PWR_PDCRA_PD0             PWR_PDCRA_PD0_Msk                            /*!< Pin PA0 Pull-Down set */
4145 #define PWR_PDCRA_PD1_Pos         (1U)
4146 #define PWR_PDCRA_PD1_Msk         (0x1UL << PWR_PDCRA_PD1_Pos)                 /*!< 0x00000002 */
4147 #define PWR_PDCRA_PD1             PWR_PDCRA_PD1_Msk                            /*!< Pin PA1 Pull-Down set */
4148 #define PWR_PDCRA_PD2_Pos         (2U)
4149 #define PWR_PDCRA_PD2_Msk         (0x1UL << PWR_PDCRA_PD2_Pos)                 /*!< 0x00000004 */
4150 #define PWR_PDCRA_PD2             PWR_PDCRA_PD2_Msk                            /*!< Pin PA2 Pull-Down set */
4151 #define PWR_PDCRA_PD3_Pos         (3U)
4152 #define PWR_PDCRA_PD3_Msk         (0x1UL << PWR_PDCRA_PD3_Pos)                 /*!< 0x00000008 */
4153 #define PWR_PDCRA_PD3             PWR_PDCRA_PD3_Msk                            /*!< Pin PA3 Pull-Down set */
4154 #define PWR_PDCRA_PD4_Pos         (4U)
4155 #define PWR_PDCRA_PD4_Msk         (0x1UL << PWR_PDCRA_PD4_Pos)                 /*!< 0x00000010 */
4156 #define PWR_PDCRA_PD4             PWR_PDCRA_PD4_Msk                            /*!< Pin PA4 Pull-Down set */
4157 #define PWR_PDCRA_PD5_Pos         (5U)
4158 #define PWR_PDCRA_PD5_Msk         (0x1UL << PWR_PDCRA_PD5_Pos)                 /*!< 0x00000020 */
4159 #define PWR_PDCRA_PD5             PWR_PDCRA_PD5_Msk                            /*!< Pin PA5 Pull-Down set */
4160 #define PWR_PDCRA_PD6_Pos         (6U)
4161 #define PWR_PDCRA_PD6_Msk         (0x1UL << PWR_PDCRA_PD6_Pos)                 /*!< 0x00000040 */
4162 #define PWR_PDCRA_PD6             PWR_PDCRA_PD6_Msk                            /*!< Pin PA6 Pull-Down set */
4163 #define PWR_PDCRA_PD7_Pos         (7U)
4164 #define PWR_PDCRA_PD7_Msk         (0x1UL << PWR_PDCRA_PD7_Pos)                 /*!< 0x00000080 */
4165 #define PWR_PDCRA_PD7             PWR_PDCRA_PD7_Msk                            /*!< Pin PA7 Pull-Down set */
4166 #define PWR_PDCRA_PD8_Pos         (8U)
4167 #define PWR_PDCRA_PD8_Msk         (0x1UL << PWR_PDCRA_PD8_Pos)                 /*!< 0x00000100 */
4168 #define PWR_PDCRA_PD8             PWR_PDCRA_PD8_Msk                            /*!< Pin PA8 Pull-Down set */
4169 #define PWR_PDCRA_PD9_Pos         (9U)
4170 #define PWR_PDCRA_PD9_Msk         (0x1UL << PWR_PDCRA_PD9_Pos)                 /*!< 0x00000200 */
4171 #define PWR_PDCRA_PD9             PWR_PDCRA_PD9_Msk                            /*!< Pin PA9 Pull-Down set */
4172 #define PWR_PDCRA_PD10_Pos        (10U)
4173 #define PWR_PDCRA_PD10_Msk        (0x1UL << PWR_PDCRA_PD10_Pos)                /*!< 0x00000400 */
4174 #define PWR_PDCRA_PD10            PWR_PDCRA_PD10_Msk                           /*!< Pin PA10 Pull-Down set */
4175 #define PWR_PDCRA_PD11_Pos        (11U)
4176 #define PWR_PDCRA_PD11_Msk        (0x1UL << PWR_PDCRA_PD11_Pos)                /*!< 0x00000800 */
4177 #define PWR_PDCRA_PD11            PWR_PDCRA_PD11_Msk                           /*!< Pin PA11 Pull-Down set */
4178 #define PWR_PDCRA_PD12_Pos        (12U)
4179 #define PWR_PDCRA_PD12_Msk        (0x1UL << PWR_PDCRA_PD12_Pos)                /*!< 0x00001000 */
4180 #define PWR_PDCRA_PD12            PWR_PDCRA_PD12_Msk                           /*!< Pin PA12 Pull-Down set */
4181 #define PWR_PDCRA_PD13_Pos        (13U)
4182 #define PWR_PDCRA_PD13_Msk        (0x1UL << PWR_PDCRA_PD13_Pos)                /*!< 0x00002000 */
4183 #define PWR_PDCRA_PD13            PWR_PDCRA_PD13_Msk                           /*!< Pin PA13 Pull-Down set */
4184 #define PWR_PDCRA_PD14_Pos        (14U)
4185 #define PWR_PDCRA_PD14_Msk        (0x1UL << PWR_PDCRA_PD14_Pos)                /*!< 0x00004000 */
4186 #define PWR_PDCRA_PD14            PWR_PDCRA_PD14_Msk                           /*!< Pin PA14 Pull-Down set */
4187 #define PWR_PDCRA_PD15_Pos        (15U)
4188 #define PWR_PDCRA_PD15_Msk        (0x1UL << PWR_PDCRA_PD15_Pos)                /*!< 0x00008000 */
4189 #define PWR_PDCRA_PD15            PWR_PDCRA_PD15_Msk                           /*!< Pin PA15 Pull-Down set */
4190 
4191 /********************  Bit definition for PWR_PUCRB register  *****************/
4192 #define PWR_PUCRB_PU0_Pos         (0U)
4193 #define PWR_PUCRB_PU0_Msk         (0x1UL << PWR_PUCRB_PU0_Pos)                 /*!< 0x00000001 */
4194 #define PWR_PUCRB_PU0             PWR_PUCRB_PU0_Msk                            /*!< Pin PB0 Pull-Up set */
4195 #define PWR_PUCRB_PU1_Pos         (1U)
4196 #define PWR_PUCRB_PU1_Msk         (0x1UL << PWR_PUCRB_PU1_Pos)                 /*!< 0x00000002 */
4197 #define PWR_PUCRB_PU1             PWR_PUCRB_PU1_Msk                            /*!< Pin PB1 Pull-Up set */
4198 #define PWR_PUCRB_PU2_Pos         (2U)
4199 #define PWR_PUCRB_PU2_Msk         (0x1UL << PWR_PUCRB_PU2_Pos)                 /*!< 0x00000004 */
4200 #define PWR_PUCRB_PU2             PWR_PUCRB_PU2_Msk                            /*!< Pin PB2 Pull-Up set */
4201 #define PWR_PUCRB_PU3_Pos         (3U)
4202 #define PWR_PUCRB_PU3_Msk         (0x1UL << PWR_PUCRB_PU3_Pos)                 /*!< 0x00000008 */
4203 #define PWR_PUCRB_PU3             PWR_PUCRB_PU3_Msk                            /*!< Pin PB3 Pull-Up set */
4204 #define PWR_PUCRB_PU4_Pos         (4U)
4205 #define PWR_PUCRB_PU4_Msk         (0x1UL << PWR_PUCRB_PU4_Pos)                 /*!< 0x00000010 */
4206 #define PWR_PUCRB_PU4             PWR_PUCRB_PU4_Msk                            /*!< Pin PB4 Pull-Up set */
4207 #define PWR_PUCRB_PU5_Pos         (5U)
4208 #define PWR_PUCRB_PU5_Msk         (0x1UL << PWR_PUCRB_PU5_Pos)                 /*!< 0x00000020 */
4209 #define PWR_PUCRB_PU5             PWR_PUCRB_PU5_Msk                            /*!< Pin PB5 Pull-Up set */
4210 #define PWR_PUCRB_PU6_Pos         (6U)
4211 #define PWR_PUCRB_PU6_Msk         (0x1UL << PWR_PUCRB_PU6_Pos)                 /*!< 0x00000040 */
4212 #define PWR_PUCRB_PU6             PWR_PUCRB_PU6_Msk                            /*!< Pin PB6 Pull-Up set */
4213 #define PWR_PUCRB_PU7_Pos         (7U)
4214 #define PWR_PUCRB_PU7_Msk         (0x1UL << PWR_PUCRB_PU7_Pos)                 /*!< 0x00000080 */
4215 #define PWR_PUCRB_PU7             PWR_PUCRB_PU7_Msk                            /*!< Pin PB7 Pull-Up set */
4216 #define PWR_PUCRB_PU8_Pos         (8U)
4217 #define PWR_PUCRB_PU8_Msk         (0x1UL << PWR_PUCRB_PU8_Pos)                 /*!< 0x00000100 */
4218 #define PWR_PUCRB_PU8             PWR_PUCRB_PU8_Msk                            /*!< Pin PB8 Pull-Up set */
4219 #define PWR_PUCRB_PU9_Pos         (9U)
4220 #define PWR_PUCRB_PU9_Msk         (0x1UL << PWR_PUCRB_PU9_Pos)                 /*!< 0x00000200 */
4221 #define PWR_PUCRB_PU9             PWR_PUCRB_PU9_Msk                            /*!< Pin PB9 Pull-Up set */
4222 #define PWR_PUCRB_PU10_Pos        (10U)
4223 #define PWR_PUCRB_PU10_Msk        (0x1UL << PWR_PUCRB_PU10_Pos)                /*!< 0x00000400 */
4224 #define PWR_PUCRB_PU10            PWR_PUCRB_PU10_Msk                           /*!< Pin PB10 Pull-Up set */
4225 #define PWR_PUCRB_PU11_Pos        (11U)
4226 #define PWR_PUCRB_PU11_Msk        (0x1UL << PWR_PUCRB_PU11_Pos)                /*!< 0x00000800 */
4227 #define PWR_PUCRB_PU11            PWR_PUCRB_PU11_Msk                           /*!< Pin PB11 Pull-Up set */
4228 #define PWR_PUCRB_PU12_Pos        (12U)
4229 #define PWR_PUCRB_PU12_Msk        (0x1UL << PWR_PUCRB_PU12_Pos)                /*!< 0x00001000 */
4230 #define PWR_PUCRB_PU12            PWR_PUCRB_PU12_Msk                           /*!< Pin PB12 Pull-Up set */
4231 #define PWR_PUCRB_PU13_Pos        (13U)
4232 #define PWR_PUCRB_PU13_Msk        (0x1UL << PWR_PUCRB_PU13_Pos)                /*!< 0x00002000 */
4233 #define PWR_PUCRB_PU13            PWR_PUCRB_PU13_Msk                           /*!< Pin PB13 Pull-Up set */
4234 #define PWR_PUCRB_PU14_Pos        (14U)
4235 #define PWR_PUCRB_PU14_Msk        (0x1UL << PWR_PUCRB_PU14_Pos)                /*!< 0x00004000 */
4236 #define PWR_PUCRB_PU14            PWR_PUCRB_PU14_Msk                           /*!< Pin PB14 Pull-Up set */
4237 #define PWR_PUCRB_PU15_Pos        (15U)
4238 #define PWR_PUCRB_PU15_Msk        (0x1UL << PWR_PUCRB_PU15_Pos)                /*!< 0x00008000 */
4239 #define PWR_PUCRB_PU15            PWR_PUCRB_PU15_Msk                           /*!< Pin PB15 Pull-Up set */
4240 
4241 /********************  Bit definition for PWR_PDCRB register  *****************/
4242 #define PWR_PDCRB_PD0_Pos         (0U)
4243 #define PWR_PDCRB_PD0_Msk         (0x1UL << PWR_PDCRB_PD0_Pos)                 /*!< 0x00000001 */
4244 #define PWR_PDCRB_PD0             PWR_PDCRB_PD0_Msk                            /*!< Pin PB0 Pull-Down set */
4245 #define PWR_PDCRB_PD1_Pos         (1U)
4246 #define PWR_PDCRB_PD1_Msk         (0x1UL << PWR_PDCRB_PD1_Pos)                 /*!< 0x00000002 */
4247 #define PWR_PDCRB_PD1             PWR_PDCRB_PD1_Msk                            /*!< Pin PB1 Pull-Down set */
4248 #define PWR_PDCRB_PD2_Pos         (2U)
4249 #define PWR_PDCRB_PD2_Msk         (0x1UL << PWR_PDCRB_PD2_Pos)                 /*!< 0x00000004 */
4250 #define PWR_PDCRB_PD2             PWR_PDCRB_PD2_Msk                            /*!< Pin PB2 Pull-Down set */
4251 #define PWR_PDCRB_PD3_Pos         (3U)
4252 #define PWR_PDCRB_PD3_Msk         (0x1UL << PWR_PDCRB_PD3_Pos)                 /*!< 0x00000008 */
4253 #define PWR_PDCRB_PD3             PWR_PDCRB_PD3_Msk                            /*!< Pin PB3 Pull-Down set */
4254 #define PWR_PDCRB_PD4_Pos         (4U)
4255 #define PWR_PDCRB_PD4_Msk         (0x1UL << PWR_PDCRB_PD4_Pos)                 /*!< 0x00000010 */
4256 #define PWR_PDCRB_PD4             PWR_PDCRB_PD4_Msk                            /*!< Pin PB4 Pull-Down set */
4257 #define PWR_PDCRB_PD5_Pos         (5U)
4258 #define PWR_PDCRB_PD5_Msk         (0x1UL << PWR_PDCRB_PD5_Pos)                 /*!< 0x00000020 */
4259 #define PWR_PDCRB_PD5             PWR_PDCRB_PD5_Msk                            /*!< Pin PB5 Pull-Down set */
4260 #define PWR_PDCRB_PD6_Pos         (6U)
4261 #define PWR_PDCRB_PD6_Msk         (0x1UL << PWR_PDCRB_PD6_Pos)                 /*!< 0x00000040 */
4262 #define PWR_PDCRB_PD6             PWR_PDCRB_PD6_Msk                            /*!< Pin PB6 Pull-Down set */
4263 #define PWR_PDCRB_PD7_Pos         (7U)
4264 #define PWR_PDCRB_PD7_Msk         (0x1UL << PWR_PDCRB_PD7_Pos)                 /*!< 0x00000080 */
4265 #define PWR_PDCRB_PD7             PWR_PDCRB_PD7_Msk                            /*!< Pin PB7 Pull-Down set */
4266 #define PWR_PDCRB_PD8_Pos         (8U)
4267 #define PWR_PDCRB_PD8_Msk         (0x1UL << PWR_PDCRB_PD8_Pos)                 /*!< 0x00000100 */
4268 #define PWR_PDCRB_PD8             PWR_PDCRB_PD8_Msk                            /*!< Pin PB8 Pull-Down set */
4269 #define PWR_PDCRB_PD9_Pos         (9U)
4270 #define PWR_PDCRB_PD9_Msk         (0x1UL << PWR_PDCRB_PD9_Pos)                 /*!< 0x00000200 */
4271 #define PWR_PDCRB_PD9             PWR_PDCRB_PD9_Msk                            /*!< Pin PB9 Pull-Down set */
4272 #define PWR_PDCRB_PD10_Pos        (10U)
4273 #define PWR_PDCRB_PD10_Msk        (0x1UL << PWR_PDCRB_PD10_Pos)                /*!< 0x00000400 */
4274 #define PWR_PDCRB_PD10            PWR_PDCRB_PD10_Msk                           /*!< Pin PB10 Pull-Down set */
4275 #define PWR_PDCRB_PD11_Pos        (11U)
4276 #define PWR_PDCRB_PD11_Msk        (0x1UL << PWR_PDCRB_PD11_Pos)                /*!< 0x00000800 */
4277 #define PWR_PDCRB_PD11            PWR_PDCRB_PD11_Msk                           /*!< Pin PB11 Pull-Down set */
4278 #define PWR_PDCRB_PD12_Pos        (12U)
4279 #define PWR_PDCRB_PD12_Msk        (0x1UL << PWR_PDCRB_PD12_Pos)                /*!< 0x00001000 */
4280 #define PWR_PDCRB_PD12            PWR_PDCRB_PD12_Msk                           /*!< Pin PB12 Pull-Down set */
4281 #define PWR_PDCRB_PD13_Pos        (13U)
4282 #define PWR_PDCRB_PD13_Msk        (0x1UL << PWR_PDCRB_PD13_Pos)                /*!< 0x00002000 */
4283 #define PWR_PDCRB_PD13            PWR_PDCRB_PD13_Msk                           /*!< Pin PB13 Pull-Down set */
4284 #define PWR_PDCRB_PD14_Pos        (14U)
4285 #define PWR_PDCRB_PD14_Msk        (0x1UL << PWR_PDCRB_PD14_Pos)                /*!< 0x00004000 */
4286 #define PWR_PDCRB_PD14            PWR_PDCRB_PD14_Msk                           /*!< Pin PB14 Pull-Down set */
4287 #define PWR_PDCRB_PD15_Pos        (15U)
4288 #define PWR_PDCRB_PD15_Msk        (0x1UL << PWR_PDCRB_PD15_Pos)                /*!< 0x00008000 */
4289 #define PWR_PDCRB_PD15            PWR_PDCRB_PD15_Msk                           /*!< Pin PB15 Pull-Down set */
4290 
4291 /********************  Bit definition for PWR_PUCRC register  *****************/
4292 #define PWR_PUCRC_PU6_Pos         (6U)
4293 #define PWR_PUCRC_PU6_Msk         (0x1UL << PWR_PUCRC_PU6_Pos)                 /*!< 0x00000040 */
4294 #define PWR_PUCRC_PU6             PWR_PUCRC_PU6_Msk                            /*!< Pin PC6 Pull-Up set */
4295 #define PWR_PUCRC_PU7_Pos         (7U)
4296 #define PWR_PUCRC_PU7_Msk         (0x1UL << PWR_PUCRC_PU7_Pos)                 /*!< 0x00000080 */
4297 #define PWR_PUCRC_PU7             PWR_PUCRC_PU7_Msk                            /*!< Pin PC7 Pull-Up set */
4298 #define PWR_PUCRC_PU13_Pos        (13U)
4299 #define PWR_PUCRC_PU13_Msk        (0x1UL << PWR_PUCRC_PU13_Pos)                /*!< 0x00002000 */
4300 #define PWR_PUCRC_PU13            PWR_PUCRC_PU13_Msk                           /*!< Pin PC13 Pull-Up set */
4301 #define PWR_PUCRC_PU14_Pos        (14U)
4302 #define PWR_PUCRC_PU14_Msk        (0x1UL << PWR_PUCRC_PU14_Pos)                /*!< 0x00004000 */
4303 #define PWR_PUCRC_PU14            PWR_PUCRC_PU14_Msk                           /*!< Pin PC14 Pull-Up set */
4304 #define PWR_PUCRC_PU15_Pos        (15U)
4305 #define PWR_PUCRC_PU15_Msk        (0x1UL << PWR_PUCRC_PU15_Pos)                /*!< 0x00008000 */
4306 #define PWR_PUCRC_PU15            PWR_PUCRC_PU15_Msk                           /*!< Pin PC15 Pull-Up set */
4307 
4308 /********************  Bit definition for PWR_PDCRC register  *****************/
4309 #define PWR_PDCRC_PD6_Pos         (6U)
4310 #define PWR_PDCRC_PD6_Msk         (0x1UL << PWR_PDCRC_PD6_Pos)                 /*!< 0x00000040 */
4311 #define PWR_PDCRC_PD6             PWR_PDCRC_PD6_Msk                            /*!< Pin PC6 Pull-Down set */
4312 #define PWR_PDCRC_PD7_Pos         (7U)
4313 #define PWR_PDCRC_PD7_Msk         (0x1UL << PWR_PDCRC_PD7_Pos)                 /*!< 0x00000080 */
4314 #define PWR_PDCRC_PD7             PWR_PDCRC_PD7_Msk                            /*!< Pin PC7 Pull-Down set */
4315 #define PWR_PDCRC_PD13_Pos        (13U)
4316 #define PWR_PDCRC_PD13_Msk        (0x1UL << PWR_PDCRC_PD13_Pos)                /*!< 0x00002000 */
4317 #define PWR_PDCRC_PD13            PWR_PDCRC_PD13_Msk                           /*!< Pin PC13 Pull-Down set */
4318 #define PWR_PDCRC_PD14_Pos        (14U)
4319 #define PWR_PDCRC_PD14_Msk        (0x1UL << PWR_PDCRC_PD14_Pos)                /*!< 0x00004000 */
4320 #define PWR_PDCRC_PD14            PWR_PDCRC_PD14_Msk                           /*!< Pin PC14 Pull-Down set */
4321 #define PWR_PDCRC_PD15_Pos        (15U)
4322 #define PWR_PDCRC_PD15_Msk        (0x1UL << PWR_PDCRC_PD15_Pos)                /*!< 0x00008000 */
4323 #define PWR_PDCRC_PD15            PWR_PDCRC_PD15_Msk                           /*!< Pin PC15 Pull-Down set */
4324 
4325 /********************  Bit definition for PWR_PUCRD register  *****************/
4326 #define PWR_PUCRD_PU0_Pos         (0U)
4327 #define PWR_PUCRD_PU0_Msk         (0x1UL << PWR_PUCRD_PU0_Pos)                 /*!< 0x00000001 */
4328 #define PWR_PUCRD_PU0             PWR_PUCRD_PU0_Msk                            /*!< Pin PD0 Pull-Up set */
4329 #define PWR_PUCRD_PU1_Pos         (1U)
4330 #define PWR_PUCRD_PU1_Msk         (0x1UL << PWR_PUCRD_PU1_Pos)                 /*!< 0x00000002 */
4331 #define PWR_PUCRD_PU1             PWR_PUCRD_PU1_Msk                            /*!< Pin PD1 Pull-Up set */
4332 #define PWR_PUCRD_PU2_Pos         (2U)
4333 #define PWR_PUCRD_PU2_Msk         (0x1UL << PWR_PUCRD_PU2_Pos)                 /*!< 0x00000004 */
4334 #define PWR_PUCRD_PU2             PWR_PUCRD_PU2_Msk                            /*!< Pin PD2 Pull-Up set */
4335 #define PWR_PUCRD_PU3_Pos         (3U)
4336 #define PWR_PUCRD_PU3_Msk         (0x1UL << PWR_PUCRD_PU3_Pos)                 /*!< 0x00000008 */
4337 #define PWR_PUCRD_PU3             PWR_PUCRD_PU3_Msk                            /*!< Pin PD3 Pull-Up set */
4338 
4339 /********************  Bit definition for PWR_PDCRD register  *****************/
4340 #define PWR_PDCRD_PD0_Pos         (0U)
4341 #define PWR_PDCRD_PD0_Msk         (0x1UL << PWR_PDCRD_PD0_Pos)                 /*!< 0x00000001 */
4342 #define PWR_PDCRD_PD0             PWR_PDCRD_PD0_Msk                            /*!< Pin PD0 Pull-Down set */
4343 #define PWR_PDCRD_PD1_Pos         (1U)
4344 #define PWR_PDCRD_PD1_Msk         (0x1UL << PWR_PDCRD_PD1_Pos)                 /*!< 0x00000002 */
4345 #define PWR_PDCRD_PD1             PWR_PDCRD_PD1_Msk                            /*!< Pin PD1 Pull-Down set */
4346 #define PWR_PDCRD_PD2_Pos         (2U)
4347 #define PWR_PDCRD_PD2_Msk         (0x1UL << PWR_PDCRD_PD2_Pos)                 /*!< 0x00000004 */
4348 #define PWR_PDCRD_PD2             PWR_PDCRD_PD2_Msk                            /*!< Pin PD2 Pull-Down set */
4349 #define PWR_PDCRD_PD3_Pos         (3U)
4350 #define PWR_PDCRD_PD3_Msk         (0x1UL << PWR_PDCRD_PD3_Pos)                 /*!< 0x00000008 */
4351 #define PWR_PDCRD_PD3             PWR_PDCRD_PD3_Msk                            /*!< Pin PD3 Pull-Down set */
4352 
4353 /********************  Bit definition for PWR_PUCRF register  *****************/
4354 #define PWR_PUCRF_PU0_Pos         (0U)
4355 #define PWR_PUCRF_PU0_Msk         (0x1UL << PWR_PUCRF_PU0_Pos)                 /*!< 0x00000001 */
4356 #define PWR_PUCRF_PU0             PWR_PUCRF_PU0_Msk                            /*!< Pin PF0 Pull-Up set */
4357 #define PWR_PUCRF_PU1_Pos         (1U)
4358 #define PWR_PUCRF_PU1_Msk         (0x1UL << PWR_PUCRF_PU1_Pos)                 /*!< 0x00000002 */
4359 #define PWR_PUCRF_PU1             PWR_PUCRF_PU1_Msk                            /*!< Pin PF1 Pull-Up set */
4360 #define PWR_PUCRF_PU2_Pos         (2U)
4361 #define PWR_PUCRF_PU2_Msk         (0x1UL << PWR_PUCRF_PU2_Pos)                 /*!< 0x00000004 */
4362 #define PWR_PUCRF_PU2             PWR_PUCRF_PU2_Msk                            /*!< Pin PF2 Pull-Up set */
4363 
4364 /********************  Bit definition for PWR_PDCRF register  *****************/
4365 #define PWR_PDCRF_PD0_Pos         (0U)
4366 #define PWR_PDCRF_PD0_Msk         (0x1UL << PWR_PDCRF_PD0_Pos)                 /*!< 0x00000001 */
4367 #define PWR_PDCRF_PD0             PWR_PDCRF_PD0_Msk                            /*!< Pin PF0 Pull-Down set */
4368 #define PWR_PDCRF_PD1_Pos         (1U)
4369 #define PWR_PDCRF_PD1_Msk         (0x1UL << PWR_PDCRF_PD1_Pos)                 /*!< 0x00000002 */
4370 #define PWR_PDCRF_PD1             PWR_PDCRF_PD1_Msk                            /*!< Pin PF1 Pull-Down set */
4371 #define PWR_PDCRF_PD2_Pos         (2U)
4372 #define PWR_PDCRF_PD2_Msk         (0x1UL << PWR_PDCRF_PD2_Pos)                 /*!< 0x00000004 */
4373 #define PWR_PDCRF_PD2             PWR_PDCRF_PD2_Msk                            /*!< Pin PF2 Pull-Down set */
4374 
4375 /******************************************************************************/
4376 /*                                                                            */
4377 /*                           Reset and Clock Control                          */
4378 /*                                                                            */
4379 /******************************************************************************/
4380 /*
4381 * @brief Specific device feature definitions  (not present on all devices in the STM32G0 series)
4382 */
4383 #define RCC_PLLQ_SUPPORT
4384 
4385 /********************  Bit definition for RCC_CR register  *****************/
4386 #define RCC_CR_HSION_Pos                 (8U)
4387 #define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000100 */
4388 #define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
4389 #define RCC_CR_HSIKERON_Pos              (9U)
4390 #define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)        /*!< 0x00000200 */
4391 #define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
4392 #define RCC_CR_HSIRDY_Pos                (10U)
4393 #define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)          /*!< 0x00000400 */
4394 #define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
4395 #define RCC_CR_HSIDIV_Pos                (11U)
4396 #define RCC_CR_HSIDIV_Msk                (0x7UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00003800 */
4397 #define RCC_CR_HSIDIV                    RCC_CR_HSIDIV_Msk                     /*!< HSIDIV[13:11] Internal High Speed clock division factor */
4398 #define RCC_CR_HSIDIV_0                  (0x1UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00000800 */
4399 #define RCC_CR_HSIDIV_1                  (0x2UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00001000 */
4400 #define RCC_CR_HSIDIV_2                  (0x4UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00002000 */
4401 #define RCC_CR_HSEON_Pos                 (16U)
4402 #define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00010000 */
4403 #define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
4404 #define RCC_CR_HSERDY_Pos                (17U)
4405 #define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)          /*!< 0x00020000 */
4406 #define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready */
4407 #define RCC_CR_HSEBYP_Pos                (18U)
4408 #define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)          /*!< 0x00040000 */
4409 #define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
4410 #define RCC_CR_CSSON_Pos                 (19U)
4411 #define RCC_CR_CSSON_Msk                 (0x1UL << RCC_CR_CSSON_Pos)           /*!< 0x00080000 */
4412 #define RCC_CR_CSSON                     RCC_CR_CSSON_Msk                      /*!< HSE Clock Security System enable */
4413 
4414 #define RCC_CR_PLLON_Pos                 (24U)
4415 #define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)           /*!< 0x01000000 */
4416 #define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< System PLL clock enable */
4417 #define RCC_CR_PLLRDY_Pos                (25U)
4418 #define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)          /*!< 0x02000000 */
4419 #define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< System PLL clock ready */
4420 
4421 /********************  Bit definition for RCC_ICSCR register  ***************/
4422 /*!< HSICAL configuration */
4423 #define RCC_ICSCR_HSICAL_Pos             (0U)
4424 #define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x000000FF */
4425 #define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< HSICAL[7:0] bits */
4426 #define RCC_ICSCR_HSICAL_0               (0x01UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000001 */
4427 #define RCC_ICSCR_HSICAL_1               (0x02UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000002 */
4428 #define RCC_ICSCR_HSICAL_2               (0x04UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000004 */
4429 #define RCC_ICSCR_HSICAL_3               (0x08UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000008 */
4430 #define RCC_ICSCR_HSICAL_4               (0x10UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000010 */
4431 #define RCC_ICSCR_HSICAL_5               (0x20UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000020 */
4432 #define RCC_ICSCR_HSICAL_6               (0x40UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000040 */
4433 #define RCC_ICSCR_HSICAL_7               (0x80UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000080 */
4434 
4435 /*!< HSITRIM configuration */
4436 #define RCC_ICSCR_HSITRIM_Pos            (8U)
4437 #define RCC_ICSCR_HSITRIM_Msk            (0x7FUL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00007F00 */
4438 #define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< HSITRIM[14:8] bits */
4439 #define RCC_ICSCR_HSITRIM_0              (0x01UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000100 */
4440 #define RCC_ICSCR_HSITRIM_1              (0x02UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000200 */
4441 #define RCC_ICSCR_HSITRIM_2              (0x04UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000400 */
4442 #define RCC_ICSCR_HSITRIM_3              (0x08UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000800 */
4443 #define RCC_ICSCR_HSITRIM_4              (0x10UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00001000 */
4444 #define RCC_ICSCR_HSITRIM_5              (0x20UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00002000 */
4445 #define RCC_ICSCR_HSITRIM_6              (0x40UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00004000 */
4446 
4447 /********************  Bit definition for RCC_CFGR register  ***************/
4448 /*!< SW configuration */
4449 #define RCC_CFGR_SW_Pos                (0U)
4450 #define RCC_CFGR_SW_Msk                (0x7UL << RCC_CFGR_SW_Pos)              /*!< 0x00000007 */
4451 #define RCC_CFGR_SW                    RCC_CFGR_SW_Msk                         /*!< SW[2:0] bits (System clock Switch) */
4452 #define RCC_CFGR_SW_0                  (0x1UL << RCC_CFGR_SW_Pos)              /*!< 0x00000001 */
4453 #define RCC_CFGR_SW_1                  (0x2UL << RCC_CFGR_SW_Pos)              /*!< 0x00000002 */
4454 #define RCC_CFGR_SW_2                  (0x4UL << RCC_CFGR_SW_Pos)              /*!< 0x00000004 */
4455 
4456 /*!< SWS configuration */
4457 #define RCC_CFGR_SWS_Pos               (3U)
4458 #define RCC_CFGR_SWS_Msk               (0x7UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000038 */
4459 #define RCC_CFGR_SWS                   RCC_CFGR_SWS_Msk                        /*!< SWS[2:0] bits (System Clock Switch Status) */
4460 #define RCC_CFGR_SWS_0                 (0x1UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000008 */
4461 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
4462 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
4463 
4464 /*!< HPRE configuration */
4465 #define RCC_CFGR_HPRE_Pos              (8U)
4466 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
4467 #define RCC_CFGR_HPRE                  RCC_CFGR_HPRE_Msk                       /*!< HPRE[3:0] bits (AHB prescaler) */
4468 #define RCC_CFGR_HPRE_0                (0x1UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000100 */
4469 #define RCC_CFGR_HPRE_1                (0x2UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000200 */
4470 #define RCC_CFGR_HPRE_2                (0x4UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000400 */
4471 #define RCC_CFGR_HPRE_3                (0x8UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000800 */
4472 
4473 /*!< PPRE configuration */
4474 #define RCC_CFGR_PPRE_Pos              (12U)
4475 #define RCC_CFGR_PPRE_Msk              (0x7UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00007000 */
4476 #define RCC_CFGR_PPRE                  RCC_CFGR_PPRE_Msk                       /*!< PRE1[2:0] bits (APB prescaler) */
4477 #define RCC_CFGR_PPRE_0                (0x1UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00001000 */
4478 #define RCC_CFGR_PPRE_1                (0x2UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00002000 */
4479 #define RCC_CFGR_PPRE_2                (0x4UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00004000 */
4480 
4481 
4482 /*!< MCOSEL configuration */
4483 #define RCC_CFGR_MCOSEL_Pos            (24U)
4484 #define RCC_CFGR_MCOSEL_Msk            (0x7UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x07000000 */
4485 #define RCC_CFGR_MCOSEL                RCC_CFGR_MCOSEL_Msk                     /*!< MCOSEL [2:0] bits (Clock output selection) */
4486 #define RCC_CFGR_MCOSEL_0              (0x1UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x01000000 */
4487 #define RCC_CFGR_MCOSEL_1              (0x2UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x02000000 */
4488 #define RCC_CFGR_MCOSEL_2              (0x4UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x04000000 */
4489 
4490 /*!< MCO Prescaler configuration */
4491 #define RCC_CFGR_MCOPRE_Pos            (28U)
4492 #define RCC_CFGR_MCOPRE_Msk            (0x7UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x70000000 */
4493 #define RCC_CFGR_MCOPRE                RCC_CFGR_MCOPRE_Msk                     /*!< MCO prescaler [2:0] */
4494 #define RCC_CFGR_MCOPRE_0              (0x1UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x10000000 */
4495 #define RCC_CFGR_MCOPRE_1              (0x2UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x20000000 */
4496 #define RCC_CFGR_MCOPRE_2              (0x4UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x40000000 */
4497 
4498 /********************  Bit definition for RCC_PLLCFGR register  ***************/
4499 #define RCC_PLLCFGR_PLLSRC_Pos           (0U)
4500 #define RCC_PLLCFGR_PLLSRC_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)     /*!< 0x00000003 */
4501 #define RCC_PLLCFGR_PLLSRC               RCC_PLLCFGR_PLLSRC_Msk
4502 #define RCC_PLLCFGR_PLLSRC_0             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)     /*!< 0x00000001 */
4503 #define RCC_PLLCFGR_PLLSRC_1             (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)     /*!< 0x00000002 */
4504 
4505 #define RCC_PLLCFGR_PLLSRC_NONE          (0x00000000UL)                        /*!< No clock sent to PLL      */
4506 #define RCC_PLLCFGR_PLLSRC_HSI_Pos       (1U)
4507 #define RCC_PLLCFGR_PLLSRC_HSI_Msk       (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
4508 #define RCC_PLLCFGR_PLLSRC_HSI           RCC_PLLCFGR_PLLSRC_HSI_Msk            /*!< HSI source clock selected */
4509 #define RCC_PLLCFGR_PLLSRC_HSE_Pos       (0U)
4510 #define RCC_PLLCFGR_PLLSRC_HSE_Msk       (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
4511 #define RCC_PLLCFGR_PLLSRC_HSE           RCC_PLLCFGR_PLLSRC_HSE_Msk            /*!< HSE source clock selected */
4512 
4513 #define RCC_PLLCFGR_PLLM_Pos             (4U)
4514 #define RCC_PLLCFGR_PLLM_Msk             (0x7UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000070 */
4515 #define RCC_PLLCFGR_PLLM                 RCC_PLLCFGR_PLLM_Msk
4516 #define RCC_PLLCFGR_PLLM_0               (0x1UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000010 */
4517 #define RCC_PLLCFGR_PLLM_1               (0x2UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000020 */
4518 #define RCC_PLLCFGR_PLLM_2               (0x4UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000040 */
4519 
4520 #define RCC_PLLCFGR_PLLN_Pos             (8U)
4521 #define RCC_PLLCFGR_PLLN_Msk             (0x7FUL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00007F00 */
4522 #define RCC_PLLCFGR_PLLN                 RCC_PLLCFGR_PLLN_Msk
4523 #define RCC_PLLCFGR_PLLN_0               (0x01UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000100 */
4524 #define RCC_PLLCFGR_PLLN_1               (0x02UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000200 */
4525 #define RCC_PLLCFGR_PLLN_2               (0x04UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000400 */
4526 #define RCC_PLLCFGR_PLLN_3               (0x08UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000800 */
4527 #define RCC_PLLCFGR_PLLN_4               (0x10UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00001000 */
4528 #define RCC_PLLCFGR_PLLN_5               (0x20UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00002000 */
4529 #define RCC_PLLCFGR_PLLN_6               (0x40UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00004000 */
4530 
4531 #define RCC_PLLCFGR_PLLPEN_Pos           (16U)
4532 #define RCC_PLLCFGR_PLLPEN_Msk           (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)     /*!< 0x00010000 */
4533 #define RCC_PLLCFGR_PLLPEN               RCC_PLLCFGR_PLLPEN_Msk
4534 
4535 #define RCC_PLLCFGR_PLLP_Pos              (17U)
4536 #define RCC_PLLCFGR_PLLP_Msk              (0x1FUL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x003E0000 */
4537 #define RCC_PLLCFGR_PLLP                  RCC_PLLCFGR_PLLP_Msk
4538 #define RCC_PLLCFGR_PLLP_0                (0x01UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00020000 */
4539 #define RCC_PLLCFGR_PLLP_1                (0x02UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00040000 */
4540 #define RCC_PLLCFGR_PLLP_2                (0x04UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00080000 */
4541 #define RCC_PLLCFGR_PLLP_3                (0x08UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00100000 */
4542 #define RCC_PLLCFGR_PLLP_4                (0x10UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00200000 */
4543 
4544 #define RCC_PLLCFGR_PLLQEN_Pos           (24U)
4545 #define RCC_PLLCFGR_PLLQEN_Msk           (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)     /*!< 0x01000000 */
4546 #define RCC_PLLCFGR_PLLQEN               RCC_PLLCFGR_PLLQEN_Msk
4547 
4548 #define RCC_PLLCFGR_PLLQ_Pos             (25U)
4549 #define RCC_PLLCFGR_PLLQ_Msk             (0x7UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x0E000000 */
4550 #define RCC_PLLCFGR_PLLQ                 RCC_PLLCFGR_PLLQ_Msk
4551 #define RCC_PLLCFGR_PLLQ_0               (0x1UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x02000000 */
4552 #define RCC_PLLCFGR_PLLQ_1               (0x2UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x04000000 */
4553 #define RCC_PLLCFGR_PLLQ_2               (0x4UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x08000000 */
4554 
4555 #define RCC_PLLCFGR_PLLREN_Pos           (28U)
4556 #define RCC_PLLCFGR_PLLREN_Msk           (0x1UL << RCC_PLLCFGR_PLLREN_Pos)     /*!< 0x10000000 */
4557 #define RCC_PLLCFGR_PLLREN               RCC_PLLCFGR_PLLREN_Msk
4558 
4559 #define RCC_PLLCFGR_PLLR_Pos             (29U)
4560 #define RCC_PLLCFGR_PLLR_Msk             (0x7UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0xE0000000 */
4561 #define RCC_PLLCFGR_PLLR                 RCC_PLLCFGR_PLLR_Msk
4562 #define RCC_PLLCFGR_PLLR_0               (0x1UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0x20000000 */
4563 #define RCC_PLLCFGR_PLLR_1               (0x2UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0x40000000 */
4564 #define RCC_PLLCFGR_PLLR_2               (0x4UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0x80000000 */
4565 
4566 /********************  Bit definition for RCC_CIER register  ******************/
4567 #define RCC_CIER_LSIRDYIE_Pos            (0U)
4568 #define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */
4569 #define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk
4570 #define RCC_CIER_LSERDYIE_Pos            (1U)
4571 #define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */
4572 #define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk
4573 #define RCC_CIER_HSIRDYIE_Pos            (3U)
4574 #define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */
4575 #define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk
4576 #define RCC_CIER_HSERDYIE_Pos            (4U)
4577 #define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */
4578 #define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk
4579 #define RCC_CIER_PLLRDYIE_Pos            (5U)
4580 #define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)      /*!< 0x00000020 */
4581 #define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk
4582 
4583 /********************  Bit definition for RCC_CIFR register  ******************/
4584 #define RCC_CIFR_LSIRDYF_Pos             (0U)
4585 #define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */
4586 #define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk
4587 #define RCC_CIFR_LSERDYF_Pos             (1U)
4588 #define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */
4589 #define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk
4590 #define RCC_CIFR_HSIRDYF_Pos             (3U)
4591 #define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */
4592 #define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk
4593 #define RCC_CIFR_HSERDYF_Pos             (4U)
4594 #define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */
4595 #define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk
4596 #define RCC_CIFR_PLLRDYF_Pos             (5U)
4597 #define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)       /*!< 0x00000020 */
4598 #define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk
4599 #define RCC_CIFR_CSSF_Pos                (8U)
4600 #define RCC_CIFR_CSSF_Msk                (0x1UL << RCC_CIFR_CSSF_Pos)          /*!< 0x00000100 */
4601 #define RCC_CIFR_CSSF                    RCC_CIFR_CSSF_Msk
4602 #define RCC_CIFR_LSECSSF_Pos             (9U)
4603 #define RCC_CIFR_LSECSSF_Msk             (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00000200 */
4604 #define RCC_CIFR_LSECSSF                 RCC_CIFR_LSECSSF_Msk
4605 
4606 /********************  Bit definition for RCC_CICR register  ******************/
4607 #define RCC_CICR_LSIRDYC_Pos             (0U)
4608 #define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */
4609 #define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk
4610 #define RCC_CICR_LSERDYC_Pos             (1U)
4611 #define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */
4612 #define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk
4613 #define RCC_CICR_HSIRDYC_Pos             (3U)
4614 #define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */
4615 #define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk
4616 #define RCC_CICR_HSERDYC_Pos             (4U)
4617 #define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */
4618 #define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk
4619 #define RCC_CICR_PLLRDYC_Pos             (5U)
4620 #define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)       /*!< 0x00000020 */
4621 #define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk
4622 #define RCC_CICR_CSSC_Pos                (8U)
4623 #define RCC_CICR_CSSC_Msk                (0x1UL << RCC_CICR_CSSC_Pos)          /*!< 0x00000100 */
4624 #define RCC_CICR_CSSC                    RCC_CICR_CSSC_Msk
4625 #define RCC_CICR_LSECSSC_Pos             (9U)
4626 #define RCC_CICR_LSECSSC_Msk             (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00000200 */
4627 #define RCC_CICR_LSECSSC                 RCC_CICR_LSECSSC_Msk
4628 
4629 /********************  Bit definition for RCC_IOPRSTR register  ****************/
4630 #define RCC_IOPRSTR_GPIOARST_Pos         (0U)
4631 #define RCC_IOPRSTR_GPIOARST_Msk         (0x1UL << RCC_IOPRSTR_GPIOARST_Pos)   /*!< 0x00000001 */
4632 #define RCC_IOPRSTR_GPIOARST             RCC_IOPRSTR_GPIOARST_Msk
4633 #define RCC_IOPRSTR_GPIOBRST_Pos         (1U)
4634 #define RCC_IOPRSTR_GPIOBRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos)   /*!< 0x00000002 */
4635 #define RCC_IOPRSTR_GPIOBRST             RCC_IOPRSTR_GPIOBRST_Msk
4636 #define RCC_IOPRSTR_GPIOCRST_Pos         (2U)
4637 #define RCC_IOPRSTR_GPIOCRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos)   /*!< 0x00000004 */
4638 #define RCC_IOPRSTR_GPIOCRST             RCC_IOPRSTR_GPIOCRST_Msk
4639 #define RCC_IOPRSTR_GPIODRST_Pos         (3U)
4640 #define RCC_IOPRSTR_GPIODRST_Msk         (0x1UL << RCC_IOPRSTR_GPIODRST_Pos)   /*!< 0x00000008 */
4641 #define RCC_IOPRSTR_GPIODRST             RCC_IOPRSTR_GPIODRST_Msk
4642 #define RCC_IOPRSTR_GPIOFRST_Pos         (5U)
4643 #define RCC_IOPRSTR_GPIOFRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos)   /*!< 0x00000020 */
4644 #define RCC_IOPRSTR_GPIOFRST             RCC_IOPRSTR_GPIOFRST_Msk
4645 
4646 /********************  Bit definition for RCC_AHBRSTR register  ***************/
4647 #define RCC_AHBRSTR_DMA1RST_Pos          (0U)
4648 #define RCC_AHBRSTR_DMA1RST_Msk          (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)    /*!< 0x00000001 */
4649 #define RCC_AHBRSTR_DMA1RST              RCC_AHBRSTR_DMA1RST_Msk
4650 #define RCC_AHBRSTR_FLASHRST_Pos         (8U)
4651 #define RCC_AHBRSTR_FLASHRST_Msk         (0x1UL << RCC_AHBRSTR_FLASHRST_Pos)   /*!< 0x00000100 */
4652 #define RCC_AHBRSTR_FLASHRST             RCC_AHBRSTR_FLASHRST_Msk
4653 #define RCC_AHBRSTR_CRCRST_Pos           (12U)
4654 #define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)     /*!< 0x00001000 */
4655 #define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk
4656 #define RCC_AHBRSTR_AESRST_Pos           (16U)
4657 #define RCC_AHBRSTR_AESRST_Msk           (0x1UL << RCC_AHBRSTR_AESRST_Pos)     /*!< 0x00010000 */
4658 #define RCC_AHBRSTR_AESRST               RCC_AHBRSTR_AESRST_Msk
4659 #define RCC_AHBRSTR_RNGRST_Pos           (18U)
4660 #define RCC_AHBRSTR_RNGRST_Msk           (0x1UL << RCC_AHBRSTR_RNGRST_Pos)     /*!< 0x00040000 */
4661 #define RCC_AHBRSTR_RNGRST               RCC_AHBRSTR_RNGRST_Msk
4662 
4663 /********************  Bit definition for RCC_APBRSTR1 register  **************/
4664 #define RCC_APBRSTR1_TIM2RST_Pos         (0U)
4665 #define RCC_APBRSTR1_TIM2RST_Msk         (0x1UL << RCC_APBRSTR1_TIM2RST_Pos)   /*!< 0x00000001 */
4666 #define RCC_APBRSTR1_TIM2RST             RCC_APBRSTR1_TIM2RST_Msk
4667 #define RCC_APBRSTR1_TIM3RST_Pos         (1U)
4668 #define RCC_APBRSTR1_TIM3RST_Msk         (0x1UL << RCC_APBRSTR1_TIM3RST_Pos)   /*!< 0x00000002 */
4669 #define RCC_APBRSTR1_TIM3RST             RCC_APBRSTR1_TIM3RST_Msk
4670 #define RCC_APBRSTR1_SPI2RST_Pos         (14U)
4671 #define RCC_APBRSTR1_SPI2RST_Msk         (0x1UL << RCC_APBRSTR1_SPI2RST_Pos)   /*!< 0x00004000 */
4672 #define RCC_APBRSTR1_SPI2RST             RCC_APBRSTR1_SPI2RST_Msk
4673 #define RCC_APBRSTR1_USART2RST_Pos       (17U)
4674 #define RCC_APBRSTR1_USART2RST_Msk       (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */
4675 #define RCC_APBRSTR1_USART2RST           RCC_APBRSTR1_USART2RST_Msk
4676 #define RCC_APBRSTR1_LPUART1RST_Pos      (20U)
4677 #define RCC_APBRSTR1_LPUART1RST_Msk      (0x1UL << RCC_APBRSTR1_LPUART1RST_Pos) /*!< 0x00100000 */
4678 #define RCC_APBRSTR1_LPUART1RST          RCC_APBRSTR1_LPUART1RST_Msk
4679 #define RCC_APBRSTR1_I2C1RST_Pos         (21U)
4680 #define RCC_APBRSTR1_I2C1RST_Msk         (0x1UL << RCC_APBRSTR1_I2C1RST_Pos)    /*!< 0x00200000 */
4681 #define RCC_APBRSTR1_I2C1RST             RCC_APBRSTR1_I2C1RST_Msk
4682 #define RCC_APBRSTR1_I2C2RST_Pos         (22U)
4683 #define RCC_APBRSTR1_I2C2RST_Msk         (0x1UL << RCC_APBRSTR1_I2C2RST_Pos)    /*!< 0x00400000 */
4684 #define RCC_APBRSTR1_I2C2RST             RCC_APBRSTR1_I2C2RST_Msk
4685 #define RCC_APBRSTR1_DBGRST_Pos          (27U)
4686 #define RCC_APBRSTR1_DBGRST_Msk          (0x1UL << RCC_APBRSTR1_DBGRST_Pos)     /*!< 0x08000000 */
4687 #define RCC_APBRSTR1_DBGRST              RCC_APBRSTR1_DBGRST_Msk
4688 #define RCC_APBRSTR1_PWRRST_Pos          (28U)
4689 #define RCC_APBRSTR1_PWRRST_Msk          (0x1UL << RCC_APBRSTR1_PWRRST_Pos)     /*!< 0x10000000 */
4690 #define RCC_APBRSTR1_PWRRST              RCC_APBRSTR1_PWRRST_Msk
4691 #define RCC_APBRSTR1_LPTIM2RST_Pos       (30U)
4692 #define RCC_APBRSTR1_LPTIM2RST_Msk       (0x1UL << RCC_APBRSTR1_LPTIM2RST_Pos)  /*!< 0x40000000 */
4693 #define RCC_APBRSTR1_LPTIM2RST           RCC_APBRSTR1_LPTIM2RST_Msk
4694 #define RCC_APBRSTR1_LPTIM1RST_Pos       (31U)
4695 #define RCC_APBRSTR1_LPTIM1RST_Msk       (0x1UL << RCC_APBRSTR1_LPTIM1RST_Pos)  /*!< 0x80000000 */
4696 #define RCC_APBRSTR1_LPTIM1RST           RCC_APBRSTR1_LPTIM1RST_Msk
4697 
4698 /********************  Bit definition for RCC_APBRSTR2 register  **************/
4699 #define RCC_APBRSTR2_SYSCFGRST_Pos       (0U)
4700 #define RCC_APBRSTR2_SYSCFGRST_Msk       (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos)  /*!< 0x00000001 */
4701 #define RCC_APBRSTR2_SYSCFGRST           RCC_APBRSTR2_SYSCFGRST_Msk
4702 #define RCC_APBRSTR2_TIM1RST_Pos         (11U)
4703 #define RCC_APBRSTR2_TIM1RST_Msk         (0x1UL << RCC_APBRSTR2_TIM1RST_Pos)    /*!< 0x00000800 */
4704 #define RCC_APBRSTR2_TIM1RST             RCC_APBRSTR2_TIM1RST_Msk
4705 #define RCC_APBRSTR2_SPI1RST_Pos         (12U)
4706 #define RCC_APBRSTR2_SPI1RST_Msk         (0x1UL << RCC_APBRSTR2_SPI1RST_Pos)    /*!< 0x00001000 */
4707 #define RCC_APBRSTR2_SPI1RST             RCC_APBRSTR2_SPI1RST_Msk
4708 #define RCC_APBRSTR2_USART1RST_Pos       (14U)
4709 #define RCC_APBRSTR2_USART1RST_Msk       (0x1UL << RCC_APBRSTR2_USART1RST_Pos)  /*!< 0x00004000 */
4710 #define RCC_APBRSTR2_USART1RST           RCC_APBRSTR2_USART1RST_Msk
4711 #define RCC_APBRSTR2_TIM14RST_Pos        (15U)
4712 #define RCC_APBRSTR2_TIM14RST_Msk        (0x1UL << RCC_APBRSTR2_TIM14RST_Pos)   /*!< 0x00008000 */
4713 #define RCC_APBRSTR2_TIM14RST            RCC_APBRSTR2_TIM14RST_Msk
4714 #define RCC_APBRSTR2_TIM16RST_Pos        (17U)
4715 #define RCC_APBRSTR2_TIM16RST_Msk        (0x1UL << RCC_APBRSTR2_TIM16RST_Pos)   /*!< 0x00020000 */
4716 #define RCC_APBRSTR2_TIM16RST            RCC_APBRSTR2_TIM16RST_Msk
4717 #define RCC_APBRSTR2_TIM17RST_Pos        (18U)
4718 #define RCC_APBRSTR2_TIM17RST_Msk        (0x1UL << RCC_APBRSTR2_TIM17RST_Pos)   /*!< 0x00040000 */
4719 #define RCC_APBRSTR2_TIM17RST            RCC_APBRSTR2_TIM17RST_Msk
4720 #define RCC_APBRSTR2_ADCRST_Pos          (20U)
4721 #define RCC_APBRSTR2_ADCRST_Msk          (0x1UL << RCC_APBRSTR2_ADCRST_Pos)     /*!< 0x00100000 */
4722 #define RCC_APBRSTR2_ADCRST              RCC_APBRSTR2_ADCRST_Msk
4723 
4724 /********************  Bit definition for RCC_IOPENR register  ****************/
4725 #define RCC_IOPENR_GPIOAEN_Pos           (0U)
4726 #define RCC_IOPENR_GPIOAEN_Msk           (0x1UL << RCC_IOPENR_GPIOAEN_Pos)      /*!< 0x00000001 */
4727 #define RCC_IOPENR_GPIOAEN               RCC_IOPENR_GPIOAEN_Msk
4728 #define RCC_IOPENR_GPIOBEN_Pos           (1U)
4729 #define RCC_IOPENR_GPIOBEN_Msk           (0x1UL << RCC_IOPENR_GPIOBEN_Pos)      /*!< 0x00000002 */
4730 #define RCC_IOPENR_GPIOBEN               RCC_IOPENR_GPIOBEN_Msk
4731 #define RCC_IOPENR_GPIOCEN_Pos           (2U)
4732 #define RCC_IOPENR_GPIOCEN_Msk           (0x1UL << RCC_IOPENR_GPIOCEN_Pos)      /*!< 0x00000004 */
4733 #define RCC_IOPENR_GPIOCEN               RCC_IOPENR_GPIOCEN_Msk
4734 #define RCC_IOPENR_GPIODEN_Pos           (3U)
4735 #define RCC_IOPENR_GPIODEN_Msk           (0x1UL << RCC_IOPENR_GPIODEN_Pos)      /*!< 0x00000008 */
4736 #define RCC_IOPENR_GPIODEN               RCC_IOPENR_GPIODEN_Msk
4737 #define RCC_IOPENR_GPIOFEN_Pos           (5U)
4738 #define RCC_IOPENR_GPIOFEN_Msk           (0x1UL << RCC_IOPENR_GPIOFEN_Pos)      /*!< 0x00000020 */
4739 #define RCC_IOPENR_GPIOFEN               RCC_IOPENR_GPIOFEN_Msk
4740 
4741 /********************  Bit definition for RCC_AHBENR register  ****************/
4742 #define RCC_AHBENR_DMA1EN_Pos            (0U)
4743 #define RCC_AHBENR_DMA1EN_Msk            (0x1UL << RCC_AHBENR_DMA1EN_Pos)       /*!< 0x00000001 */
4744 #define RCC_AHBENR_DMA1EN                RCC_AHBENR_DMA1EN_Msk
4745 #define RCC_AHBENR_FLASHEN_Pos           (8U)
4746 #define RCC_AHBENR_FLASHEN_Msk           (0x1UL << RCC_AHBENR_FLASHEN_Pos)      /*!< 0x00000100 */
4747 #define RCC_AHBENR_FLASHEN               RCC_AHBENR_FLASHEN_Msk
4748 #define RCC_AHBENR_CRCEN_Pos             (12U)
4749 #define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
4750 #define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk
4751 #define RCC_AHBENR_AESEN_Pos             (16U)
4752 #define RCC_AHBENR_AESEN_Msk             (0x1UL << RCC_AHBENR_AESEN_Pos)        /*!< 0x00010000 */
4753 #define RCC_AHBENR_AESEN                 RCC_AHBENR_AESEN_Msk
4754 #define RCC_AHBENR_RNGEN_Pos             (18U)
4755 #define RCC_AHBENR_RNGEN_Msk             (0x1UL << RCC_AHBENR_RNGEN_Pos)        /*!< 0x00040000 */
4756 #define RCC_AHBENR_RNGEN                 RCC_AHBENR_RNGEN_Msk
4757 
4758 /********************  Bit definition for RCC_APBENR1 register  ***************/
4759 #define RCC_APBENR1_TIM2EN_Pos           (0U)
4760 #define RCC_APBENR1_TIM2EN_Msk           (0x1UL << RCC_APBENR1_TIM2EN_Pos)      /*!< 0x00000001 */
4761 #define RCC_APBENR1_TIM2EN               RCC_APBENR1_TIM2EN_Msk
4762 #define RCC_APBENR1_TIM3EN_Pos           (1U)
4763 #define RCC_APBENR1_TIM3EN_Msk           (0x1UL << RCC_APBENR1_TIM3EN_Pos)      /*!< 0x00000002 */
4764 #define RCC_APBENR1_TIM3EN               RCC_APBENR1_TIM3EN_Msk
4765 #define RCC_APBENR1_RTCAPBEN_Pos         (10U)
4766 #define RCC_APBENR1_RTCAPBEN_Msk         (0x1UL << RCC_APBENR1_RTCAPBEN_Pos)    /*!< 0x00000400 */
4767 #define RCC_APBENR1_RTCAPBEN             RCC_APBENR1_RTCAPBEN_Msk
4768 #define RCC_APBENR1_WWDGEN_Pos           (11U)
4769 #define RCC_APBENR1_WWDGEN_Msk           (0x1UL << RCC_APBENR1_WWDGEN_Pos)      /*!< 0x00000800 */
4770 #define RCC_APBENR1_WWDGEN               RCC_APBENR1_WWDGEN_Msk
4771 #define RCC_APBENR1_SPI2EN_Pos           (14U)
4772 #define RCC_APBENR1_SPI2EN_Msk           (0x1UL << RCC_APBENR1_SPI2EN_Pos)      /*!< 0x00004000 */
4773 #define RCC_APBENR1_SPI2EN               RCC_APBENR1_SPI2EN_Msk
4774 #define RCC_APBENR1_USART2EN_Pos         (17U)
4775 #define RCC_APBENR1_USART2EN_Msk         (0x1UL << RCC_APBENR1_USART2EN_Pos)    /*!< 0x00020000 */
4776 #define RCC_APBENR1_USART2EN             RCC_APBENR1_USART2EN_Msk
4777 #define RCC_APBENR1_LPUART1EN_Pos        (20U)
4778 #define RCC_APBENR1_LPUART1EN_Msk        (0x1UL << RCC_APBENR1_LPUART1EN_Pos)   /*!< 0x00100000 */
4779 #define RCC_APBENR1_LPUART1EN            RCC_APBENR1_LPUART1EN_Msk
4780 #define RCC_APBENR1_I2C1EN_Pos           (21U)
4781 #define RCC_APBENR1_I2C1EN_Msk           (0x1UL << RCC_APBENR1_I2C1EN_Pos)      /*!< 0x00200000 */
4782 #define RCC_APBENR1_I2C1EN               RCC_APBENR1_I2C1EN_Msk
4783 #define RCC_APBENR1_I2C2EN_Pos           (22U)
4784 #define RCC_APBENR1_I2C2EN_Msk           (0x1UL << RCC_APBENR1_I2C2EN_Pos)      /*!< 0x00400000 */
4785 #define RCC_APBENR1_I2C2EN               RCC_APBENR1_I2C2EN_Msk
4786 #define RCC_APBENR1_DBGEN_Pos            (27U)
4787 #define RCC_APBENR1_DBGEN_Msk            (0x1UL << RCC_APBENR1_DBGEN_Pos)       /*!< 0x08000000 */
4788 #define RCC_APBENR1_DBGEN                RCC_APBENR1_DBGEN_Msk
4789 #define RCC_APBENR1_PWREN_Pos            (28U)
4790 #define RCC_APBENR1_PWREN_Msk            (0x1UL << RCC_APBENR1_PWREN_Pos)       /*!< 0x10000000 */
4791 #define RCC_APBENR1_PWREN                RCC_APBENR1_PWREN_Msk
4792 #define RCC_APBENR1_LPTIM2EN_Pos         (30U)
4793 #define RCC_APBENR1_LPTIM2EN_Msk         (0x1UL << RCC_APBENR1_LPTIM2EN_Pos)    /*!< 0x40000000 */
4794 #define RCC_APBENR1_LPTIM2EN             RCC_APBENR1_LPTIM2EN_Msk
4795 #define RCC_APBENR1_LPTIM1EN_Pos         (31U)
4796 #define RCC_APBENR1_LPTIM1EN_Msk         (0x1UL << RCC_APBENR1_LPTIM1EN_Pos)    /*!< 0x80000000 */
4797 #define RCC_APBENR1_LPTIM1EN             RCC_APBENR1_LPTIM1EN_Msk
4798 
4799 /********************  Bit definition for RCC_APBENR2 register  **************/
4800 #define RCC_APBENR2_SYSCFGEN_Pos         (0U)
4801 #define RCC_APBENR2_SYSCFGEN_Msk         (0x1UL << RCC_APBENR2_SYSCFGEN_Pos)    /*!< 0x00000001 */
4802 #define RCC_APBENR2_SYSCFGEN             RCC_APBENR2_SYSCFGEN_Msk
4803 #define RCC_APBENR2_TIM1EN_Pos           (11U)
4804 #define RCC_APBENR2_TIM1EN_Msk           (0x1UL << RCC_APBENR2_TIM1EN_Pos)      /*!< 0x00000800 */
4805 #define RCC_APBENR2_TIM1EN               RCC_APBENR2_TIM1EN_Msk
4806 #define RCC_APBENR2_SPI1EN_Pos           (12U)
4807 #define RCC_APBENR2_SPI1EN_Msk           (0x1UL << RCC_APBENR2_SPI1EN_Pos)      /*!< 0x00001000 */
4808 #define RCC_APBENR2_SPI1EN               RCC_APBENR2_SPI1EN_Msk
4809 #define RCC_APBENR2_USART1EN_Pos         (14U)
4810 #define RCC_APBENR2_USART1EN_Msk         (0x1UL << RCC_APBENR2_USART1EN_Pos)    /*!< 0x00004000 */
4811 #define RCC_APBENR2_USART1EN             RCC_APBENR2_USART1EN_Msk
4812 #define RCC_APBENR2_TIM14EN_Pos          (15U)
4813 #define RCC_APBENR2_TIM14EN_Msk          (0x1UL << RCC_APBENR2_TIM14EN_Pos)     /*!< 0x00008000 */
4814 #define RCC_APBENR2_TIM14EN              RCC_APBENR2_TIM14EN_Msk
4815 #define RCC_APBENR2_TIM16EN_Pos          (17U)
4816 #define RCC_APBENR2_TIM16EN_Msk          (0x1UL << RCC_APBENR2_TIM16EN_Pos)     /*!< 0x00020000 */
4817 #define RCC_APBENR2_TIM16EN              RCC_APBENR2_TIM16EN_Msk
4818 #define RCC_APBENR2_TIM17EN_Pos          (18U)
4819 #define RCC_APBENR2_TIM17EN_Msk          (0x1UL << RCC_APBENR2_TIM17EN_Pos)     /*!< 0x00040000 */
4820 #define RCC_APBENR2_TIM17EN              RCC_APBENR2_TIM17EN_Msk
4821 #define RCC_APBENR2_ADCEN_Pos            (20U)
4822 #define RCC_APBENR2_ADCEN_Msk            (0x1UL << RCC_APBENR2_ADCEN_Pos)       /*!< 0x00100000 */
4823 #define RCC_APBENR2_ADCEN                RCC_APBENR2_ADCEN_Msk
4824 
4825 /********************  Bit definition for RCC_IOPSMENR register  *************/
4826 #define RCC_IOPSMENR_GPIOASMEN_Pos       (0U)
4827 #define RCC_IOPSMENR_GPIOASMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos)  /*!< 0x00000001 */
4828 #define RCC_IOPSMENR_GPIOASMEN           RCC_IOPSMENR_GPIOASMEN_Msk
4829 #define RCC_IOPSMENR_GPIOBSMEN_Pos       (1U)
4830 #define RCC_IOPSMENR_GPIOBSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos)  /*!< 0x00000002 */
4831 #define RCC_IOPSMENR_GPIOBSMEN           RCC_IOPSMENR_GPIOBSMEN_Msk
4832 #define RCC_IOPSMENR_GPIOCSMEN_Pos       (2U)
4833 #define RCC_IOPSMENR_GPIOCSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos)  /*!< 0x00000004 */
4834 #define RCC_IOPSMENR_GPIOCSMEN           RCC_IOPSMENR_GPIOCSMEN_Msk
4835 #define RCC_IOPSMENR_GPIODSMEN_Pos       (3U)
4836 #define RCC_IOPSMENR_GPIODSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos)  /*!< 0x00000008 */
4837 #define RCC_IOPSMENR_GPIODSMEN           RCC_IOPSMENR_GPIODSMEN_Msk
4838 #define RCC_IOPSMENR_GPIOFSMEN_Pos       (5U)
4839 #define RCC_IOPSMENR_GPIOFSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos)  /*!< 0x00000020 */
4840 #define RCC_IOPSMENR_GPIOFSMEN           RCC_IOPSMENR_GPIOFSMEN_Msk
4841 
4842 /********************  Bit definition for RCC_AHBSMENR register  *************/
4843 #define RCC_AHBSMENR_DMA1SMEN_Pos        (0U)
4844 #define RCC_AHBSMENR_DMA1SMEN_Msk        (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos)   /*!< 0x00000001 */
4845 #define RCC_AHBSMENR_DMA1SMEN            RCC_AHBSMENR_DMA1SMEN_Msk
4846 #define RCC_AHBSMENR_FLASHSMEN_Pos       (8U)
4847 #define RCC_AHBSMENR_FLASHSMEN_Msk       (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos)  /*!< 0x00000100 */
4848 #define RCC_AHBSMENR_FLASHSMEN           RCC_AHBSMENR_FLASHSMEN_Msk
4849 #define RCC_AHBSMENR_SRAMSMEN_Pos        (9U)
4850 #define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
4851 #define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk
4852 #define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
4853 #define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
4854 #define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk
4855 #define RCC_AHBSMENR_AESSMEN_Pos         (16U)
4856 #define RCC_AHBSMENR_AESSMEN_Msk         (0x1UL << RCC_AHBSMENR_AESSMEN_Pos)    /*!< 0x00010000 */
4857 #define RCC_AHBSMENR_AESSMEN             RCC_AHBSMENR_AESSMEN_Msk
4858 #define RCC_AHBSMENR_RNGSMEN_Pos         (18U)
4859 #define RCC_AHBSMENR_RNGSMEN_Msk         (0x1UL << RCC_AHBSMENR_RNGSMEN_Pos)    /*!< 0x00040000 */
4860 #define RCC_AHBSMENR_RNGSMEN             RCC_AHBSMENR_RNGSMEN_Msk
4861 
4862 /********************  Bit definition for RCC_APBSMENR1 register  *************/
4863 #define RCC_APBSMENR1_TIM2SMEN_Pos       (0U)
4864 #define RCC_APBSMENR1_TIM2SMEN_Msk       (0x1UL << RCC_APBSMENR1_TIM2SMEN_Pos)  /*!< 0x00000001 */
4865 #define RCC_APBSMENR1_TIM2SMEN           RCC_APBSMENR1_TIM2SMEN_Msk
4866 #define RCC_APBSMENR1_TIM3SMEN_Pos       (1U)
4867 #define RCC_APBSMENR1_TIM3SMEN_Msk       (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos)  /*!< 0x00000002 */
4868 #define RCC_APBSMENR1_TIM3SMEN           RCC_APBSMENR1_TIM3SMEN_Msk
4869 #define RCC_APBSMENR1_RTCAPBSMEN_Pos     (10U)
4870 #define RCC_APBSMENR1_RTCAPBSMEN_Msk     (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
4871 #define RCC_APBSMENR1_RTCAPBSMEN         RCC_APBSMENR1_RTCAPBSMEN_Msk
4872 #define RCC_APBSMENR1_WWDGSMEN_Pos       (11U)
4873 #define RCC_APBSMENR1_WWDGSMEN_Msk       (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos)   /*!< 0x00000800 */
4874 #define RCC_APBSMENR1_WWDGSMEN           RCC_APBSMENR1_WWDGSMEN_Msk
4875 #define RCC_APBSMENR1_SPI2SMEN_Pos       (14U)
4876 #define RCC_APBSMENR1_SPI2SMEN_Msk       (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos)   /*!< 0x00004000 */
4877 #define RCC_APBSMENR1_SPI2SMEN           RCC_APBSMENR1_SPI2SMEN_Msk
4878 #define RCC_APBSMENR1_USART2SMEN_Pos     (17U)
4879 #define RCC_APBSMENR1_USART2SMEN_Msk     (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
4880 #define RCC_APBSMENR1_USART2SMEN         RCC_APBSMENR1_USART2SMEN_Msk
4881 #define RCC_APBSMENR1_LPUART1SMEN_Pos    (20U)
4882 #define RCC_APBSMENR1_LPUART1SMEN_Msk    (0x1UL << RCC_APBSMENR1_LPUART1SMEN_Pos) /*!< 0x00100000 */
4883 #define RCC_APBSMENR1_LPUART1SMEN        RCC_APBSMENR1_LPUART1SMEN_Msk
4884 #define RCC_APBSMENR1_I2C1SMEN_Pos       (21U)
4885 #define RCC_APBSMENR1_I2C1SMEN_Msk       (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos)   /*!< 0x00200000 */
4886 #define RCC_APBSMENR1_I2C1SMEN           RCC_APBSMENR1_I2C1SMEN_Msk
4887 #define RCC_APBSMENR1_I2C2SMEN_Pos       (22U)
4888 #define RCC_APBSMENR1_I2C2SMEN_Msk       (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos)   /*!< 0x00400000 */
4889 #define RCC_APBSMENR1_I2C2SMEN           RCC_APBSMENR1_I2C2SMEN_Msk
4890 #define RCC_APBSMENR1_DBGSMEN_Pos        (27U)
4891 #define RCC_APBSMENR1_DBGSMEN_Msk        (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos)    /*!< 0x08000000 */
4892 #define RCC_APBSMENR1_DBGSMEN            RCC_APBSMENR1_DBGSMEN_Msk
4893 #define RCC_APBSMENR1_PWRSMEN_Pos        (28U)
4894 #define RCC_APBSMENR1_PWRSMEN_Msk        (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos)    /*!< 0x10000000 */
4895 #define RCC_APBSMENR1_PWRSMEN            RCC_APBSMENR1_PWRSMEN_Msk
4896 #define RCC_APBSMENR1_LPTIM2SMEN_Pos     (30U)
4897 #define RCC_APBSMENR1_LPTIM2SMEN_Msk     (0x1UL << RCC_APBSMENR1_LPTIM2SMEN_Pos) /*!< 0x40000000 */
4898 #define RCC_APBSMENR1_LPTIM2SMEN         RCC_APBSMENR1_LPTIM2SMEN_Msk
4899 #define RCC_APBSMENR1_LPTIM1SMEN_Pos     (31U)
4900 #define RCC_APBSMENR1_LPTIM1SMEN_Msk     (0x1UL << RCC_APBSMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
4901 #define RCC_APBSMENR1_LPTIM1SMEN         RCC_APBSMENR1_LPTIM1SMEN_Msk
4902 
4903 /********************  Bit definition for RCC_APBSMENR2 register  *************/
4904 #define RCC_APBSMENR2_SYSCFGSMEN_Pos     (0U)
4905 #define RCC_APBSMENR2_SYSCFGSMEN_Msk     (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
4906 #define RCC_APBSMENR2_SYSCFGSMEN         RCC_APBSMENR2_SYSCFGSMEN_Msk
4907 #define RCC_APBSMENR2_TIM1SMEN_Pos       (11U)
4908 #define RCC_APBSMENR2_TIM1SMEN_Msk       (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos)  /*!< 0x00000800 */
4909 #define RCC_APBSMENR2_TIM1SMEN           RCC_APBSMENR2_TIM1SMEN_Msk
4910 #define RCC_APBSMENR2_SPI1SMEN_Pos       (12U)
4911 #define RCC_APBSMENR2_SPI1SMEN_Msk       (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos)  /*!< 0x00001000 */
4912 #define RCC_APBSMENR2_SPI1SMEN           RCC_APBSMENR2_SPI1SMEN_Msk
4913 #define RCC_APBSMENR2_USART1SMEN_Pos     (14U)
4914 #define RCC_APBSMENR2_USART1SMEN_Msk     (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
4915 #define RCC_APBSMENR2_USART1SMEN         RCC_APBSMENR2_USART1SMEN_Msk
4916 #define RCC_APBSMENR2_TIM14SMEN_Pos      (15U)
4917 #define RCC_APBSMENR2_TIM14SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */
4918 #define RCC_APBSMENR2_TIM14SMEN          RCC_APBSMENR2_TIM14SMEN_Msk
4919 #define RCC_APBSMENR2_TIM16SMEN_Pos      (17U)
4920 #define RCC_APBSMENR2_TIM16SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */
4921 #define RCC_APBSMENR2_TIM16SMEN          RCC_APBSMENR2_TIM16SMEN_Msk
4922 #define RCC_APBSMENR2_TIM17SMEN_Pos      (18U)
4923 #define RCC_APBSMENR2_TIM17SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */
4924 #define RCC_APBSMENR2_TIM17SMEN          RCC_APBSMENR2_TIM17SMEN_Msk
4925 #define RCC_APBSMENR2_ADCSMEN_Pos        (20U)
4926 #define RCC_APBSMENR2_ADCSMEN_Msk        (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos)   /*!< 0x00100000 */
4927 #define RCC_APBSMENR2_ADCSMEN            RCC_APBSMENR2_ADCSMEN_Msk
4928 
4929 /********************  Bit definition for RCC_CCIPR register  ******************/
4930 #define RCC_CCIPR_USART1SEL_Pos          (0U)
4931 #define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
4932 #define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk
4933 #define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
4934 #define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
4935 
4936 
4937 
4938 #define RCC_CCIPR_LPUART1SEL_Pos         (10U)
4939 #define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
4940 #define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk
4941 #define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000400 */
4942 #define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000800 */
4943 
4944 #define RCC_CCIPR_I2C1SEL_Pos            (12U)
4945 #define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
4946 #define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk
4947 #define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
4948 #define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
4949 
4950 #define RCC_CCIPR_I2S1SEL_Pos            (14U)
4951 #define RCC_CCIPR_I2S1SEL_Msk            (0x3UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x0000C000 */
4952 #define RCC_CCIPR_I2S1SEL                RCC_CCIPR_I2S1SEL_Msk
4953 #define RCC_CCIPR_I2S1SEL_0              (0x1UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x00004000 */
4954 #define RCC_CCIPR_I2S1SEL_1              (0x2UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x00008000 */
4955 
4956 #define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
4957 #define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
4958 #define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk
4959 #define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
4960 #define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
4961 
4962 #define RCC_CCIPR_LPTIM2SEL_Pos          (20U)
4963 #define RCC_CCIPR_LPTIM2SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)     /*!< 0x00300000 */
4964 #define RCC_CCIPR_LPTIM2SEL              RCC_CCIPR_LPTIM2SEL_Msk
4965 #define RCC_CCIPR_LPTIM2SEL_0            (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)     /*!< 0x00100000 */
4966 #define RCC_CCIPR_LPTIM2SEL_1            (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)     /*!< 0x00200000 */
4967 
4968 #define RCC_CCIPR_TIM1SEL_Pos            (22U)
4969 #define RCC_CCIPR_TIM1SEL_Msk            (0x1UL << RCC_CCIPR_TIM1SEL_Pos)       /*!< 0x00400000 */
4970 #define RCC_CCIPR_TIM1SEL                RCC_CCIPR_TIM1SEL_Msk
4971 
4972 
4973 #define RCC_CCIPR_RNGSEL_Pos             (26U)
4974 #define RCC_CCIPR_RNGSEL_Msk             (0x3UL << RCC_CCIPR_RNGSEL_Pos)        /*!< 0x0C000000 */
4975 #define RCC_CCIPR_RNGSEL                 RCC_CCIPR_RNGSEL_Msk
4976 #define RCC_CCIPR_RNGSEL_0               (0x1UL << RCC_CCIPR_RNGSEL_Pos)        /*!< 0x04000000 */
4977 #define RCC_CCIPR_RNGSEL_1               (0x2UL << RCC_CCIPR_RNGSEL_Pos)        /*!< 0x08000000 */
4978 
4979 #define RCC_CCIPR_RNGDIV_Pos             (28U)
4980 #define RCC_CCIPR_RNGDIV_Msk             (0x3UL << RCC_CCIPR_RNGDIV_Pos)        /*!< 0x30000000 */
4981 #define RCC_CCIPR_RNGDIV                 RCC_CCIPR_RNGDIV_Msk
4982 #define RCC_CCIPR_RNGDIV_0               (0x1UL << RCC_CCIPR_RNGDIV_Pos)        /*!< 0x10000000 */
4983 #define RCC_CCIPR_RNGDIV_1               (0x2UL << RCC_CCIPR_RNGDIV_Pos)        /*!< 0x20000000 */
4984 
4985 #define RCC_CCIPR_ADCSEL_Pos             (30U)
4986 #define RCC_CCIPR_ADCSEL_Msk             (0x3UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0xC0000000 */
4987 #define RCC_CCIPR_ADCSEL                 RCC_CCIPR_ADCSEL_Msk
4988 #define RCC_CCIPR_ADCSEL_0               (0x1UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0x40000000 */
4989 #define RCC_CCIPR_ADCSEL_1               (0x2UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0x80000000 */
4990 
4991 /********************  Bit definition for RCC_BDCR register  ******************/
4992 #define RCC_BDCR_LSEON_Pos               (0U)
4993 #define RCC_BDCR_LSEON_Msk               (0x1UL << RCC_BDCR_LSEON_Pos)          /*!< 0x00000001 */
4994 #define RCC_BDCR_LSEON                   RCC_BDCR_LSEON_Msk
4995 #define RCC_BDCR_LSERDY_Pos              (1U)
4996 #define RCC_BDCR_LSERDY_Msk              (0x1UL << RCC_BDCR_LSERDY_Pos)         /*!< 0x00000002 */
4997 #define RCC_BDCR_LSERDY                  RCC_BDCR_LSERDY_Msk
4998 #define RCC_BDCR_LSEBYP_Pos              (2U)
4999 #define RCC_BDCR_LSEBYP_Msk              (0x1UL << RCC_BDCR_LSEBYP_Pos)         /*!< 0x00000004 */
5000 #define RCC_BDCR_LSEBYP                  RCC_BDCR_LSEBYP_Msk
5001 
5002 #define RCC_BDCR_LSEDRV_Pos              (3U)
5003 #define RCC_BDCR_LSEDRV_Msk              (0x3UL << RCC_BDCR_LSEDRV_Pos)         /*!< 0x00000018 */
5004 #define RCC_BDCR_LSEDRV                  RCC_BDCR_LSEDRV_Msk
5005 #define RCC_BDCR_LSEDRV_0                (0x1UL << RCC_BDCR_LSEDRV_Pos)         /*!< 0x00000008 */
5006 #define RCC_BDCR_LSEDRV_1                (0x2UL << RCC_BDCR_LSEDRV_Pos)         /*!< 0x00000010 */
5007 
5008 #define RCC_BDCR_LSECSSON_Pos            (5U)
5009 #define RCC_BDCR_LSECSSON_Msk            (0x1UL << RCC_BDCR_LSECSSON_Pos)       /*!< 0x00000020 */
5010 #define RCC_BDCR_LSECSSON                RCC_BDCR_LSECSSON_Msk
5011 #define RCC_BDCR_LSECSSD_Pos             (6U)
5012 #define RCC_BDCR_LSECSSD_Msk             (0x1UL << RCC_BDCR_LSECSSD_Pos)        /*!< 0x00000040 */
5013 #define RCC_BDCR_LSECSSD                 RCC_BDCR_LSECSSD_Msk
5014 
5015 #define RCC_BDCR_RTCSEL_Pos              (8U)
5016 #define RCC_BDCR_RTCSEL_Msk              (0x3UL << RCC_BDCR_RTCSEL_Pos)         /*!< 0x00000300 */
5017 #define RCC_BDCR_RTCSEL                  RCC_BDCR_RTCSEL_Msk
5018 #define RCC_BDCR_RTCSEL_0                (0x1UL << RCC_BDCR_RTCSEL_Pos)         /*!< 0x00000100 */
5019 #define RCC_BDCR_RTCSEL_1                (0x2UL << RCC_BDCR_RTCSEL_Pos)         /*!< 0x00000200 */
5020 
5021 #define RCC_BDCR_RTCEN_Pos               (15U)
5022 #define RCC_BDCR_RTCEN_Msk               (0x1UL << RCC_BDCR_RTCEN_Pos)          /*!< 0x00008000 */
5023 #define RCC_BDCR_RTCEN                   RCC_BDCR_RTCEN_Msk
5024 #define RCC_BDCR_BDRST_Pos               (16U)
5025 #define RCC_BDCR_BDRST_Msk               (0x1UL << RCC_BDCR_BDRST_Pos)          /*!< 0x00010000 */
5026 #define RCC_BDCR_BDRST                   RCC_BDCR_BDRST_Msk
5027 
5028 #define RCC_BDCR_LSCOEN_Pos              (24U)
5029 #define RCC_BDCR_LSCOEN_Msk              (0x1UL << RCC_BDCR_LSCOEN_Pos)         /*!< 0x01000000 */
5030 #define RCC_BDCR_LSCOEN                  RCC_BDCR_LSCOEN_Msk
5031 #define RCC_BDCR_LSCOSEL_Pos             (25U)
5032 #define RCC_BDCR_LSCOSEL_Msk             (0x1UL << RCC_BDCR_LSCOSEL_Pos)        /*!< 0x02000000 */
5033 #define RCC_BDCR_LSCOSEL                 RCC_BDCR_LSCOSEL_Msk
5034 
5035 /********************  Bit definition for RCC_CSR register  *******************/
5036 #define RCC_CSR_LSION_Pos                (0U)
5037 #define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
5038 #define RCC_CSR_LSION                    RCC_CSR_LSION_Msk
5039 #define RCC_CSR_LSIRDY_Pos               (1U)
5040 #define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
5041 #define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk
5042 
5043 #define RCC_CSR_RMVF_Pos                 (23U)
5044 #define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
5045 #define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk
5046 #define RCC_CSR_OBLRSTF_Pos              (25U)
5047 #define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
5048 #define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk
5049 #define RCC_CSR_PINRSTF_Pos              (26U)
5050 #define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
5051 #define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk
5052 #define RCC_CSR_PWRRSTF_Pos              (27U)
5053 #define RCC_CSR_PWRRSTF_Msk              (0x1UL << RCC_CSR_PWRRSTF_Pos)         /*!< 0x08000000 */
5054 #define RCC_CSR_PWRRSTF                  RCC_CSR_PWRRSTF_Msk
5055 #define RCC_CSR_SFTRSTF_Pos              (28U)
5056 #define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
5057 #define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk
5058 #define RCC_CSR_IWDGRSTF_Pos             (29U)
5059 #define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
5060 #define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk
5061 #define RCC_CSR_WWDGRSTF_Pos             (30U)
5062 #define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
5063 #define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk
5064 #define RCC_CSR_LPWRRSTF_Pos             (31U)
5065 #define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
5066 #define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk
5067 
5068 /******************************************************************************/
5069 /*                                                                            */
5070 /*                                    RNG                                     */
5071 /*                                                                            */
5072 /******************************************************************************/
5073 /********************  Bits definition for RNG_CR register  *******************/
5074 #define RNG_CR_RNGEN_Pos    (2U)
5075 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
5076 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
5077 #define RNG_CR_IE_Pos       (3U)
5078 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
5079 #define RNG_CR_IE           RNG_CR_IE_Msk
5080 #define RNG_CR_CED_Pos      (5U)
5081 #define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                           /*!< 0x00000020 */
5082 #define RNG_CR_CED          RNG_CR_CED_Msk
5083 
5084 /********************  Bits definition for RNG_SR register  *******************/
5085 #define RNG_SR_DRDY_Pos     (0U)
5086 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
5087 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
5088 #define RNG_SR_CECS_Pos     (1U)
5089 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
5090 #define RNG_SR_CECS         RNG_SR_CECS_Msk
5091 #define RNG_SR_SECS_Pos     (2U)
5092 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
5093 #define RNG_SR_SECS         RNG_SR_SECS_Msk
5094 #define RNG_SR_CEIS_Pos     (5U)
5095 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
5096 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
5097 #define RNG_SR_SEIS_Pos     (6U)
5098 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
5099 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
5100 
5101 /******************************************************************************/
5102 /*                                                                            */
5103 /*                           Real-Time Clock (RTC)                            */
5104 /*                                                                            */
5105 /******************************************************************************/
5106 /*
5107 * @brief Specific device feature definitions
5108 */
5109 #define RTC_WAKEUP_SUPPORT
5110 #define RTC_BACKUP_SUPPORT
5111 
5112 /********************  Bits definition for RTC_TR register  *******************/
5113 #define RTC_TR_PM_Pos                (22U)
5114 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
5115 #define RTC_TR_PM                    RTC_TR_PM_Msk
5116 #define RTC_TR_HT_Pos                (20U)
5117 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
5118 #define RTC_TR_HT                    RTC_TR_HT_Msk
5119 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
5120 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
5121 #define RTC_TR_HU_Pos                (16U)
5122 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
5123 #define RTC_TR_HU                    RTC_TR_HU_Msk
5124 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
5125 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
5126 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
5127 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
5128 #define RTC_TR_MNT_Pos               (12U)
5129 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
5130 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
5131 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
5132 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
5133 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
5134 #define RTC_TR_MNU_Pos               (8U)
5135 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
5136 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
5137 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
5138 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
5139 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
5140 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
5141 #define RTC_TR_ST_Pos                (4U)
5142 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
5143 #define RTC_TR_ST                    RTC_TR_ST_Msk
5144 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
5145 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
5146 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
5147 #define RTC_TR_SU_Pos                (0U)
5148 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
5149 #define RTC_TR_SU                    RTC_TR_SU_Msk
5150 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
5151 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
5152 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
5153 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
5154 
5155 /********************  Bits definition for RTC_DR register  *******************/
5156 #define RTC_DR_YT_Pos                (20U)
5157 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
5158 #define RTC_DR_YT                    RTC_DR_YT_Msk
5159 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
5160 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
5161 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
5162 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
5163 #define RTC_DR_YU_Pos                (16U)
5164 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
5165 #define RTC_DR_YU                    RTC_DR_YU_Msk
5166 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
5167 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
5168 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
5169 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
5170 #define RTC_DR_WDU_Pos               (13U)
5171 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
5172 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
5173 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
5174 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
5175 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
5176 #define RTC_DR_MT_Pos                (12U)
5177 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
5178 #define RTC_DR_MT                    RTC_DR_MT_Msk
5179 #define RTC_DR_MU_Pos                (8U)
5180 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
5181 #define RTC_DR_MU                    RTC_DR_MU_Msk
5182 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
5183 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
5184 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
5185 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
5186 #define RTC_DR_DT_Pos                (4U)
5187 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
5188 #define RTC_DR_DT                    RTC_DR_DT_Msk
5189 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
5190 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
5191 #define RTC_DR_DU_Pos                (0U)
5192 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
5193 #define RTC_DR_DU                    RTC_DR_DU_Msk
5194 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
5195 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
5196 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
5197 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
5198 
5199 /********************  Bits definition for RTC_SSR register  ******************/
5200 #define RTC_SSR_SS_Pos               (0U)
5201 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
5202 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
5203 
5204 /********************  Bits definition for RTC_ICSR register  ******************/
5205 #define RTC_ICSR_RECALPF_Pos         (16U)
5206 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)            /*!< 0x00010000 */
5207 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
5208 #define RTC_ICSR_INIT_Pos            (7U)
5209 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)               /*!< 0x00000080 */
5210 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
5211 #define RTC_ICSR_INITF_Pos           (6U)
5212 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)              /*!< 0x00000040 */
5213 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
5214 #define RTC_ICSR_RSF_Pos             (5U)
5215 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)                /*!< 0x00000020 */
5216 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
5217 #define RTC_ICSR_INITS_Pos           (4U)
5218 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)              /*!< 0x00000010 */
5219 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
5220 #define RTC_ICSR_SHPF_Pos            (3U)
5221 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)               /*!< 0x00000008 */
5222 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
5223 #define RTC_ICSR_WUTWF_Pos           (2U)
5224 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)              /*!< 0x00000004 */
5225 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk                         /*!< Wakeup timer write flag > */
5226 #define RTC_ICSR_ALRBWF_Pos          (1U)
5227 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)             /*!< 0x00000002 */
5228 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
5229 #define RTC_ICSR_ALRAWF_Pos          (0U)
5230 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)             /*!< 0x00000001 */
5231 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
5232 
5233 /********************  Bits definition for RTC_PRER register  *****************/
5234 #define RTC_PRER_PREDIV_A_Pos        (16U)
5235 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
5236 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
5237 #define RTC_PRER_PREDIV_S_Pos        (0U)
5238 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
5239 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
5240 
5241 /********************  Bits definition for RTC_WUTR register  *****************/
5242 #define RTC_WUTR_WUT_Pos             (0U)
5243 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
5244 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk                          /*!< Wakeup auto-reload value bits > */
5245 
5246 /********************  Bits definition for RTC_CR register  *******************/
5247 #define RTC_CR_OUT2EN_Pos            (31U)
5248 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
5249 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!< RTC_OUT2 output enable */
5250 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
5251 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
5252 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!< TAMPALARM output type  */
5253 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
5254 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
5255 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!< TAMPALARM output pull-up config */
5256 #define RTC_CR_TAMPOE_Pos            (26U)
5257 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
5258 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!< Tamper detection output enable on TAMPALARM  */
5259 #define RTC_CR_TAMPTS_Pos            (25U)
5260 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
5261 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!< Activate timestamp on tamper detection event  */
5262 #define RTC_CR_ITSE_Pos              (24U)
5263 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
5264 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!< Timestamp on internal event enable  */
5265 #define RTC_CR_COE_Pos               (23U)
5266 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
5267 #define RTC_CR_COE                   RTC_CR_COE_Msk
5268 #define RTC_CR_OSEL_Pos              (21U)
5269 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
5270 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
5271 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
5272 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
5273 #define RTC_CR_POL_Pos               (20U)
5274 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
5275 #define RTC_CR_POL                   RTC_CR_POL_Msk
5276 #define RTC_CR_COSEL_Pos             (19U)
5277 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
5278 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
5279 #define RTC_CR_BKP_Pos               (18U)
5280 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
5281 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
5282 #define RTC_CR_SUB1H_Pos             (17U)
5283 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
5284 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
5285 #define RTC_CR_ADD1H_Pos             (16U)
5286 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
5287 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
5288 #define RTC_CR_TSIE_Pos              (15U)
5289 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
5290 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk                           /*!< Timestamp interrupt enable > */
5291 #define RTC_CR_WUTIE_Pos             (14U)
5292 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
5293 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk                          /*!< Wakeup timer interrupt enable > */
5294 #define RTC_CR_ALRBIE_Pos            (13U)
5295 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
5296 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
5297 #define RTC_CR_ALRAIE_Pos            (12U)
5298 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
5299 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
5300 #define RTC_CR_TSE_Pos               (11U)
5301 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
5302 #define RTC_CR_TSE                   RTC_CR_TSE_Msk                            /*!< timestamp enable > */
5303 #define RTC_CR_WUTE_Pos              (10U)
5304 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
5305 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk                           /*!< Wakeup timer enable > */
5306 #define RTC_CR_ALRBE_Pos             (9U)
5307 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
5308 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
5309 #define RTC_CR_ALRAE_Pos             (8U)
5310 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
5311 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
5312 #define RTC_CR_FMT_Pos               (6U)
5313 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
5314 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
5315 #define RTC_CR_BYPSHAD_Pos           (5U)
5316 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
5317 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
5318 #define RTC_CR_REFCKON_Pos           (4U)
5319 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
5320 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
5321 #define RTC_CR_TSEDGE_Pos            (3U)
5322 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
5323 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         /*!< Timestamp event active edge > */
5324 #define RTC_CR_WUCKSEL_Pos           (0U)
5325 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
5326 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk                        /*!< Wakeup clock selection > */
5327 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
5328 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
5329 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
5330 
5331 /********************  Bits definition for RTC_WPR register  ******************/
5332 #define RTC_WPR_KEY_Pos              (0U)
5333 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
5334 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
5335 
5336 /********************  Bits definition for RTC_CALR register  *****************/
5337 #define RTC_CALR_CALP_Pos            (15U)
5338 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
5339 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
5340 #define RTC_CALR_CALW8_Pos           (14U)
5341 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
5342 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
5343 #define RTC_CALR_CALW16_Pos          (13U)
5344 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
5345 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
5346 #define RTC_CALR_CALM_Pos            (0U)
5347 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
5348 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
5349 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
5350 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
5351 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
5352 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
5353 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
5354 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
5355 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
5356 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
5357 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
5358 
5359 /********************  Bits definition for RTC_SHIFTR register  ***************/
5360 #define RTC_SHIFTR_SUBFS_Pos         (0U)
5361 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
5362 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
5363 #define RTC_SHIFTR_ADD1S_Pos         (31U)
5364 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
5365 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
5366 
5367 /********************  Bits definition for RTC_TSTR register  *****************/
5368 #define RTC_TSTR_PM_Pos              (22U)
5369 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
5370 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           /*!< AM-PM notation > */
5371 #define RTC_TSTR_HT_Pos              (20U)
5372 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
5373 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
5374 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
5375 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
5376 #define RTC_TSTR_HU_Pos              (16U)
5377 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
5378 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
5379 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
5380 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
5381 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
5382 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
5383 #define RTC_TSTR_MNT_Pos             (12U)
5384 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
5385 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
5386 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
5387 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
5388 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
5389 #define RTC_TSTR_MNU_Pos             (8U)
5390 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
5391 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
5392 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
5393 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
5394 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
5395 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
5396 #define RTC_TSTR_ST_Pos              (4U)
5397 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
5398 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
5399 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
5400 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
5401 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
5402 #define RTC_TSTR_SU_Pos              (0U)
5403 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
5404 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
5405 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
5406 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
5407 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
5408 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
5409 
5410 /********************  Bits definition for RTC_TSDR register  *****************/
5411 #define RTC_TSDR_WDU_Pos             (13U)
5412 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
5413 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          /*!< Week day units > */
5414 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
5415 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
5416 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
5417 #define RTC_TSDR_MT_Pos              (12U)
5418 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
5419 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
5420 #define RTC_TSDR_MU_Pos              (8U)
5421 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
5422 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
5423 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
5424 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
5425 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
5426 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
5427 #define RTC_TSDR_DT_Pos              (4U)
5428 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
5429 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
5430 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
5431 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
5432 #define RTC_TSDR_DU_Pos              (0U)
5433 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
5434 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
5435 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
5436 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
5437 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
5438 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
5439 
5440 /********************  Bits definition for RTC_TSSSR register  ****************/
5441 #define RTC_TSSSR_SS_Pos             (0U)
5442 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
5443 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          /*!< Sub second value > */
5444 
5445 /********************  Bits definition for RTC_ALRMAR register  ***************/
5446 #define RTC_ALRMAR_MSK4_Pos          (31U)
5447 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
5448 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
5449 #define RTC_ALRMAR_WDSEL_Pos         (30U)
5450 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
5451 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
5452 #define RTC_ALRMAR_DT_Pos            (28U)
5453 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
5454 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
5455 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
5456 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
5457 #define RTC_ALRMAR_DU_Pos            (24U)
5458 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
5459 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
5460 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
5461 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
5462 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
5463 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
5464 #define RTC_ALRMAR_MSK3_Pos          (23U)
5465 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
5466 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
5467 #define RTC_ALRMAR_PM_Pos            (22U)
5468 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
5469 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
5470 #define RTC_ALRMAR_HT_Pos            (20U)
5471 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
5472 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
5473 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
5474 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
5475 #define RTC_ALRMAR_HU_Pos            (16U)
5476 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
5477 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
5478 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
5479 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
5480 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
5481 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
5482 #define RTC_ALRMAR_MSK2_Pos          (15U)
5483 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
5484 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
5485 #define RTC_ALRMAR_MNT_Pos           (12U)
5486 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
5487 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
5488 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
5489 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
5490 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
5491 #define RTC_ALRMAR_MNU_Pos           (8U)
5492 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
5493 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
5494 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
5495 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
5496 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
5497 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
5498 #define RTC_ALRMAR_MSK1_Pos          (7U)
5499 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
5500 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
5501 #define RTC_ALRMAR_ST_Pos            (4U)
5502 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
5503 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
5504 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
5505 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
5506 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
5507 #define RTC_ALRMAR_SU_Pos            (0U)
5508 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
5509 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
5510 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
5511 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
5512 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
5513 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
5514 
5515 /********************  Bits definition for RTC_ALRMASSR register  *************/
5516 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
5517 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
5518 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
5519 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
5520 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
5521 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
5522 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
5523 #define RTC_ALRMASSR_SS_Pos          (0U)
5524 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
5525 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
5526 
5527 /********************  Bits definition for RTC_ALRMBR register  ***************/
5528 #define RTC_ALRMBR_MSK4_Pos          (31U)
5529 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
5530 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
5531 #define RTC_ALRMBR_WDSEL_Pos         (30U)
5532 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
5533 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
5534 #define RTC_ALRMBR_DT_Pos            (28U)
5535 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
5536 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
5537 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
5538 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
5539 #define RTC_ALRMBR_DU_Pos            (24U)
5540 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
5541 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
5542 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
5543 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
5544 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
5545 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
5546 #define RTC_ALRMBR_MSK3_Pos          (23U)
5547 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
5548 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
5549 #define RTC_ALRMBR_PM_Pos            (22U)
5550 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
5551 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
5552 #define RTC_ALRMBR_HT_Pos            (20U)
5553 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
5554 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
5555 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
5556 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
5557 #define RTC_ALRMBR_HU_Pos            (16U)
5558 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
5559 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
5560 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
5561 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
5562 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
5563 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
5564 #define RTC_ALRMBR_MSK2_Pos          (15U)
5565 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
5566 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
5567 #define RTC_ALRMBR_MNT_Pos           (12U)
5568 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
5569 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
5570 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
5571 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
5572 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
5573 #define RTC_ALRMBR_MNU_Pos           (8U)
5574 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
5575 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
5576 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
5577 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
5578 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
5579 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
5580 #define RTC_ALRMBR_MSK1_Pos          (7U)
5581 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
5582 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
5583 #define RTC_ALRMBR_ST_Pos            (4U)
5584 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
5585 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
5586 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
5587 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
5588 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
5589 #define RTC_ALRMBR_SU_Pos            (0U)
5590 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
5591 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
5592 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
5593 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
5594 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
5595 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
5596 
5597 /********************  Bits definition for RTC_ALRMASSR register  *************/
5598 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
5599 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
5600 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
5601 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
5602 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
5603 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
5604 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
5605 #define RTC_ALRMBSSR_SS_Pos          (0U)
5606 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
5607 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
5608 
5609 /********************  Bits definition for RTC_SR register  *******************/
5610 #define RTC_SR_ITSF_Pos              (5U)
5611 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
5612 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
5613 #define RTC_SR_TSOVF_Pos             (4U)
5614 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
5615 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk                          /*!< Timestamp overflow flag > */
5616 #define RTC_SR_TSF_Pos               (3U)
5617 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
5618 #define RTC_SR_TSF                   RTC_SR_TSF_Msk                            /*!< Timestamp flag > */
5619 #define RTC_SR_WUTF_Pos              (2U)
5620 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
5621 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk                           /*!< Wakeup timer flag > */
5622 #define RTC_SR_ALRBF_Pos             (1U)
5623 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
5624 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
5625 #define RTC_SR_ALRAF_Pos             (0U)
5626 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
5627 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
5628 
5629 /********************  Bits definition for RTC_MISR register  *****************/
5630 #define RTC_MISR_ITSMF_Pos           (5U)
5631 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
5632 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
5633 #define RTC_MISR_TSOVMF_Pos          (4U)
5634 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
5635 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk                       /*!< Timestamp overflow masked flag > */
5636 #define RTC_MISR_TSMF_Pos            (3U)
5637 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
5638 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk                         /*!< Timestamp masked flag > */
5639 #define RTC_MISR_WUTMF_Pos           (2U)
5640 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
5641 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk                        /*!< Wakeup timer masked flag > */
5642 #define RTC_MISR_ALRBMF_Pos          (1U)
5643 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
5644 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
5645 #define RTC_MISR_ALRAMF_Pos          (0U)
5646 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
5647 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
5648 
5649 /********************  Bits definition for RTC_SCR register  ******************/
5650 #define RTC_SCR_CITSF_Pos            (5U)
5651 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
5652 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
5653 #define RTC_SCR_CTSOVF_Pos           (4U)
5654 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
5655 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk                        /*!< Clear timestamp overflow flag > */
5656 #define RTC_SCR_CTSF_Pos             (3U)
5657 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
5658 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk                          /*!< Clear timestamp flag > */
5659 #define RTC_SCR_CWUTF_Pos            (2U)
5660 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
5661 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk                         /*!< Clear wakeup timer flag > */
5662 #define RTC_SCR_CALRBF_Pos           (1U)
5663 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
5664 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
5665 #define RTC_SCR_CALRAF_Pos           (0U)
5666 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
5667 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
5668 
5669 /******************************************************************************/
5670 /*                                                                            */
5671 /*                     Tamper and backup register (TAMP)                      */
5672 /*                                                                            */
5673 /******************************************************************************/
5674 /********************  Bits definition for TAMP_CR1 register  *****************/
5675 #define TAMP_CR1_TAMP1E_Pos          (0U)
5676 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)             /*!< 0x00000001 */
5677 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
5678 #define TAMP_CR1_TAMP2E_Pos          (1U)
5679 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)             /*!< 0x00000002 */
5680 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
5681 #define TAMP_CR1_ITAMP3E_Pos         (18U)
5682 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)            /*!< 0x00040000 */
5683 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
5684 #define TAMP_CR1_ITAMP4E_Pos         (19U)
5685 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)            /*!< 0x00080000 */
5686 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
5687 #define TAMP_CR1_ITAMP5E_Pos         (20U)
5688 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)            /*!< 0x00100000 */
5689 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
5690 #define TAMP_CR1_ITAMP6E_Pos         (21U)
5691 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)            /*!< 0x00200000 */
5692 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
5693 
5694 /********************  Bits definition for TAMP_CR2 register  *****************/
5695 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
5696 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)       /*!< 0x00000001 */
5697 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
5698 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
5699 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)       /*!< 0x00000002 */
5700 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
5701 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
5702 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
5703 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
5704 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
5705 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
5706 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
5707 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
5708 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)           /*!< 0x01000000 */
5709 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
5710 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
5711 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)           /*!< 0x02000000 */
5712 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
5713 
5714 /********************  Bits definition for TAMP_FLTCR register  ***************/
5715 #define TAMP_FLTCR_TAMPFREQ_0        0x00000001U
5716 #define TAMP_FLTCR_TAMPFREQ_1        0x00000002U
5717 #define TAMP_FLTCR_TAMPFREQ_2        0x00000004U
5718 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
5719 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */
5720 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
5721 #define TAMP_FLTCR_TAMPFLT_0         0x00000008U
5722 #define TAMP_FLTCR_TAMPFLT_1         0x00000010U
5723 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
5724 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */
5725 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
5726 #define TAMP_FLTCR_TAMPPRCH_0        0x00000020U
5727 #define TAMP_FLTCR_TAMPPRCH_1        0x00000040U
5728 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
5729 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */
5730 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
5731 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
5732 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */
5733 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
5734 
5735 /********************  Bits definition for TAMP_IER register  *****************/
5736 #define TAMP_IER_TAMP1IE_Pos         (0U)
5737 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)            /*!< 0x00000001 */
5738 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
5739 #define TAMP_IER_TAMP2IE_Pos         (1U)
5740 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)            /*!< 0x00000002 */
5741 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
5742 #define TAMP_IER_ITAMP3IE_Pos        (18U)
5743 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)           /*!< 0x00040000 */
5744 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
5745 #define TAMP_IER_ITAMP4IE_Pos        (19U)
5746 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)           /*!< 0x00080000 */
5747 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
5748 #define TAMP_IER_ITAMP5IE_Pos        (20U)
5749 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)           /*!< 0x00100000 */
5750 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
5751 #define TAMP_IER_ITAMP6IE_Pos        (21U)
5752 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)           /*!< 0x00200000 */
5753 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
5754 
5755 /********************  Bits definition for TAMP_SR register  ******************/
5756 #define TAMP_SR_TAMP1F_Pos           (0U)
5757 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)              /*!< 0x00000001 */
5758 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
5759 #define TAMP_SR_TAMP2F_Pos           (1U)
5760 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)              /*!< 0x00000002 */
5761 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
5762 #define TAMP_SR_ITAMP3F_Pos          (18U)
5763 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)             /*!< 0x00040000 */
5764 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
5765 #define TAMP_SR_ITAMP4F_Pos          (19U)
5766 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)             /*!< 0x00080000 */
5767 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
5768 #define TAMP_SR_ITAMP5F_Pos          (20U)
5769 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)             /*!< 0x00100000 */
5770 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
5771 #define TAMP_SR_ITAMP6F_Pos          (21U)
5772 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)             /*!< 0x00200000 */
5773 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
5774 
5775 /********************  Bits definition for TAMP_MISR register  ****************/
5776 #define TAMP_MISR_TAMP1MF_Pos        (0U)
5777 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */
5778 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
5779 #define TAMP_MISR_TAMP2MF_Pos        (1U)
5780 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */
5781 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
5782 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
5783 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)          /*!< 0x00040000 */
5784 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
5785 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
5786 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)          /*!< 0x00080000 */
5787 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
5788 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
5789 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)          /*!< 0x00100000 */
5790 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
5791 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
5792 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)          /*!< 0x00200000 */
5793 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
5794 
5795 /********************  Bits definition for TAMP_SCR register  *****************/
5796 #define TAMP_SCR_CTAMP1F_Pos         (0U)
5797 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */
5798 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
5799 #define TAMP_SCR_CTAMP2F_Pos         (1U)
5800 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */
5801 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
5802 #define TAMP_SCR_CITAMP3F_Pos        (18U)
5803 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)           /*!< 0x00040000 */
5804 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
5805 #define TAMP_SCR_CITAMP4F_Pos        (19U)
5806 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)           /*!< 0x00080000 */
5807 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
5808 #define TAMP_SCR_CITAMP5F_Pos        (20U)
5809 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)           /*!< 0x00100000 */
5810 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
5811 #define TAMP_SCR_CITAMP6F_Pos        (21U)
5812 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)           /*!< 0x00200000 */
5813 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
5814 
5815 /********************  Bits definition for TAMP_BKP0R register  ***************/
5816 #define TAMP_BKP0R_Pos               (0U)
5817 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */
5818 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
5819 
5820 /********************  Bits definition for TAMP_BKP1R register  ***************/
5821 #define TAMP_BKP1R_Pos               (0U)
5822 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */
5823 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
5824 
5825 /********************  Bits definition for TAMP_BKP2R register  ***************/
5826 #define TAMP_BKP2R_Pos               (0U)
5827 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */
5828 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
5829 
5830 /********************  Bits definition for TAMP_BKP3R register  ***************/
5831 #define TAMP_BKP3R_Pos               (0U)
5832 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */
5833 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
5834 
5835 /********************  Bits definition for TAMP_BKP4R register  ***************/
5836 #define TAMP_BKP4R_Pos               (0U)
5837 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */
5838 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
5839 
5840 /******************************************************************************/
5841 /*                                                                            */
5842 /*                        Serial Peripheral Interface (SPI)                   */
5843 /*                                                                            */
5844 /******************************************************************************/
5845 /*
5846  * @brief Specific device feature definitions (not present on all devices in the STM32G0 series)
5847  */
5848 #define SPI_I2S_SUPPORT                       /*!< I2S support */
5849 
5850 /*******************  Bit definition for SPI_CR1 register  ********************/
5851 #define SPI_CR1_CPHA_Pos            (0U)
5852 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
5853 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
5854 #define SPI_CR1_CPOL_Pos            (1U)
5855 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
5856 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
5857 #define SPI_CR1_MSTR_Pos            (2U)
5858 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
5859 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
5860 
5861 #define SPI_CR1_BR_Pos              (3U)
5862 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
5863 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
5864 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
5865 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
5866 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
5867 
5868 #define SPI_CR1_SPE_Pos             (6U)
5869 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
5870 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
5871 #define SPI_CR1_LSBFIRST_Pos        (7U)
5872 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
5873 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
5874 #define SPI_CR1_SSI_Pos             (8U)
5875 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
5876 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
5877 #define SPI_CR1_SSM_Pos             (9U)
5878 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
5879 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
5880 #define SPI_CR1_RXONLY_Pos          (10U)
5881 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
5882 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
5883 #define SPI_CR1_CRCL_Pos            (11U)
5884 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
5885 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
5886 #define SPI_CR1_CRCNEXT_Pos         (12U)
5887 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
5888 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
5889 #define SPI_CR1_CRCEN_Pos           (13U)
5890 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
5891 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
5892 #define SPI_CR1_BIDIOE_Pos          (14U)
5893 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
5894 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
5895 #define SPI_CR1_BIDIMODE_Pos        (15U)
5896 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
5897 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
5898 
5899 /*******************  Bit definition for SPI_CR2 register  ********************/
5900 #define SPI_CR2_RXDMAEN_Pos         (0U)
5901 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
5902 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
5903 #define SPI_CR2_TXDMAEN_Pos         (1U)
5904 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
5905 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
5906 #define SPI_CR2_SSOE_Pos            (2U)
5907 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
5908 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
5909 #define SPI_CR2_NSSP_Pos            (3U)
5910 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
5911 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
5912 #define SPI_CR2_FRF_Pos             (4U)
5913 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
5914 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
5915 #define SPI_CR2_ERRIE_Pos           (5U)
5916 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
5917 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
5918 #define SPI_CR2_RXNEIE_Pos          (6U)
5919 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
5920 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
5921 #define SPI_CR2_TXEIE_Pos           (7U)
5922 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
5923 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
5924 #define SPI_CR2_DS_Pos              (8U)
5925 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
5926 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
5927 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
5928 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
5929 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
5930 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
5931 #define SPI_CR2_FRXTH_Pos           (12U)
5932 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
5933 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
5934 #define SPI_CR2_LDMARX_Pos          (13U)
5935 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
5936 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
5937 #define SPI_CR2_LDMATX_Pos          (14U)
5938 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
5939 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
5940 
5941 /********************  Bit definition for SPI_SR register  ********************/
5942 #define SPI_SR_RXNE_Pos             (0U)
5943 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
5944 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
5945 #define SPI_SR_TXE_Pos              (1U)
5946 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
5947 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
5948 #define SPI_SR_CHSIDE_Pos           (2U)
5949 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
5950 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
5951 #define SPI_SR_UDR_Pos              (3U)
5952 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
5953 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
5954 #define SPI_SR_CRCERR_Pos           (4U)
5955 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
5956 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
5957 #define SPI_SR_MODF_Pos             (5U)
5958 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
5959 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
5960 #define SPI_SR_OVR_Pos              (6U)
5961 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
5962 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
5963 #define SPI_SR_BSY_Pos              (7U)
5964 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
5965 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
5966 #define SPI_SR_FRE_Pos              (8U)
5967 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
5968 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
5969 #define SPI_SR_FRLVL_Pos            (9U)
5970 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
5971 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
5972 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
5973 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
5974 #define SPI_SR_FTLVL_Pos            (11U)
5975 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
5976 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
5977 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
5978 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
5979 
5980 /********************  Bit definition for SPI_DR register  ********************/
5981 #define SPI_DR_DR_Pos               (0U)
5982 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
5983 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
5984 
5985 /*******************  Bit definition for SPI_CRCPR register  ******************/
5986 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
5987 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
5988 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
5989 
5990 /******************  Bit definition for SPI_RXCRCR register  ******************/
5991 #define SPI_RXCRCR_RXCRC_Pos        (0U)
5992 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
5993 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
5994 
5995 /******************  Bit definition for SPI_TXCRCR register  ******************/
5996 #define SPI_TXCRCR_TXCRC_Pos        (0U)
5997 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
5998 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
5999 
6000 /******************  Bit definition for SPI_I2SCFGR register  *****************/
6001 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
6002 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
6003 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
6004 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
6005 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
6006 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
6007 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
6008 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
6009 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
6010 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
6011 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
6012 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
6013 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
6014 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
6015 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
6016 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
6017 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
6018 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
6019 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
6020 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
6021 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
6022 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6023 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
6024 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
6025 #define SPI_I2SCFGR_I2SE_Pos        (10U)
6026 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
6027 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
6028 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
6029 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
6030 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
6031 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
6032 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
6033 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
6034 
6035 /******************  Bit definition for SPI_I2SPR register  *******************/
6036 #define SPI_I2SPR_I2SDIV_Pos        (0U)
6037 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
6038 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
6039 #define SPI_I2SPR_ODD_Pos           (8U)
6040 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
6041 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
6042 #define SPI_I2SPR_MCKOE_Pos         (9U)
6043 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
6044 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
6045 
6046 /******************************************************************************/
6047 /*                                                                            */
6048 /*                                 SYSCFG                                     */
6049 /*                                                                            */
6050 /******************************************************************************/
6051 #define SYSCFG_CDEN_SUPPORT
6052 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
6053 #define SYSCFG_CFGR1_MEM_MODE_Pos             (0U)
6054 #define SYSCFG_CFGR1_MEM_MODE_Msk             (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
6055 #define SYSCFG_CFGR1_MEM_MODE                 SYSCFG_CFGR1_MEM_MODE_Msk            /*!< SYSCFG_Memory Remap Config */
6056 #define SYSCFG_CFGR1_MEM_MODE_0               (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
6057 #define SYSCFG_CFGR1_MEM_MODE_1               (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
6058 #define SYSCFG_CFGR1_PA11_RMP_Pos             (3U)
6059 #define SYSCFG_CFGR1_PA11_RMP_Msk             (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */
6060 #define SYSCFG_CFGR1_PA11_RMP                 SYSCFG_CFGR1_PA11_RMP_Msk            /*!< PA11 Remap */
6061 #define SYSCFG_CFGR1_PA12_RMP_Pos             (4U)
6062 #define SYSCFG_CFGR1_PA12_RMP_Msk             (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */
6063 #define SYSCFG_CFGR1_PA12_RMP                 SYSCFG_CFGR1_PA12_RMP_Msk            /*!< PA12 Remap */
6064 #define SYSCFG_CFGR1_IR_POL_Pos               (5U)
6065 #define SYSCFG_CFGR1_IR_POL_Msk               (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */
6066 #define SYSCFG_CFGR1_IR_POL                   SYSCFG_CFGR1_IR_POL_Msk            /*!< IROut Polarity Selection */
6067 #define SYSCFG_CFGR1_IR_MOD_Pos               (6U)
6068 #define SYSCFG_CFGR1_IR_MOD_Msk               (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
6069 #define SYSCFG_CFGR1_IR_MOD                   SYSCFG_CFGR1_IR_MOD_Msk            /*!< IRDA Modulation Envelope signal source selection */
6070 #define SYSCFG_CFGR1_IR_MOD_0                 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
6071 #define SYSCFG_CFGR1_IR_MOD_1                 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
6072 #define SYSCFG_CFGR1_BOOSTEN_Pos              (8U)
6073 #define SYSCFG_CFGR1_BOOSTEN_Msk              (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
6074 #define SYSCFG_CFGR1_BOOSTEN                  SYSCFG_CFGR1_BOOSTEN_Msk            /*!< I/O analog switch voltage booster enable */
6075 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos          (16U)
6076 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)  /*!< 0x00010000 */
6077 #define SYSCFG_CFGR1_I2C_PB6_FMP              SYSCFG_CFGR1_I2C_PB6_FMP_Msk             /*!< I2C PB6 Fast mode plus */
6078 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos          (17U)
6079 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)  /*!< 0x00020000 */
6080 #define SYSCFG_CFGR1_I2C_PB7_FMP              SYSCFG_CFGR1_I2C_PB7_FMP_Msk             /*!< I2C PB7 Fast mode plus */
6081 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos          (18U)
6082 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)  /*!< 0x00040000 */
6083 #define SYSCFG_CFGR1_I2C_PB8_FMP              SYSCFG_CFGR1_I2C_PB8_FMP_Msk             /*!< I2C PB8 Fast mode plus */
6084 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos          (19U)
6085 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)  /*!< 0x00080000 */
6086 #define SYSCFG_CFGR1_I2C_PB9_FMP              SYSCFG_CFGR1_I2C_PB9_FMP_Msk             /*!< I2C PB9 Fast mode plus */
6087 #define SYSCFG_CFGR1_I2C1_FMP_Pos             (20U)
6088 #define SYSCFG_CFGR1_I2C1_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)     /*!< 0x00100000 */
6089 #define SYSCFG_CFGR1_I2C1_FMP                 SYSCFG_CFGR1_I2C1_FMP_Msk                /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7  */
6090 #define SYSCFG_CFGR1_I2C2_FMP_Pos             (21U)
6091 #define SYSCFG_CFGR1_I2C2_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)     /*!< 0x00200000 */
6092 #define SYSCFG_CFGR1_I2C2_FMP                 SYSCFG_CFGR1_I2C2_FMP_Msk                /*!< Enable I2C2 Fast mode plus  */
6093 #define SYSCFG_CFGR1_I2C_PA9_FMP_Pos          (22U)
6094 #define SYSCFG_CFGR1_I2C_PA9_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos)  /*!< 0x00400000 */
6095 #define SYSCFG_CFGR1_I2C_PA9_FMP              SYSCFG_CFGR1_I2C_PA9_FMP_Msk             /*!< Enable Fast Mode Plus on PA9  */
6096 #define SYSCFG_CFGR1_I2C_PA10_FMP_Pos         (23U)
6097 #define SYSCFG_CFGR1_I2C_PA10_FMP_Msk         (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
6098 #define SYSCFG_CFGR1_I2C_PA10_FMP             SYSCFG_CFGR1_I2C_PA10_FMP_Msk            /*!< Enable Fast Mode Plus on PA10 */
6099 
6100 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
6101 #define SYSCFG_CFGR2_CLL_Pos                  (0U)
6102 #define SYSCFG_CFGR2_CLL_Msk                  (0x1UL << SYSCFG_CFGR2_CLL_Pos)   /*!< 0x00000001 */
6103 #define SYSCFG_CFGR2_CLL                      SYSCFG_CFGR2_CLL_Msk              /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
6104 #define SYSCFG_CFGR2_SPL_Pos                  (1U)
6105 #define SYSCFG_CFGR2_SPL_Msk                  (0x1UL << SYSCFG_CFGR2_SPL_Pos)   /*!< 0x00000002 */
6106 #define SYSCFG_CFGR2_SPL                      SYSCFG_CFGR2_SPL_Msk              /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
6107 #define SYSCFG_CFGR2_PVDL_Pos                 (2U)
6108 #define SYSCFG_CFGR2_PVDL_Msk                 (0x1UL << SYSCFG_CFGR2_PVDL_Pos)  /*!< 0x00000004 */
6109 #define SYSCFG_CFGR2_PVDL                     SYSCFG_CFGR2_PVDL_Msk             /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
6110 #define SYSCFG_CFGR2_ECCL_Pos                 (3U)
6111 #define SYSCFG_CFGR2_ECCL_Msk                 (0x1UL << SYSCFG_CFGR2_ECCL_Pos)  /*!< 0x00000008 */
6112 #define SYSCFG_CFGR2_ECCL                     SYSCFG_CFGR2_ECCL_Msk             /*!< ECCL */
6113 #define SYSCFG_CFGR2_SPF_Pos                  (8U)
6114 #define SYSCFG_CFGR2_SPF_Msk                  (0x1UL << SYSCFG_CFGR2_SPF_Pos)   /*!< 0x00000100 */
6115 #define SYSCFG_CFGR2_SPF                      SYSCFG_CFGR2_SPF_Msk              /*!< SRAM Parity error flag */
6116 #define SYSCFG_CFGR2_SRAM_PE                  SYSCFG_CFGR2_SPF                  /*!< SRAM Parity error flag (define maintained for legacy purpose) */
6117 
6118 #define SYSCFG_CFGR2_PA1_CDEN_Pos             (16U)
6119 #define SYSCFG_CFGR2_PA1_CDEN_Msk             (0x1UL << SYSCFG_CFGR2_PA1_CDEN_Pos)   /* 0x00010000 */
6120 #define SYSCFG_CFGR2_PA1_CDEN                 SYSCFG_CFGR2_PA1_CDEN_Msk              /*!< PA[1] Clamping Diode Enable */
6121 #define SYSCFG_CFGR2_PA3_CDEN_Pos             (17U)
6122 #define SYSCFG_CFGR2_PA3_CDEN_Msk             (0x1UL << SYSCFG_CFGR2_PA3_CDEN_Pos)   /* 0x00020000 */
6123 #define SYSCFG_CFGR2_PA3_CDEN                 SYSCFG_CFGR2_PA3_CDEN_Msk              /*!< PA[3] Clamping Diode Enable */
6124 #define SYSCFG_CFGR2_PA5_CDEN_Pos             (18U)
6125 #define SYSCFG_CFGR2_PA5_CDEN_Msk             (0x1UL << SYSCFG_CFGR2_PA5_CDEN_Pos)   /* 0x00040000 */
6126 #define SYSCFG_CFGR2_PA5_CDEN                 SYSCFG_CFGR2_PA5_CDEN_Msk              /*!< PA[5] Clamping Diode Enable */
6127 #define SYSCFG_CFGR2_PA6_CDEN_Pos             (19U)
6128 #define SYSCFG_CFGR2_PA6_CDEN_Msk             (0x1UL << SYSCFG_CFGR2_PA6_CDEN_Pos)   /* 0x00080000 */
6129 #define SYSCFG_CFGR2_PA6_CDEN                 SYSCFG_CFGR2_PA6_CDEN_Msk              /*!< PA[6] Clamping Diode Enable */
6130 #define SYSCFG_CFGR2_PA13_CDEN_Pos            (20U)
6131 #define SYSCFG_CFGR2_PA13_CDEN_Msk            (0x1UL << SYSCFG_CFGR2_PA13_CDEN_Pos)  /* 0x00100000 */
6132 #define SYSCFG_CFGR2_PA13_CDEN                 SYSCFG_CFGR2_PA13_CDEN_Msk            /*!< PA[13] Clamping Diode Enable */
6133 #define SYSCFG_CFGR2_PB0_CDEN_Pos             (21U)
6134 #define SYSCFG_CFGR2_PB0_CDEN_Msk             (0x1UL << SYSCFG_CFGR2_PB0_CDEN_Pos)   /* 0x00200000 */
6135 #define SYSCFG_CFGR2_PB0_CDEN                 SYSCFG_CFGR2_PB0_CDEN_Msk              /*!< PB[0] Clamping Diode Enable */
6136 #define SYSCFG_CFGR2_PB1_CDEN_Pos             (22U)
6137 #define SYSCFG_CFGR2_PB1_CDEN_Msk             (0x1UL << SYSCFG_CFGR2_PB1_CDEN_Pos)   /* 0x00400000 */
6138 #define SYSCFG_CFGR2_PB1_CDEN                 SYSCFG_CFGR2_PB1_CDEN_Msk              /*!< PB[1] Clamping Diode Enable */
6139 #define SYSCFG_CFGR2_PB2_CDEN_Pos             (23U)
6140 #define SYSCFG_CFGR2_PB2_CDEN_Msk             (0x1UL << SYSCFG_CFGR2_PB2_CDEN_Pos)   /* 0x00800000 */
6141 #define SYSCFG_CFGR2_PB2_CDEN                 SYSCFG_CFGR2_PB2_CDEN_Msk              /*!< PB[2] Clamping Diode Enable */
6142 /*****************  Bit definition for SYSCFG_ITLINEx ISR Wrapper register  ****************/
6143 #define SYSCFG_ITLINE0_SR_EWDG_Pos            (0U)
6144 #define SYSCFG_ITLINE0_SR_EWDG_Msk            (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
6145 #define SYSCFG_ITLINE0_SR_EWDG                SYSCFG_ITLINE0_SR_EWDG_Msk       /*!< EWDG interrupt */
6146 #define SYSCFG_ITLINE1_SR_PVDOUT_Pos          (0U)
6147 #define SYSCFG_ITLINE1_SR_PVDOUT_Msk          (0x1UL << SYSCFG_ITLINE1_SR_PVDOUT_Pos) /*!< 0x00000001 */
6148 #define SYSCFG_ITLINE1_SR_PVDOUT              SYSCFG_ITLINE1_SR_PVDOUT_Msk     /*!< Power voltage detection -> exti[16] Interrupt */
6149 #define SYSCFG_ITLINE2_SR_TAMPER_Pos          (0U)
6150 #define SYSCFG_ITLINE2_SR_TAMPER_Msk          (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */
6151 #define SYSCFG_ITLINE2_SR_TAMPER              SYSCFG_ITLINE2_SR_TAMPER_Msk     /*!< TAMPER -> exti[21] interrupt */
6152 #define SYSCFG_ITLINE2_SR_RTC_Pos             (1U)
6153 #define SYSCFG_ITLINE2_SR_RTC_Msk             (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */
6154 #define SYSCFG_ITLINE2_SR_RTC                 SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */
6155 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos       (0U)
6156 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk       (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */
6157 #define SYSCFG_ITLINE3_SR_FLASH_ECC           SYSCFG_ITLINE3_SR_FLASH_ECC_Msk  /*!< Flash ITF ECC interrupt */
6158 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos       (1U)
6159 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk       (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
6160 #define SYSCFG_ITLINE3_SR_FLASH_ITF           SYSCFG_ITLINE3_SR_FLASH_ITF_Msk  /*!< FLASH ITF interrupt */
6161 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos        (0U)
6162 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk        (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
6163 #define SYSCFG_ITLINE4_SR_CLK_CTRL            SYSCFG_ITLINE4_SR_CLK_CTRL_Msk   /*!< RCC interrupt */
6164 #define SYSCFG_ITLINE5_SR_EXTI0_Pos           (0U)
6165 #define SYSCFG_ITLINE5_SR_EXTI0_Msk           (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
6166 #define SYSCFG_ITLINE5_SR_EXTI0               SYSCFG_ITLINE5_SR_EXTI0_Msk      /*!< External Interrupt 0 */
6167 #define SYSCFG_ITLINE5_SR_EXTI1_Pos           (1U)
6168 #define SYSCFG_ITLINE5_SR_EXTI1_Msk           (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
6169 #define SYSCFG_ITLINE5_SR_EXTI1               SYSCFG_ITLINE5_SR_EXTI1_Msk      /*!< External Interrupt 1 */
6170 #define SYSCFG_ITLINE6_SR_EXTI2_Pos           (0U)
6171 #define SYSCFG_ITLINE6_SR_EXTI2_Msk           (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
6172 #define SYSCFG_ITLINE6_SR_EXTI2               SYSCFG_ITLINE6_SR_EXTI2_Msk      /*!< External Interrupt 2 */
6173 #define SYSCFG_ITLINE6_SR_EXTI3_Pos           (1U)
6174 #define SYSCFG_ITLINE6_SR_EXTI3_Msk           (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
6175 #define SYSCFG_ITLINE6_SR_EXTI3               SYSCFG_ITLINE6_SR_EXTI3_Msk      /*!< External Interrupt 3 */
6176 #define SYSCFG_ITLINE7_SR_EXTI4_Pos           (0U)
6177 #define SYSCFG_ITLINE7_SR_EXTI4_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
6178 #define SYSCFG_ITLINE7_SR_EXTI4               SYSCFG_ITLINE7_SR_EXTI4_Msk      /*!< External Interrupt 4 */
6179 #define SYSCFG_ITLINE7_SR_EXTI5_Pos           (1U)
6180 #define SYSCFG_ITLINE7_SR_EXTI5_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
6181 #define SYSCFG_ITLINE7_SR_EXTI5               SYSCFG_ITLINE7_SR_EXTI5_Msk      /*!< External Interrupt 5 */
6182 #define SYSCFG_ITLINE7_SR_EXTI6_Pos           (2U)
6183 #define SYSCFG_ITLINE7_SR_EXTI6_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
6184 #define SYSCFG_ITLINE7_SR_EXTI6               SYSCFG_ITLINE7_SR_EXTI6_Msk      /*!< External Interrupt 6 */
6185 #define SYSCFG_ITLINE7_SR_EXTI7_Pos           (3U)
6186 #define SYSCFG_ITLINE7_SR_EXTI7_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
6187 #define SYSCFG_ITLINE7_SR_EXTI7               SYSCFG_ITLINE7_SR_EXTI7_Msk      /*!< External Interrupt 7 */
6188 #define SYSCFG_ITLINE7_SR_EXTI8_Pos           (4U)
6189 #define SYSCFG_ITLINE7_SR_EXTI8_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
6190 #define SYSCFG_ITLINE7_SR_EXTI8               SYSCFG_ITLINE7_SR_EXTI8_Msk      /*!< External Interrupt 8 */
6191 #define SYSCFG_ITLINE7_SR_EXTI9_Pos           (5U)
6192 #define SYSCFG_ITLINE7_SR_EXTI9_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
6193 #define SYSCFG_ITLINE7_SR_EXTI9               SYSCFG_ITLINE7_SR_EXTI9_Msk      /*!< External Interrupt 9 */
6194 #define SYSCFG_ITLINE7_SR_EXTI10_Pos          (6U)
6195 #define SYSCFG_ITLINE7_SR_EXTI10_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
6196 #define SYSCFG_ITLINE7_SR_EXTI10              SYSCFG_ITLINE7_SR_EXTI10_Msk     /*!< External Interrupt 10 */
6197 #define SYSCFG_ITLINE7_SR_EXTI11_Pos          (7U)
6198 #define SYSCFG_ITLINE7_SR_EXTI11_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
6199 #define SYSCFG_ITLINE7_SR_EXTI11              SYSCFG_ITLINE7_SR_EXTI11_Msk     /*!< External Interrupt 11 */
6200 #define SYSCFG_ITLINE7_SR_EXTI12_Pos          (8U)
6201 #define SYSCFG_ITLINE7_SR_EXTI12_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
6202 #define SYSCFG_ITLINE7_SR_EXTI12              SYSCFG_ITLINE7_SR_EXTI12_Msk     /*!< External Interrupt 12 */
6203 #define SYSCFG_ITLINE7_SR_EXTI13_Pos          (9U)
6204 #define SYSCFG_ITLINE7_SR_EXTI13_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
6205 #define SYSCFG_ITLINE7_SR_EXTI13              SYSCFG_ITLINE7_SR_EXTI13_Msk     /*!< External Interrupt 13 */
6206 #define SYSCFG_ITLINE7_SR_EXTI14_Pos          (10U)
6207 #define SYSCFG_ITLINE7_SR_EXTI14_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
6208 #define SYSCFG_ITLINE7_SR_EXTI14              SYSCFG_ITLINE7_SR_EXTI14_Msk     /*!< External Interrupt 14 */
6209 #define SYSCFG_ITLINE7_SR_EXTI15_Pos          (11U)
6210 #define SYSCFG_ITLINE7_SR_EXTI15_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
6211 #define SYSCFG_ITLINE7_SR_EXTI15              SYSCFG_ITLINE7_SR_EXTI15_Msk     /*!< External Interrupt 15 */
6212 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos        (0U)
6213 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk        (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
6214 #define SYSCFG_ITLINE9_SR_DMA1_CH1            SYSCFG_ITLINE9_SR_DMA1_CH1_Msk   /*!< DMA1 Channel 1 Interrupt */
6215 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos       (0U)
6216 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk       (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
6217 #define SYSCFG_ITLINE10_SR_DMA1_CH2           SYSCFG_ITLINE10_SR_DMA1_CH2_Msk  /*!< DMA1 Channel 2 Interrupt */
6218 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos       (1U)
6219 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk       (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
6220 #define SYSCFG_ITLINE10_SR_DMA1_CH3           SYSCFG_ITLINE10_SR_DMA1_CH3_Msk  /*!< DMA2 Channel 3 Interrupt */
6221 #define SYSCFG_ITLINE11_SR_DMAMUX1_Pos        (0U)
6222 #define SYSCFG_ITLINE11_SR_DMAMUX1_Msk        (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
6223 #define SYSCFG_ITLINE11_SR_DMAMUX1            SYSCFG_ITLINE11_SR_DMAMUX1_Msk    /*!< DMAMUX Interrupt */
6224 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos       (1U)
6225 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk       (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
6226 #define SYSCFG_ITLINE11_SR_DMA1_CH4           SYSCFG_ITLINE11_SR_DMA1_CH4_Msk  /*!< DMA1 Channel 4 Interrupt */
6227 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos       (2U)
6228 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk       (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */
6229 #define SYSCFG_ITLINE11_SR_DMA1_CH5           SYSCFG_ITLINE11_SR_DMA1_CH5_Msk  /*!< DMA1 Channel 5 Interrupt */
6230 #define SYSCFG_ITLINE12_SR_ADC_Pos            (0U)
6231 #define SYSCFG_ITLINE12_SR_ADC_Msk            (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
6232 #define SYSCFG_ITLINE12_SR_ADC                SYSCFG_ITLINE12_SR_ADC_Msk       /*!< ADC Interrupt */
6233 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos       (0U)
6234 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */
6235 #define SYSCFG_ITLINE13_SR_TIM1_CCU           SYSCFG_ITLINE13_SR_TIM1_CCU_Msk  /*!< TIM1 CCU Interrupt */
6236 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos       (1U)
6237 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */
6238 #define SYSCFG_ITLINE13_SR_TIM1_TRG           SYSCFG_ITLINE13_SR_TIM1_TRG_Msk  /*!< TIM1 TRG Interrupt */
6239 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos       (2U)
6240 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */
6241 #define SYSCFG_ITLINE13_SR_TIM1_UPD           SYSCFG_ITLINE13_SR_TIM1_UPD_Msk  /*!< TIM1 UPD Interrupt */
6242 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos       (3U)
6243 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */
6244 #define SYSCFG_ITLINE13_SR_TIM1_BRK           SYSCFG_ITLINE13_SR_TIM1_BRK_Msk  /*!< TIM1 BRK Interrupt */
6245 #define SYSCFG_ITLINE14_SR_TIM1_CC_Pos        (0U)
6246 #define SYSCFG_ITLINE14_SR_TIM1_CC_Msk        (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
6247 #define SYSCFG_ITLINE14_SR_TIM1_CC            SYSCFG_ITLINE14_SR_TIM1_CC_Msk   /*!< TIM1 CC Interrupt */
6248 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos       (0U)
6249 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk       (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */
6250 #define SYSCFG_ITLINE15_SR_TIM2_GLB           SYSCFG_ITLINE15_SR_TIM2_GLB_Msk  /*!< TIM2 GLB Interrupt */
6251 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos       (0U)
6252 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk       (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
6253 #define SYSCFG_ITLINE16_SR_TIM3_GLB           SYSCFG_ITLINE16_SR_TIM3_GLB_Msk  /*!< TIM3 GLB Interrupt */
6254 #define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos     (2U)
6255 #define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk     (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */
6256 #define SYSCFG_ITLINE17_SR_LPTIM1_GLB         SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */
6257 #define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos     (1U)
6258 #define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk     (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */
6259 #define SYSCFG_ITLINE18_SR_LPTIM2_GLB         SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */
6260 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos      (0U)
6261 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk      (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
6262 #define SYSCFG_ITLINE19_SR_TIM14_GLB          SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
6263 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos      (0U)
6264 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk      (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
6265 #define SYSCFG_ITLINE21_SR_TIM16_GLB          SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
6266 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos      (0U)
6267 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk      (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
6268 #define SYSCFG_ITLINE22_SR_TIM17_GLB          SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
6269 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos       (0U)
6270 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk       (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
6271 #define SYSCFG_ITLINE23_SR_I2C1_GLB           SYSCFG_ITLINE23_SR_I2C1_GLB_Msk  /*!< I2C1 GLB Interrupt -> exti[23] */
6272 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos       (0U)
6273 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk       (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
6274 #define SYSCFG_ITLINE24_SR_I2C2_GLB           SYSCFG_ITLINE24_SR_I2C2_GLB_Msk  /*!< I2C2 GLB Interrupt  -> exti[22]*/
6275 #define SYSCFG_ITLINE25_SR_SPI1_Pos           (0U)
6276 #define SYSCFG_ITLINE25_SR_SPI1_Msk           (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
6277 #define SYSCFG_ITLINE25_SR_SPI1               SYSCFG_ITLINE25_SR_SPI1_Msk      /*!< SPI1 Interrupt */
6278 #define SYSCFG_ITLINE26_SR_SPI2_Pos           (0U)
6279 #define SYSCFG_ITLINE26_SR_SPI2_Msk           (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
6280 #define SYSCFG_ITLINE26_SR_SPI2               SYSCFG_ITLINE26_SR_SPI2_Msk      /*!< SPI2  Interrupt */
6281 #define SYSCFG_ITLINE27_SR_USART1_GLB_Pos     (0U)
6282 #define SYSCFG_ITLINE27_SR_USART1_GLB_Msk     (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
6283 #define SYSCFG_ITLINE27_SR_USART1_GLB         SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
6284 #define SYSCFG_ITLINE28_SR_USART2_GLB_Pos     (0U)
6285 #define SYSCFG_ITLINE28_SR_USART2_GLB_Msk     (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
6286 #define SYSCFG_ITLINE28_SR_USART2_GLB         SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
6287 #define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos    (2U)
6288 #define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */
6289 #define SYSCFG_ITLINE29_SR_LPUART1_GLB        SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */
6290 #define SYSCFG_ITLINE31_SR_RNG_Pos            (0U)
6291 #define SYSCFG_ITLINE31_SR_RNG_Msk            (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */
6292 #define SYSCFG_ITLINE31_SR_RNG                SYSCFG_ITLINE31_SR_RNG_Msk       /*!< RNG Interrupt */
6293 #define SYSCFG_ITLINE31_SR_AES_Pos            (1U)
6294 #define SYSCFG_ITLINE31_SR_AES_Msk            (0x1UL << SYSCFG_ITLINE31_SR_AES_Pos) /*!< 0x00000002 */
6295 #define SYSCFG_ITLINE31_SR_AES                SYSCFG_ITLINE31_SR_AES_Msk       /*!< AES Interrupt */
6296 
6297 /******************************************************************************/
6298 /*                                                                            */
6299 /*                                    TIM                                     */
6300 /*                                                                            */
6301 /******************************************************************************/
6302 /*******************  Bit definition for TIM_CR1 register  ********************/
6303 #define TIM_CR1_CEN_Pos           (0U)
6304 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
6305 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
6306 #define TIM_CR1_UDIS_Pos          (1U)
6307 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
6308 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
6309 #define TIM_CR1_URS_Pos           (2U)
6310 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
6311 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
6312 #define TIM_CR1_OPM_Pos           (3U)
6313 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
6314 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
6315 #define TIM_CR1_DIR_Pos           (4U)
6316 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
6317 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
6318 
6319 #define TIM_CR1_CMS_Pos           (5U)
6320 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
6321 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
6322 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
6323 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
6324 
6325 #define TIM_CR1_ARPE_Pos          (7U)
6326 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
6327 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
6328 
6329 #define TIM_CR1_CKD_Pos           (8U)
6330 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
6331 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
6332 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
6333 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
6334 
6335 #define TIM_CR1_UIFREMAP_Pos      (11U)
6336 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
6337 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
6338 
6339 /*******************  Bit definition for TIM_CR2 register  ********************/
6340 #define TIM_CR2_CCPC_Pos          (0U)
6341 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
6342 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
6343 #define TIM_CR2_CCUS_Pos          (2U)
6344 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
6345 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
6346 #define TIM_CR2_CCDS_Pos          (3U)
6347 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
6348 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
6349 
6350 #define TIM_CR2_MMS_Pos           (4U)
6351 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
6352 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
6353 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
6354 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
6355 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
6356 
6357 #define TIM_CR2_TI1S_Pos          (7U)
6358 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
6359 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
6360 #define TIM_CR2_OIS1_Pos          (8U)
6361 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
6362 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
6363 #define TIM_CR2_OIS1N_Pos         (9U)
6364 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
6365 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
6366 #define TIM_CR2_OIS2_Pos          (10U)
6367 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
6368 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
6369 #define TIM_CR2_OIS2N_Pos         (11U)
6370 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
6371 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
6372 #define TIM_CR2_OIS3_Pos          (12U)
6373 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
6374 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
6375 #define TIM_CR2_OIS3N_Pos         (13U)
6376 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
6377 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
6378 #define TIM_CR2_OIS4_Pos          (14U)
6379 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
6380 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
6381 #define TIM_CR2_OIS5_Pos          (16U)
6382 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
6383 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
6384 #define TIM_CR2_OIS6_Pos          (18U)
6385 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
6386 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
6387 
6388 #define TIM_CR2_MMS2_Pos          (20U)
6389 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
6390 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
6391 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
6392 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
6393 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
6394 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
6395 
6396 /*******************  Bit definition for TIM_SMCR register  *******************/
6397 #define TIM_SMCR_SMS_Pos          (0U)
6398 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
6399 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
6400 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
6401 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
6402 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
6403 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
6404 
6405 #define TIM_SMCR_OCCS_Pos         (3U)
6406 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
6407 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
6408 
6409 #define TIM_SMCR_TS_Pos           (4U)
6410 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
6411 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
6412 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
6413 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
6414 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
6415 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
6416 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
6417 
6418 #define TIM_SMCR_MSM_Pos          (7U)
6419 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
6420 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
6421 
6422 #define TIM_SMCR_ETF_Pos          (8U)
6423 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
6424 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
6425 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
6426 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
6427 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
6428 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
6429 
6430 #define TIM_SMCR_ETPS_Pos         (12U)
6431 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
6432 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
6433 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
6434 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
6435 
6436 #define TIM_SMCR_ECE_Pos          (14U)
6437 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
6438 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
6439 #define TIM_SMCR_ETP_Pos          (15U)
6440 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
6441 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
6442 
6443 /*******************  Bit definition for TIM_DIER register  *******************/
6444 #define TIM_DIER_UIE_Pos          (0U)
6445 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
6446 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
6447 #define TIM_DIER_CC1IE_Pos        (1U)
6448 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
6449 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
6450 #define TIM_DIER_CC2IE_Pos        (2U)
6451 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
6452 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
6453 #define TIM_DIER_CC3IE_Pos        (3U)
6454 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
6455 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
6456 #define TIM_DIER_CC4IE_Pos        (4U)
6457 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
6458 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
6459 #define TIM_DIER_COMIE_Pos        (5U)
6460 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
6461 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
6462 #define TIM_DIER_TIE_Pos          (6U)
6463 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
6464 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
6465 #define TIM_DIER_BIE_Pos          (7U)
6466 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
6467 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
6468 #define TIM_DIER_UDE_Pos          (8U)
6469 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
6470 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
6471 #define TIM_DIER_CC1DE_Pos        (9U)
6472 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
6473 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
6474 #define TIM_DIER_CC2DE_Pos        (10U)
6475 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
6476 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
6477 #define TIM_DIER_CC3DE_Pos        (11U)
6478 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
6479 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
6480 #define TIM_DIER_CC4DE_Pos        (12U)
6481 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
6482 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
6483 #define TIM_DIER_COMDE_Pos        (13U)
6484 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
6485 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
6486 #define TIM_DIER_TDE_Pos          (14U)
6487 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
6488 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
6489 
6490 /********************  Bit definition for TIM_SR register  ********************/
6491 #define TIM_SR_UIF_Pos            (0U)
6492 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
6493 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
6494 #define TIM_SR_CC1IF_Pos          (1U)
6495 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
6496 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
6497 #define TIM_SR_CC2IF_Pos          (2U)
6498 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
6499 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
6500 #define TIM_SR_CC3IF_Pos          (3U)
6501 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
6502 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
6503 #define TIM_SR_CC4IF_Pos          (4U)
6504 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
6505 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
6506 #define TIM_SR_COMIF_Pos          (5U)
6507 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
6508 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
6509 #define TIM_SR_TIF_Pos            (6U)
6510 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
6511 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
6512 #define TIM_SR_BIF_Pos            (7U)
6513 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
6514 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
6515 #define TIM_SR_B2IF_Pos           (8U)
6516 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
6517 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
6518 #define TIM_SR_CC1OF_Pos          (9U)
6519 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
6520 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
6521 #define TIM_SR_CC2OF_Pos          (10U)
6522 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
6523 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
6524 #define TIM_SR_CC3OF_Pos          (11U)
6525 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
6526 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
6527 #define TIM_SR_CC4OF_Pos          (12U)
6528 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
6529 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
6530 #define TIM_SR_SBIF_Pos           (13U)
6531 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
6532 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
6533 #define TIM_SR_CC5IF_Pos          (16U)
6534 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
6535 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
6536 #define TIM_SR_CC6IF_Pos          (17U)
6537 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
6538 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
6539 
6540 
6541 /*******************  Bit definition for TIM_EGR register  ********************/
6542 #define TIM_EGR_UG_Pos            (0U)
6543 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
6544 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
6545 #define TIM_EGR_CC1G_Pos          (1U)
6546 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
6547 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
6548 #define TIM_EGR_CC2G_Pos          (2U)
6549 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
6550 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
6551 #define TIM_EGR_CC3G_Pos          (3U)
6552 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
6553 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
6554 #define TIM_EGR_CC4G_Pos          (4U)
6555 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
6556 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
6557 #define TIM_EGR_COMG_Pos          (5U)
6558 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
6559 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
6560 #define TIM_EGR_TG_Pos            (6U)
6561 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
6562 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
6563 #define TIM_EGR_BG_Pos            (7U)
6564 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
6565 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
6566 #define TIM_EGR_B2G_Pos           (8U)
6567 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
6568 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
6569 
6570 
6571 /******************  Bit definition for TIM_CCMR1 register  *******************/
6572 #define TIM_CCMR1_CC1S_Pos        (0U)
6573 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
6574 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6575 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
6576 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
6577 
6578 #define TIM_CCMR1_OC1FE_Pos       (2U)
6579 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
6580 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
6581 #define TIM_CCMR1_OC1PE_Pos       (3U)
6582 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
6583 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
6584 
6585 #define TIM_CCMR1_OC1M_Pos        (4U)
6586 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
6587 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6588 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
6589 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
6590 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
6591 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
6592 
6593 #define TIM_CCMR1_OC1CE_Pos       (7U)
6594 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
6595 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
6596 
6597 #define TIM_CCMR1_CC2S_Pos        (8U)
6598 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
6599 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6600 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
6601 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
6602 
6603 #define TIM_CCMR1_OC2FE_Pos       (10U)
6604 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
6605 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
6606 #define TIM_CCMR1_OC2PE_Pos       (11U)
6607 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
6608 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
6609 
6610 #define TIM_CCMR1_OC2M_Pos        (12U)
6611 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
6612 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6613 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
6614 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
6615 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
6616 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
6617 
6618 #define TIM_CCMR1_OC2CE_Pos       (15U)
6619 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
6620 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
6621 
6622 /*----------------------------------------------------------------------------*/
6623 #define TIM_CCMR1_IC1PSC_Pos      (2U)
6624 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
6625 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6626 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
6627 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
6628 
6629 #define TIM_CCMR1_IC1F_Pos        (4U)
6630 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
6631 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6632 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
6633 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
6634 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
6635 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
6636 
6637 #define TIM_CCMR1_IC2PSC_Pos      (10U)
6638 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
6639 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6640 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
6641 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
6642 
6643 #define TIM_CCMR1_IC2F_Pos        (12U)
6644 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
6645 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6646 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
6647 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
6648 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
6649 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
6650 
6651 /******************  Bit definition for TIM_CCMR2 register  *******************/
6652 #define TIM_CCMR2_CC3S_Pos        (0U)
6653 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
6654 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6655 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
6656 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
6657 
6658 #define TIM_CCMR2_OC3FE_Pos       (2U)
6659 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
6660 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
6661 #define TIM_CCMR2_OC3PE_Pos       (3U)
6662 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
6663 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
6664 
6665 #define TIM_CCMR2_OC3M_Pos        (4U)
6666 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
6667 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6668 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
6669 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
6670 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
6671 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
6672 
6673 #define TIM_CCMR2_OC3CE_Pos       (7U)
6674 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
6675 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
6676 
6677 #define TIM_CCMR2_CC4S_Pos        (8U)
6678 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
6679 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6680 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
6681 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
6682 
6683 #define TIM_CCMR2_OC4FE_Pos       (10U)
6684 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
6685 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
6686 #define TIM_CCMR2_OC4PE_Pos       (11U)
6687 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
6688 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
6689 
6690 #define TIM_CCMR2_OC4M_Pos        (12U)
6691 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
6692 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6693 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
6694 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
6695 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
6696 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
6697 
6698 #define TIM_CCMR2_OC4CE_Pos       (15U)
6699 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
6700 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
6701 
6702 /*----------------------------------------------------------------------------*/
6703 #define TIM_CCMR2_IC3PSC_Pos      (2U)
6704 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
6705 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6706 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
6707 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
6708 
6709 #define TIM_CCMR2_IC3F_Pos        (4U)
6710 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
6711 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6712 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
6713 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
6714 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
6715 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
6716 
6717 #define TIM_CCMR2_IC4PSC_Pos      (10U)
6718 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
6719 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6720 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
6721 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
6722 
6723 #define TIM_CCMR2_IC4F_Pos        (12U)
6724 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
6725 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6726 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
6727 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
6728 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
6729 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
6730 
6731 /******************  Bit definition for TIM_CCMR3 register  *******************/
6732 #define TIM_CCMR3_OC5FE_Pos       (2U)
6733 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
6734 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
6735 #define TIM_CCMR3_OC5PE_Pos       (3U)
6736 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
6737 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
6738 
6739 #define TIM_CCMR3_OC5M_Pos        (4U)
6740 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
6741 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
6742 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
6743 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
6744 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
6745 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
6746 
6747 #define TIM_CCMR3_OC5CE_Pos       (7U)
6748 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
6749 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
6750 
6751 #define TIM_CCMR3_OC6FE_Pos       (10U)
6752 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
6753 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
6754 #define TIM_CCMR3_OC6PE_Pos       (11U)
6755 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
6756 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
6757 
6758 #define TIM_CCMR3_OC6M_Pos        (12U)
6759 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
6760 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
6761 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
6762 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
6763 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
6764 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
6765 
6766 #define TIM_CCMR3_OC6CE_Pos       (15U)
6767 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
6768 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
6769 
6770 /*******************  Bit definition for TIM_CCER register  *******************/
6771 #define TIM_CCER_CC1E_Pos         (0U)
6772 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
6773 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
6774 #define TIM_CCER_CC1P_Pos         (1U)
6775 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
6776 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
6777 #define TIM_CCER_CC1NE_Pos        (2U)
6778 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
6779 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
6780 #define TIM_CCER_CC1NP_Pos        (3U)
6781 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
6782 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
6783 #define TIM_CCER_CC2E_Pos         (4U)
6784 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
6785 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
6786 #define TIM_CCER_CC2P_Pos         (5U)
6787 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
6788 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
6789 #define TIM_CCER_CC2NE_Pos        (6U)
6790 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
6791 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
6792 #define TIM_CCER_CC2NP_Pos        (7U)
6793 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
6794 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
6795 #define TIM_CCER_CC3E_Pos         (8U)
6796 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
6797 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
6798 #define TIM_CCER_CC3P_Pos         (9U)
6799 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
6800 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
6801 #define TIM_CCER_CC3NE_Pos        (10U)
6802 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
6803 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
6804 #define TIM_CCER_CC3NP_Pos        (11U)
6805 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
6806 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
6807 #define TIM_CCER_CC4E_Pos         (12U)
6808 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
6809 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
6810 #define TIM_CCER_CC4P_Pos         (13U)
6811 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
6812 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
6813 #define TIM_CCER_CC4NP_Pos        (15U)
6814 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
6815 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
6816 #define TIM_CCER_CC5E_Pos         (16U)
6817 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
6818 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
6819 #define TIM_CCER_CC5P_Pos         (17U)
6820 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
6821 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
6822 #define TIM_CCER_CC6E_Pos         (20U)
6823 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
6824 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
6825 #define TIM_CCER_CC6P_Pos         (21U)
6826 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
6827 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
6828 
6829 /*******************  Bit definition for TIM_CNT register  ********************/
6830 #define TIM_CNT_CNT_Pos           (0U)
6831 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
6832 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
6833 #define TIM_CNT_UIFCPY_Pos        (31U)
6834 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
6835 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
6836 
6837 /*******************  Bit definition for TIM_PSC register  ********************/
6838 #define TIM_PSC_PSC_Pos           (0U)
6839 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
6840 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
6841 
6842 /*******************  Bit definition for TIM_ARR register  ********************/
6843 #define TIM_ARR_ARR_Pos           (0U)
6844 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
6845 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
6846 
6847 /*******************  Bit definition for TIM_RCR register  ********************/
6848 #define TIM_RCR_REP_Pos           (0U)
6849 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
6850 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
6851 
6852 /*******************  Bit definition for TIM_CCR1 register  *******************/
6853 #define TIM_CCR1_CCR1_Pos         (0U)
6854 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
6855 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
6856 
6857 /*******************  Bit definition for TIM_CCR2 register  *******************/
6858 #define TIM_CCR2_CCR2_Pos         (0U)
6859 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
6860 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
6861 
6862 /*******************  Bit definition for TIM_CCR3 register  *******************/
6863 #define TIM_CCR3_CCR3_Pos         (0U)
6864 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
6865 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
6866 
6867 /*******************  Bit definition for TIM_CCR4 register  *******************/
6868 #define TIM_CCR4_CCR4_Pos         (0U)
6869 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
6870 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
6871 
6872 /*******************  Bit definition for TIM_CCR5 register  *******************/
6873 #define TIM_CCR5_CCR5_Pos         (0U)
6874 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
6875 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
6876 #define TIM_CCR5_GC5C1_Pos        (29U)
6877 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
6878 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
6879 #define TIM_CCR5_GC5C2_Pos        (30U)
6880 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
6881 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
6882 #define TIM_CCR5_GC5C3_Pos        (31U)
6883 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
6884 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
6885 
6886 /*******************  Bit definition for TIM_CCR6 register  *******************/
6887 #define TIM_CCR6_CCR6_Pos         (0U)
6888 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
6889 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
6890 
6891 /*******************  Bit definition for TIM_BDTR register  *******************/
6892 #define TIM_BDTR_DTG_Pos          (0U)
6893 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
6894 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
6895 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
6896 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
6897 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
6898 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
6899 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
6900 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
6901 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
6902 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
6903 
6904 #define TIM_BDTR_LOCK_Pos         (8U)
6905 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
6906 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
6907 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
6908 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
6909 
6910 #define TIM_BDTR_OSSI_Pos         (10U)
6911 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
6912 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
6913 #define TIM_BDTR_OSSR_Pos         (11U)
6914 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
6915 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
6916 #define TIM_BDTR_BKE_Pos          (12U)
6917 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
6918 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
6919 #define TIM_BDTR_BKP_Pos          (13U)
6920 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
6921 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
6922 #define TIM_BDTR_AOE_Pos          (14U)
6923 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
6924 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
6925 #define TIM_BDTR_MOE_Pos          (15U)
6926 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
6927 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
6928 
6929 #define TIM_BDTR_BKF_Pos          (16U)
6930 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
6931 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
6932 #define TIM_BDTR_BK2F_Pos         (20U)
6933 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
6934 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
6935 
6936 #define TIM_BDTR_BK2E_Pos         (24U)
6937 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
6938 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
6939 #define TIM_BDTR_BK2P_Pos         (25U)
6940 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
6941 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
6942 
6943 #define TIM_BDTR_BKDSRM_Pos       (26U)
6944 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
6945 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
6946 #define TIM_BDTR_BK2DSRM_Pos      (27U)
6947 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
6948 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
6949 
6950 #define TIM_BDTR_BKBID_Pos        (28U)
6951 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
6952 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
6953 #define TIM_BDTR_BK2BID_Pos       (29U)
6954 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
6955 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
6956 
6957 /*******************  Bit definition for TIM_DCR register  ********************/
6958 #define TIM_DCR_DBA_Pos           (0U)
6959 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
6960 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
6961 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
6962 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
6963 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
6964 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
6965 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
6966 
6967 #define TIM_DCR_DBL_Pos           (8U)
6968 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
6969 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
6970 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
6971 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
6972 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
6973 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
6974 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
6975 
6976 /*******************  Bit definition for TIM_DMAR register  *******************/
6977 #define TIM_DMAR_DMAB_Pos         (0U)
6978 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
6979 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
6980 
6981 /*******************  Bit definition for TIM1_OR1 register  *******************/
6982 #define TIM1_OR1_OCREF_CLR_Pos     (0U)
6983 #define TIM1_OR1_OCREF_CLR_Msk     (0x1UL << TIM1_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */
6984 #define TIM1_OR1_OCREF_CLR         TIM1_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */
6985 
6986 /*******************  Bit definition for TIM1_AF1 register  *******************/
6987 #define TIM1_AF1_BKINE_Pos        (0U)
6988 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
6989 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
6990 #define TIM1_AF1_BKCMP1E_Pos      (1U)
6991 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
6992 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
6993 #define TIM1_AF1_BKCMP2E_Pos      (2U)
6994 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
6995 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
6996 #define TIM1_AF1_BKINP_Pos        (9U)
6997 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
6998 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
6999 #define TIM1_AF1_BKCMP1P_Pos      (10U)
7000 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7001 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7002 #define TIM1_AF1_BKCMP2P_Pos      (11U)
7003 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7004 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7005 
7006 #define TIM1_AF1_ETRSEL_Pos       (14U)
7007 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
7008 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
7009 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
7010 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
7011 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
7012 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
7013 
7014 /*******************  Bit definition for TIM1_AF2 register  *******************/
7015 #define TIM1_AF2_BK2INE_Pos       (0U)
7016 #define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
7017 #define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
7018 #define TIM1_AF2_BK2CMP1E_Pos     (1U)
7019 #define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
7020 #define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
7021 #define TIM1_AF2_BK2CMP2E_Pos     (2U)
7022 #define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
7023 #define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
7024 #define TIM1_AF2_BK2INP_Pos       (9U)
7025 #define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
7026 #define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
7027 #define TIM1_AF2_BK2CMP1P_Pos     (10U)
7028 #define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
7029 #define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
7030 #define TIM1_AF2_BK2CMP2P_Pos     (11U)
7031 #define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
7032 #define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
7033 
7034 /*******************  Bit definition for TIM2_OR1 register  *******************/
7035 #define TIM2_OR1_OCREF_CLR_Pos     (0U)
7036 #define TIM2_OR1_OCREF_CLR_Msk     (0x1UL << TIM2_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */
7037 #define TIM2_OR1_OCREF_CLR         TIM2_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */
7038 
7039 /*******************  Bit definition for TIM2_AF1 register  *******************/
7040 #define TIM2_AF1_ETRSEL_Pos       (14U)
7041 #define TIM2_AF1_ETRSEL_Msk       (0xFUL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
7042 #define TIM2_AF1_ETRSEL           TIM2_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM2 ETR source selection) */
7043 #define TIM2_AF1_ETRSEL_0         (0x1UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
7044 #define TIM2_AF1_ETRSEL_1         (0x2UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
7045 #define TIM2_AF1_ETRSEL_2         (0x4UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
7046 #define TIM2_AF1_ETRSEL_3         (0x8UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
7047 
7048 /*******************  Bit definition for TIM3_OR1 register  *******************/
7049 #define TIM3_OR1_OCREF_CLR_Pos     (0U)
7050 #define TIM3_OR1_OCREF_CLR_Msk     (0x1UL << TIM3_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */
7051 #define TIM3_OR1_OCREF_CLR         TIM3_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */
7052 
7053 /*******************  Bit definition for TIM3_AF1 register  *******************/
7054 #define TIM3_AF1_ETRSEL_Pos       (14U)
7055 #define TIM3_AF1_ETRSEL_Msk       (0xFUL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
7056 #define TIM3_AF1_ETRSEL           TIM3_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
7057 #define TIM3_AF1_ETRSEL_0         (0x1UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
7058 #define TIM3_AF1_ETRSEL_1         (0x2UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
7059 #define TIM3_AF1_ETRSEL_2         (0x4UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
7060 #define TIM3_AF1_ETRSEL_3         (0x8UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
7061 
7062 /*******************  Bit definition for TIM14_AF1 register  *******************/
7063 #define TIM14_AF1_ETRSEL_Pos      (14U)
7064 #define TIM14_AF1_ETRSEL_Msk      (0xFUL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
7065 #define TIM14_AF1_ETRSEL          TIM14_AF1_ETRSEL_Msk                         /*!<ETRSEL[3:0] bits (TIM14 ETR source selection) */
7066 #define TIM14_AF1_ETRSEL_0        (0x1UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
7067 #define TIM14_AF1_ETRSEL_1        (0x2UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
7068 #define TIM14_AF1_ETRSEL_2        (0x4UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
7069 #define TIM14_AF1_ETRSEL_3        (0x8UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
7070 
7071 
7072 /*******************  Bit definition for TIM16_AF1 register  ******************/
7073 #define TIM16_AF1_BKINE_Pos      (0U)
7074 #define TIM16_AF1_BKINE_Msk      (0x1UL << TIM16_AF1_BKINE_Pos)                /*!< 0x00000001 */
7075 #define TIM16_AF1_BKINE          TIM16_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
7076 #define TIM16_AF1_BKCMP1E_Pos    (1U)
7077 #define TIM16_AF1_BKCMP1E_Msk    (0x1UL << TIM16_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
7078 #define TIM16_AF1_BKCMP1E        TIM16_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
7079 #define TIM16_AF1_BKCMP2E_Pos    (2U)
7080 #define TIM16_AF1_BKCMP2E_Msk    (0x1UL << TIM16_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
7081 #define TIM16_AF1_BKCMP2E        TIM16_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
7082 #define TIM16_AF1_BKINP_Pos      (9U)
7083 #define TIM16_AF1_BKINP_Msk      (0x1UL << TIM16_AF1_BKINP_Pos)                /*!< 0x00000200 */
7084 #define TIM16_AF1_BKINP          TIM16_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
7085 #define TIM16_AF1_BKCMP1P_Pos    (10U)
7086 #define TIM16_AF1_BKCMP1P_Msk    (0x1UL << TIM16_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7087 #define TIM16_AF1_BKCMP1P        TIM16_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7088 #define TIM16_AF1_BKCMP2P_Pos    (11U)
7089 #define TIM16_AF1_BKCMP2P_Msk    (0x1UL << TIM16_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7090 #define TIM16_AF1_BKCMP2P        TIM16_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7091 
7092 /*******************  Bit definition for TIM17_AF1 register  ******************/
7093 #define TIM17_AF1_BKINE_Pos      (0U)
7094 #define TIM17_AF1_BKINE_Msk      (0x1UL << TIM17_AF1_BKINE_Pos)                /*!< 0x00000001 */
7095 #define TIM17_AF1_BKINE          TIM17_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
7096 #define TIM17_AF1_BKCMP1E_Pos    (1U)
7097 #define TIM17_AF1_BKCMP1E_Msk    (0x1UL << TIM17_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
7098 #define TIM17_AF1_BKCMP1E        TIM17_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
7099 #define TIM17_AF1_BKCMP2E_Pos    (2U)
7100 #define TIM17_AF1_BKCMP2E_Msk    (0x1UL << TIM17_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
7101 #define TIM17_AF1_BKCMP2E        TIM17_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
7102 #define TIM17_AF1_BKINP_Pos      (9U)
7103 #define TIM17_AF1_BKINP_Msk      (0x1UL << TIM17_AF1_BKINP_Pos)                /*!< 0x00000200 */
7104 #define TIM17_AF1_BKINP          TIM17_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
7105 #define TIM17_AF1_BKCMP1P_Pos    (10U)
7106 #define TIM17_AF1_BKCMP1P_Msk    (0x1UL << TIM17_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7107 #define TIM17_AF1_BKCMP1P        TIM17_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7108 #define TIM17_AF1_BKCMP2P_Pos    (11U)
7109 #define TIM17_AF1_BKCMP2P_Msk    (0x1UL << TIM17_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7110 #define TIM17_AF1_BKCMP2P        TIM17_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7111 
7112 /*******************  Bit definition for TIM_TISEL register  *********************/
7113 #define TIM_TISEL_TI1SEL_Pos      (0U)
7114 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
7115 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
7116 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
7117 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
7118 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
7119 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
7120 
7121 #define TIM_TISEL_TI2SEL_Pos      (8U)
7122 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
7123 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
7124 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
7125 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
7126 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
7127 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
7128 
7129 #define TIM_TISEL_TI3SEL_Pos      (16U)
7130 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
7131 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
7132 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
7133 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
7134 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
7135 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
7136 
7137 #define TIM_TISEL_TI4SEL_Pos      (24U)
7138 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
7139 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
7140 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
7141 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
7142 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
7143 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
7144 
7145 /******************************************************************************/
7146 /*                                                                            */
7147 /*                         Low Power Timer (LPTIM)                            */
7148 /*                                                                            */
7149 /******************************************************************************/
7150 /******************  Bit definition for LPTIM_ISR register  *******************/
7151 #define LPTIM_ISR_CMPM_Pos          (0U)
7152 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
7153 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
7154 #define LPTIM_ISR_ARRM_Pos          (1U)
7155 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
7156 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
7157 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
7158 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
7159 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
7160 #define LPTIM_ISR_CMPOK_Pos         (3U)
7161 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
7162 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
7163 #define LPTIM_ISR_ARROK_Pos         (4U)
7164 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
7165 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
7166 #define LPTIM_ISR_UP_Pos            (5U)
7167 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
7168 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
7169 #define LPTIM_ISR_DOWN_Pos          (6U)
7170 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
7171 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
7172 
7173 /******************  Bit definition for LPTIM_ICR register  *******************/
7174 #define LPTIM_ICR_CMPMCF_Pos        (0U)
7175 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
7176 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
7177 #define LPTIM_ICR_ARRMCF_Pos        (1U)
7178 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
7179 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
7180 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
7181 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
7182 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
7183 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
7184 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
7185 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
7186 #define LPTIM_ICR_ARROKCF_Pos       (4U)
7187 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
7188 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
7189 #define LPTIM_ICR_UPCF_Pos          (5U)
7190 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
7191 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
7192 #define LPTIM_ICR_DOWNCF_Pos        (6U)
7193 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
7194 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
7195 
7196 /******************  Bit definition for LPTIM_IER register ********************/
7197 #define LPTIM_IER_CMPMIE_Pos        (0U)
7198 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
7199 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
7200 #define LPTIM_IER_ARRMIE_Pos        (1U)
7201 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
7202 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
7203 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
7204 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
7205 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
7206 #define LPTIM_IER_CMPOKIE_Pos       (3U)
7207 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
7208 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
7209 #define LPTIM_IER_ARROKIE_Pos       (4U)
7210 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
7211 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
7212 #define LPTIM_IER_UPIE_Pos          (5U)
7213 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
7214 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
7215 #define LPTIM_IER_DOWNIE_Pos        (6U)
7216 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
7217 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
7218 
7219 /******************  Bit definition for LPTIM_CFGR register *******************/
7220 #define LPTIM_CFGR_CKSEL_Pos        (0U)
7221 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
7222 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
7223 
7224 #define LPTIM_CFGR_CKPOL_Pos        (1U)
7225 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
7226 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
7227 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
7228 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
7229 
7230 #define LPTIM_CFGR_CKFLT_Pos        (3U)
7231 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
7232 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7233 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
7234 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
7235 
7236 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
7237 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
7238 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7239 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
7240 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
7241 
7242 #define LPTIM_CFGR_PRESC_Pos        (9U)
7243 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
7244 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
7245 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
7246 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
7247 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
7248 
7249 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
7250 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
7251 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7252 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
7253 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
7254 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
7255 
7256 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
7257 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
7258 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7259 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
7260 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
7261 
7262 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
7263 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
7264 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timeout enable */
7265 #define LPTIM_CFGR_WAVE_Pos         (20U)
7266 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
7267 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
7268 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
7269 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
7270 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
7271 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
7272 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
7273 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
7274 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
7275 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
7276 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
7277 #define LPTIM_CFGR_ENC_Pos          (24U)
7278 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
7279 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
7280 
7281 /******************  Bit definition for LPTIM_CR register  ********************/
7282 #define LPTIM_CR_ENABLE_Pos         (0U)
7283 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
7284 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
7285 #define LPTIM_CR_SNGSTRT_Pos        (1U)
7286 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
7287 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
7288 #define LPTIM_CR_CNTSTRT_Pos        (2U)
7289 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
7290 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
7291 #define LPTIM_CR_COUNTRST_Pos       (3U)
7292 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
7293 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
7294 #define LPTIM_CR_RSTARE_Pos         (4U)
7295 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
7296 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
7297 
7298 /******************  Bit definition for LPTIM_CMP register  *******************/
7299 #define LPTIM_CMP_CMP_Pos           (0U)
7300 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
7301 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
7302 
7303 /******************  Bit definition for LPTIM_ARR register  *******************/
7304 #define LPTIM_ARR_ARR_Pos           (0U)
7305 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
7306 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
7307 
7308 /******************  Bit definition for LPTIM_CNT register  *******************/
7309 #define LPTIM_CNT_CNT_Pos           (0U)
7310 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
7311 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
7312 
7313 /******************  Bit definition for LPTIM_CFGR2 register  *******************/
7314 #define LPTIM_CFGR2_IN1SEL_Pos      (0U)
7315 #define LPTIM_CFGR2_IN1SEL_Msk      (0xFUL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x0000000F */
7316 #define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< CFGR2[3:0] bits (INPUT1 selection) */
7317 #define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000001 */
7318 #define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000002 */
7319 #define LPTIM_CFGR2_IN1SEL_2        (0x4UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000004 */
7320 #define LPTIM_CFGR2_IN1SEL_3        (0x8UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000008 */
7321 
7322 #define LPTIM_CFGR2_IN2SEL_Pos      (4U)
7323 #define LPTIM_CFGR2_IN2SEL_Msk      (0xFUL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x000000F0 */
7324 #define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< CFGR2[7:4] bits (INPUT2 selection) */
7325 #define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000010 */
7326 #define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000020 */
7327 #define LPTIM_CFGR2_IN2SEL_2        (0x4UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000040 */
7328 #define LPTIM_CFGR2_IN2SEL_3        (0x8UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000080 */
7329 
7330 
7331 /******************************************************************************/
7332 /*                                                                            */
7333 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
7334 /*                                                                            */
7335 /******************************************************************************/
7336 /******************  Bit definition for USART_CR1 register  *******************/
7337 #define USART_CR1_UE_Pos             (0U)
7338 #define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
7339 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
7340 #define USART_CR1_UESM_Pos           (1U)
7341 #define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
7342 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
7343 #define USART_CR1_RE_Pos             (2U)
7344 #define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
7345 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
7346 #define USART_CR1_TE_Pos             (3U)
7347 #define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
7348 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
7349 #define USART_CR1_IDLEIE_Pos         (4U)
7350 #define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
7351 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
7352 #define USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)
7353 #define USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
7354 #define USART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE_Msk            /*!< RXNE/RXFIFO not empty Interrupt Enable */
7355 #define USART_CR1_TCIE_Pos           (6U)
7356 #define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
7357 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
7358 #define USART_CR1_TXEIE_TXFNFIE_Pos  (7U)
7359 #define USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)   /*!< 0x00000080 */
7360 #define USART_CR1_TXEIE_TXFNFIE       USART_CR1_TXEIE_TXFNFIE_Msk              /*!< TXE/TXFIFO not full Interrupt Enable */
7361 #define USART_CR1_PEIE_Pos           (8U)
7362 #define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
7363 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
7364 #define USART_CR1_PS_Pos             (9U)
7365 #define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
7366 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
7367 #define USART_CR1_PCE_Pos            (10U)
7368 #define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
7369 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
7370 #define USART_CR1_WAKE_Pos           (11U)
7371 #define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
7372 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
7373 #define USART_CR1_M_Pos              (12U)
7374 #define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
7375 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
7376 #define USART_CR1_M0_Pos             (12U)
7377 #define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
7378 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
7379 #define USART_CR1_MME_Pos            (13U)
7380 #define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
7381 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
7382 #define USART_CR1_CMIE_Pos           (14U)
7383 #define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
7384 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
7385 #define USART_CR1_OVER8_Pos          (15U)
7386 #define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
7387 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
7388 #define USART_CR1_DEDT_Pos           (16U)
7389 #define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
7390 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
7391 #define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
7392 #define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
7393 #define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
7394 #define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
7395 #define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
7396 #define USART_CR1_DEAT_Pos           (21U)
7397 #define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
7398 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
7399 #define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
7400 #define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
7401 #define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
7402 #define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
7403 #define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
7404 #define USART_CR1_RTOIE_Pos          (26U)
7405 #define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
7406 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
7407 #define USART_CR1_EOBIE_Pos          (27U)
7408 #define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
7409 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
7410 #define USART_CR1_M1_Pos             (28U)
7411 #define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
7412 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
7413 #define USART_CR1_FIFOEN_Pos         (29U)
7414 #define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
7415 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
7416 #define USART_CR1_TXFEIE_Pos         (30U)
7417 #define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
7418 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
7419 #define USART_CR1_RXFFIE_Pos         (31U)
7420 #define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
7421 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
7422 
7423 /******************  Bit definition for USART_CR2 register  *******************/
7424 #define USART_CR2_SLVEN_Pos          (0U)
7425 #define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
7426 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
7427 #define USART_CR2_DIS_NSS_Pos        (3U)
7428 #define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
7429 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< NSS input pin disable for SPI slave selection */
7430 #define USART_CR2_ADDM7_Pos          (4U)
7431 #define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
7432 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
7433 #define USART_CR2_LBDL_Pos           (5U)
7434 #define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
7435 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
7436 #define USART_CR2_LBDIE_Pos          (6U)
7437 #define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
7438 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
7439 #define USART_CR2_LBCL_Pos           (8U)
7440 #define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
7441 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
7442 #define USART_CR2_CPHA_Pos           (9U)
7443 #define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
7444 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
7445 #define USART_CR2_CPOL_Pos           (10U)
7446 #define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
7447 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
7448 #define USART_CR2_CLKEN_Pos          (11U)
7449 #define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
7450 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
7451 #define USART_CR2_STOP_Pos           (12U)
7452 #define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
7453 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
7454 #define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
7455 #define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
7456 #define USART_CR2_LINEN_Pos          (14U)
7457 #define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
7458 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
7459 #define USART_CR2_SWAP_Pos           (15U)
7460 #define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
7461 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
7462 #define USART_CR2_RXINV_Pos          (16U)
7463 #define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
7464 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
7465 #define USART_CR2_TXINV_Pos          (17U)
7466 #define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
7467 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
7468 #define USART_CR2_DATAINV_Pos        (18U)
7469 #define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
7470 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
7471 #define USART_CR2_MSBFIRST_Pos       (19U)
7472 #define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
7473 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
7474 #define USART_CR2_ABREN_Pos          (20U)
7475 #define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
7476 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
7477 #define USART_CR2_ABRMODE_Pos        (21U)
7478 #define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
7479 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
7480 #define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
7481 #define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
7482 #define USART_CR2_RTOEN_Pos          (23U)
7483 #define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
7484 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
7485 #define USART_CR2_ADD_Pos            (24U)
7486 #define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
7487 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
7488 
7489 /******************  Bit definition for USART_CR3 register  *******************/
7490 #define USART_CR3_EIE_Pos            (0U)
7491 #define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
7492 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
7493 #define USART_CR3_IREN_Pos           (1U)
7494 #define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
7495 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
7496 #define USART_CR3_IRLP_Pos           (2U)
7497 #define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
7498 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
7499 #define USART_CR3_HDSEL_Pos          (3U)
7500 #define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
7501 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
7502 #define USART_CR3_NACK_Pos           (4U)
7503 #define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
7504 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
7505 #define USART_CR3_SCEN_Pos           (5U)
7506 #define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
7507 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
7508 #define USART_CR3_DMAR_Pos           (6U)
7509 #define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
7510 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
7511 #define USART_CR3_DMAT_Pos           (7U)
7512 #define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
7513 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
7514 #define USART_CR3_RTSE_Pos           (8U)
7515 #define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
7516 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
7517 #define USART_CR3_CTSE_Pos           (9U)
7518 #define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
7519 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
7520 #define USART_CR3_CTSIE_Pos          (10U)
7521 #define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
7522 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
7523 #define USART_CR3_ONEBIT_Pos         (11U)
7524 #define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
7525 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
7526 #define USART_CR3_OVRDIS_Pos         (12U)
7527 #define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
7528 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
7529 #define USART_CR3_DDRE_Pos           (13U)
7530 #define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
7531 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
7532 #define USART_CR3_DEM_Pos            (14U)
7533 #define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
7534 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
7535 #define USART_CR3_DEP_Pos            (15U)
7536 #define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
7537 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
7538 #define USART_CR3_SCARCNT_Pos        (17U)
7539 #define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
7540 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
7541 #define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
7542 #define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
7543 #define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
7544 #define USART_CR3_WUS_Pos            (20U)
7545 #define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
7546 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
7547 #define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
7548 #define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
7549 #define USART_CR3_WUFIE_Pos          (22U)
7550 #define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
7551 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
7552 #define USART_CR3_TXFTIE_Pos         (23U)
7553 #define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
7554 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
7555 #define USART_CR3_TCBGTIE_Pos        (24U)
7556 #define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
7557 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
7558 #define USART_CR3_RXFTCFG_Pos        (25U)
7559 #define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
7560 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
7561 #define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
7562 #define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
7563 #define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
7564 #define USART_CR3_RXFTIE_Pos         (28U)
7565 #define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
7566 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
7567 #define USART_CR3_TXFTCFG_Pos        (29U)
7568 #define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
7569 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
7570 #define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
7571 #define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
7572 #define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
7573 
7574 /******************  Bit definition for USART_BRR register  *******************/
7575 #define USART_BRR_LPUART_Pos         (0U)
7576 #define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
7577 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
7578 #define USART_BRR_BRR                ((uint16_t)0xFFFF)                        /*!< USART  Baud rate register [15:0] */
7579 
7580 /******************  Bit definition for USART_GTPR register  ******************/
7581 #define USART_GTPR_PSC_Pos           (0U)
7582 #define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
7583 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
7584 #define USART_GTPR_GT_Pos            (8U)
7585 #define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
7586 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
7587 
7588 /*******************  Bit definition for USART_RTOR register  *****************/
7589 #define USART_RTOR_RTO_Pos           (0U)
7590 #define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
7591 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
7592 #define USART_RTOR_BLEN_Pos          (24U)
7593 #define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
7594 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
7595 
7596 /*******************  Bit definition for USART_RQR register  ******************/
7597 #define USART_RQR_ABRRQ        ((uint16_t)0x0001)                              /*!< Auto-Baud Rate Request */
7598 #define USART_RQR_SBKRQ        ((uint16_t)0x0002)                              /*!< Send Break Request */
7599 #define USART_RQR_MMRQ         ((uint16_t)0x0004)                              /*!< Mute Mode Request */
7600 #define USART_RQR_RXFRQ        ((uint16_t)0x0008)                              /*!< Receive Data flush Request */
7601 #define USART_RQR_TXFRQ        ((uint16_t)0x0010)                              /*!< Transmit data flush Request */
7602 
7603 /*******************  Bit definition for USART_ISR register  ******************/
7604 #define USART_ISR_PE_Pos             (0U)
7605 #define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
7606 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
7607 #define USART_ISR_FE_Pos             (1U)
7608 #define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
7609 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
7610 #define USART_ISR_NE_Pos             (2U)
7611 #define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
7612 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
7613 #define USART_ISR_ORE_Pos            (3U)
7614 #define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
7615 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
7616 #define USART_ISR_IDLE_Pos           (4U)
7617 #define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
7618 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
7619 #define USART_ISR_RXNE_RXFNE_Pos     (5U)
7620 #define USART_ISR_RXNE_RXFNE_Msk     (0x1UL << USART_ISR_RXNE_RXFNE_Pos)       /*!< 0x00000020 */
7621 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_RXFNE_Msk                  /*!< Read Data Register Not Empty/RXFIFO Not Empty */
7622 #define USART_ISR_TC_Pos             (6U)
7623 #define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
7624 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
7625 #define USART_ISR_TXE_TXFNF_Pos      (7U)
7626 #define USART_ISR_TXE_TXFNF_Msk      (0x1UL << USART_ISR_TXE_TXFNF_Pos)        /*!< 0x00000080 */
7627 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_TXFNF_Msk                   /*!< Transmit Data Register Empty/TXFIFO Not Full */
7628 #define USART_ISR_LBDF_Pos           (8U)
7629 #define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
7630 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
7631 #define USART_ISR_CTSIF_Pos          (9U)
7632 #define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
7633 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
7634 #define USART_ISR_CTS_Pos            (10U)
7635 #define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
7636 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
7637 #define USART_ISR_RTOF_Pos           (11U)
7638 #define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
7639 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
7640 #define USART_ISR_EOBF_Pos           (12U)
7641 #define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
7642 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
7643 #define USART_ISR_UDR_Pos            (13U)
7644 #define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
7645 #define USART_ISR_UDR                 USART_ISR_UDR_Msk                        /*!< SPI Slave Underrun Error Flag */
7646 #define USART_ISR_ABRE_Pos           (14U)
7647 #define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
7648 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
7649 #define USART_ISR_ABRF_Pos           (15U)
7650 #define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
7651 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
7652 #define USART_ISR_BUSY_Pos           (16U)
7653 #define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
7654 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
7655 #define USART_ISR_CMF_Pos            (17U)
7656 #define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
7657 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
7658 #define USART_ISR_SBKF_Pos           (18U)
7659 #define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
7660 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
7661 #define USART_ISR_RWU_Pos            (19U)
7662 #define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
7663 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
7664 #define USART_ISR_WUF_Pos            (20U)
7665 #define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
7666 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
7667 #define USART_ISR_TEACK_Pos          (21U)
7668 #define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
7669 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
7670 #define USART_ISR_REACK_Pos          (22U)
7671 #define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
7672 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
7673 #define USART_ISR_TXFE_Pos           (23U)
7674 #define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
7675 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty Flag */
7676 #define USART_ISR_RXFF_Pos           (24U)
7677 #define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
7678 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full Flag */
7679 #define USART_ISR_TCBGT_Pos          (25U)
7680 #define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
7681 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time Completion Flag */
7682 #define USART_ISR_RXFT_Pos           (26U)
7683 #define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
7684 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO Threshold Flag */
7685 #define USART_ISR_TXFT_Pos           (27U)
7686 #define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
7687 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO Threshold Flag */
7688 
7689 /*******************  Bit definition for USART_ICR register  ******************/
7690 #define USART_ICR_PECF_Pos           (0U)
7691 #define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
7692 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
7693 #define USART_ICR_FECF_Pos           (1U)
7694 #define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
7695 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
7696 #define USART_ICR_NECF_Pos           (2U)
7697 #define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
7698 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise Error detected Clear Flag */
7699 #define USART_ICR_ORECF_Pos          (3U)
7700 #define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
7701 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
7702 #define USART_ICR_IDLECF_Pos         (4U)
7703 #define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
7704 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
7705 #define USART_ICR_TXFECF_Pos         (5U)
7706 #define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
7707 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO Empty Clear Flag */
7708 #define USART_ICR_TCCF_Pos           (6U)
7709 #define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
7710 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
7711 #define USART_ICR_TCBGTCF_Pos        (7U)
7712 #define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
7713 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
7714 #define USART_ICR_LBDCF_Pos          (8U)
7715 #define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
7716 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
7717 #define USART_ICR_CTSCF_Pos          (9U)
7718 #define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
7719 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
7720 #define USART_ICR_RTOCF_Pos          (11U)
7721 #define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
7722 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
7723 #define USART_ICR_EOBCF_Pos          (12U)
7724 #define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
7725 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
7726 #define USART_ICR_UDRCF_Pos          (13U)
7727 #define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
7728 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
7729 #define USART_ICR_CMCF_Pos           (17U)
7730 #define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
7731 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
7732 #define USART_ICR_WUCF_Pos           (20U)
7733 #define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
7734 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
7735 
7736 /*******************  Bit definition for USART_RDR register  ******************/
7737 #define USART_RDR_RDR_Pos             (0U)
7738 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
7739 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
7740 
7741 /*******************  Bit definition for USART_TDR register  ******************/
7742 #define USART_TDR_TDR_Pos             (0U)
7743 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
7744 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
7745 
7746 /*******************  Bit definition for USART_PRESC register  ****************/
7747 #define USART_PRESC_PRESCALER_Pos    (0U)
7748 #define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
7749 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
7750 #define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
7751 #define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
7752 #define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
7753 #define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
7754 
7755 /******************************************************************************/
7756 /*                                                                            */
7757 /*                                 VREFBUF                                    */
7758 /*                                                                            */
7759 /******************************************************************************/
7760 /*******************  Bit definition for VREFBUF_CSR register  ****************/
7761 #define VREFBUF_CSR_ENVR_Pos    (0U)
7762 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
7763 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
7764 #define VREFBUF_CSR_HIZ_Pos     (1U)
7765 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
7766 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
7767 #define VREFBUF_CSR_VRS_Pos     (2U)
7768 #define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
7769 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
7770 #define VREFBUF_CSR_VRR_Pos     (3U)
7771 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
7772 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
7773 
7774 /*******************  Bit definition for VREFBUF_CCR register  ******************/
7775 #define VREFBUF_CCR_TRIM_Pos    (0U)
7776 #define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
7777 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
7778 
7779 /******************************************************************************/
7780 /*                                                                            */
7781 /*                            Window WATCHDOG                                 */
7782 /*                                                                            */
7783 /******************************************************************************/
7784 /*******************  Bit definition for WWDG_CR register  ********************/
7785 #define WWDG_CR_T_Pos           (0U)
7786 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
7787 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
7788 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
7789 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
7790 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
7791 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
7792 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
7793 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
7794 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
7795 
7796 #define WWDG_CR_WDGA_Pos        (7U)
7797 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
7798 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
7799 
7800 /*******************  Bit definition for WWDG_CFR register  *******************/
7801 #define WWDG_CFR_W_Pos          (0U)
7802 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
7803 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
7804 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
7805 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
7806 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
7807 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
7808 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
7809 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
7810 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
7811 
7812 #define WWDG_CFR_WDGTB_Pos      (11U)
7813 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
7814 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
7815 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
7816 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
7817 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
7818 
7819 #define WWDG_CFR_EWI_Pos        (9U)
7820 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
7821 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
7822 
7823 /*******************  Bit definition for WWDG_SR register  ********************/
7824 #define WWDG_SR_EWIF_Pos        (0U)
7825 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
7826 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
7827 
7828 /******************************************************************************/
7829 /*                                                                            */
7830 /*                                Debug MCU                                   */
7831 /*                                                                            */
7832 /******************************************************************************/
7833 /********************  Bit definition for DBG_IDCODE register  *************/
7834 #define DBG_IDCODE_DEV_ID_Pos                          (0U)
7835 #define DBG_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBG_IDCODE_DEV_ID_Pos)  /*!< 0x00000FFF */
7836 #define DBG_IDCODE_DEV_ID                              DBG_IDCODE_DEV_ID_Msk
7837 #define DBG_IDCODE_REV_ID_Pos                          (16U)
7838 #define DBG_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
7839 #define DBG_IDCODE_REV_ID                              DBG_IDCODE_REV_ID_Msk
7840 
7841 /********************  Bit definition for DBG_CR register  *****************/
7842 #define DBG_CR_DBG_STOP_Pos                            (1U)
7843 #define DBG_CR_DBG_STOP_Msk                            (0x1UL << DBG_CR_DBG_STOP_Pos)      /*!< 0x00000002 */
7844 #define DBG_CR_DBG_STOP                                DBG_CR_DBG_STOP_Msk
7845 #define DBG_CR_DBG_STANDBY_Pos                         (2U)
7846 #define DBG_CR_DBG_STANDBY_Msk                         (0x1UL << DBG_CR_DBG_STANDBY_Pos)   /*!< 0x00000004 */
7847 #define DBG_CR_DBG_STANDBY                             DBG_CR_DBG_STANDBY_Msk
7848 
7849 
7850 /********************  Bit definition for DBG_APB_FZ1 register  ***********/
7851 #define DBG_APB_FZ1_DBG_TIM2_STOP_Pos                  (0U)
7852 #define DBG_APB_FZ1_DBG_TIM2_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
7853 #define DBG_APB_FZ1_DBG_TIM2_STOP                      DBG_APB_FZ1_DBG_TIM2_STOP_Msk
7854 #define DBG_APB_FZ1_DBG_TIM3_STOP_Pos                  (1U)
7855 #define DBG_APB_FZ1_DBG_TIM3_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
7856 #define DBG_APB_FZ1_DBG_TIM3_STOP                      DBG_APB_FZ1_DBG_TIM3_STOP_Msk
7857 #define DBG_APB_FZ1_DBG_RTC_STOP_Pos                   (10U)
7858 #define DBG_APB_FZ1_DBG_RTC_STOP_Msk                   (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos)  /*!< 0x00000400 */
7859 #define DBG_APB_FZ1_DBG_RTC_STOP                       DBG_APB_FZ1_DBG_RTC_STOP_Msk
7860 #define DBG_APB_FZ1_DBG_WWDG_STOP_Pos                  (11U)
7861 #define DBG_APB_FZ1_DBG_WWDG_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
7862 #define DBG_APB_FZ1_DBG_WWDG_STOP                      DBG_APB_FZ1_DBG_WWDG_STOP_Msk
7863 #define DBG_APB_FZ1_DBG_IWDG_STOP_Pos                  (12U)
7864 #define DBG_APB_FZ1_DBG_IWDG_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
7865 #define DBG_APB_FZ1_DBG_IWDG_STOP                      DBG_APB_FZ1_DBG_IWDG_STOP_Msk
7866 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos    (21U)
7867 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk    (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */
7868 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP        DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk
7869 #define DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos                (30U)
7870 #define DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk                (0x1UL << DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x40000000 */
7871 #define DBG_APB_FZ1_DBG_LPTIM2_STOP                    DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk
7872 #define DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos                (31U)
7873 #define DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk                (0x1UL << DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
7874 #define DBG_APB_FZ1_DBG_LPTIM1_STOP                    DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk
7875 
7876 /********************  Bit definition for DBG_APB_FZ2 register  ************/
7877 #define DBG_APB_FZ2_DBG_TIM1_STOP_Pos                  (11U)
7878 #define DBG_APB_FZ2_DBG_TIM1_STOP_Msk                  (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos)  /*!< 0x00000800 */
7879 #define DBG_APB_FZ2_DBG_TIM1_STOP                      DBG_APB_FZ2_DBG_TIM1_STOP_Msk
7880 #define DBG_APB_FZ2_DBG_TIM14_STOP_Pos                 (15U)
7881 #define DBG_APB_FZ2_DBG_TIM14_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
7882 #define DBG_APB_FZ2_DBG_TIM14_STOP                     DBG_APB_FZ2_DBG_TIM14_STOP_Msk
7883 #define DBG_APB_FZ2_DBG_TIM16_STOP_Pos                 (17U)
7884 #define DBG_APB_FZ2_DBG_TIM16_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
7885 #define DBG_APB_FZ2_DBG_TIM16_STOP                     DBG_APB_FZ2_DBG_TIM16_STOP_Msk
7886 #define DBG_APB_FZ2_DBG_TIM17_STOP_Pos                 (18U)
7887 #define DBG_APB_FZ2_DBG_TIM17_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
7888 #define DBG_APB_FZ2_DBG_TIM17_STOP                     DBG_APB_FZ2_DBG_TIM17_STOP_Msk
7889 
7890 
7891 /** @addtogroup Exported_macros
7892   * @{
7893   */
7894 
7895 /******************************* ADC Instances ********************************/
7896 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
7897 
7898 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
7899 
7900 /******************************* AES Instances ********************************/
7901 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
7902 
7903 
7904 
7905 /******************************* CRC Instances ********************************/
7906 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
7907 
7908 
7909 /******************************** DMA Instances *******************************/
7910 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
7911                                        ((INSTANCE) == DMA1_Channel2) || \
7912                                        ((INSTANCE) == DMA1_Channel3) || \
7913                                        ((INSTANCE) == DMA1_Channel4) || \
7914                                        ((INSTANCE) == DMA1_Channel5))
7915 /******************************** DMAMUX Instances ****************************/
7916 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
7917 
7918 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
7919                                                       ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
7920                                                       ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
7921                                                       ((INSTANCE) == DMAMUX1_RequestGenerator3))
7922 
7923 /******************************* GPIO Instances *******************************/
7924 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7925                                         ((INSTANCE) == GPIOB) || \
7926                                         ((INSTANCE) == GPIOC) || \
7927                                         ((INSTANCE) == GPIOD) || \
7928                                         ((INSTANCE) == GPIOF))
7929 /******************************* GPIO AF Instances ****************************/
7930 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
7931 
7932 /**************************** GPIO Lock Instances *****************************/
7933 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
7934                                          ((INSTANCE) == GPIOB) || \
7935                                          ((INSTANCE) == GPIOC))
7936 
7937 /******************************** I2C Instances *******************************/
7938 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
7939                                        ((INSTANCE) == I2C2))
7940 
7941 /******************************* RNG Instances ********************************/
7942 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
7943 
7944 /****************************** RTC Instances *********************************/
7945 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
7946 
7947 /****************************** SMBUS Instances *******************************/
7948 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
7949 
7950 /****************************** WAKEUP_FROMSTOP Instances *******************************/
7951 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
7952 
7953 /******************************** SPI Instances *******************************/
7954 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
7955                                        ((INSTANCE) == SPI2))
7956 
7957 /******************************** SPI Instances *******************************/
7958 #define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI1)
7959 
7960 /****************** LPTIM Instances : All supported instances *****************/
7961 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
7962                                          ((INSTANCE) == LPTIM2))
7963 
7964 /****************** LPTIM Instances : All supported instances *****************/
7965 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
7966 
7967 /****************** TIM Instances : All supported instances *******************/
7968 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
7969                                          ((INSTANCE) == TIM2)   || \
7970                                          ((INSTANCE) == TIM3)   || \
7971                                          ((INSTANCE) == TIM14)  || \
7972                                          ((INSTANCE) == TIM16)  || \
7973                                          ((INSTANCE) == TIM17))
7974 
7975 /****************** TIM Instances : supporting 32 bits counter ****************/
7976 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
7977 
7978 /****************** TIM Instances : supporting the break function *************/
7979 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
7980                                             ((INSTANCE) == TIM16)   || \
7981                                             ((INSTANCE) == TIM17))
7982 
7983 /************** TIM Instances : supporting Break source selection *************/
7984 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
7985                                                ((INSTANCE) == TIM16)  || \
7986                                                ((INSTANCE) == TIM17))
7987 
7988 /****************** TIM Instances : supporting 2 break inputs *****************/
7989 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
7990 
7991 /************* TIM Instances : at least 1 capture/compare channel *************/
7992 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
7993                                          ((INSTANCE) == TIM2)   || \
7994                                          ((INSTANCE) == TIM3)   || \
7995                                          ((INSTANCE) == TIM14)  || \
7996                                          ((INSTANCE) == TIM16)  || \
7997                                          ((INSTANCE) == TIM17))
7998 
7999 /************ TIM Instances : at least 2 capture/compare channels *************/
8000 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8001                                          ((INSTANCE) == TIM2)   || \
8002                                          ((INSTANCE) == TIM3))
8003 
8004 /************ TIM Instances : at least 3 capture/compare channels *************/
8005 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8006                                          ((INSTANCE) == TIM2)   || \
8007                                          ((INSTANCE) == TIM3))
8008 
8009 /************ TIM Instances : at least 4 capture/compare channels *************/
8010 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8011                                          ((INSTANCE) == TIM2)   || \
8012                                          ((INSTANCE) == TIM3))
8013 
8014 /****************** TIM Instances : at least 5 capture/compare channels *******/
8015 #define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
8016 
8017 /****************** TIM Instances : at least 6 capture/compare channels *******/
8018 #define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
8019 
8020 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
8021 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
8022                                             ((INSTANCE) == TIM16)  || \
8023                                             ((INSTANCE) == TIM17))
8024 
8025 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
8026 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
8027                                             ((INSTANCE) == TIM2)   || \
8028                                             ((INSTANCE) == TIM3)   || \
8029                                             ((INSTANCE) == TIM16)  || \
8030                                             ((INSTANCE) == TIM17))
8031 
8032 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
8033 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8034                                             ((INSTANCE) == TIM2)   || \
8035                                             ((INSTANCE) == TIM3)   || \
8036                                             ((INSTANCE) == TIM14)  || \
8037                                             ((INSTANCE) == TIM16)  || \
8038                                             ((INSTANCE) == TIM17))
8039 
8040 /******************** TIM Instances : DMA burst feature ***********************/
8041 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
8042                                             ((INSTANCE) == TIM2)   || \
8043                                             ((INSTANCE) == TIM3)   || \
8044                                             ((INSTANCE) == TIM16)  || \
8045                                             ((INSTANCE) == TIM17))
8046 
8047 /******************* TIM Instances : output(s) available **********************/
8048 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8049     ((((INSTANCE) == TIM1) &&                  \
8050      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8051       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8052       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8053       ((CHANNEL) == TIM_CHANNEL_4) ||          \
8054       ((CHANNEL) == TIM_CHANNEL_5) ||          \
8055       ((CHANNEL) == TIM_CHANNEL_6)))           \
8056      ||                                        \
8057      (((INSTANCE) == TIM2) &&                  \
8058      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8059       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8060       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8061       ((CHANNEL) == TIM_CHANNEL_4)))           \
8062      ||                                        \
8063      (((INSTANCE) == TIM3) &&                  \
8064      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8065       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8066       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8067       ((CHANNEL) == TIM_CHANNEL_4)))           \
8068      ||                                        \
8069      (((INSTANCE) == TIM14) &&                 \
8070      (((CHANNEL) == TIM_CHANNEL_1)))           \
8071      ||                                        \
8072      (((INSTANCE) == TIM16) &&                 \
8073      (((CHANNEL) == TIM_CHANNEL_1)))           \
8074      ||                                        \
8075      (((INSTANCE) == TIM17) &&                 \
8076       (((CHANNEL) == TIM_CHANNEL_1))))
8077 
8078 /****************** TIM Instances : supporting complementary output(s) ********/
8079 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8080    ((((INSTANCE) == TIM1) &&                    \
8081      (((CHANNEL) == TIM_CHANNEL_1) ||           \
8082       ((CHANNEL) == TIM_CHANNEL_2) ||           \
8083       ((CHANNEL) == TIM_CHANNEL_3)))            \
8084     ||                                          \
8085     (((INSTANCE) == TIM16) &&                   \
8086      ((CHANNEL) == TIM_CHANNEL_1))              \
8087     ||                                          \
8088     (((INSTANCE) == TIM17) &&                   \
8089      ((CHANNEL) == TIM_CHANNEL_1)))
8090 
8091 /****************** TIM Instances : supporting clock division *****************/
8092 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
8093                                                     ((INSTANCE) == TIM2)    || \
8094                                                     ((INSTANCE) == TIM3)    || \
8095                                                     ((INSTANCE) == TIM14)   || \
8096                                                     ((INSTANCE) == TIM16)   || \
8097                                                     ((INSTANCE) == TIM17))
8098 
8099 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
8100 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8101                                                         ((INSTANCE) == TIM2) || \
8102                                                         ((INSTANCE) == TIM3))
8103 
8104 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
8105 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8106                                                         ((INSTANCE) == TIM2) || \
8107                                                         ((INSTANCE) == TIM3))
8108 
8109 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
8110 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
8111                                                         ((INSTANCE) == TIM2) || \
8112                                                         ((INSTANCE) == TIM3))
8113 
8114 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
8115 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
8116                                                         ((INSTANCE) == TIM2) || \
8117                                                         ((INSTANCE) == TIM3))
8118 
8119 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
8120 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
8121 
8122 /****************** TIM Instances : supporting commutation event generation ***/
8123 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
8124                                                      ((INSTANCE) == TIM16)  || \
8125                                                      ((INSTANCE) == TIM17))
8126 
8127 /****************** TIM Instances : supporting counting mode selection ********/
8128 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
8129                                                         ((INSTANCE) == TIM2) || \
8130                                                         ((INSTANCE) == TIM3))
8131 
8132 /****************** TIM Instances : supporting encoder interface **************/
8133 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
8134                                                       ((INSTANCE) == TIM2)  || \
8135                                                       ((INSTANCE) == TIM3))
8136 
8137 /****************** TIM Instances : supporting Hall sensor interface **********/
8138 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
8139                                                          ((INSTANCE) == TIM2)   || \
8140                                                          ((INSTANCE) == TIM3))
8141 
8142 /**************** TIM Instances : external trigger input available ************/
8143 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
8144                                             ((INSTANCE) == TIM2)  || \
8145                                             ((INSTANCE) == TIM3))
8146 
8147 /************* TIM Instances : supporting ETR source selection ***************/
8148 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
8149                                              ((INSTANCE) == TIM2)  || \
8150                                              ((INSTANCE) == TIM3))
8151 
8152 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
8153 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
8154                                             ((INSTANCE) == TIM2)  || \
8155                                             ((INSTANCE) == TIM3))
8156 
8157 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8158 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
8159                                             ((INSTANCE) == TIM2)  || \
8160                                             ((INSTANCE) == TIM3))
8161 
8162 /****************** TIM Instances : supporting OCxREF clear *******************/
8163 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
8164                                                        ((INSTANCE) == TIM2) || \
8165                                                        ((INSTANCE) == TIM3))
8166 
8167 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
8168 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
8169                                                        ((INSTANCE) == TIM2)  || \
8170                                                        ((INSTANCE) == TIM3))
8171 
8172 /****************** TIM Instances : remapping capability **********************/
8173 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
8174                                             ((INSTANCE) == TIM2)  || \
8175                                             ((INSTANCE) == TIM3))
8176 
8177 /****************** TIM Instances : supporting repetition counter *************/
8178 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
8179                                                        ((INSTANCE) == TIM16) || \
8180                                                        ((INSTANCE) == TIM17))
8181 
8182 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
8183 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
8184 
8185 /******************* TIM Instances : Timer input XOR function *****************/
8186 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
8187                                             ((INSTANCE) == TIM2)   || \
8188                                             ((INSTANCE) == TIM3))
8189 
8190 /******************* TIM Instances : Timer input selection ********************/
8191 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
8192                                          ((INSTANCE) == TIM2)   || \
8193                                          ((INSTANCE) == TIM3)   || \
8194                                          ((INSTANCE) == TIM14)  || \
8195                                          ((INSTANCE) == TIM16)  || \
8196                                          ((INSTANCE) == TIM17))
8197 
8198 /************ TIM Instances : Advanced timers  ********************************/
8199 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
8200 
8201 /******************** UART Instances : Asynchronous mode **********************/
8202 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8203                                     ((INSTANCE) == USART2))
8204 
8205 /******************** USART Instances : Synchronous mode **********************/
8206 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8207                                      ((INSTANCE) == USART2))
8208 /****************** UART Instances : Hardware Flow control ********************/
8209 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8210                                            ((INSTANCE) == USART2) || \
8211                                            ((INSTANCE) == LPUART1))
8212 
8213 /********************* USART Instances : Smard card mode ***********************/
8214 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
8215 /****************** UART Instances : Auto Baud Rate detection ****************/
8216 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
8217 /******************** UART Instances : Half-Duplex mode **********************/
8218 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
8219                                                  ((INSTANCE) == USART2) || \
8220                                                  ((INSTANCE) == LPUART1))
8221 
8222 /******************** UART Instances : LIN mode **********************/
8223 #define IS_UART_LIN_INSTANCE(INSTANCE)   ((INSTANCE) == USART1)
8224 /******************** UART Instances : Wake-up from Stop mode **********************/
8225 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
8226                                                       ((INSTANCE) == LPUART1))
8227 
8228 /****************** UART Instances : Driver Enable *****************/
8229 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
8230                                                       ((INSTANCE) == USART2) || \
8231                                                       ((INSTANCE) == LPUART1))
8232 
8233 /****************** UART Instances : SPI Slave selection mode ***************/
8234 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8235                                               ((INSTANCE) == USART2))
8236 
8237 /****************** UART Instances : Driver Enable *****************/
8238 #define IS_UART_FIFO_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
8239                                              ((INSTANCE) == LPUART1))
8240 
8241 /*********************** UART Instances : IRDA mode ***************************/
8242 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
8243 
8244 /******************** LPUART Instance *****************************************/
8245 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
8246 
8247 /****************************** IWDG Instances ********************************/
8248 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
8249 
8250 /****************************** WWDG Instances ********************************/
8251 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
8252 
8253 
8254 /******************************************************************************/
8255 /*  For a painless codes migration between the STM32G0xx device product       */
8256 /*  lines, the aliases defined below are put in place to overcome the         */
8257 /*  differences in the interrupt handlers and IRQn definitions.               */
8258 /*  No need to update developed interrupt code when moving across             */
8259 /*  product lines within the same STM32G0 Family                              */
8260 /******************************************************************************/
8261 /* Aliases for IRQn_Type */
8262 #define SVC_IRQn              SVCall_IRQn
8263 
8264 /**
8265   * @}
8266   */
8267 
8268  /**
8269   * @}
8270   */
8271 
8272 /**
8273   * @}
8274   */
8275 
8276 #ifdef __cplusplus
8277 }
8278 #endif /* __cplusplus */
8279 
8280 #endif /* STM32G041xx_H */
8281 
8282 /**
8283   * @}
8284   */
8285 
8286   /**
8287   * @}
8288   */
8289