1/*
2 * Copyright (c) 2018 Seitz & Associates
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f3/stm32f3.dtsi>
8#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
9
10/ {
11	soc {
12		compatible = "st,stm32f302", "st,stm32f3", "simple-bus";
13
14		usb: usb@40005c00 {
15			/* Remap USB_LP IRQ to enable use with CAN_1 */
16			interrupts = <75 0>;
17		};
18
19		i2c2: i2c@40005800 {
20			compatible = "st,stm32-i2c-v2";
21			clock-frequency = <I2C_BITRATE_STANDARD>;
22			#address-cells = <1>;
23			#size-cells = <0>;
24			reg = <0x40005800 0x400>;
25			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
26				 /* I2C clock source should always be defined,
27				  * even for the default value
28				  */
29				 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
30			interrupts = <33 0>, <34 0>;
31			interrupt-names = "event", "error";
32			status = "disabled";
33		};
34
35		i2c3: i2c@40007800 {
36			compatible = "st,stm32-i2c-v2";
37			clock-frequency = <I2C_BITRATE_STANDARD>;
38			#address-cells = <1>;
39			#size-cells = <0>;
40			reg = <0x40007800 0x400>;
41			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>,
42				 /* I2C clock source should always be defined,
43				  * even for the default value
44				  */
45				 <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>;
46			interrupts = <72 0>, <73 0>;
47			interrupt-names = "event", "error";
48			status = "disabled";
49		};
50
51		spi2: spi@40003800 {
52			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
53			#address-cells = <1>;
54			#size-cells = <0>;
55			reg = <0x40003800 0x400>;
56			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
57			interrupts = <36 5>;
58			status = "disabled";
59		};
60
61		spi3: spi@40003c00 {
62			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
63			#address-cells = <1>;
64			#size-cells = <0>;
65			reg = <0X40003c00 0x400>;
66			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
67			interrupts = <51 5>;
68			status = "disabled";
69		};
70
71		timers1: timers@40012c00 {
72			compatible = "st,stm32-timers";
73			reg = <0x40012c00 0x400>;
74			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
75			resets = <&rctl STM32_RESET(APB2, 11U)>;
76			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
77			interrupt-names = "brk", "up", "trgcom", "cc";
78			st,prescaler = <0>;
79			status = "disabled";
80
81			pwm {
82				compatible = "st,stm32-pwm";
83				status = "disabled";
84				#pwm-cells = <3>;
85			};
86		};
87
88		timers4: timers@40000800 {
89			compatible = "st,stm32-timers";
90			reg = <0x40000800 0x400>;
91			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
92			resets = <&rctl STM32_RESET(APB1, 2U)>;
93			interrupts = <30 0>;
94			interrupt-names = "global";
95			st,prescaler = <0>;
96			status = "disabled";
97
98			pwm {
99				compatible = "st,stm32-pwm";
100				status = "disabled";
101				#pwm-cells = <3>;
102			};
103		};
104
105		adc1: adc@50000000 {
106			compatible = "st,stm32-adc";
107			reg = <0x50000000 0x400>;
108			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
109			interrupts = <18 0>;
110			status = "disabled";
111			#io-channel-cells = <1>;
112			resolutions = <STM32_ADC_RES(12, 0x00)
113				       STM32_ADC_RES(10, 0x01)
114				       STM32_ADC_RES(8, 0x02)
115				       STM32_ADC_RES(6, 0x03)>;
116			sampling-times = <2 3 5 8 20 62 182 602>;
117			st,adc-sequencer = <FULLY_CONFIGURABLE>;
118		};
119	};
120};
121