1 /**
2   ******************************************************************************
3   * @file    stm32f217xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32F217xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains :
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripherals registers declarations and bits definition
10   *           - Macros to access peripheral�s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
16   * All rights reserved.</center></h2>
17   *
18   * This software component is licensed by ST under BSD 3-Clause license,
19   * the "License"; You may not use this file except in compliance with the
20   * License. You may obtain a copy of the License at:
21   *                        opensource.org/licenses/BSD-3-Clause
22   *
23   ******************************************************************************
24   */
25 
26 /** @addtogroup CMSIS_Device
27   * @{
28   */
29 
30 /** @addtogroup stm32f217xx
31   * @{
32   */
33 
34 #ifndef __STM32F217xx_H
35 #define __STM32F217xx_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
41 /** @addtogroup Configuration_section_for_CMSIS
42   * @{
43   */
44 
45 /**
46   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
47   */
48 #define __CM3_REV                 0x0200U  /*!< Core revision r0p1                            */
49 #define __MPU_PRESENT             1U       /*!< STM32F2XX provides an MPU                     */
50 #define __NVIC_PRIO_BITS          4U       /*!< STM32F2XX uses 4 Bits for the Priority Levels */
51 #define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
52 
53 /**
54   * @}
55   */
56 
57 /** @addtogroup Peripheral_interrupt_number_definition
58   * @{
59   */
60 
61 /**
62  * @brief STM32F2XX Interrupt Number Definition, according to the selected device
63  *        in @ref Library_configuration_section
64  */
65 typedef enum
66 {
67 /******  Cortex-M3 Processor Exceptions Numbers ****************************************************************/
68   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
69   HardFault_IRQn              = -13,    /*!< 3 Hard Fault Interrupt                                            */
70   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                           */
71   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                                   */
72   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                                 */
73   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                                    */
74   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                              */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                                    */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                                */
77 /******  STM32 specific Interrupt Numbers **********************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
80   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
81   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
82   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
83   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
84   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
85   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
86   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
87   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
88   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
89   DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
90   DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
91   DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
92   DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
93   DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
94   DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
95   DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
96   ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
97   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
98   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
99   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
100   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
101   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
102   TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
103   TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
104   TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
105   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
106   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
107   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
108   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
109   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
110   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
111   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
112   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
113   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
114   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
117   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
118   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
119   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
120   OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
121   TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
122   TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
123   TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
124   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
125   DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
126   FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
127   SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
128   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
129   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
130   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
131   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
132   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
133   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
134   DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
135   DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
136   DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
137   DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
138   DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
139   ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
140   ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
141   CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
142   CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
143   CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
144   CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
145   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
146   DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
147   DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
148   DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
149   USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
150   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
151   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
152   OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
153   OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
154   OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
155   OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
156   DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
157   CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
158   HASH_RNG_IRQn               = 80      /*!< Hash and Rng global interrupt                                     */
159 } IRQn_Type;
160 
161 /**
162   * @}
163   */
164 
165 #include "core_cm3.h"
166 #include "system_stm32f2xx.h"
167 #include <stdint.h>
168 
169 /** @addtogroup Peripheral_registers_structures
170   * @{
171   */
172 
173 /**
174   * @brief Analog to Digital Converter
175   */
176 
177 typedef struct
178 {
179   __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
180   __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
181   __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
182   __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
183   __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
184   __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
185   __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
186   __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
187   __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
188   __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
189   __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
190   __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
191   __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
192   __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
193   __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38 */
194   __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
195   __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
196   __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
197   __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
198   __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
199 } ADC_TypeDef;
200 
201 typedef struct
202 {
203   __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
204   __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
205   __IO uint32_t CDR;    /*!< ADC common regular data register for dual
206                              AND triple modes,                            Address offset: ADC1 base address + 0x308 */
207 } ADC_Common_TypeDef;
208 
209 
210 /**
211   * @brief Controller Area Network TxMailBox
212   */
213 
214 typedef struct
215 {
216   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
217   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
218   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
219   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
220 } CAN_TxMailBox_TypeDef;
221 
222 /**
223   * @brief Controller Area Network FIFOMailBox
224   */
225 
226 typedef struct
227 {
228   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
229   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
230   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
231   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
232 } CAN_FIFOMailBox_TypeDef;
233 
234 /**
235   * @brief Controller Area Network FilterRegister
236   */
237 
238 typedef struct
239 {
240   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
241   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
242 } CAN_FilterRegister_TypeDef;
243 
244 /**
245   * @brief Controller Area Network
246   */
247 
248 typedef struct
249 {
250   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
251   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
252   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
253   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
254   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
255   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
256   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
257   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
258   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
259   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
260   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
261   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
262   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
263   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
264   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
265   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
266   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
267   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
268   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
269   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
270   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
271   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
272 } CAN_TypeDef;
273 
274 /**
275   * @brief CRC calculation unit
276   */
277 
278 typedef struct
279 {
280   __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
281   __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
282   uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
283   uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
284   __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
285 } CRC_TypeDef;
286 
287 /**
288   * @brief Digital to Analog Converter
289   */
290 
291 typedef struct
292 {
293   __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
294   __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
295   __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
296   __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
297   __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
298   __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
299   __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
300   __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
301   __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
302   __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
303   __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
304   __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
305   __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
306   __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
307 } DAC_TypeDef;
308 
309 /**
310   * @brief Debug MCU
311   */
312 
313 typedef struct
314 {
315   __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
316   __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
317   __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
318   __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
319 }DBGMCU_TypeDef;
320 
321 /**
322   * @brief DCMI
323   */
324 
325 typedef struct
326 {
327   __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
328   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
329   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
330   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
331   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
332   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
333   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
334   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
335   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
336   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
337   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
338 } DCMI_TypeDef;
339 
340 /**
341   * @brief DMA Controller
342   */
343 
344 typedef struct
345 {
346   __IO uint32_t CR;     /*!< DMA stream x configuration register      */
347   __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
348   __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
349   __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
350   __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
351   __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
352 } DMA_Stream_TypeDef;
353 
354 typedef struct
355 {
356   __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
357   __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
358   __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
359   __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
360 } DMA_TypeDef;
361 
362 
363 /**
364   * @brief Ethernet MAC
365   */
366 
367 typedef struct
368 {
369   __IO uint32_t MACCR;
370   __IO uint32_t MACFFR;
371   __IO uint32_t MACHTHR;
372   __IO uint32_t MACHTLR;
373   __IO uint32_t MACMIIAR;
374   __IO uint32_t MACMIIDR;
375   __IO uint32_t MACFCR;
376   __IO uint32_t MACVLANTR;             /*    8 */
377   uint32_t      RESERVED0[2];
378   __IO uint32_t MACRWUFFR;             /*   11 */
379   __IO uint32_t MACPMTCSR;
380   uint32_t      RESERVED1;
381   __IO uint32_t MACDBGR;
382   __IO uint32_t MACSR;                 /*   15 */
383   __IO uint32_t MACIMR;
384   __IO uint32_t MACA0HR;
385   __IO uint32_t MACA0LR;
386   __IO uint32_t MACA1HR;
387   __IO uint32_t MACA1LR;
388   __IO uint32_t MACA2HR;
389   __IO uint32_t MACA2LR;
390   __IO uint32_t MACA3HR;
391   __IO uint32_t MACA3LR;               /*   24 */
392   uint32_t      RESERVED2[40];
393   __IO uint32_t MMCCR;                 /*   65 */
394   __IO uint32_t MMCRIR;
395   __IO uint32_t MMCTIR;
396   __IO uint32_t MMCRIMR;
397   __IO uint32_t MMCTIMR;               /*   69 */
398   uint32_t      RESERVED3[14];
399   __IO uint32_t MMCTGFSCCR;            /*   84 */
400   __IO uint32_t MMCTGFMSCCR;
401   uint32_t      RESERVED4[5];
402   __IO uint32_t MMCTGFCR;
403   uint32_t      RESERVED5[10];
404   __IO uint32_t MMCRFCECR;
405   __IO uint32_t MMCRFAECR;
406   uint32_t      RESERVED6[10];
407   __IO uint32_t MMCRGUFCR;
408   uint32_t      RESERVED7[334];
409   __IO uint32_t PTPTSCR;
410   __IO uint32_t PTPSSIR;
411   __IO uint32_t PTPTSHR;
412   __IO uint32_t PTPTSLR;
413   __IO uint32_t PTPTSHUR;
414   __IO uint32_t PTPTSLUR;
415   __IO uint32_t PTPTSAR;
416   __IO uint32_t PTPTTHR;
417   __IO uint32_t PTPTTLR;
418   __IO uint32_t RESERVED8;
419   __IO uint32_t PTPTSSR;
420   uint32_t      RESERVED9[565];
421   __IO uint32_t DMABMR;
422   __IO uint32_t DMATPDR;
423   __IO uint32_t DMARPDR;
424   __IO uint32_t DMARDLAR;
425   __IO uint32_t DMATDLAR;
426   __IO uint32_t DMASR;
427   __IO uint32_t DMAOMR;
428   __IO uint32_t DMAIER;
429   __IO uint32_t DMAMFBOCR;
430   __IO uint32_t DMARSWTR;
431   uint32_t      RESERVED10[8];
432   __IO uint32_t DMACHTDR;
433   __IO uint32_t DMACHRDR;
434   __IO uint32_t DMACHTBAR;
435   __IO uint32_t DMACHRBAR;
436 } ETH_TypeDef;
437 
438 /**
439   * @brief External Interrupt/Event Controller
440   */
441 
442 typedef struct
443 {
444   __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
445   __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
446   __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
447   __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
448   __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
449   __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
450 } EXTI_TypeDef;
451 
452 /**
453   * @brief FLASH Registers
454   */
455 
456 typedef struct
457 {
458   __IO uint32_t ACR;      /*!< FLASH access control register, Address offset: 0x00 */
459   __IO uint32_t KEYR;     /*!< FLASH key register,            Address offset: 0x04 */
460   __IO uint32_t OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */
461   __IO uint32_t SR;       /*!< FLASH status register,         Address offset: 0x0C */
462   __IO uint32_t CR;       /*!< FLASH control register,        Address offset: 0x10 */
463   __IO uint32_t OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */
464 } FLASH_TypeDef;
465 
466 
467 /**
468   * @brief Flexible Static Memory Controller
469   */
470 
471 typedef struct
472 {
473   __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
474 } FSMC_Bank1_TypeDef;
475 
476 /**
477   * @brief Flexible Static Memory Controller Bank1E
478   */
479 
480 typedef struct
481 {
482   __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
483 } FSMC_Bank1E_TypeDef;
484 
485 /**
486   * @brief Flexible Static Memory Controller Bank2
487   */
488 
489 typedef struct
490 {
491   __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
492   __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
493   __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
494   __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
495   uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
496   __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
497   uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
498   uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
499   __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
500   __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
501   __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
502   __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
503   uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
504   __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
505 } FSMC_Bank2_3_TypeDef;
506 
507 /**
508   * @brief Flexible Static Memory Controller Bank4
509   */
510 
511 typedef struct
512 {
513   __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
514   __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
515   __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
516   __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
517   __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
518 } FSMC_Bank4_TypeDef;
519 
520 
521 /**
522   * @brief General Purpose I/O
523   */
524 
525 typedef struct
526 {
527   __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
528   __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
529   __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
530   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
531   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
532   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
533   __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
534   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
535   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
536 } GPIO_TypeDef;
537 
538 /**
539   * @brief System configuration controller
540   */
541 
542 typedef struct
543 {
544   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
545   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
546   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
547   uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
548   __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
549 } SYSCFG_TypeDef;
550 
551 /**
552   * @brief Inter-integrated Circuit Interface
553   */
554 
555 typedef struct
556 {
557   __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
558   __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
559   __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
560   __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
561   __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
562   __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
563   __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
564   __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
565   __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
566 } I2C_TypeDef;
567 
568 /**
569   * @brief Independent WATCHDOG
570   */
571 
572 typedef struct
573 {
574   __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
575   __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
576   __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
577   __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
578 } IWDG_TypeDef;
579 
580 /**
581   * @brief Power Control
582   */
583 
584 typedef struct
585 {
586   __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
587   __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
588 } PWR_TypeDef;
589 
590 /**
591   * @brief Reset and Clock Control
592   */
593 
594 typedef struct
595 {
596   __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
597   __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
598   __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
599   __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
600   __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
601   __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
602   __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
603   uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
604   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
605   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
606   uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
607   __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
608   __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
609   __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
610   uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
611   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
612   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
613   uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
614   __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
615   __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
616   __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
617   uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
618   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
619   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
620   uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
621   __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
622   __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
623   uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
624   __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
625   __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
626 
627 } RCC_TypeDef;
628 
629 /**
630   * @brief Real-Time Clock
631   */
632 
633 typedef struct
634 {
635   __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
636   __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
637   __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
638   __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
639   __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
640   __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
641   __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
642   __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
643   __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
644   __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
645   uint32_t RESERVED1;    /*!< Reserved, 0x28                                                                 */
646   uint32_t RESERVED2;    /*!< Reserved, 0x2C                                                                 */
647   __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
648   __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
649   uint32_t RESERVED3;    /*!< Reserved, 0x38                                                                 */
650   uint32_t RESERVED4;    /*!< Reserved, 0x3C                                                                 */
651   __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
652   uint32_t RESERVED5;    /*!< Reserved, 0x44                                                                 */
653   uint32_t RESERVED6;    /*!< Reserved, 0x48                                                                 */
654   uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
655   __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
656   __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
657   __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
658   __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
659   __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
660   __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
661   __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
662   __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
663   __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
664   __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
665   __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
666   __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
667   __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
668   __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
669   __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
670   __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
671   __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
672   __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
673   __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
674   __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
675 } RTC_TypeDef;
676 
677 
678 /**
679   * @brief SD host Interface
680   */
681 
682 typedef struct
683 {
684   __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
685   __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
686   __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
687   __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
688   __IO const uint32_t  RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
689   __IO const uint32_t  RESP1;   /*!< SDIO response 1 register,       Address offset: 0x14 */
690   __IO const uint32_t  RESP2;   /*!< SDIO response 2 register,       Address offset: 0x18 */
691   __IO const uint32_t  RESP3;   /*!< SDIO response 3 register,       Address offset: 0x1C */
692   __IO const uint32_t  RESP4;   /*!< SDIO response 4 register,       Address offset: 0x20 */
693   __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
694   __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
695   __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
696   __IO const uint32_t  DCOUNT;  /*!< SDIO data counter register,     Address offset: 0x30 */
697   __IO const uint32_t  STA;     /*!< SDIO status register,           Address offset: 0x34 */
698   __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
699   __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
700   uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
701   __IO const uint32_t  FIFOCNT; /*!< SDIO FIFO counter register,     Address offset: 0x48 */
702   uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
703   __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
704 } SDIO_TypeDef;
705 
706 /**
707   * @brief Serial Peripheral Interface
708   */
709 
710 typedef struct
711 {
712   __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
713   __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
714   __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
715   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
716   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
717   __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
718   __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
719   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
720   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
721 } SPI_TypeDef;
722 
723 /**
724   * @brief TIM
725   */
726 
727 typedef struct
728 {
729   __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
730   __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
731   __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
732   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
733   __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
734   __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
735   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
736   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
737   __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
738   __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
739   __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
740   __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
741   __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
742   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
743   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
744   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
745   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
746   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
747   __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
748   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
749   __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
750 } TIM_TypeDef;
751 
752 /**
753   * @brief Universal Synchronous Asynchronous Receiver Transmitter
754   */
755 
756 typedef struct
757 {
758   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
759   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
760   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
761   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
762   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
763   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
764   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
765 } USART_TypeDef;
766 
767 /**
768   * @brief Window WATCHDOG
769   */
770 
771 typedef struct
772 {
773   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
774   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
775   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
776 } WWDG_TypeDef;
777 
778 
779 /**
780   * @brief Crypto Processor
781   */
782 
783 typedef struct
784 {
785   __IO uint32_t CR;     /*!< CRYP control register,                            Address offset: 0x00 */
786   __IO uint32_t SR;     /*!< CRYP status register,                             Address offset: 0x04 */
787   __IO uint32_t DIN;    /*!< CRYP data input register,                                 Address offset: 0x08 */
788   __IO uint32_t DOUT;   /*!< CRYP data output register,                        Address offset: 0x0C */
789   __IO uint32_t DMACR;  /*!< CRYP DMA control register,                        Address offset: 0x10 */
790   __IO uint32_t IMSCR;  /*!< CRYP interrupt mask set/clear register,           Address offset: 0x14 */
791   __IO uint32_t RISR;   /*!< CRYP raw interrupt status register,               Address offset: 0x18 */
792   __IO uint32_t MISR;   /*!< CRYP masked interrupt status register,            Address offset: 0x1C */
793   __IO uint32_t K0LR;   /*!< CRYP key left  register 0,                        Address offset: 0x20 */
794   __IO uint32_t K0RR;   /*!< CRYP key right register 0,                        Address offset: 0x24 */
795   __IO uint32_t K1LR;   /*!< CRYP key left  register 1,                        Address offset: 0x28 */
796   __IO uint32_t K1RR;   /*!< CRYP key right register 1,                        Address offset: 0x2C */
797   __IO uint32_t K2LR;   /*!< CRYP key left  register 2,                        Address offset: 0x30 */
798   __IO uint32_t K2RR;   /*!< CRYP key right register 2,                        Address offset: 0x34 */
799   __IO uint32_t K3LR;   /*!< CRYP key left  register 3,                        Address offset: 0x38 */
800   __IO uint32_t K3RR;   /*!< CRYP key right register 3,                        Address offset: 0x3C */
801   __IO uint32_t IV0LR;  /*!< CRYP initialization vector left-word  register 0, Address offset: 0x40 */
802   __IO uint32_t IV0RR;  /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
803   __IO uint32_t IV1LR;  /*!< CRYP initialization vector left-word  register 1, Address offset: 0x48 */
804   __IO uint32_t IV1RR;  /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
805 } CRYP_TypeDef;
806 
807 /**
808   * @brief HASH
809   */
810 
811 typedef struct
812 {
813   __IO uint32_t CR;        /*!< HASH control register,          Address offset: 0x00        */
814   __IO uint32_t DIN;       /*!< HASH data input register,       Address offset: 0x04        */
815   __IO uint32_t STR;       /*!< HASH start register,            Address offset: 0x08        */
816   __IO uint32_t HR[5];     /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
817   __IO uint32_t IMR;       /*!< HASH interrupt enable register, Address offset: 0x20        */
818   __IO uint32_t SR;        /*!< HASH status register,           Address offset: 0x24        */
819   uint32_t  RESERVED[52];  /*!< Reserved, 0x28-0xF4                                         */
820   __IO uint32_t CSR[51];   /*!< HASH context swap registers,    Address offset: 0x0F8-0x1C0 */
821 } HASH_TypeDef;
822 
823 /**
824   * @brief RNG
825   */
826 
827 typedef struct
828 {
829   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
830   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
831   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
832 } RNG_TypeDef;
833 
834 
835 
836 /**
837   * @brief __USB_OTG_Core_register
838   */
839 typedef struct
840 {
841   __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register    Address offset : 0x00      */
842   __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register             Address offset : 0x04      */
843   __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register        Address offset : 0x08      */
844   __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register        Address offset : 0x0C      */
845   __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                    Address offset : 0x10      */
846   __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                Address offset : 0x14      */
847   __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register           Address offset : 0x18      */
848   __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register            Address offset : 0x1C      */
849   __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register      Address offset : 0x20      */
850   __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                Address offset : 0x24      */
851   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28    */
852   __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg     Address offset : 0x2C      */
853   uint32_t Reserved30[2];             /* Reserved                                  Address offset : 0x30      */
854   __IO uint32_t GCCFG;                /*!<  General Purpose IO Register            Address offset : 0x38      */
855   __IO uint32_t CID;                  /*!< User ID Register                          Address offset : 0x3C      */
856   uint32_t  Reserved40[48];           /*!< Reserved                                  Address offset : 0x40-0xFF */
857   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg            Address offset : 0x100 */
858   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
859 }
860 USB_OTG_GlobalTypeDef;
861 
862 
863 
864 /**
865   * @brief __device_Registers
866   */
867 typedef struct
868 {
869   __IO uint32_t DCFG;         /*!< dev Configuration Register   Address offset : 0x800 */
870   __IO uint32_t DCTL;         /*!< dev Control Register         Address offset : 0x804 */
871   __IO uint32_t DSTS;         /*!< dev Status Register (RO)     Address offset : 0x808 */
872   uint32_t Reserved0C;        /*!< Reserved                     Address offset : 0x80C */
873   __IO uint32_t DIEPMSK;      /*!< dev IN Endpoint Mask        Address offset : 0x810 */
874   __IO uint32_t DOEPMSK;      /*!< dev OUT Endpoint Mask        Address offset : 0x814 */
875   __IO uint32_t DAINT;        /*!< dev All Endpoints Itr Reg    Address offset : 0x818 */
876   __IO uint32_t DAINTMSK;     /*!< dev All Endpoints Itr Mask   Address offset : 0x81C */
877   uint32_t  Reserved20;       /*!< Reserved                     Address offset : 0x820 */
878   uint32_t Reserved9;         /*!< Reserved                     Address offset : 0x824 */
879   __IO uint32_t DVBUSDIS;     /*!< dev VBUS discharge Register  Address offset : 0x828 */
880   __IO uint32_t DVBUSPULSE;   /*!< dev VBUS Pulse Register      Address offset : 0x82C */
881   __IO uint32_t DTHRCTL;      /*!< dev thr                      Address offset : 0x830 */
882   __IO uint32_t DIEPEMPMSK;   /*!< dev empty msk                Address offset : 0x834 */
883   __IO uint32_t DEACHINT;     /*!< dedicated EP interrupt       Address offset : 0x838 */
884   __IO uint32_t DEACHMSK;     /*!< dedicated EP msk             Address offset : 0x83C */
885   uint32_t Reserved40;        /*!< dedicated EP mask            Address offset : 0x840 */
886   __IO uint32_t DINEP1MSK;    /*!< dedicated EP mask            Address offset : 0x844 */
887   uint32_t  Reserved44[15];   /*!< Reserved                     Address offset : 0x844-0x87C */
888   __IO uint32_t DOUTEP1MSK;   /*!< dedicated EP msk             Address offset : 0x884 */
889 }
890 USB_OTG_DeviceTypeDef;
891 
892 
893 /**
894   * @brief __IN_Endpoint-Specific_Register
895   */
896 typedef struct
897 {
898   __IO uint32_t DIEPCTL;        /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h     */
899   uint32_t Reserved04;          /* Reserved                       900h + (ep_num * 20h) + 04h  */
900   __IO uint32_t DIEPINT;        /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h     */
901   uint32_t Reserved0C;          /* Reserved                       900h + (ep_num * 20h) + 0Ch  */
902   __IO uint32_t DIEPTSIZ;       /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h        */
903   __IO uint32_t DIEPDMA;        /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h  */
904   __IO uint32_t DTXFSTS;        /* IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h   */
905   uint32_t Reserved18;          /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
906 }
907 USB_OTG_INEndpointTypeDef;
908 
909 
910 /**
911   * @brief __OUT_Endpoint-Specific_Registers
912   */
913 typedef struct
914 {
915   __IO uint32_t DOEPCTL;       /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
916   uint32_t Reserved04;         /* Reserved                      B00h + (ep_num * 20h) + 04h*/
917   __IO uint32_t DOEPINT;       /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
918   uint32_t Reserved0C;         /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
919   __IO uint32_t DOEPTSIZ;      /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
920   __IO uint32_t DOEPDMA;       /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
921   uint32_t Reserved18[2];      /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
922 }
923 USB_OTG_OUTEndpointTypeDef;
924 
925 
926 /**
927   * @brief __Host_Mode_Register_Structures
928   */
929 typedef struct
930 {
931   __IO uint32_t HCFG;             /* Host Configuration Register    400h*/
932   __IO uint32_t HFIR;             /* Host Frame Interval Register   404h*/
933   __IO uint32_t HFNUM;            /* Host Frame Nbr/Frame Remaining 408h*/
934   uint32_t Reserved40C;           /* Reserved                       40Ch*/
935   __IO uint32_t HPTXSTS;          /* Host Periodic Tx FIFO/ Queue Status 410h*/
936   __IO uint32_t HAINT;            /* Host All Channels Interrupt Register 414h*/
937   __IO uint32_t HAINTMSK;         /* Host All Channels Interrupt Mask 418h*/
938 }
939 USB_OTG_HostTypeDef;
940 
941 
942 /**
943   * @brief __Host_Channel_Specific_Registers
944   */
945 typedef struct
946 {
947   __IO uint32_t HCCHAR;
948   __IO uint32_t HCSPLT;
949   __IO uint32_t HCINT;
950   __IO uint32_t HCINTMSK;
951   __IO uint32_t HCTSIZ;
952   __IO uint32_t HCDMA;
953   uint32_t Reserved[2];
954 }
955 USB_OTG_HostChannelTypeDef;
956 
957 
958 /**
959   * @brief Peripheral_memory_map
960   */
961 #define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
962 #define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                             */
963 #define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
964 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
965 #define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
966 #define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
967 #define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
968 #define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
969 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
970 #define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
971 #define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
972 #define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
973 #define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
974 
975 /* Legacy defines */
976 #define SRAM_BASE             SRAM1_BASE
977 #define SRAM_BB_BASE          SRAM1_BB_BASE
978 
979 
980 /*!< Peripheral memory map */
981 #define APB1PERIPH_BASE       PERIPH_BASE
982 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
983 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
984 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
985 
986 /*!< APB1 peripherals */
987 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
988 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
989 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
990 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
991 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
992 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
993 #define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
994 #define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
995 #define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
996 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
997 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
998 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
999 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
1000 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
1001 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
1002 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
1003 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
1004 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
1005 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
1006 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
1007 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
1008 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
1009 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
1010 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
1011 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
1012 
1013 /*!< APB2 peripherals */
1014 #define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
1015 #define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
1016 #define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
1017 #define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
1018 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
1019 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
1020 #define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
1021 #define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
1022 /* Legacy define */
1023 #define ADC_BASE               ADC123_COMMON_BASE
1024 
1025 #define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
1026 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
1027 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
1028 #define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
1029 #define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
1030 #define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
1031 #define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
1032 
1033 /*!< AHB1 peripherals */
1034 #define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
1035 #define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
1036 #define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
1037 #define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
1038 #define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
1039 #define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
1040 #define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
1041 #define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
1042 #define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
1043 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
1044 #define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
1045 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
1046 #define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
1047 #define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
1048 #define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
1049 #define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
1050 #define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
1051 #define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
1052 #define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
1053 #define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
1054 #define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
1055 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
1056 #define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
1057 #define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
1058 #define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
1059 #define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
1060 #define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
1061 #define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
1062 #define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
1063 #define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
1064 #define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
1065 #define ETH_MAC_BASE          (ETH_BASE)
1066 #define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
1067 #define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
1068 #define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
1069 
1070 /*!< AHB2 peripherals */
1071 #define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
1072 #define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000UL)
1073 #define HASH_BASE             (AHB2PERIPH_BASE + 0x60400UL)
1074 #define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
1075 
1076 /*!< FSMC Bankx registers base address */
1077 #define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
1078 #define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
1079 #define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
1080 #define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)
1081 
1082 /* Debug MCU registers base address */
1083 #define DBGMCU_BASE           0xE0042000UL
1084 
1085 /*!< USB registers base address */
1086 #define USB_OTG_HS_PERIPH_BASE               0x40040000UL
1087 #define USB_OTG_FS_PERIPH_BASE               0x50000000UL
1088 
1089 #define USB_OTG_GLOBAL_BASE                  0x000UL
1090 #define USB_OTG_DEVICE_BASE                  0x800UL
1091 #define USB_OTG_IN_ENDPOINT_BASE             0x900UL
1092 #define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
1093 #define USB_OTG_EP_REG_SIZE                  0x20UL
1094 #define USB_OTG_HOST_BASE                    0x400UL
1095 #define USB_OTG_HOST_PORT_BASE               0x440UL
1096 #define USB_OTG_HOST_CHANNEL_BASE            0x500UL
1097 #define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
1098 #define USB_OTG_PCGCCTL_BASE                 0xE00UL
1099 #define USB_OTG_FIFO_BASE                    0x1000UL
1100 #define USB_OTG_FIFO_SIZE                    0x1000UL
1101 
1102 /*******************  Device electronic signature  ***************/
1103 #define UID_BASE             0x1FFF7A10UL        /*!< Unique device ID register base address */
1104 #define FLASHSIZE_BASE       0x1FFF7A22UL        /*!< FLASH Size register base address */
1105 
1106 /**
1107   * @}
1108   */
1109 
1110 /** @addtogroup Peripheral_declaration
1111   * @{
1112   */
1113 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1114 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1115 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1116 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1117 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1118 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1119 #define TIM12               ((TIM_TypeDef *) TIM12_BASE)
1120 #define TIM13               ((TIM_TypeDef *) TIM13_BASE)
1121 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
1122 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1123 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1124 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1125 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1126 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1127 #define USART2              ((USART_TypeDef *) USART2_BASE)
1128 #define USART3              ((USART_TypeDef *) USART3_BASE)
1129 #define UART4               ((USART_TypeDef *) UART4_BASE)
1130 #define UART5               ((USART_TypeDef *) UART5_BASE)
1131 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1132 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1133 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1134 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1135 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1136 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1137 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
1138 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1139 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1140 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1141 #define USART1              ((USART_TypeDef *) USART1_BASE)
1142 #define USART6              ((USART_TypeDef *) USART6_BASE)
1143 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1144 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1145 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1146 #define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1147 /* Legacy define */
1148 #define ADC                  ADC123_COMMON
1149 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
1150 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1151 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1152 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1153 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
1154 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
1155 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
1156 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1157 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1158 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1159 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1160 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1161 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1162 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1163 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1164 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
1165 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1166 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1167 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1168 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1169 #define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1170 #define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1171 #define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1172 #define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1173 #define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1174 #define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1175 #define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1176 #define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1177 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1178 #define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1179 #define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1180 #define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1181 #define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1182 #define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1183 #define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1184 #define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1185 #define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1186 #define ETH                 ((ETH_TypeDef *) ETH_BASE)
1187 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1188 #define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
1189 #define HASH                ((HASH_TypeDef *) HASH_BASE)
1190 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1191 #define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
1192 #define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
1193 #define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
1194 #define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
1195 
1196 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1197 
1198 #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1199 #define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1200 
1201 /**
1202   * @}
1203   */
1204 
1205 /** @addtogroup Exported_constants
1206   * @{
1207   */
1208 
1209   /** @addtogroup Hardware_Constant_Definition
1210   * @{
1211   */
1212 #define LSI_STARTUP_TIME                40U /*!< LSI Maximum startup time in us */
1213 /**
1214   * @}
1215   */
1216 
1217   /** @addtogroup Peripheral_Registers_Bits_Definition
1218   * @{
1219   */
1220 
1221 /******************************************************************************/
1222 /*                         Peripheral Registers_Bits_Definition               */
1223 /******************************************************************************/
1224 
1225 /******************************************************************************/
1226 /*                                                                            */
1227 /*                        Analog to Digital Converter                         */
1228 /*                                                                            */
1229 /******************************************************************************/
1230 /********************  Bit definition for ADC_SR register  ********************/
1231 #define ADC_SR_AWD_Pos            (0U)
1232 #define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
1233 #define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
1234 #define ADC_SR_EOC_Pos            (1U)
1235 #define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
1236 #define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
1237 #define ADC_SR_JEOC_Pos           (2U)
1238 #define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
1239 #define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
1240 #define ADC_SR_JSTRT_Pos          (3U)
1241 #define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
1242 #define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
1243 #define ADC_SR_STRT_Pos           (4U)
1244 #define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
1245 #define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
1246 #define ADC_SR_OVR_Pos            (5U)
1247 #define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
1248 #define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
1249 
1250 /*******************  Bit definition for ADC_CR1 register  ********************/
1251 #define ADC_CR1_AWDCH_Pos         (0U)
1252 #define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
1253 #define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1254 #define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
1255 #define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
1256 #define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
1257 #define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
1258 #define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
1259 #define ADC_CR1_EOCIE_Pos         (5U)
1260 #define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
1261 #define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
1262 #define ADC_CR1_AWDIE_Pos         (6U)
1263 #define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
1264 #define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
1265 #define ADC_CR1_JEOCIE_Pos        (7U)
1266 #define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
1267 #define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
1268 #define ADC_CR1_SCAN_Pos          (8U)
1269 #define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
1270 #define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
1271 #define ADC_CR1_AWDSGL_Pos        (9U)
1272 #define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
1273 #define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
1274 #define ADC_CR1_JAUTO_Pos         (10U)
1275 #define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
1276 #define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
1277 #define ADC_CR1_DISCEN_Pos        (11U)
1278 #define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
1279 #define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
1280 #define ADC_CR1_JDISCEN_Pos       (12U)
1281 #define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
1282 #define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
1283 #define ADC_CR1_DISCNUM_Pos       (13U)
1284 #define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
1285 #define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1286 #define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
1287 #define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
1288 #define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
1289 #define ADC_CR1_JAWDEN_Pos        (22U)
1290 #define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
1291 #define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
1292 #define ADC_CR1_AWDEN_Pos         (23U)
1293 #define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
1294 #define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
1295 #define ADC_CR1_RES_Pos           (24U)
1296 #define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
1297 #define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
1298 #define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
1299 #define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
1300 #define ADC_CR1_OVRIE_Pos         (26U)
1301 #define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
1302 #define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
1303 
1304 /*******************  Bit definition for ADC_CR2 register  ********************/
1305 #define ADC_CR2_ADON_Pos          (0U)
1306 #define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
1307 #define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
1308 #define ADC_CR2_CONT_Pos          (1U)
1309 #define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
1310 #define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
1311 #define ADC_CR2_DMA_Pos           (8U)
1312 #define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
1313 #define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
1314 #define ADC_CR2_DDS_Pos           (9U)
1315 #define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
1316 #define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
1317 #define ADC_CR2_EOCS_Pos          (10U)
1318 #define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
1319 #define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
1320 #define ADC_CR2_ALIGN_Pos         (11U)
1321 #define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
1322 #define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
1323 #define ADC_CR2_JEXTSEL_Pos       (16U)
1324 #define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
1325 #define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1326 #define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
1327 #define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
1328 #define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
1329 #define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
1330 #define ADC_CR2_JEXTEN_Pos        (20U)
1331 #define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
1332 #define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1333 #define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
1334 #define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
1335 #define ADC_CR2_JSWSTART_Pos      (22U)
1336 #define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
1337 #define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
1338 #define ADC_CR2_EXTSEL_Pos        (24U)
1339 #define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
1340 #define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1341 #define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
1342 #define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
1343 #define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
1344 #define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
1345 #define ADC_CR2_EXTEN_Pos         (28U)
1346 #define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
1347 #define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1348 #define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
1349 #define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
1350 #define ADC_CR2_SWSTART_Pos       (30U)
1351 #define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
1352 #define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
1353 
1354 /******************  Bit definition for ADC_SMPR1 register  *******************/
1355 #define ADC_SMPR1_SMP10_Pos       (0U)
1356 #define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
1357 #define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1358 #define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
1359 #define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
1360 #define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
1361 #define ADC_SMPR1_SMP11_Pos       (3U)
1362 #define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
1363 #define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1364 #define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
1365 #define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
1366 #define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
1367 #define ADC_SMPR1_SMP12_Pos       (6U)
1368 #define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
1369 #define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1370 #define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
1371 #define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
1372 #define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
1373 #define ADC_SMPR1_SMP13_Pos       (9U)
1374 #define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
1375 #define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1376 #define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
1377 #define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
1378 #define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
1379 #define ADC_SMPR1_SMP14_Pos       (12U)
1380 #define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
1381 #define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1382 #define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
1383 #define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
1384 #define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
1385 #define ADC_SMPR1_SMP15_Pos       (15U)
1386 #define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
1387 #define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1388 #define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
1389 #define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
1390 #define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
1391 #define ADC_SMPR1_SMP16_Pos       (18U)
1392 #define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
1393 #define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1394 #define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
1395 #define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
1396 #define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
1397 #define ADC_SMPR1_SMP17_Pos       (21U)
1398 #define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
1399 #define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1400 #define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
1401 #define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
1402 #define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
1403 #define ADC_SMPR1_SMP18_Pos       (24U)
1404 #define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
1405 #define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1406 #define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
1407 #define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
1408 #define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
1409 
1410 /******************  Bit definition for ADC_SMPR2 register  *******************/
1411 #define ADC_SMPR2_SMP0_Pos        (0U)
1412 #define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
1413 #define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1414 #define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
1415 #define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
1416 #define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
1417 #define ADC_SMPR2_SMP1_Pos        (3U)
1418 #define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
1419 #define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1420 #define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
1421 #define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
1422 #define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
1423 #define ADC_SMPR2_SMP2_Pos        (6U)
1424 #define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
1425 #define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1426 #define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
1427 #define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
1428 #define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
1429 #define ADC_SMPR2_SMP3_Pos        (9U)
1430 #define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
1431 #define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1432 #define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
1433 #define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
1434 #define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
1435 #define ADC_SMPR2_SMP4_Pos        (12U)
1436 #define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
1437 #define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1438 #define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
1439 #define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
1440 #define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
1441 #define ADC_SMPR2_SMP5_Pos        (15U)
1442 #define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
1443 #define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1444 #define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
1445 #define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
1446 #define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
1447 #define ADC_SMPR2_SMP6_Pos        (18U)
1448 #define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
1449 #define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1450 #define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
1451 #define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
1452 #define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
1453 #define ADC_SMPR2_SMP7_Pos        (21U)
1454 #define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
1455 #define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1456 #define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
1457 #define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
1458 #define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
1459 #define ADC_SMPR2_SMP8_Pos        (24U)
1460 #define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
1461 #define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1462 #define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
1463 #define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
1464 #define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
1465 #define ADC_SMPR2_SMP9_Pos        (27U)
1466 #define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
1467 #define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1468 #define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
1469 #define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
1470 #define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
1471 
1472 /******************  Bit definition for ADC_JOFR1 register  *******************/
1473 #define ADC_JOFR1_JOFFSET1_Pos    (0U)
1474 #define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
1475 #define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
1476 
1477 /******************  Bit definition for ADC_JOFR2 register  *******************/
1478 #define ADC_JOFR2_JOFFSET2_Pos    (0U)
1479 #define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
1480 #define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
1481 
1482 /******************  Bit definition for ADC_JOFR3 register  *******************/
1483 #define ADC_JOFR3_JOFFSET3_Pos    (0U)
1484 #define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
1485 #define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
1486 
1487 /******************  Bit definition for ADC_JOFR4 register  *******************/
1488 #define ADC_JOFR4_JOFFSET4_Pos    (0U)
1489 #define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
1490 #define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
1491 
1492 /*******************  Bit definition for ADC_HTR register  ********************/
1493 #define ADC_HTR_HT_Pos            (0U)
1494 #define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
1495 #define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
1496 
1497 /*******************  Bit definition for ADC_LTR register  ********************/
1498 #define ADC_LTR_LT_Pos            (0U)
1499 #define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
1500 #define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
1501 
1502 /*******************  Bit definition for ADC_SQR1 register  *******************/
1503 #define ADC_SQR1_SQ13_Pos         (0U)
1504 #define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
1505 #define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1506 #define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
1507 #define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
1508 #define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
1509 #define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
1510 #define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
1511 #define ADC_SQR1_SQ14_Pos         (5U)
1512 #define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
1513 #define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1514 #define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
1515 #define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
1516 #define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
1517 #define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
1518 #define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
1519 #define ADC_SQR1_SQ15_Pos         (10U)
1520 #define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
1521 #define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1522 #define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
1523 #define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
1524 #define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
1525 #define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
1526 #define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
1527 #define ADC_SQR1_SQ16_Pos         (15U)
1528 #define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
1529 #define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1530 #define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
1531 #define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
1532 #define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
1533 #define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
1534 #define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
1535 #define ADC_SQR1_L_Pos            (20U)
1536 #define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
1537 #define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
1538 #define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
1539 #define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
1540 #define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
1541 #define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
1542 
1543 /*******************  Bit definition for ADC_SQR2 register  *******************/
1544 #define ADC_SQR2_SQ7_Pos          (0U)
1545 #define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
1546 #define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1547 #define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
1548 #define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
1549 #define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
1550 #define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
1551 #define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
1552 #define ADC_SQR2_SQ8_Pos          (5U)
1553 #define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
1554 #define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1555 #define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
1556 #define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
1557 #define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
1558 #define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
1559 #define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
1560 #define ADC_SQR2_SQ9_Pos          (10U)
1561 #define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
1562 #define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1563 #define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
1564 #define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
1565 #define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
1566 #define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
1567 #define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
1568 #define ADC_SQR2_SQ10_Pos         (15U)
1569 #define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
1570 #define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1571 #define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
1572 #define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
1573 #define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
1574 #define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
1575 #define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
1576 #define ADC_SQR2_SQ11_Pos         (20U)
1577 #define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
1578 #define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1579 #define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
1580 #define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
1581 #define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
1582 #define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
1583 #define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
1584 #define ADC_SQR2_SQ12_Pos         (25U)
1585 #define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
1586 #define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1587 #define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
1588 #define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
1589 #define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
1590 #define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
1591 #define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
1592 
1593 /*******************  Bit definition for ADC_SQR3 register  *******************/
1594 #define ADC_SQR3_SQ1_Pos          (0U)
1595 #define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
1596 #define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1597 #define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
1598 #define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
1599 #define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
1600 #define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
1601 #define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
1602 #define ADC_SQR3_SQ2_Pos          (5U)
1603 #define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
1604 #define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1605 #define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
1606 #define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
1607 #define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
1608 #define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
1609 #define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
1610 #define ADC_SQR3_SQ3_Pos          (10U)
1611 #define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
1612 #define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1613 #define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
1614 #define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
1615 #define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
1616 #define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
1617 #define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
1618 #define ADC_SQR3_SQ4_Pos          (15U)
1619 #define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
1620 #define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1621 #define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
1622 #define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
1623 #define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
1624 #define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
1625 #define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
1626 #define ADC_SQR3_SQ5_Pos          (20U)
1627 #define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
1628 #define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1629 #define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
1630 #define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
1631 #define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
1632 #define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
1633 #define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
1634 #define ADC_SQR3_SQ6_Pos          (25U)
1635 #define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
1636 #define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1637 #define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
1638 #define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
1639 #define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
1640 #define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
1641 #define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
1642 
1643 /*******************  Bit definition for ADC_JSQR register  *******************/
1644 #define ADC_JSQR_JSQ1_Pos         (0U)
1645 #define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
1646 #define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1647 #define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
1648 #define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
1649 #define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
1650 #define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
1651 #define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
1652 #define ADC_JSQR_JSQ2_Pos         (5U)
1653 #define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
1654 #define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1655 #define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
1656 #define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
1657 #define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
1658 #define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
1659 #define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
1660 #define ADC_JSQR_JSQ3_Pos         (10U)
1661 #define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
1662 #define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1663 #define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
1664 #define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
1665 #define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
1666 #define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
1667 #define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
1668 #define ADC_JSQR_JSQ4_Pos         (15U)
1669 #define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
1670 #define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1671 #define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
1672 #define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
1673 #define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
1674 #define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
1675 #define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
1676 #define ADC_JSQR_JL_Pos           (20U)
1677 #define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
1678 #define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
1679 #define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
1680 #define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
1681 
1682 /*******************  Bit definition for ADC_JDR1 register  *******************/
1683 #define ADC_JDR1_JDATA_Pos        (0U)
1684 #define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
1685 #define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
1686 
1687 /*******************  Bit definition for ADC_JDR2 register  *******************/
1688 #define ADC_JDR2_JDATA_Pos        (0U)
1689 #define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
1690 #define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
1691 
1692 /*******************  Bit definition for ADC_JDR3 register  *******************/
1693 #define ADC_JDR3_JDATA_Pos        (0U)
1694 #define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
1695 #define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
1696 
1697 /*******************  Bit definition for ADC_JDR4 register  *******************/
1698 #define ADC_JDR4_JDATA_Pos        (0U)
1699 #define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
1700 #define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
1701 
1702 /********************  Bit definition for ADC_DR register  ********************/
1703 #define ADC_DR_DATA_Pos           (0U)
1704 #define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
1705 #define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
1706 #define ADC_DR_ADC2DATA_Pos       (16U)
1707 #define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
1708 #define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
1709 
1710 /*******************  Bit definition for ADC_CSR register  ********************/
1711 #define ADC_CSR_AWD1_Pos          (0U)
1712 #define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
1713 #define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
1714 #define ADC_CSR_EOC1_Pos          (1U)
1715 #define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
1716 #define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
1717 #define ADC_CSR_JEOC1_Pos         (2U)
1718 #define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
1719 #define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
1720 #define ADC_CSR_JSTRT1_Pos        (3U)
1721 #define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
1722 #define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
1723 #define ADC_CSR_STRT1_Pos         (4U)
1724 #define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
1725 #define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
1726 #define ADC_CSR_OVR1_Pos          (5U)
1727 #define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
1728 #define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
1729 #define ADC_CSR_AWD2_Pos          (8U)
1730 #define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
1731 #define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
1732 #define ADC_CSR_EOC2_Pos          (9U)
1733 #define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
1734 #define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
1735 #define ADC_CSR_JEOC2_Pos         (10U)
1736 #define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
1737 #define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
1738 #define ADC_CSR_JSTRT2_Pos        (11U)
1739 #define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
1740 #define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
1741 #define ADC_CSR_STRT2_Pos         (12U)
1742 #define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
1743 #define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
1744 #define ADC_CSR_OVR2_Pos          (13U)
1745 #define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
1746 #define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
1747 #define ADC_CSR_AWD3_Pos          (16U)
1748 #define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
1749 #define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
1750 #define ADC_CSR_EOC3_Pos          (17U)
1751 #define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
1752 #define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
1753 #define ADC_CSR_JEOC3_Pos         (18U)
1754 #define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
1755 #define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
1756 #define ADC_CSR_JSTRT3_Pos        (19U)
1757 #define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
1758 #define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
1759 #define ADC_CSR_STRT3_Pos         (20U)
1760 #define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
1761 #define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
1762 #define ADC_CSR_OVR3_Pos          (21U)
1763 #define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
1764 #define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
1765 
1766 /* Legacy defines */
1767 #define  ADC_CSR_DOVR1            ADC_CSR_OVR1
1768 #define  ADC_CSR_DOVR2            ADC_CSR_OVR2
1769 #define  ADC_CSR_DOVR3            ADC_CSR_OVR3
1770 
1771 /*******************  Bit definition for ADC_CCR register  ********************/
1772 #define ADC_CCR_MULTI_Pos         (0U)
1773 #define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
1774 #define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1775 #define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
1776 #define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
1777 #define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
1778 #define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
1779 #define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
1780 #define ADC_CCR_DELAY_Pos         (8U)
1781 #define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
1782 #define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1783 #define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
1784 #define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
1785 #define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
1786 #define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
1787 #define ADC_CCR_DDS_Pos           (13U)
1788 #define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
1789 #define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
1790 #define ADC_CCR_DMA_Pos           (14U)
1791 #define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
1792 #define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1793 #define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
1794 #define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
1795 #define ADC_CCR_ADCPRE_Pos        (16U)
1796 #define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
1797 #define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
1798 #define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
1799 #define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
1800 #define ADC_CCR_VBATE_Pos         (22U)
1801 #define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
1802 #define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
1803 #define ADC_CCR_TSVREFE_Pos       (23U)
1804 #define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
1805 #define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
1806 
1807 /*******************  Bit definition for ADC_CDR register  ********************/
1808 #define ADC_CDR_DATA1_Pos         (0U)
1809 #define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
1810 #define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
1811 #define ADC_CDR_DATA2_Pos         (16U)
1812 #define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
1813 #define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
1814 
1815 /* Legacy defines */
1816 #define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
1817 #define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
1818 
1819 /******************************************************************************/
1820 /*                                                                            */
1821 /*                         Controller Area Network                            */
1822 /*                                                                            */
1823 /******************************************************************************/
1824 /*!<CAN control and status registers */
1825 /*******************  Bit definition for CAN_MCR register  ********************/
1826 #define CAN_MCR_INRQ_Pos       (0U)
1827 #define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
1828 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
1829 #define CAN_MCR_SLEEP_Pos      (1U)
1830 #define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
1831 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
1832 #define CAN_MCR_TXFP_Pos       (2U)
1833 #define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
1834 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
1835 #define CAN_MCR_RFLM_Pos       (3U)
1836 #define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
1837 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
1838 #define CAN_MCR_NART_Pos       (4U)
1839 #define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
1840 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
1841 #define CAN_MCR_AWUM_Pos       (5U)
1842 #define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
1843 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
1844 #define CAN_MCR_ABOM_Pos       (6U)
1845 #define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
1846 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
1847 #define CAN_MCR_TTCM_Pos       (7U)
1848 #define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
1849 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
1850 #define CAN_MCR_RESET_Pos      (15U)
1851 #define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
1852 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
1853 #define CAN_MCR_DBF_Pos        (16U)
1854 #define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
1855 #define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
1856 /*******************  Bit definition for CAN_MSR register  ********************/
1857 #define CAN_MSR_INAK_Pos       (0U)
1858 #define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
1859 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
1860 #define CAN_MSR_SLAK_Pos       (1U)
1861 #define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
1862 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
1863 #define CAN_MSR_ERRI_Pos       (2U)
1864 #define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
1865 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
1866 #define CAN_MSR_WKUI_Pos       (3U)
1867 #define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
1868 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
1869 #define CAN_MSR_SLAKI_Pos      (4U)
1870 #define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
1871 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
1872 #define CAN_MSR_TXM_Pos        (8U)
1873 #define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
1874 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
1875 #define CAN_MSR_RXM_Pos        (9U)
1876 #define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
1877 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
1878 #define CAN_MSR_SAMP_Pos       (10U)
1879 #define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
1880 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
1881 #define CAN_MSR_RX_Pos         (11U)
1882 #define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
1883 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
1884 
1885 /*******************  Bit definition for CAN_TSR register  ********************/
1886 #define CAN_TSR_RQCP0_Pos      (0U)
1887 #define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
1888 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
1889 #define CAN_TSR_TXOK0_Pos      (1U)
1890 #define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
1891 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
1892 #define CAN_TSR_ALST0_Pos      (2U)
1893 #define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
1894 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
1895 #define CAN_TSR_TERR0_Pos      (3U)
1896 #define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
1897 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
1898 #define CAN_TSR_ABRQ0_Pos      (7U)
1899 #define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
1900 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
1901 #define CAN_TSR_RQCP1_Pos      (8U)
1902 #define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
1903 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
1904 #define CAN_TSR_TXOK1_Pos      (9U)
1905 #define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
1906 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
1907 #define CAN_TSR_ALST1_Pos      (10U)
1908 #define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
1909 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
1910 #define CAN_TSR_TERR1_Pos      (11U)
1911 #define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
1912 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
1913 #define CAN_TSR_ABRQ1_Pos      (15U)
1914 #define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
1915 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
1916 #define CAN_TSR_RQCP2_Pos      (16U)
1917 #define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
1918 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
1919 #define CAN_TSR_TXOK2_Pos      (17U)
1920 #define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
1921 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
1922 #define CAN_TSR_ALST2_Pos      (18U)
1923 #define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
1924 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
1925 #define CAN_TSR_TERR2_Pos      (19U)
1926 #define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
1927 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
1928 #define CAN_TSR_ABRQ2_Pos      (23U)
1929 #define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
1930 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
1931 #define CAN_TSR_CODE_Pos       (24U)
1932 #define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
1933 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
1934 
1935 #define CAN_TSR_TME_Pos        (26U)
1936 #define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
1937 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
1938 #define CAN_TSR_TME0_Pos       (26U)
1939 #define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
1940 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
1941 #define CAN_TSR_TME1_Pos       (27U)
1942 #define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
1943 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
1944 #define CAN_TSR_TME2_Pos       (28U)
1945 #define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
1946 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
1947 
1948 #define CAN_TSR_LOW_Pos        (29U)
1949 #define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
1950 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
1951 #define CAN_TSR_LOW0_Pos       (29U)
1952 #define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
1953 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
1954 #define CAN_TSR_LOW1_Pos       (30U)
1955 #define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
1956 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
1957 #define CAN_TSR_LOW2_Pos       (31U)
1958 #define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
1959 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
1960 
1961 /*******************  Bit definition for CAN_RF0R register  *******************/
1962 #define CAN_RF0R_FMP0_Pos      (0U)
1963 #define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
1964 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
1965 #define CAN_RF0R_FULL0_Pos     (3U)
1966 #define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
1967 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
1968 #define CAN_RF0R_FOVR0_Pos     (4U)
1969 #define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
1970 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
1971 #define CAN_RF0R_RFOM0_Pos     (5U)
1972 #define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
1973 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
1974 
1975 /*******************  Bit definition for CAN_RF1R register  *******************/
1976 #define CAN_RF1R_FMP1_Pos      (0U)
1977 #define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
1978 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
1979 #define CAN_RF1R_FULL1_Pos     (3U)
1980 #define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
1981 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
1982 #define CAN_RF1R_FOVR1_Pos     (4U)
1983 #define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
1984 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
1985 #define CAN_RF1R_RFOM1_Pos     (5U)
1986 #define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
1987 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
1988 
1989 /********************  Bit definition for CAN_IER register  *******************/
1990 #define CAN_IER_TMEIE_Pos      (0U)
1991 #define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
1992 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
1993 #define CAN_IER_FMPIE0_Pos     (1U)
1994 #define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
1995 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
1996 #define CAN_IER_FFIE0_Pos      (2U)
1997 #define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
1998 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
1999 #define CAN_IER_FOVIE0_Pos     (3U)
2000 #define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
2001 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
2002 #define CAN_IER_FMPIE1_Pos     (4U)
2003 #define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
2004 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2005 #define CAN_IER_FFIE1_Pos      (5U)
2006 #define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
2007 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
2008 #define CAN_IER_FOVIE1_Pos     (6U)
2009 #define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
2010 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
2011 #define CAN_IER_EWGIE_Pos      (8U)
2012 #define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
2013 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
2014 #define CAN_IER_EPVIE_Pos      (9U)
2015 #define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
2016 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
2017 #define CAN_IER_BOFIE_Pos      (10U)
2018 #define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
2019 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
2020 #define CAN_IER_LECIE_Pos      (11U)
2021 #define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
2022 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
2023 #define CAN_IER_ERRIE_Pos      (15U)
2024 #define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
2025 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
2026 #define CAN_IER_WKUIE_Pos      (16U)
2027 #define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
2028 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
2029 #define CAN_IER_SLKIE_Pos      (17U)
2030 #define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
2031 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
2032 
2033 /********************  Bit definition for CAN_ESR register  *******************/
2034 #define CAN_ESR_EWGF_Pos       (0U)
2035 #define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
2036 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
2037 #define CAN_ESR_EPVF_Pos       (1U)
2038 #define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
2039 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
2040 #define CAN_ESR_BOFF_Pos       (2U)
2041 #define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
2042 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
2043 
2044 #define CAN_ESR_LEC_Pos        (4U)
2045 #define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
2046 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
2047 #define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
2048 #define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
2049 #define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
2050 
2051 #define CAN_ESR_TEC_Pos        (16U)
2052 #define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
2053 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
2054 #define CAN_ESR_REC_Pos        (24U)
2055 #define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
2056 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
2057 
2058 /*******************  Bit definition for CAN_BTR register  ********************/
2059 #define CAN_BTR_BRP_Pos        (0U)
2060 #define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
2061 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
2062 #define CAN_BTR_TS1_Pos        (16U)
2063 #define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
2064 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
2065 #define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
2066 #define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
2067 #define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
2068 #define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
2069 #define CAN_BTR_TS2_Pos        (20U)
2070 #define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
2071 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
2072 #define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
2073 #define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
2074 #define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
2075 #define CAN_BTR_SJW_Pos        (24U)
2076 #define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
2077 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
2078 #define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
2079 #define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
2080 #define CAN_BTR_LBKM_Pos       (30U)
2081 #define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
2082 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
2083 #define CAN_BTR_SILM_Pos       (31U)
2084 #define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
2085 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
2086 
2087 
2088 /*!<Mailbox registers */
2089 /******************  Bit definition for CAN_TI0R register  ********************/
2090 #define CAN_TI0R_TXRQ_Pos      (0U)
2091 #define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
2092 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2093 #define CAN_TI0R_RTR_Pos       (1U)
2094 #define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
2095 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
2096 #define CAN_TI0R_IDE_Pos       (2U)
2097 #define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
2098 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
2099 #define CAN_TI0R_EXID_Pos      (3U)
2100 #define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2101 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
2102 #define CAN_TI0R_STID_Pos      (21U)
2103 #define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
2104 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2105 
2106 /******************  Bit definition for CAN_TDT0R register  *******************/
2107 #define CAN_TDT0R_DLC_Pos      (0U)
2108 #define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
2109 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
2110 #define CAN_TDT0R_TGT_Pos      (8U)
2111 #define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
2112 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
2113 #define CAN_TDT0R_TIME_Pos     (16U)
2114 #define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2115 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
2116 
2117 /******************  Bit definition for CAN_TDL0R register  *******************/
2118 #define CAN_TDL0R_DATA0_Pos    (0U)
2119 #define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2120 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
2121 #define CAN_TDL0R_DATA1_Pos    (8U)
2122 #define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2123 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
2124 #define CAN_TDL0R_DATA2_Pos    (16U)
2125 #define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2126 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
2127 #define CAN_TDL0R_DATA3_Pos    (24U)
2128 #define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2129 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
2130 
2131 /******************  Bit definition for CAN_TDH0R register  *******************/
2132 #define CAN_TDH0R_DATA4_Pos    (0U)
2133 #define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2134 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
2135 #define CAN_TDH0R_DATA5_Pos    (8U)
2136 #define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2137 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
2138 #define CAN_TDH0R_DATA6_Pos    (16U)
2139 #define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2140 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
2141 #define CAN_TDH0R_DATA7_Pos    (24U)
2142 #define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2143 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
2144 
2145 /*******************  Bit definition for CAN_TI1R register  *******************/
2146 #define CAN_TI1R_TXRQ_Pos      (0U)
2147 #define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
2148 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2149 #define CAN_TI1R_RTR_Pos       (1U)
2150 #define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
2151 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
2152 #define CAN_TI1R_IDE_Pos       (2U)
2153 #define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
2154 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
2155 #define CAN_TI1R_EXID_Pos      (3U)
2156 #define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2157 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
2158 #define CAN_TI1R_STID_Pos      (21U)
2159 #define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
2160 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2161 
2162 /*******************  Bit definition for CAN_TDT1R register  ******************/
2163 #define CAN_TDT1R_DLC_Pos      (0U)
2164 #define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
2165 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
2166 #define CAN_TDT1R_TGT_Pos      (8U)
2167 #define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
2168 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
2169 #define CAN_TDT1R_TIME_Pos     (16U)
2170 #define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2171 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
2172 
2173 /*******************  Bit definition for CAN_TDL1R register  ******************/
2174 #define CAN_TDL1R_DATA0_Pos    (0U)
2175 #define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2176 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
2177 #define CAN_TDL1R_DATA1_Pos    (8U)
2178 #define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2179 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
2180 #define CAN_TDL1R_DATA2_Pos    (16U)
2181 #define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2182 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
2183 #define CAN_TDL1R_DATA3_Pos    (24U)
2184 #define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2185 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
2186 
2187 /*******************  Bit definition for CAN_TDH1R register  ******************/
2188 #define CAN_TDH1R_DATA4_Pos    (0U)
2189 #define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2190 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
2191 #define CAN_TDH1R_DATA5_Pos    (8U)
2192 #define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2193 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
2194 #define CAN_TDH1R_DATA6_Pos    (16U)
2195 #define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2196 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
2197 #define CAN_TDH1R_DATA7_Pos    (24U)
2198 #define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2199 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
2200 
2201 /*******************  Bit definition for CAN_TI2R register  *******************/
2202 #define CAN_TI2R_TXRQ_Pos      (0U)
2203 #define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
2204 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
2205 #define CAN_TI2R_RTR_Pos       (1U)
2206 #define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
2207 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
2208 #define CAN_TI2R_IDE_Pos       (2U)
2209 #define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
2210 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
2211 #define CAN_TI2R_EXID_Pos      (3U)
2212 #define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
2213 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
2214 #define CAN_TI2R_STID_Pos      (21U)
2215 #define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
2216 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2217 
2218 /*******************  Bit definition for CAN_TDT2R register  ******************/
2219 #define CAN_TDT2R_DLC_Pos      (0U)
2220 #define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
2221 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
2222 #define CAN_TDT2R_TGT_Pos      (8U)
2223 #define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
2224 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
2225 #define CAN_TDT2R_TIME_Pos     (16U)
2226 #define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
2227 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
2228 
2229 /*******************  Bit definition for CAN_TDL2R register  ******************/
2230 #define CAN_TDL2R_DATA0_Pos    (0U)
2231 #define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
2232 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
2233 #define CAN_TDL2R_DATA1_Pos    (8U)
2234 #define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
2235 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
2236 #define CAN_TDL2R_DATA2_Pos    (16U)
2237 #define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
2238 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
2239 #define CAN_TDL2R_DATA3_Pos    (24U)
2240 #define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
2241 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
2242 
2243 /*******************  Bit definition for CAN_TDH2R register  ******************/
2244 #define CAN_TDH2R_DATA4_Pos    (0U)
2245 #define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
2246 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
2247 #define CAN_TDH2R_DATA5_Pos    (8U)
2248 #define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
2249 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
2250 #define CAN_TDH2R_DATA6_Pos    (16U)
2251 #define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
2252 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
2253 #define CAN_TDH2R_DATA7_Pos    (24U)
2254 #define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
2255 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
2256 
2257 /*******************  Bit definition for CAN_RI0R register  *******************/
2258 #define CAN_RI0R_RTR_Pos       (1U)
2259 #define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
2260 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
2261 #define CAN_RI0R_IDE_Pos       (2U)
2262 #define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
2263 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
2264 #define CAN_RI0R_EXID_Pos      (3U)
2265 #define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
2266 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
2267 #define CAN_RI0R_STID_Pos      (21U)
2268 #define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
2269 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2270 
2271 /*******************  Bit definition for CAN_RDT0R register  ******************/
2272 #define CAN_RDT0R_DLC_Pos      (0U)
2273 #define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
2274 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
2275 #define CAN_RDT0R_FMI_Pos      (8U)
2276 #define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
2277 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
2278 #define CAN_RDT0R_TIME_Pos     (16U)
2279 #define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
2280 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
2281 
2282 /*******************  Bit definition for CAN_RDL0R register  ******************/
2283 #define CAN_RDL0R_DATA0_Pos    (0U)
2284 #define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
2285 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
2286 #define CAN_RDL0R_DATA1_Pos    (8U)
2287 #define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
2288 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
2289 #define CAN_RDL0R_DATA2_Pos    (16U)
2290 #define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
2291 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
2292 #define CAN_RDL0R_DATA3_Pos    (24U)
2293 #define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
2294 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
2295 
2296 /*******************  Bit definition for CAN_RDH0R register  ******************/
2297 #define CAN_RDH0R_DATA4_Pos    (0U)
2298 #define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
2299 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
2300 #define CAN_RDH0R_DATA5_Pos    (8U)
2301 #define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
2302 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
2303 #define CAN_RDH0R_DATA6_Pos    (16U)
2304 #define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
2305 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
2306 #define CAN_RDH0R_DATA7_Pos    (24U)
2307 #define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
2308 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
2309 
2310 /*******************  Bit definition for CAN_RI1R register  *******************/
2311 #define CAN_RI1R_RTR_Pos       (1U)
2312 #define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
2313 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
2314 #define CAN_RI1R_IDE_Pos       (2U)
2315 #define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
2316 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
2317 #define CAN_RI1R_EXID_Pos      (3U)
2318 #define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
2319 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
2320 #define CAN_RI1R_STID_Pos      (21U)
2321 #define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
2322 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
2323 
2324 /*******************  Bit definition for CAN_RDT1R register  ******************/
2325 #define CAN_RDT1R_DLC_Pos      (0U)
2326 #define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
2327 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
2328 #define CAN_RDT1R_FMI_Pos      (8U)
2329 #define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
2330 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
2331 #define CAN_RDT1R_TIME_Pos     (16U)
2332 #define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
2333 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
2334 
2335 /*******************  Bit definition for CAN_RDL1R register  ******************/
2336 #define CAN_RDL1R_DATA0_Pos    (0U)
2337 #define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
2338 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
2339 #define CAN_RDL1R_DATA1_Pos    (8U)
2340 #define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
2341 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
2342 #define CAN_RDL1R_DATA2_Pos    (16U)
2343 #define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
2344 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
2345 #define CAN_RDL1R_DATA3_Pos    (24U)
2346 #define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
2347 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
2348 
2349 /*******************  Bit definition for CAN_RDH1R register  ******************/
2350 #define CAN_RDH1R_DATA4_Pos    (0U)
2351 #define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
2352 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
2353 #define CAN_RDH1R_DATA5_Pos    (8U)
2354 #define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
2355 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
2356 #define CAN_RDH1R_DATA6_Pos    (16U)
2357 #define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
2358 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
2359 #define CAN_RDH1R_DATA7_Pos    (24U)
2360 #define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
2361 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
2362 
2363 /*!<CAN filter registers */
2364 /*******************  Bit definition for CAN_FMR register  ********************/
2365 #define CAN_FMR_FINIT_Pos      (0U)
2366 #define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
2367 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
2368 #define CAN_FMR_CAN2SB_Pos     (8U)
2369 #define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
2370 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
2371 
2372 /*************  Bit definition for CAN_FM1R register  *******************/
2373 #define CAN_FM1R_FBM_Pos       (0U)
2374 #define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
2375 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
2376 #define CAN_FM1R_FBM0_Pos      (0U)
2377 #define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
2378 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
2379 #define CAN_FM1R_FBM1_Pos      (1U)
2380 #define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
2381 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
2382 #define CAN_FM1R_FBM2_Pos      (2U)
2383 #define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
2384 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
2385 #define CAN_FM1R_FBM3_Pos      (3U)
2386 #define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
2387 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
2388 #define CAN_FM1R_FBM4_Pos      (4U)
2389 #define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
2390 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
2391 #define CAN_FM1R_FBM5_Pos      (5U)
2392 #define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
2393 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
2394 #define CAN_FM1R_FBM6_Pos      (6U)
2395 #define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
2396 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
2397 #define CAN_FM1R_FBM7_Pos      (7U)
2398 #define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
2399 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
2400 #define CAN_FM1R_FBM8_Pos      (8U)
2401 #define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
2402 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
2403 #define CAN_FM1R_FBM9_Pos      (9U)
2404 #define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
2405 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
2406 #define CAN_FM1R_FBM10_Pos     (10U)
2407 #define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
2408 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
2409 #define CAN_FM1R_FBM11_Pos     (11U)
2410 #define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
2411 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
2412 #define CAN_FM1R_FBM12_Pos     (12U)
2413 #define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
2414 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
2415 #define CAN_FM1R_FBM13_Pos     (13U)
2416 #define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
2417 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
2418 #define CAN_FM1R_FBM14_Pos     (14U)
2419 #define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
2420 #define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
2421 #define CAN_FM1R_FBM15_Pos     (15U)
2422 #define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
2423 #define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
2424 #define CAN_FM1R_FBM16_Pos     (16U)
2425 #define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
2426 #define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
2427 #define CAN_FM1R_FBM17_Pos     (17U)
2428 #define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
2429 #define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
2430 #define CAN_FM1R_FBM18_Pos     (18U)
2431 #define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
2432 #define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
2433 #define CAN_FM1R_FBM19_Pos     (19U)
2434 #define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
2435 #define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
2436 #define CAN_FM1R_FBM20_Pos     (20U)
2437 #define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
2438 #define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
2439 #define CAN_FM1R_FBM21_Pos     (21U)
2440 #define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
2441 #define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
2442 #define CAN_FM1R_FBM22_Pos     (22U)
2443 #define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
2444 #define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
2445 #define CAN_FM1R_FBM23_Pos     (23U)
2446 #define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
2447 #define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
2448 #define CAN_FM1R_FBM24_Pos     (24U)
2449 #define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
2450 #define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
2451 #define CAN_FM1R_FBM25_Pos     (25U)
2452 #define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
2453 #define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
2454 #define CAN_FM1R_FBM26_Pos     (26U)
2455 #define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
2456 #define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
2457 #define CAN_FM1R_FBM27_Pos     (27U)
2458 #define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
2459 #define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
2460 
2461 /*******************  Bit definition for CAN_FS1R register  *******************/
2462 #define CAN_FS1R_FSC_Pos       (0U)
2463 #define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
2464 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
2465 #define CAN_FS1R_FSC0_Pos      (0U)
2466 #define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
2467 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
2468 #define CAN_FS1R_FSC1_Pos      (1U)
2469 #define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
2470 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
2471 #define CAN_FS1R_FSC2_Pos      (2U)
2472 #define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
2473 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
2474 #define CAN_FS1R_FSC3_Pos      (3U)
2475 #define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
2476 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
2477 #define CAN_FS1R_FSC4_Pos      (4U)
2478 #define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
2479 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
2480 #define CAN_FS1R_FSC5_Pos      (5U)
2481 #define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
2482 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
2483 #define CAN_FS1R_FSC6_Pos      (6U)
2484 #define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
2485 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
2486 #define CAN_FS1R_FSC7_Pos      (7U)
2487 #define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
2488 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
2489 #define CAN_FS1R_FSC8_Pos      (8U)
2490 #define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
2491 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
2492 #define CAN_FS1R_FSC9_Pos      (9U)
2493 #define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
2494 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
2495 #define CAN_FS1R_FSC10_Pos     (10U)
2496 #define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
2497 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
2498 #define CAN_FS1R_FSC11_Pos     (11U)
2499 #define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
2500 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
2501 #define CAN_FS1R_FSC12_Pos     (12U)
2502 #define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
2503 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
2504 #define CAN_FS1R_FSC13_Pos     (13U)
2505 #define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
2506 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
2507 #define CAN_FS1R_FSC14_Pos     (14U)
2508 #define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
2509 #define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
2510 #define CAN_FS1R_FSC15_Pos     (15U)
2511 #define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
2512 #define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
2513 #define CAN_FS1R_FSC16_Pos     (16U)
2514 #define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
2515 #define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
2516 #define CAN_FS1R_FSC17_Pos     (17U)
2517 #define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
2518 #define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
2519 #define CAN_FS1R_FSC18_Pos     (18U)
2520 #define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
2521 #define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
2522 #define CAN_FS1R_FSC19_Pos     (19U)
2523 #define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
2524 #define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
2525 #define CAN_FS1R_FSC20_Pos     (20U)
2526 #define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
2527 #define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
2528 #define CAN_FS1R_FSC21_Pos     (21U)
2529 #define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
2530 #define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
2531 #define CAN_FS1R_FSC22_Pos     (22U)
2532 #define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
2533 #define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
2534 #define CAN_FS1R_FSC23_Pos     (23U)
2535 #define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
2536 #define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
2537 #define CAN_FS1R_FSC24_Pos     (24U)
2538 #define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
2539 #define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
2540 #define CAN_FS1R_FSC25_Pos     (25U)
2541 #define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
2542 #define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
2543 #define CAN_FS1R_FSC26_Pos     (26U)
2544 #define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
2545 #define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
2546 #define CAN_FS1R_FSC27_Pos     (27U)
2547 #define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
2548 #define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
2549 
2550 /******************  Bit definition for CAN_FFA1R register  *******************/
2551 #define CAN_FFA1R_FFA_Pos      (0U)
2552 #define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
2553 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
2554 #define CAN_FFA1R_FFA0_Pos     (0U)
2555 #define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
2556 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
2557 #define CAN_FFA1R_FFA1_Pos     (1U)
2558 #define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
2559 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
2560 #define CAN_FFA1R_FFA2_Pos     (2U)
2561 #define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
2562 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
2563 #define CAN_FFA1R_FFA3_Pos     (3U)
2564 #define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
2565 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
2566 #define CAN_FFA1R_FFA4_Pos     (4U)
2567 #define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
2568 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
2569 #define CAN_FFA1R_FFA5_Pos     (5U)
2570 #define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
2571 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
2572 #define CAN_FFA1R_FFA6_Pos     (6U)
2573 #define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
2574 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
2575 #define CAN_FFA1R_FFA7_Pos     (7U)
2576 #define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
2577 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
2578 #define CAN_FFA1R_FFA8_Pos     (8U)
2579 #define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
2580 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
2581 #define CAN_FFA1R_FFA9_Pos     (9U)
2582 #define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
2583 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
2584 #define CAN_FFA1R_FFA10_Pos    (10U)
2585 #define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
2586 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
2587 #define CAN_FFA1R_FFA11_Pos    (11U)
2588 #define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
2589 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
2590 #define CAN_FFA1R_FFA12_Pos    (12U)
2591 #define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
2592 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
2593 #define CAN_FFA1R_FFA13_Pos    (13U)
2594 #define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
2595 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
2596 #define CAN_FFA1R_FFA14_Pos    (14U)
2597 #define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
2598 #define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
2599 #define CAN_FFA1R_FFA15_Pos    (15U)
2600 #define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
2601 #define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
2602 #define CAN_FFA1R_FFA16_Pos    (16U)
2603 #define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
2604 #define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
2605 #define CAN_FFA1R_FFA17_Pos    (17U)
2606 #define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
2607 #define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
2608 #define CAN_FFA1R_FFA18_Pos    (18U)
2609 #define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
2610 #define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
2611 #define CAN_FFA1R_FFA19_Pos    (19U)
2612 #define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
2613 #define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
2614 #define CAN_FFA1R_FFA20_Pos    (20U)
2615 #define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
2616 #define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
2617 #define CAN_FFA1R_FFA21_Pos    (21U)
2618 #define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
2619 #define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
2620 #define CAN_FFA1R_FFA22_Pos    (22U)
2621 #define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
2622 #define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
2623 #define CAN_FFA1R_FFA23_Pos    (23U)
2624 #define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
2625 #define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
2626 #define CAN_FFA1R_FFA24_Pos    (24U)
2627 #define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
2628 #define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
2629 #define CAN_FFA1R_FFA25_Pos    (25U)
2630 #define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
2631 #define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
2632 #define CAN_FFA1R_FFA26_Pos    (26U)
2633 #define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
2634 #define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
2635 #define CAN_FFA1R_FFA27_Pos    (27U)
2636 #define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
2637 #define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
2638 
2639 /*******************  Bit definition for CAN_FA1R register  *******************/
2640 #define CAN_FA1R_FACT_Pos      (0U)
2641 #define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
2642 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
2643 #define CAN_FA1R_FACT0_Pos     (0U)
2644 #define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
2645 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
2646 #define CAN_FA1R_FACT1_Pos     (1U)
2647 #define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
2648 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
2649 #define CAN_FA1R_FACT2_Pos     (2U)
2650 #define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
2651 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
2652 #define CAN_FA1R_FACT3_Pos     (3U)
2653 #define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
2654 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
2655 #define CAN_FA1R_FACT4_Pos     (4U)
2656 #define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
2657 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
2658 #define CAN_FA1R_FACT5_Pos     (5U)
2659 #define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
2660 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
2661 #define CAN_FA1R_FACT6_Pos     (6U)
2662 #define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
2663 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
2664 #define CAN_FA1R_FACT7_Pos     (7U)
2665 #define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
2666 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
2667 #define CAN_FA1R_FACT8_Pos     (8U)
2668 #define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
2669 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
2670 #define CAN_FA1R_FACT9_Pos     (9U)
2671 #define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
2672 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
2673 #define CAN_FA1R_FACT10_Pos    (10U)
2674 #define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
2675 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
2676 #define CAN_FA1R_FACT11_Pos    (11U)
2677 #define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
2678 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
2679 #define CAN_FA1R_FACT12_Pos    (12U)
2680 #define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
2681 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
2682 #define CAN_FA1R_FACT13_Pos    (13U)
2683 #define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
2684 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
2685 #define CAN_FA1R_FACT14_Pos    (14U)
2686 #define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
2687 #define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
2688 #define CAN_FA1R_FACT15_Pos    (15U)
2689 #define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
2690 #define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
2691 #define CAN_FA1R_FACT16_Pos    (16U)
2692 #define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
2693 #define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
2694 #define CAN_FA1R_FACT17_Pos    (17U)
2695 #define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
2696 #define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
2697 #define CAN_FA1R_FACT18_Pos    (18U)
2698 #define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
2699 #define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
2700 #define CAN_FA1R_FACT19_Pos    (19U)
2701 #define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
2702 #define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
2703 #define CAN_FA1R_FACT20_Pos    (20U)
2704 #define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
2705 #define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
2706 #define CAN_FA1R_FACT21_Pos    (21U)
2707 #define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
2708 #define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
2709 #define CAN_FA1R_FACT22_Pos    (22U)
2710 #define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
2711 #define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
2712 #define CAN_FA1R_FACT23_Pos    (23U)
2713 #define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
2714 #define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
2715 #define CAN_FA1R_FACT24_Pos    (24U)
2716 #define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
2717 #define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
2718 #define CAN_FA1R_FACT25_Pos    (25U)
2719 #define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
2720 #define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
2721 #define CAN_FA1R_FACT26_Pos    (26U)
2722 #define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
2723 #define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
2724 #define CAN_FA1R_FACT27_Pos    (27U)
2725 #define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
2726 #define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
2727 
2728 /*******************  Bit definition for CAN_F0R1 register  *******************/
2729 #define CAN_F0R1_FB0_Pos       (0U)
2730 #define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
2731 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
2732 #define CAN_F0R1_FB1_Pos       (1U)
2733 #define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
2734 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
2735 #define CAN_F0R1_FB2_Pos       (2U)
2736 #define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
2737 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
2738 #define CAN_F0R1_FB3_Pos       (3U)
2739 #define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
2740 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
2741 #define CAN_F0R1_FB4_Pos       (4U)
2742 #define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
2743 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
2744 #define CAN_F0R1_FB5_Pos       (5U)
2745 #define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
2746 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
2747 #define CAN_F0R1_FB6_Pos       (6U)
2748 #define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
2749 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
2750 #define CAN_F0R1_FB7_Pos       (7U)
2751 #define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
2752 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
2753 #define CAN_F0R1_FB8_Pos       (8U)
2754 #define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
2755 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
2756 #define CAN_F0R1_FB9_Pos       (9U)
2757 #define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
2758 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
2759 #define CAN_F0R1_FB10_Pos      (10U)
2760 #define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
2761 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
2762 #define CAN_F0R1_FB11_Pos      (11U)
2763 #define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
2764 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
2765 #define CAN_F0R1_FB12_Pos      (12U)
2766 #define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
2767 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
2768 #define CAN_F0R1_FB13_Pos      (13U)
2769 #define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
2770 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
2771 #define CAN_F0R1_FB14_Pos      (14U)
2772 #define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
2773 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
2774 #define CAN_F0R1_FB15_Pos      (15U)
2775 #define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
2776 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
2777 #define CAN_F0R1_FB16_Pos      (16U)
2778 #define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
2779 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
2780 #define CAN_F0R1_FB17_Pos      (17U)
2781 #define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
2782 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
2783 #define CAN_F0R1_FB18_Pos      (18U)
2784 #define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
2785 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
2786 #define CAN_F0R1_FB19_Pos      (19U)
2787 #define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
2788 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
2789 #define CAN_F0R1_FB20_Pos      (20U)
2790 #define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
2791 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
2792 #define CAN_F0R1_FB21_Pos      (21U)
2793 #define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
2794 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
2795 #define CAN_F0R1_FB22_Pos      (22U)
2796 #define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
2797 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
2798 #define CAN_F0R1_FB23_Pos      (23U)
2799 #define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
2800 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
2801 #define CAN_F0R1_FB24_Pos      (24U)
2802 #define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
2803 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
2804 #define CAN_F0R1_FB25_Pos      (25U)
2805 #define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
2806 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
2807 #define CAN_F0R1_FB26_Pos      (26U)
2808 #define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
2809 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
2810 #define CAN_F0R1_FB27_Pos      (27U)
2811 #define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
2812 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
2813 #define CAN_F0R1_FB28_Pos      (28U)
2814 #define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
2815 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
2816 #define CAN_F0R1_FB29_Pos      (29U)
2817 #define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
2818 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
2819 #define CAN_F0R1_FB30_Pos      (30U)
2820 #define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
2821 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
2822 #define CAN_F0R1_FB31_Pos      (31U)
2823 #define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
2824 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
2825 
2826 /*******************  Bit definition for CAN_F1R1 register  *******************/
2827 #define CAN_F1R1_FB0_Pos       (0U)
2828 #define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
2829 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
2830 #define CAN_F1R1_FB1_Pos       (1U)
2831 #define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
2832 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
2833 #define CAN_F1R1_FB2_Pos       (2U)
2834 #define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
2835 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
2836 #define CAN_F1R1_FB3_Pos       (3U)
2837 #define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
2838 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
2839 #define CAN_F1R1_FB4_Pos       (4U)
2840 #define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
2841 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
2842 #define CAN_F1R1_FB5_Pos       (5U)
2843 #define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
2844 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
2845 #define CAN_F1R1_FB6_Pos       (6U)
2846 #define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
2847 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
2848 #define CAN_F1R1_FB7_Pos       (7U)
2849 #define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
2850 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
2851 #define CAN_F1R1_FB8_Pos       (8U)
2852 #define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
2853 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
2854 #define CAN_F1R1_FB9_Pos       (9U)
2855 #define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
2856 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
2857 #define CAN_F1R1_FB10_Pos      (10U)
2858 #define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
2859 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
2860 #define CAN_F1R1_FB11_Pos      (11U)
2861 #define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
2862 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
2863 #define CAN_F1R1_FB12_Pos      (12U)
2864 #define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
2865 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
2866 #define CAN_F1R1_FB13_Pos      (13U)
2867 #define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
2868 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
2869 #define CAN_F1R1_FB14_Pos      (14U)
2870 #define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
2871 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
2872 #define CAN_F1R1_FB15_Pos      (15U)
2873 #define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
2874 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
2875 #define CAN_F1R1_FB16_Pos      (16U)
2876 #define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
2877 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
2878 #define CAN_F1R1_FB17_Pos      (17U)
2879 #define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
2880 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
2881 #define CAN_F1R1_FB18_Pos      (18U)
2882 #define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
2883 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
2884 #define CAN_F1R1_FB19_Pos      (19U)
2885 #define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
2886 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
2887 #define CAN_F1R1_FB20_Pos      (20U)
2888 #define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
2889 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
2890 #define CAN_F1R1_FB21_Pos      (21U)
2891 #define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
2892 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
2893 #define CAN_F1R1_FB22_Pos      (22U)
2894 #define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
2895 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
2896 #define CAN_F1R1_FB23_Pos      (23U)
2897 #define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
2898 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
2899 #define CAN_F1R1_FB24_Pos      (24U)
2900 #define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
2901 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
2902 #define CAN_F1R1_FB25_Pos      (25U)
2903 #define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
2904 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
2905 #define CAN_F1R1_FB26_Pos      (26U)
2906 #define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
2907 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
2908 #define CAN_F1R1_FB27_Pos      (27U)
2909 #define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
2910 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
2911 #define CAN_F1R1_FB28_Pos      (28U)
2912 #define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
2913 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
2914 #define CAN_F1R1_FB29_Pos      (29U)
2915 #define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
2916 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
2917 #define CAN_F1R1_FB30_Pos      (30U)
2918 #define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
2919 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
2920 #define CAN_F1R1_FB31_Pos      (31U)
2921 #define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
2922 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
2923 
2924 /*******************  Bit definition for CAN_F2R1 register  *******************/
2925 #define CAN_F2R1_FB0_Pos       (0U)
2926 #define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
2927 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
2928 #define CAN_F2R1_FB1_Pos       (1U)
2929 #define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
2930 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
2931 #define CAN_F2R1_FB2_Pos       (2U)
2932 #define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
2933 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
2934 #define CAN_F2R1_FB3_Pos       (3U)
2935 #define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
2936 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
2937 #define CAN_F2R1_FB4_Pos       (4U)
2938 #define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
2939 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
2940 #define CAN_F2R1_FB5_Pos       (5U)
2941 #define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
2942 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
2943 #define CAN_F2R1_FB6_Pos       (6U)
2944 #define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
2945 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
2946 #define CAN_F2R1_FB7_Pos       (7U)
2947 #define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
2948 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
2949 #define CAN_F2R1_FB8_Pos       (8U)
2950 #define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
2951 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
2952 #define CAN_F2R1_FB9_Pos       (9U)
2953 #define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
2954 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
2955 #define CAN_F2R1_FB10_Pos      (10U)
2956 #define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
2957 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
2958 #define CAN_F2R1_FB11_Pos      (11U)
2959 #define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
2960 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
2961 #define CAN_F2R1_FB12_Pos      (12U)
2962 #define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
2963 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
2964 #define CAN_F2R1_FB13_Pos      (13U)
2965 #define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
2966 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
2967 #define CAN_F2R1_FB14_Pos      (14U)
2968 #define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
2969 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
2970 #define CAN_F2R1_FB15_Pos      (15U)
2971 #define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
2972 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
2973 #define CAN_F2R1_FB16_Pos      (16U)
2974 #define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
2975 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
2976 #define CAN_F2R1_FB17_Pos      (17U)
2977 #define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
2978 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
2979 #define CAN_F2R1_FB18_Pos      (18U)
2980 #define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
2981 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
2982 #define CAN_F2R1_FB19_Pos      (19U)
2983 #define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
2984 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
2985 #define CAN_F2R1_FB20_Pos      (20U)
2986 #define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
2987 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
2988 #define CAN_F2R1_FB21_Pos      (21U)
2989 #define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
2990 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
2991 #define CAN_F2R1_FB22_Pos      (22U)
2992 #define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
2993 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
2994 #define CAN_F2R1_FB23_Pos      (23U)
2995 #define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
2996 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
2997 #define CAN_F2R1_FB24_Pos      (24U)
2998 #define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
2999 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3000 #define CAN_F2R1_FB25_Pos      (25U)
3001 #define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
3002 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3003 #define CAN_F2R1_FB26_Pos      (26U)
3004 #define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
3005 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3006 #define CAN_F2R1_FB27_Pos      (27U)
3007 #define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
3008 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3009 #define CAN_F2R1_FB28_Pos      (28U)
3010 #define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
3011 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3012 #define CAN_F2R1_FB29_Pos      (29U)
3013 #define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
3014 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3015 #define CAN_F2R1_FB30_Pos      (30U)
3016 #define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
3017 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3018 #define CAN_F2R1_FB31_Pos      (31U)
3019 #define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
3020 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3021 
3022 /*******************  Bit definition for CAN_F3R1 register  *******************/
3023 #define CAN_F3R1_FB0_Pos       (0U)
3024 #define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
3025 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3026 #define CAN_F3R1_FB1_Pos       (1U)
3027 #define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
3028 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3029 #define CAN_F3R1_FB2_Pos       (2U)
3030 #define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
3031 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3032 #define CAN_F3R1_FB3_Pos       (3U)
3033 #define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
3034 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3035 #define CAN_F3R1_FB4_Pos       (4U)
3036 #define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
3037 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3038 #define CAN_F3R1_FB5_Pos       (5U)
3039 #define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
3040 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3041 #define CAN_F3R1_FB6_Pos       (6U)
3042 #define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3043 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3044 #define CAN_F3R1_FB7_Pos       (7U)
3045 #define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3046 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3047 #define CAN_F3R1_FB8_Pos       (8U)
3048 #define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3049 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3050 #define CAN_F3R1_FB9_Pos       (9U)
3051 #define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3052 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3053 #define CAN_F3R1_FB10_Pos      (10U)
3054 #define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3055 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3056 #define CAN_F3R1_FB11_Pos      (11U)
3057 #define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3058 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3059 #define CAN_F3R1_FB12_Pos      (12U)
3060 #define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3061 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3062 #define CAN_F3R1_FB13_Pos      (13U)
3063 #define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3064 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3065 #define CAN_F3R1_FB14_Pos      (14U)
3066 #define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3067 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3068 #define CAN_F3R1_FB15_Pos      (15U)
3069 #define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3070 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3071 #define CAN_F3R1_FB16_Pos      (16U)
3072 #define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3073 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3074 #define CAN_F3R1_FB17_Pos      (17U)
3075 #define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3076 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3077 #define CAN_F3R1_FB18_Pos      (18U)
3078 #define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3079 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3080 #define CAN_F3R1_FB19_Pos      (19U)
3081 #define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3082 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3083 #define CAN_F3R1_FB20_Pos      (20U)
3084 #define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3085 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3086 #define CAN_F3R1_FB21_Pos      (21U)
3087 #define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3088 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3089 #define CAN_F3R1_FB22_Pos      (22U)
3090 #define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3091 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3092 #define CAN_F3R1_FB23_Pos      (23U)
3093 #define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3094 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3095 #define CAN_F3R1_FB24_Pos      (24U)
3096 #define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3097 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3098 #define CAN_F3R1_FB25_Pos      (25U)
3099 #define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3100 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3101 #define CAN_F3R1_FB26_Pos      (26U)
3102 #define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3103 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3104 #define CAN_F3R1_FB27_Pos      (27U)
3105 #define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3106 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3107 #define CAN_F3R1_FB28_Pos      (28U)
3108 #define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3109 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3110 #define CAN_F3R1_FB29_Pos      (29U)
3111 #define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3112 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3113 #define CAN_F3R1_FB30_Pos      (30U)
3114 #define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3115 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3116 #define CAN_F3R1_FB31_Pos      (31U)
3117 #define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3118 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3119 
3120 /*******************  Bit definition for CAN_F4R1 register  *******************/
3121 #define CAN_F4R1_FB0_Pos       (0U)
3122 #define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3123 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3124 #define CAN_F4R1_FB1_Pos       (1U)
3125 #define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3126 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3127 #define CAN_F4R1_FB2_Pos       (2U)
3128 #define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3129 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3130 #define CAN_F4R1_FB3_Pos       (3U)
3131 #define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3132 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3133 #define CAN_F4R1_FB4_Pos       (4U)
3134 #define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3135 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3136 #define CAN_F4R1_FB5_Pos       (5U)
3137 #define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3138 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3139 #define CAN_F4R1_FB6_Pos       (6U)
3140 #define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3141 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3142 #define CAN_F4R1_FB7_Pos       (7U)
3143 #define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3144 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3145 #define CAN_F4R1_FB8_Pos       (8U)
3146 #define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3147 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3148 #define CAN_F4R1_FB9_Pos       (9U)
3149 #define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3150 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3151 #define CAN_F4R1_FB10_Pos      (10U)
3152 #define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3153 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3154 #define CAN_F4R1_FB11_Pos      (11U)
3155 #define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3156 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3157 #define CAN_F4R1_FB12_Pos      (12U)
3158 #define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3159 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3160 #define CAN_F4R1_FB13_Pos      (13U)
3161 #define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3162 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3163 #define CAN_F4R1_FB14_Pos      (14U)
3164 #define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3165 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3166 #define CAN_F4R1_FB15_Pos      (15U)
3167 #define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3168 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3169 #define CAN_F4R1_FB16_Pos      (16U)
3170 #define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3171 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3172 #define CAN_F4R1_FB17_Pos      (17U)
3173 #define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3174 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3175 #define CAN_F4R1_FB18_Pos      (18U)
3176 #define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3177 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3178 #define CAN_F4R1_FB19_Pos      (19U)
3179 #define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3180 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3181 #define CAN_F4R1_FB20_Pos      (20U)
3182 #define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3183 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3184 #define CAN_F4R1_FB21_Pos      (21U)
3185 #define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3186 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3187 #define CAN_F4R1_FB22_Pos      (22U)
3188 #define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3189 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3190 #define CAN_F4R1_FB23_Pos      (23U)
3191 #define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3192 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3193 #define CAN_F4R1_FB24_Pos      (24U)
3194 #define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3195 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3196 #define CAN_F4R1_FB25_Pos      (25U)
3197 #define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3198 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3199 #define CAN_F4R1_FB26_Pos      (26U)
3200 #define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3201 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3202 #define CAN_F4R1_FB27_Pos      (27U)
3203 #define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
3204 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
3205 #define CAN_F4R1_FB28_Pos      (28U)
3206 #define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
3207 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
3208 #define CAN_F4R1_FB29_Pos      (29U)
3209 #define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
3210 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
3211 #define CAN_F4R1_FB30_Pos      (30U)
3212 #define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
3213 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
3214 #define CAN_F4R1_FB31_Pos      (31U)
3215 #define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
3216 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
3217 
3218 /*******************  Bit definition for CAN_F5R1 register  *******************/
3219 #define CAN_F5R1_FB0_Pos       (0U)
3220 #define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
3221 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
3222 #define CAN_F5R1_FB1_Pos       (1U)
3223 #define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
3224 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
3225 #define CAN_F5R1_FB2_Pos       (2U)
3226 #define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
3227 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
3228 #define CAN_F5R1_FB3_Pos       (3U)
3229 #define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
3230 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
3231 #define CAN_F5R1_FB4_Pos       (4U)
3232 #define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
3233 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
3234 #define CAN_F5R1_FB5_Pos       (5U)
3235 #define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
3236 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
3237 #define CAN_F5R1_FB6_Pos       (6U)
3238 #define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
3239 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
3240 #define CAN_F5R1_FB7_Pos       (7U)
3241 #define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
3242 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
3243 #define CAN_F5R1_FB8_Pos       (8U)
3244 #define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
3245 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
3246 #define CAN_F5R1_FB9_Pos       (9U)
3247 #define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
3248 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
3249 #define CAN_F5R1_FB10_Pos      (10U)
3250 #define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
3251 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
3252 #define CAN_F5R1_FB11_Pos      (11U)
3253 #define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
3254 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
3255 #define CAN_F5R1_FB12_Pos      (12U)
3256 #define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
3257 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
3258 #define CAN_F5R1_FB13_Pos      (13U)
3259 #define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
3260 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
3261 #define CAN_F5R1_FB14_Pos      (14U)
3262 #define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
3263 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
3264 #define CAN_F5R1_FB15_Pos      (15U)
3265 #define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
3266 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
3267 #define CAN_F5R1_FB16_Pos      (16U)
3268 #define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
3269 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
3270 #define CAN_F5R1_FB17_Pos      (17U)
3271 #define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
3272 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
3273 #define CAN_F5R1_FB18_Pos      (18U)
3274 #define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
3275 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
3276 #define CAN_F5R1_FB19_Pos      (19U)
3277 #define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
3278 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
3279 #define CAN_F5R1_FB20_Pos      (20U)
3280 #define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
3281 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
3282 #define CAN_F5R1_FB21_Pos      (21U)
3283 #define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
3284 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
3285 #define CAN_F5R1_FB22_Pos      (22U)
3286 #define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
3287 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
3288 #define CAN_F5R1_FB23_Pos      (23U)
3289 #define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
3290 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
3291 #define CAN_F5R1_FB24_Pos      (24U)
3292 #define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
3293 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
3294 #define CAN_F5R1_FB25_Pos      (25U)
3295 #define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
3296 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
3297 #define CAN_F5R1_FB26_Pos      (26U)
3298 #define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
3299 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
3300 #define CAN_F5R1_FB27_Pos      (27U)
3301 #define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
3302 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
3303 #define CAN_F5R1_FB28_Pos      (28U)
3304 #define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
3305 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
3306 #define CAN_F5R1_FB29_Pos      (29U)
3307 #define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
3308 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
3309 #define CAN_F5R1_FB30_Pos      (30U)
3310 #define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
3311 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
3312 #define CAN_F5R1_FB31_Pos      (31U)
3313 #define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
3314 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
3315 
3316 /*******************  Bit definition for CAN_F6R1 register  *******************/
3317 #define CAN_F6R1_FB0_Pos       (0U)
3318 #define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
3319 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
3320 #define CAN_F6R1_FB1_Pos       (1U)
3321 #define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
3322 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
3323 #define CAN_F6R1_FB2_Pos       (2U)
3324 #define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
3325 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
3326 #define CAN_F6R1_FB3_Pos       (3U)
3327 #define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
3328 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
3329 #define CAN_F6R1_FB4_Pos       (4U)
3330 #define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
3331 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
3332 #define CAN_F6R1_FB5_Pos       (5U)
3333 #define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
3334 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
3335 #define CAN_F6R1_FB6_Pos       (6U)
3336 #define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
3337 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
3338 #define CAN_F6R1_FB7_Pos       (7U)
3339 #define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
3340 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
3341 #define CAN_F6R1_FB8_Pos       (8U)
3342 #define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
3343 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
3344 #define CAN_F6R1_FB9_Pos       (9U)
3345 #define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
3346 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
3347 #define CAN_F6R1_FB10_Pos      (10U)
3348 #define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
3349 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
3350 #define CAN_F6R1_FB11_Pos      (11U)
3351 #define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
3352 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
3353 #define CAN_F6R1_FB12_Pos      (12U)
3354 #define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
3355 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
3356 #define CAN_F6R1_FB13_Pos      (13U)
3357 #define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
3358 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
3359 #define CAN_F6R1_FB14_Pos      (14U)
3360 #define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
3361 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
3362 #define CAN_F6R1_FB15_Pos      (15U)
3363 #define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
3364 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
3365 #define CAN_F6R1_FB16_Pos      (16U)
3366 #define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
3367 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
3368 #define CAN_F6R1_FB17_Pos      (17U)
3369 #define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
3370 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
3371 #define CAN_F6R1_FB18_Pos      (18U)
3372 #define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
3373 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
3374 #define CAN_F6R1_FB19_Pos      (19U)
3375 #define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
3376 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
3377 #define CAN_F6R1_FB20_Pos      (20U)
3378 #define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
3379 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
3380 #define CAN_F6R1_FB21_Pos      (21U)
3381 #define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
3382 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
3383 #define CAN_F6R1_FB22_Pos      (22U)
3384 #define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
3385 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
3386 #define CAN_F6R1_FB23_Pos      (23U)
3387 #define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
3388 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
3389 #define CAN_F6R1_FB24_Pos      (24U)
3390 #define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
3391 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
3392 #define CAN_F6R1_FB25_Pos      (25U)
3393 #define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
3394 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
3395 #define CAN_F6R1_FB26_Pos      (26U)
3396 #define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
3397 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
3398 #define CAN_F6R1_FB27_Pos      (27U)
3399 #define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
3400 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
3401 #define CAN_F6R1_FB28_Pos      (28U)
3402 #define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
3403 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
3404 #define CAN_F6R1_FB29_Pos      (29U)
3405 #define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
3406 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
3407 #define CAN_F6R1_FB30_Pos      (30U)
3408 #define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
3409 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
3410 #define CAN_F6R1_FB31_Pos      (31U)
3411 #define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
3412 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
3413 
3414 /*******************  Bit definition for CAN_F7R1 register  *******************/
3415 #define CAN_F7R1_FB0_Pos       (0U)
3416 #define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
3417 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
3418 #define CAN_F7R1_FB1_Pos       (1U)
3419 #define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
3420 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
3421 #define CAN_F7R1_FB2_Pos       (2U)
3422 #define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
3423 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
3424 #define CAN_F7R1_FB3_Pos       (3U)
3425 #define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
3426 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
3427 #define CAN_F7R1_FB4_Pos       (4U)
3428 #define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
3429 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
3430 #define CAN_F7R1_FB5_Pos       (5U)
3431 #define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
3432 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
3433 #define CAN_F7R1_FB6_Pos       (6U)
3434 #define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
3435 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
3436 #define CAN_F7R1_FB7_Pos       (7U)
3437 #define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
3438 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
3439 #define CAN_F7R1_FB8_Pos       (8U)
3440 #define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
3441 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
3442 #define CAN_F7R1_FB9_Pos       (9U)
3443 #define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
3444 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
3445 #define CAN_F7R1_FB10_Pos      (10U)
3446 #define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
3447 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
3448 #define CAN_F7R1_FB11_Pos      (11U)
3449 #define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
3450 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
3451 #define CAN_F7R1_FB12_Pos      (12U)
3452 #define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
3453 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
3454 #define CAN_F7R1_FB13_Pos      (13U)
3455 #define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
3456 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
3457 #define CAN_F7R1_FB14_Pos      (14U)
3458 #define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
3459 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
3460 #define CAN_F7R1_FB15_Pos      (15U)
3461 #define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
3462 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
3463 #define CAN_F7R1_FB16_Pos      (16U)
3464 #define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
3465 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
3466 #define CAN_F7R1_FB17_Pos      (17U)
3467 #define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
3468 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
3469 #define CAN_F7R1_FB18_Pos      (18U)
3470 #define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
3471 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
3472 #define CAN_F7R1_FB19_Pos      (19U)
3473 #define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
3474 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
3475 #define CAN_F7R1_FB20_Pos      (20U)
3476 #define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
3477 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
3478 #define CAN_F7R1_FB21_Pos      (21U)
3479 #define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
3480 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
3481 #define CAN_F7R1_FB22_Pos      (22U)
3482 #define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
3483 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
3484 #define CAN_F7R1_FB23_Pos      (23U)
3485 #define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
3486 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
3487 #define CAN_F7R1_FB24_Pos      (24U)
3488 #define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
3489 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
3490 #define CAN_F7R1_FB25_Pos      (25U)
3491 #define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
3492 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
3493 #define CAN_F7R1_FB26_Pos      (26U)
3494 #define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
3495 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
3496 #define CAN_F7R1_FB27_Pos      (27U)
3497 #define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
3498 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
3499 #define CAN_F7R1_FB28_Pos      (28U)
3500 #define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
3501 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
3502 #define CAN_F7R1_FB29_Pos      (29U)
3503 #define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
3504 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
3505 #define CAN_F7R1_FB30_Pos      (30U)
3506 #define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
3507 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
3508 #define CAN_F7R1_FB31_Pos      (31U)
3509 #define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
3510 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
3511 
3512 /*******************  Bit definition for CAN_F8R1 register  *******************/
3513 #define CAN_F8R1_FB0_Pos       (0U)
3514 #define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
3515 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
3516 #define CAN_F8R1_FB1_Pos       (1U)
3517 #define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
3518 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
3519 #define CAN_F8R1_FB2_Pos       (2U)
3520 #define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
3521 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
3522 #define CAN_F8R1_FB3_Pos       (3U)
3523 #define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
3524 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
3525 #define CAN_F8R1_FB4_Pos       (4U)
3526 #define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
3527 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
3528 #define CAN_F8R1_FB5_Pos       (5U)
3529 #define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
3530 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
3531 #define CAN_F8R1_FB6_Pos       (6U)
3532 #define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
3533 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
3534 #define CAN_F8R1_FB7_Pos       (7U)
3535 #define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
3536 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
3537 #define CAN_F8R1_FB8_Pos       (8U)
3538 #define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
3539 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
3540 #define CAN_F8R1_FB9_Pos       (9U)
3541 #define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
3542 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
3543 #define CAN_F8R1_FB10_Pos      (10U)
3544 #define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
3545 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
3546 #define CAN_F8R1_FB11_Pos      (11U)
3547 #define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
3548 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
3549 #define CAN_F8R1_FB12_Pos      (12U)
3550 #define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
3551 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
3552 #define CAN_F8R1_FB13_Pos      (13U)
3553 #define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
3554 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
3555 #define CAN_F8R1_FB14_Pos      (14U)
3556 #define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
3557 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
3558 #define CAN_F8R1_FB15_Pos      (15U)
3559 #define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
3560 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
3561 #define CAN_F8R1_FB16_Pos      (16U)
3562 #define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
3563 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
3564 #define CAN_F8R1_FB17_Pos      (17U)
3565 #define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
3566 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
3567 #define CAN_F8R1_FB18_Pos      (18U)
3568 #define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
3569 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
3570 #define CAN_F8R1_FB19_Pos      (19U)
3571 #define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
3572 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
3573 #define CAN_F8R1_FB20_Pos      (20U)
3574 #define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
3575 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
3576 #define CAN_F8R1_FB21_Pos      (21U)
3577 #define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
3578 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
3579 #define CAN_F8R1_FB22_Pos      (22U)
3580 #define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
3581 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
3582 #define CAN_F8R1_FB23_Pos      (23U)
3583 #define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
3584 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
3585 #define CAN_F8R1_FB24_Pos      (24U)
3586 #define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
3587 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
3588 #define CAN_F8R1_FB25_Pos      (25U)
3589 #define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
3590 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
3591 #define CAN_F8R1_FB26_Pos      (26U)
3592 #define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
3593 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
3594 #define CAN_F8R1_FB27_Pos      (27U)
3595 #define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
3596 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
3597 #define CAN_F8R1_FB28_Pos      (28U)
3598 #define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
3599 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
3600 #define CAN_F8R1_FB29_Pos      (29U)
3601 #define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
3602 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
3603 #define CAN_F8R1_FB30_Pos      (30U)
3604 #define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
3605 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
3606 #define CAN_F8R1_FB31_Pos      (31U)
3607 #define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
3608 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
3609 
3610 /*******************  Bit definition for CAN_F9R1 register  *******************/
3611 #define CAN_F9R1_FB0_Pos       (0U)
3612 #define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
3613 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
3614 #define CAN_F9R1_FB1_Pos       (1U)
3615 #define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
3616 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
3617 #define CAN_F9R1_FB2_Pos       (2U)
3618 #define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
3619 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
3620 #define CAN_F9R1_FB3_Pos       (3U)
3621 #define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
3622 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
3623 #define CAN_F9R1_FB4_Pos       (4U)
3624 #define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
3625 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
3626 #define CAN_F9R1_FB5_Pos       (5U)
3627 #define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
3628 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
3629 #define CAN_F9R1_FB6_Pos       (6U)
3630 #define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
3631 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
3632 #define CAN_F9R1_FB7_Pos       (7U)
3633 #define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
3634 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
3635 #define CAN_F9R1_FB8_Pos       (8U)
3636 #define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
3637 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
3638 #define CAN_F9R1_FB9_Pos       (9U)
3639 #define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
3640 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
3641 #define CAN_F9R1_FB10_Pos      (10U)
3642 #define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
3643 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
3644 #define CAN_F9R1_FB11_Pos      (11U)
3645 #define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
3646 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
3647 #define CAN_F9R1_FB12_Pos      (12U)
3648 #define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
3649 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
3650 #define CAN_F9R1_FB13_Pos      (13U)
3651 #define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
3652 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
3653 #define CAN_F9R1_FB14_Pos      (14U)
3654 #define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
3655 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
3656 #define CAN_F9R1_FB15_Pos      (15U)
3657 #define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
3658 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
3659 #define CAN_F9R1_FB16_Pos      (16U)
3660 #define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
3661 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
3662 #define CAN_F9R1_FB17_Pos      (17U)
3663 #define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
3664 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
3665 #define CAN_F9R1_FB18_Pos      (18U)
3666 #define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
3667 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
3668 #define CAN_F9R1_FB19_Pos      (19U)
3669 #define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
3670 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
3671 #define CAN_F9R1_FB20_Pos      (20U)
3672 #define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
3673 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
3674 #define CAN_F9R1_FB21_Pos      (21U)
3675 #define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
3676 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
3677 #define CAN_F9R1_FB22_Pos      (22U)
3678 #define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
3679 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
3680 #define CAN_F9R1_FB23_Pos      (23U)
3681 #define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
3682 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
3683 #define CAN_F9R1_FB24_Pos      (24U)
3684 #define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
3685 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
3686 #define CAN_F9R1_FB25_Pos      (25U)
3687 #define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
3688 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
3689 #define CAN_F9R1_FB26_Pos      (26U)
3690 #define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
3691 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
3692 #define CAN_F9R1_FB27_Pos      (27U)
3693 #define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
3694 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
3695 #define CAN_F9R1_FB28_Pos      (28U)
3696 #define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
3697 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
3698 #define CAN_F9R1_FB29_Pos      (29U)
3699 #define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
3700 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
3701 #define CAN_F9R1_FB30_Pos      (30U)
3702 #define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
3703 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
3704 #define CAN_F9R1_FB31_Pos      (31U)
3705 #define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
3706 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
3707 
3708 /*******************  Bit definition for CAN_F10R1 register  ******************/
3709 #define CAN_F10R1_FB0_Pos      (0U)
3710 #define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
3711 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
3712 #define CAN_F10R1_FB1_Pos      (1U)
3713 #define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
3714 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
3715 #define CAN_F10R1_FB2_Pos      (2U)
3716 #define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
3717 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
3718 #define CAN_F10R1_FB3_Pos      (3U)
3719 #define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
3720 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
3721 #define CAN_F10R1_FB4_Pos      (4U)
3722 #define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
3723 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
3724 #define CAN_F10R1_FB5_Pos      (5U)
3725 #define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
3726 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
3727 #define CAN_F10R1_FB6_Pos      (6U)
3728 #define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
3729 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
3730 #define CAN_F10R1_FB7_Pos      (7U)
3731 #define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
3732 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
3733 #define CAN_F10R1_FB8_Pos      (8U)
3734 #define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
3735 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
3736 #define CAN_F10R1_FB9_Pos      (9U)
3737 #define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
3738 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
3739 #define CAN_F10R1_FB10_Pos     (10U)
3740 #define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
3741 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
3742 #define CAN_F10R1_FB11_Pos     (11U)
3743 #define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
3744 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
3745 #define CAN_F10R1_FB12_Pos     (12U)
3746 #define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
3747 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
3748 #define CAN_F10R1_FB13_Pos     (13U)
3749 #define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
3750 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
3751 #define CAN_F10R1_FB14_Pos     (14U)
3752 #define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
3753 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
3754 #define CAN_F10R1_FB15_Pos     (15U)
3755 #define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
3756 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
3757 #define CAN_F10R1_FB16_Pos     (16U)
3758 #define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
3759 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
3760 #define CAN_F10R1_FB17_Pos     (17U)
3761 #define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
3762 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
3763 #define CAN_F10R1_FB18_Pos     (18U)
3764 #define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
3765 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
3766 #define CAN_F10R1_FB19_Pos     (19U)
3767 #define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
3768 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
3769 #define CAN_F10R1_FB20_Pos     (20U)
3770 #define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
3771 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
3772 #define CAN_F10R1_FB21_Pos     (21U)
3773 #define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
3774 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
3775 #define CAN_F10R1_FB22_Pos     (22U)
3776 #define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
3777 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
3778 #define CAN_F10R1_FB23_Pos     (23U)
3779 #define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
3780 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
3781 #define CAN_F10R1_FB24_Pos     (24U)
3782 #define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
3783 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
3784 #define CAN_F10R1_FB25_Pos     (25U)
3785 #define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
3786 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
3787 #define CAN_F10R1_FB26_Pos     (26U)
3788 #define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
3789 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
3790 #define CAN_F10R1_FB27_Pos     (27U)
3791 #define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
3792 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
3793 #define CAN_F10R1_FB28_Pos     (28U)
3794 #define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
3795 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
3796 #define CAN_F10R1_FB29_Pos     (29U)
3797 #define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
3798 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
3799 #define CAN_F10R1_FB30_Pos     (30U)
3800 #define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
3801 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
3802 #define CAN_F10R1_FB31_Pos     (31U)
3803 #define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
3804 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
3805 
3806 /*******************  Bit definition for CAN_F11R1 register  ******************/
3807 #define CAN_F11R1_FB0_Pos      (0U)
3808 #define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
3809 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
3810 #define CAN_F11R1_FB1_Pos      (1U)
3811 #define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
3812 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
3813 #define CAN_F11R1_FB2_Pos      (2U)
3814 #define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
3815 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
3816 #define CAN_F11R1_FB3_Pos      (3U)
3817 #define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
3818 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
3819 #define CAN_F11R1_FB4_Pos      (4U)
3820 #define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
3821 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
3822 #define CAN_F11R1_FB5_Pos      (5U)
3823 #define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
3824 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
3825 #define CAN_F11R1_FB6_Pos      (6U)
3826 #define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
3827 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
3828 #define CAN_F11R1_FB7_Pos      (7U)
3829 #define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
3830 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
3831 #define CAN_F11R1_FB8_Pos      (8U)
3832 #define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
3833 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
3834 #define CAN_F11R1_FB9_Pos      (9U)
3835 #define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
3836 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
3837 #define CAN_F11R1_FB10_Pos     (10U)
3838 #define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
3839 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
3840 #define CAN_F11R1_FB11_Pos     (11U)
3841 #define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
3842 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
3843 #define CAN_F11R1_FB12_Pos     (12U)
3844 #define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
3845 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
3846 #define CAN_F11R1_FB13_Pos     (13U)
3847 #define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
3848 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
3849 #define CAN_F11R1_FB14_Pos     (14U)
3850 #define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
3851 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
3852 #define CAN_F11R1_FB15_Pos     (15U)
3853 #define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
3854 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
3855 #define CAN_F11R1_FB16_Pos     (16U)
3856 #define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
3857 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
3858 #define CAN_F11R1_FB17_Pos     (17U)
3859 #define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
3860 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
3861 #define CAN_F11R1_FB18_Pos     (18U)
3862 #define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
3863 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
3864 #define CAN_F11R1_FB19_Pos     (19U)
3865 #define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
3866 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
3867 #define CAN_F11R1_FB20_Pos     (20U)
3868 #define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
3869 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
3870 #define CAN_F11R1_FB21_Pos     (21U)
3871 #define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
3872 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
3873 #define CAN_F11R1_FB22_Pos     (22U)
3874 #define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
3875 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
3876 #define CAN_F11R1_FB23_Pos     (23U)
3877 #define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
3878 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
3879 #define CAN_F11R1_FB24_Pos     (24U)
3880 #define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
3881 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
3882 #define CAN_F11R1_FB25_Pos     (25U)
3883 #define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
3884 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
3885 #define CAN_F11R1_FB26_Pos     (26U)
3886 #define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
3887 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
3888 #define CAN_F11R1_FB27_Pos     (27U)
3889 #define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
3890 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
3891 #define CAN_F11R1_FB28_Pos     (28U)
3892 #define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
3893 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
3894 #define CAN_F11R1_FB29_Pos     (29U)
3895 #define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
3896 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
3897 #define CAN_F11R1_FB30_Pos     (30U)
3898 #define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
3899 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
3900 #define CAN_F11R1_FB31_Pos     (31U)
3901 #define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
3902 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
3903 
3904 /*******************  Bit definition for CAN_F12R1 register  ******************/
3905 #define CAN_F12R1_FB0_Pos      (0U)
3906 #define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
3907 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
3908 #define CAN_F12R1_FB1_Pos      (1U)
3909 #define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
3910 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
3911 #define CAN_F12R1_FB2_Pos      (2U)
3912 #define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
3913 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
3914 #define CAN_F12R1_FB3_Pos      (3U)
3915 #define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
3916 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
3917 #define CAN_F12R1_FB4_Pos      (4U)
3918 #define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
3919 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
3920 #define CAN_F12R1_FB5_Pos      (5U)
3921 #define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
3922 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
3923 #define CAN_F12R1_FB6_Pos      (6U)
3924 #define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
3925 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
3926 #define CAN_F12R1_FB7_Pos      (7U)
3927 #define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
3928 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
3929 #define CAN_F12R1_FB8_Pos      (8U)
3930 #define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
3931 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
3932 #define CAN_F12R1_FB9_Pos      (9U)
3933 #define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
3934 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
3935 #define CAN_F12R1_FB10_Pos     (10U)
3936 #define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
3937 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
3938 #define CAN_F12R1_FB11_Pos     (11U)
3939 #define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
3940 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
3941 #define CAN_F12R1_FB12_Pos     (12U)
3942 #define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
3943 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
3944 #define CAN_F12R1_FB13_Pos     (13U)
3945 #define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
3946 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
3947 #define CAN_F12R1_FB14_Pos     (14U)
3948 #define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
3949 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
3950 #define CAN_F12R1_FB15_Pos     (15U)
3951 #define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
3952 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
3953 #define CAN_F12R1_FB16_Pos     (16U)
3954 #define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
3955 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
3956 #define CAN_F12R1_FB17_Pos     (17U)
3957 #define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
3958 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
3959 #define CAN_F12R1_FB18_Pos     (18U)
3960 #define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
3961 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
3962 #define CAN_F12R1_FB19_Pos     (19U)
3963 #define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
3964 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
3965 #define CAN_F12R1_FB20_Pos     (20U)
3966 #define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
3967 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
3968 #define CAN_F12R1_FB21_Pos     (21U)
3969 #define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
3970 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
3971 #define CAN_F12R1_FB22_Pos     (22U)
3972 #define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
3973 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
3974 #define CAN_F12R1_FB23_Pos     (23U)
3975 #define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
3976 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
3977 #define CAN_F12R1_FB24_Pos     (24U)
3978 #define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
3979 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
3980 #define CAN_F12R1_FB25_Pos     (25U)
3981 #define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
3982 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
3983 #define CAN_F12R1_FB26_Pos     (26U)
3984 #define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
3985 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
3986 #define CAN_F12R1_FB27_Pos     (27U)
3987 #define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
3988 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
3989 #define CAN_F12R1_FB28_Pos     (28U)
3990 #define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
3991 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
3992 #define CAN_F12R1_FB29_Pos     (29U)
3993 #define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
3994 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
3995 #define CAN_F12R1_FB30_Pos     (30U)
3996 #define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
3997 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
3998 #define CAN_F12R1_FB31_Pos     (31U)
3999 #define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
4000 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4001 
4002 /*******************  Bit definition for CAN_F13R1 register  ******************/
4003 #define CAN_F13R1_FB0_Pos      (0U)
4004 #define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
4005 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4006 #define CAN_F13R1_FB1_Pos      (1U)
4007 #define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
4008 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4009 #define CAN_F13R1_FB2_Pos      (2U)
4010 #define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
4011 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4012 #define CAN_F13R1_FB3_Pos      (3U)
4013 #define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
4014 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4015 #define CAN_F13R1_FB4_Pos      (4U)
4016 #define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
4017 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4018 #define CAN_F13R1_FB5_Pos      (5U)
4019 #define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
4020 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4021 #define CAN_F13R1_FB6_Pos      (6U)
4022 #define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
4023 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4024 #define CAN_F13R1_FB7_Pos      (7U)
4025 #define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
4026 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4027 #define CAN_F13R1_FB8_Pos      (8U)
4028 #define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
4029 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4030 #define CAN_F13R1_FB9_Pos      (9U)
4031 #define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
4032 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4033 #define CAN_F13R1_FB10_Pos     (10U)
4034 #define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
4035 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4036 #define CAN_F13R1_FB11_Pos     (11U)
4037 #define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
4038 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4039 #define CAN_F13R1_FB12_Pos     (12U)
4040 #define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4041 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4042 #define CAN_F13R1_FB13_Pos     (13U)
4043 #define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4044 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4045 #define CAN_F13R1_FB14_Pos     (14U)
4046 #define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4047 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4048 #define CAN_F13R1_FB15_Pos     (15U)
4049 #define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4050 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4051 #define CAN_F13R1_FB16_Pos     (16U)
4052 #define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4053 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4054 #define CAN_F13R1_FB17_Pos     (17U)
4055 #define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4056 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4057 #define CAN_F13R1_FB18_Pos     (18U)
4058 #define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4059 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4060 #define CAN_F13R1_FB19_Pos     (19U)
4061 #define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4062 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4063 #define CAN_F13R1_FB20_Pos     (20U)
4064 #define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4065 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4066 #define CAN_F13R1_FB21_Pos     (21U)
4067 #define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4068 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4069 #define CAN_F13R1_FB22_Pos     (22U)
4070 #define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4071 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4072 #define CAN_F13R1_FB23_Pos     (23U)
4073 #define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4074 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4075 #define CAN_F13R1_FB24_Pos     (24U)
4076 #define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4077 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4078 #define CAN_F13R1_FB25_Pos     (25U)
4079 #define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4080 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4081 #define CAN_F13R1_FB26_Pos     (26U)
4082 #define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4083 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4084 #define CAN_F13R1_FB27_Pos     (27U)
4085 #define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4086 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4087 #define CAN_F13R1_FB28_Pos     (28U)
4088 #define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4089 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4090 #define CAN_F13R1_FB29_Pos     (29U)
4091 #define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4092 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4093 #define CAN_F13R1_FB30_Pos     (30U)
4094 #define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4095 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4096 #define CAN_F13R1_FB31_Pos     (31U)
4097 #define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4098 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4099 
4100 /*******************  Bit definition for CAN_F0R2 register  *******************/
4101 #define CAN_F0R2_FB0_Pos       (0U)
4102 #define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4103 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4104 #define CAN_F0R2_FB1_Pos       (1U)
4105 #define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4106 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4107 #define CAN_F0R2_FB2_Pos       (2U)
4108 #define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4109 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4110 #define CAN_F0R2_FB3_Pos       (3U)
4111 #define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4112 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4113 #define CAN_F0R2_FB4_Pos       (4U)
4114 #define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4115 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4116 #define CAN_F0R2_FB5_Pos       (5U)
4117 #define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4118 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4119 #define CAN_F0R2_FB6_Pos       (6U)
4120 #define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4121 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4122 #define CAN_F0R2_FB7_Pos       (7U)
4123 #define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4124 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4125 #define CAN_F0R2_FB8_Pos       (8U)
4126 #define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4127 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4128 #define CAN_F0R2_FB9_Pos       (9U)
4129 #define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4130 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4131 #define CAN_F0R2_FB10_Pos      (10U)
4132 #define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4133 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4134 #define CAN_F0R2_FB11_Pos      (11U)
4135 #define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4136 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4137 #define CAN_F0R2_FB12_Pos      (12U)
4138 #define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4139 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4140 #define CAN_F0R2_FB13_Pos      (13U)
4141 #define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4142 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4143 #define CAN_F0R2_FB14_Pos      (14U)
4144 #define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4145 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4146 #define CAN_F0R2_FB15_Pos      (15U)
4147 #define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4148 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4149 #define CAN_F0R2_FB16_Pos      (16U)
4150 #define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4151 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4152 #define CAN_F0R2_FB17_Pos      (17U)
4153 #define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4154 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4155 #define CAN_F0R2_FB18_Pos      (18U)
4156 #define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4157 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4158 #define CAN_F0R2_FB19_Pos      (19U)
4159 #define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4160 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4161 #define CAN_F0R2_FB20_Pos      (20U)
4162 #define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4163 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4164 #define CAN_F0R2_FB21_Pos      (21U)
4165 #define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4166 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4167 #define CAN_F0R2_FB22_Pos      (22U)
4168 #define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4169 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4170 #define CAN_F0R2_FB23_Pos      (23U)
4171 #define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4172 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4173 #define CAN_F0R2_FB24_Pos      (24U)
4174 #define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4175 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4176 #define CAN_F0R2_FB25_Pos      (25U)
4177 #define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4178 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4179 #define CAN_F0R2_FB26_Pos      (26U)
4180 #define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4181 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4182 #define CAN_F0R2_FB27_Pos      (27U)
4183 #define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4184 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4185 #define CAN_F0R2_FB28_Pos      (28U)
4186 #define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4187 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4188 #define CAN_F0R2_FB29_Pos      (29U)
4189 #define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4190 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4191 #define CAN_F0R2_FB30_Pos      (30U)
4192 #define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4193 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4194 #define CAN_F0R2_FB31_Pos      (31U)
4195 #define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4196 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4197 
4198 /*******************  Bit definition for CAN_F1R2 register  *******************/
4199 #define CAN_F1R2_FB0_Pos       (0U)
4200 #define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4201 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4202 #define CAN_F1R2_FB1_Pos       (1U)
4203 #define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
4204 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
4205 #define CAN_F1R2_FB2_Pos       (2U)
4206 #define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
4207 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
4208 #define CAN_F1R2_FB3_Pos       (3U)
4209 #define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
4210 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
4211 #define CAN_F1R2_FB4_Pos       (4U)
4212 #define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
4213 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
4214 #define CAN_F1R2_FB5_Pos       (5U)
4215 #define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
4216 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
4217 #define CAN_F1R2_FB6_Pos       (6U)
4218 #define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
4219 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
4220 #define CAN_F1R2_FB7_Pos       (7U)
4221 #define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
4222 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
4223 #define CAN_F1R2_FB8_Pos       (8U)
4224 #define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
4225 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
4226 #define CAN_F1R2_FB9_Pos       (9U)
4227 #define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
4228 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
4229 #define CAN_F1R2_FB10_Pos      (10U)
4230 #define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
4231 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
4232 #define CAN_F1R2_FB11_Pos      (11U)
4233 #define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
4234 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
4235 #define CAN_F1R2_FB12_Pos      (12U)
4236 #define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
4237 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
4238 #define CAN_F1R2_FB13_Pos      (13U)
4239 #define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
4240 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
4241 #define CAN_F1R2_FB14_Pos      (14U)
4242 #define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
4243 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
4244 #define CAN_F1R2_FB15_Pos      (15U)
4245 #define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
4246 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
4247 #define CAN_F1R2_FB16_Pos      (16U)
4248 #define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
4249 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
4250 #define CAN_F1R2_FB17_Pos      (17U)
4251 #define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
4252 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
4253 #define CAN_F1R2_FB18_Pos      (18U)
4254 #define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
4255 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
4256 #define CAN_F1R2_FB19_Pos      (19U)
4257 #define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
4258 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
4259 #define CAN_F1R2_FB20_Pos      (20U)
4260 #define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
4261 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
4262 #define CAN_F1R2_FB21_Pos      (21U)
4263 #define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
4264 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
4265 #define CAN_F1R2_FB22_Pos      (22U)
4266 #define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
4267 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
4268 #define CAN_F1R2_FB23_Pos      (23U)
4269 #define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
4270 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
4271 #define CAN_F1R2_FB24_Pos      (24U)
4272 #define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
4273 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
4274 #define CAN_F1R2_FB25_Pos      (25U)
4275 #define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
4276 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
4277 #define CAN_F1R2_FB26_Pos      (26U)
4278 #define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
4279 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
4280 #define CAN_F1R2_FB27_Pos      (27U)
4281 #define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
4282 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
4283 #define CAN_F1R2_FB28_Pos      (28U)
4284 #define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
4285 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
4286 #define CAN_F1R2_FB29_Pos      (29U)
4287 #define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
4288 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
4289 #define CAN_F1R2_FB30_Pos      (30U)
4290 #define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
4291 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
4292 #define CAN_F1R2_FB31_Pos      (31U)
4293 #define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
4294 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
4295 
4296 /*******************  Bit definition for CAN_F2R2 register  *******************/
4297 #define CAN_F2R2_FB0_Pos       (0U)
4298 #define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
4299 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
4300 #define CAN_F2R2_FB1_Pos       (1U)
4301 #define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
4302 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
4303 #define CAN_F2R2_FB2_Pos       (2U)
4304 #define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
4305 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
4306 #define CAN_F2R2_FB3_Pos       (3U)
4307 #define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
4308 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
4309 #define CAN_F2R2_FB4_Pos       (4U)
4310 #define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
4311 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
4312 #define CAN_F2R2_FB5_Pos       (5U)
4313 #define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
4314 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
4315 #define CAN_F2R2_FB6_Pos       (6U)
4316 #define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
4317 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
4318 #define CAN_F2R2_FB7_Pos       (7U)
4319 #define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
4320 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
4321 #define CAN_F2R2_FB8_Pos       (8U)
4322 #define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
4323 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
4324 #define CAN_F2R2_FB9_Pos       (9U)
4325 #define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
4326 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
4327 #define CAN_F2R2_FB10_Pos      (10U)
4328 #define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
4329 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
4330 #define CAN_F2R2_FB11_Pos      (11U)
4331 #define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
4332 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
4333 #define CAN_F2R2_FB12_Pos      (12U)
4334 #define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
4335 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
4336 #define CAN_F2R2_FB13_Pos      (13U)
4337 #define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
4338 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
4339 #define CAN_F2R2_FB14_Pos      (14U)
4340 #define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
4341 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
4342 #define CAN_F2R2_FB15_Pos      (15U)
4343 #define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
4344 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
4345 #define CAN_F2R2_FB16_Pos      (16U)
4346 #define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
4347 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
4348 #define CAN_F2R2_FB17_Pos      (17U)
4349 #define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
4350 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
4351 #define CAN_F2R2_FB18_Pos      (18U)
4352 #define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
4353 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
4354 #define CAN_F2R2_FB19_Pos      (19U)
4355 #define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
4356 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
4357 #define CAN_F2R2_FB20_Pos      (20U)
4358 #define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
4359 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
4360 #define CAN_F2R2_FB21_Pos      (21U)
4361 #define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
4362 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
4363 #define CAN_F2R2_FB22_Pos      (22U)
4364 #define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
4365 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
4366 #define CAN_F2R2_FB23_Pos      (23U)
4367 #define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
4368 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
4369 #define CAN_F2R2_FB24_Pos      (24U)
4370 #define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
4371 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
4372 #define CAN_F2R2_FB25_Pos      (25U)
4373 #define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
4374 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
4375 #define CAN_F2R2_FB26_Pos      (26U)
4376 #define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
4377 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
4378 #define CAN_F2R2_FB27_Pos      (27U)
4379 #define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
4380 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
4381 #define CAN_F2R2_FB28_Pos      (28U)
4382 #define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
4383 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
4384 #define CAN_F2R2_FB29_Pos      (29U)
4385 #define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
4386 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
4387 #define CAN_F2R2_FB30_Pos      (30U)
4388 #define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
4389 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
4390 #define CAN_F2R2_FB31_Pos      (31U)
4391 #define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
4392 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
4393 
4394 /*******************  Bit definition for CAN_F3R2 register  *******************/
4395 #define CAN_F3R2_FB0_Pos       (0U)
4396 #define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
4397 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
4398 #define CAN_F3R2_FB1_Pos       (1U)
4399 #define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
4400 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
4401 #define CAN_F3R2_FB2_Pos       (2U)
4402 #define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
4403 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
4404 #define CAN_F3R2_FB3_Pos       (3U)
4405 #define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
4406 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
4407 #define CAN_F3R2_FB4_Pos       (4U)
4408 #define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
4409 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
4410 #define CAN_F3R2_FB5_Pos       (5U)
4411 #define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
4412 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
4413 #define CAN_F3R2_FB6_Pos       (6U)
4414 #define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
4415 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
4416 #define CAN_F3R2_FB7_Pos       (7U)
4417 #define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
4418 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
4419 #define CAN_F3R2_FB8_Pos       (8U)
4420 #define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
4421 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
4422 #define CAN_F3R2_FB9_Pos       (9U)
4423 #define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
4424 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
4425 #define CAN_F3R2_FB10_Pos      (10U)
4426 #define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
4427 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
4428 #define CAN_F3R2_FB11_Pos      (11U)
4429 #define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
4430 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
4431 #define CAN_F3R2_FB12_Pos      (12U)
4432 #define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
4433 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
4434 #define CAN_F3R2_FB13_Pos      (13U)
4435 #define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
4436 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
4437 #define CAN_F3R2_FB14_Pos      (14U)
4438 #define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
4439 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
4440 #define CAN_F3R2_FB15_Pos      (15U)
4441 #define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
4442 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
4443 #define CAN_F3R2_FB16_Pos      (16U)
4444 #define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
4445 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
4446 #define CAN_F3R2_FB17_Pos      (17U)
4447 #define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
4448 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
4449 #define CAN_F3R2_FB18_Pos      (18U)
4450 #define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
4451 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
4452 #define CAN_F3R2_FB19_Pos      (19U)
4453 #define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
4454 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
4455 #define CAN_F3R2_FB20_Pos      (20U)
4456 #define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
4457 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
4458 #define CAN_F3R2_FB21_Pos      (21U)
4459 #define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
4460 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
4461 #define CAN_F3R2_FB22_Pos      (22U)
4462 #define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
4463 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
4464 #define CAN_F3R2_FB23_Pos      (23U)
4465 #define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
4466 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
4467 #define CAN_F3R2_FB24_Pos      (24U)
4468 #define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
4469 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
4470 #define CAN_F3R2_FB25_Pos      (25U)
4471 #define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
4472 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
4473 #define CAN_F3R2_FB26_Pos      (26U)
4474 #define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
4475 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
4476 #define CAN_F3R2_FB27_Pos      (27U)
4477 #define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
4478 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
4479 #define CAN_F3R2_FB28_Pos      (28U)
4480 #define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
4481 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
4482 #define CAN_F3R2_FB29_Pos      (29U)
4483 #define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
4484 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
4485 #define CAN_F3R2_FB30_Pos      (30U)
4486 #define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
4487 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
4488 #define CAN_F3R2_FB31_Pos      (31U)
4489 #define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
4490 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
4491 
4492 /*******************  Bit definition for CAN_F4R2 register  *******************/
4493 #define CAN_F4R2_FB0_Pos       (0U)
4494 #define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
4495 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
4496 #define CAN_F4R2_FB1_Pos       (1U)
4497 #define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
4498 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
4499 #define CAN_F4R2_FB2_Pos       (2U)
4500 #define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
4501 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
4502 #define CAN_F4R2_FB3_Pos       (3U)
4503 #define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
4504 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
4505 #define CAN_F4R2_FB4_Pos       (4U)
4506 #define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
4507 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
4508 #define CAN_F4R2_FB5_Pos       (5U)
4509 #define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
4510 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
4511 #define CAN_F4R2_FB6_Pos       (6U)
4512 #define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
4513 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
4514 #define CAN_F4R2_FB7_Pos       (7U)
4515 #define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
4516 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
4517 #define CAN_F4R2_FB8_Pos       (8U)
4518 #define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
4519 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
4520 #define CAN_F4R2_FB9_Pos       (9U)
4521 #define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
4522 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
4523 #define CAN_F4R2_FB10_Pos      (10U)
4524 #define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
4525 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
4526 #define CAN_F4R2_FB11_Pos      (11U)
4527 #define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
4528 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
4529 #define CAN_F4R2_FB12_Pos      (12U)
4530 #define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
4531 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
4532 #define CAN_F4R2_FB13_Pos      (13U)
4533 #define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
4534 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
4535 #define CAN_F4R2_FB14_Pos      (14U)
4536 #define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
4537 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
4538 #define CAN_F4R2_FB15_Pos      (15U)
4539 #define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
4540 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
4541 #define CAN_F4R2_FB16_Pos      (16U)
4542 #define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
4543 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
4544 #define CAN_F4R2_FB17_Pos      (17U)
4545 #define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
4546 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
4547 #define CAN_F4R2_FB18_Pos      (18U)
4548 #define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
4549 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
4550 #define CAN_F4R2_FB19_Pos      (19U)
4551 #define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
4552 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
4553 #define CAN_F4R2_FB20_Pos      (20U)
4554 #define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
4555 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
4556 #define CAN_F4R2_FB21_Pos      (21U)
4557 #define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
4558 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
4559 #define CAN_F4R2_FB22_Pos      (22U)
4560 #define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
4561 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
4562 #define CAN_F4R2_FB23_Pos      (23U)
4563 #define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
4564 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
4565 #define CAN_F4R2_FB24_Pos      (24U)
4566 #define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
4567 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
4568 #define CAN_F4R2_FB25_Pos      (25U)
4569 #define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
4570 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
4571 #define CAN_F4R2_FB26_Pos      (26U)
4572 #define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
4573 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
4574 #define CAN_F4R2_FB27_Pos      (27U)
4575 #define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
4576 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
4577 #define CAN_F4R2_FB28_Pos      (28U)
4578 #define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
4579 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
4580 #define CAN_F4R2_FB29_Pos      (29U)
4581 #define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
4582 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
4583 #define CAN_F4R2_FB30_Pos      (30U)
4584 #define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
4585 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
4586 #define CAN_F4R2_FB31_Pos      (31U)
4587 #define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
4588 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
4589 
4590 /*******************  Bit definition for CAN_F5R2 register  *******************/
4591 #define CAN_F5R2_FB0_Pos       (0U)
4592 #define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
4593 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
4594 #define CAN_F5R2_FB1_Pos       (1U)
4595 #define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
4596 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
4597 #define CAN_F5R2_FB2_Pos       (2U)
4598 #define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
4599 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
4600 #define CAN_F5R2_FB3_Pos       (3U)
4601 #define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
4602 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
4603 #define CAN_F5R2_FB4_Pos       (4U)
4604 #define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
4605 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
4606 #define CAN_F5R2_FB5_Pos       (5U)
4607 #define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
4608 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
4609 #define CAN_F5R2_FB6_Pos       (6U)
4610 #define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
4611 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
4612 #define CAN_F5R2_FB7_Pos       (7U)
4613 #define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
4614 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
4615 #define CAN_F5R2_FB8_Pos       (8U)
4616 #define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
4617 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
4618 #define CAN_F5R2_FB9_Pos       (9U)
4619 #define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
4620 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
4621 #define CAN_F5R2_FB10_Pos      (10U)
4622 #define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
4623 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
4624 #define CAN_F5R2_FB11_Pos      (11U)
4625 #define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
4626 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
4627 #define CAN_F5R2_FB12_Pos      (12U)
4628 #define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
4629 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
4630 #define CAN_F5R2_FB13_Pos      (13U)
4631 #define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
4632 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
4633 #define CAN_F5R2_FB14_Pos      (14U)
4634 #define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
4635 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
4636 #define CAN_F5R2_FB15_Pos      (15U)
4637 #define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
4638 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
4639 #define CAN_F5R2_FB16_Pos      (16U)
4640 #define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
4641 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
4642 #define CAN_F5R2_FB17_Pos      (17U)
4643 #define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
4644 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
4645 #define CAN_F5R2_FB18_Pos      (18U)
4646 #define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
4647 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
4648 #define CAN_F5R2_FB19_Pos      (19U)
4649 #define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
4650 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
4651 #define CAN_F5R2_FB20_Pos      (20U)
4652 #define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
4653 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
4654 #define CAN_F5R2_FB21_Pos      (21U)
4655 #define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
4656 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
4657 #define CAN_F5R2_FB22_Pos      (22U)
4658 #define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
4659 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
4660 #define CAN_F5R2_FB23_Pos      (23U)
4661 #define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
4662 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
4663 #define CAN_F5R2_FB24_Pos      (24U)
4664 #define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
4665 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
4666 #define CAN_F5R2_FB25_Pos      (25U)
4667 #define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
4668 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
4669 #define CAN_F5R2_FB26_Pos      (26U)
4670 #define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
4671 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
4672 #define CAN_F5R2_FB27_Pos      (27U)
4673 #define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
4674 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
4675 #define CAN_F5R2_FB28_Pos      (28U)
4676 #define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
4677 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
4678 #define CAN_F5R2_FB29_Pos      (29U)
4679 #define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
4680 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
4681 #define CAN_F5R2_FB30_Pos      (30U)
4682 #define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
4683 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
4684 #define CAN_F5R2_FB31_Pos      (31U)
4685 #define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
4686 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
4687 
4688 /*******************  Bit definition for CAN_F6R2 register  *******************/
4689 #define CAN_F6R2_FB0_Pos       (0U)
4690 #define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
4691 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
4692 #define CAN_F6R2_FB1_Pos       (1U)
4693 #define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
4694 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
4695 #define CAN_F6R2_FB2_Pos       (2U)
4696 #define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
4697 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
4698 #define CAN_F6R2_FB3_Pos       (3U)
4699 #define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
4700 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
4701 #define CAN_F6R2_FB4_Pos       (4U)
4702 #define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
4703 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
4704 #define CAN_F6R2_FB5_Pos       (5U)
4705 #define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
4706 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
4707 #define CAN_F6R2_FB6_Pos       (6U)
4708 #define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
4709 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
4710 #define CAN_F6R2_FB7_Pos       (7U)
4711 #define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
4712 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
4713 #define CAN_F6R2_FB8_Pos       (8U)
4714 #define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
4715 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
4716 #define CAN_F6R2_FB9_Pos       (9U)
4717 #define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
4718 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
4719 #define CAN_F6R2_FB10_Pos      (10U)
4720 #define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
4721 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
4722 #define CAN_F6R2_FB11_Pos      (11U)
4723 #define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
4724 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
4725 #define CAN_F6R2_FB12_Pos      (12U)
4726 #define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
4727 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
4728 #define CAN_F6R2_FB13_Pos      (13U)
4729 #define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
4730 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
4731 #define CAN_F6R2_FB14_Pos      (14U)
4732 #define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
4733 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
4734 #define CAN_F6R2_FB15_Pos      (15U)
4735 #define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
4736 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
4737 #define CAN_F6R2_FB16_Pos      (16U)
4738 #define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
4739 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
4740 #define CAN_F6R2_FB17_Pos      (17U)
4741 #define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
4742 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
4743 #define CAN_F6R2_FB18_Pos      (18U)
4744 #define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
4745 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
4746 #define CAN_F6R2_FB19_Pos      (19U)
4747 #define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
4748 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
4749 #define CAN_F6R2_FB20_Pos      (20U)
4750 #define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
4751 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
4752 #define CAN_F6R2_FB21_Pos      (21U)
4753 #define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
4754 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
4755 #define CAN_F6R2_FB22_Pos      (22U)
4756 #define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
4757 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
4758 #define CAN_F6R2_FB23_Pos      (23U)
4759 #define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
4760 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
4761 #define CAN_F6R2_FB24_Pos      (24U)
4762 #define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
4763 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
4764 #define CAN_F6R2_FB25_Pos      (25U)
4765 #define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
4766 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
4767 #define CAN_F6R2_FB26_Pos      (26U)
4768 #define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
4769 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
4770 #define CAN_F6R2_FB27_Pos      (27U)
4771 #define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
4772 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
4773 #define CAN_F6R2_FB28_Pos      (28U)
4774 #define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
4775 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
4776 #define CAN_F6R2_FB29_Pos      (29U)
4777 #define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
4778 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
4779 #define CAN_F6R2_FB30_Pos      (30U)
4780 #define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
4781 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
4782 #define CAN_F6R2_FB31_Pos      (31U)
4783 #define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
4784 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
4785 
4786 /*******************  Bit definition for CAN_F7R2 register  *******************/
4787 #define CAN_F7R2_FB0_Pos       (0U)
4788 #define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
4789 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
4790 #define CAN_F7R2_FB1_Pos       (1U)
4791 #define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
4792 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
4793 #define CAN_F7R2_FB2_Pos       (2U)
4794 #define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
4795 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
4796 #define CAN_F7R2_FB3_Pos       (3U)
4797 #define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
4798 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
4799 #define CAN_F7R2_FB4_Pos       (4U)
4800 #define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
4801 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
4802 #define CAN_F7R2_FB5_Pos       (5U)
4803 #define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
4804 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
4805 #define CAN_F7R2_FB6_Pos       (6U)
4806 #define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
4807 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
4808 #define CAN_F7R2_FB7_Pos       (7U)
4809 #define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
4810 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
4811 #define CAN_F7R2_FB8_Pos       (8U)
4812 #define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
4813 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
4814 #define CAN_F7R2_FB9_Pos       (9U)
4815 #define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
4816 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
4817 #define CAN_F7R2_FB10_Pos      (10U)
4818 #define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
4819 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
4820 #define CAN_F7R2_FB11_Pos      (11U)
4821 #define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
4822 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
4823 #define CAN_F7R2_FB12_Pos      (12U)
4824 #define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
4825 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
4826 #define CAN_F7R2_FB13_Pos      (13U)
4827 #define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
4828 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
4829 #define CAN_F7R2_FB14_Pos      (14U)
4830 #define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
4831 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
4832 #define CAN_F7R2_FB15_Pos      (15U)
4833 #define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
4834 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
4835 #define CAN_F7R2_FB16_Pos      (16U)
4836 #define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
4837 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
4838 #define CAN_F7R2_FB17_Pos      (17U)
4839 #define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
4840 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
4841 #define CAN_F7R2_FB18_Pos      (18U)
4842 #define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
4843 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
4844 #define CAN_F7R2_FB19_Pos      (19U)
4845 #define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
4846 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
4847 #define CAN_F7R2_FB20_Pos      (20U)
4848 #define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
4849 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
4850 #define CAN_F7R2_FB21_Pos      (21U)
4851 #define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
4852 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
4853 #define CAN_F7R2_FB22_Pos      (22U)
4854 #define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
4855 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
4856 #define CAN_F7R2_FB23_Pos      (23U)
4857 #define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
4858 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
4859 #define CAN_F7R2_FB24_Pos      (24U)
4860 #define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
4861 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
4862 #define CAN_F7R2_FB25_Pos      (25U)
4863 #define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
4864 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
4865 #define CAN_F7R2_FB26_Pos      (26U)
4866 #define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
4867 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
4868 #define CAN_F7R2_FB27_Pos      (27U)
4869 #define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
4870 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
4871 #define CAN_F7R2_FB28_Pos      (28U)
4872 #define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
4873 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
4874 #define CAN_F7R2_FB29_Pos      (29U)
4875 #define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
4876 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
4877 #define CAN_F7R2_FB30_Pos      (30U)
4878 #define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
4879 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
4880 #define CAN_F7R2_FB31_Pos      (31U)
4881 #define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
4882 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
4883 
4884 /*******************  Bit definition for CAN_F8R2 register  *******************/
4885 #define CAN_F8R2_FB0_Pos       (0U)
4886 #define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
4887 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
4888 #define CAN_F8R2_FB1_Pos       (1U)
4889 #define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
4890 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
4891 #define CAN_F8R2_FB2_Pos       (2U)
4892 #define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
4893 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
4894 #define CAN_F8R2_FB3_Pos       (3U)
4895 #define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
4896 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
4897 #define CAN_F8R2_FB4_Pos       (4U)
4898 #define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
4899 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
4900 #define CAN_F8R2_FB5_Pos       (5U)
4901 #define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
4902 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
4903 #define CAN_F8R2_FB6_Pos       (6U)
4904 #define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
4905 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
4906 #define CAN_F8R2_FB7_Pos       (7U)
4907 #define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
4908 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
4909 #define CAN_F8R2_FB8_Pos       (8U)
4910 #define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
4911 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
4912 #define CAN_F8R2_FB9_Pos       (9U)
4913 #define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
4914 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
4915 #define CAN_F8R2_FB10_Pos      (10U)
4916 #define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
4917 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
4918 #define CAN_F8R2_FB11_Pos      (11U)
4919 #define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
4920 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
4921 #define CAN_F8R2_FB12_Pos      (12U)
4922 #define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
4923 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
4924 #define CAN_F8R2_FB13_Pos      (13U)
4925 #define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
4926 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
4927 #define CAN_F8R2_FB14_Pos      (14U)
4928 #define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
4929 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
4930 #define CAN_F8R2_FB15_Pos      (15U)
4931 #define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
4932 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
4933 #define CAN_F8R2_FB16_Pos      (16U)
4934 #define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
4935 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
4936 #define CAN_F8R2_FB17_Pos      (17U)
4937 #define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
4938 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
4939 #define CAN_F8R2_FB18_Pos      (18U)
4940 #define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
4941 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
4942 #define CAN_F8R2_FB19_Pos      (19U)
4943 #define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
4944 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
4945 #define CAN_F8R2_FB20_Pos      (20U)
4946 #define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
4947 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
4948 #define CAN_F8R2_FB21_Pos      (21U)
4949 #define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
4950 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
4951 #define CAN_F8R2_FB22_Pos      (22U)
4952 #define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
4953 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
4954 #define CAN_F8R2_FB23_Pos      (23U)
4955 #define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
4956 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
4957 #define CAN_F8R2_FB24_Pos      (24U)
4958 #define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
4959 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
4960 #define CAN_F8R2_FB25_Pos      (25U)
4961 #define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
4962 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
4963 #define CAN_F8R2_FB26_Pos      (26U)
4964 #define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
4965 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
4966 #define CAN_F8R2_FB27_Pos      (27U)
4967 #define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
4968 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
4969 #define CAN_F8R2_FB28_Pos      (28U)
4970 #define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
4971 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
4972 #define CAN_F8R2_FB29_Pos      (29U)
4973 #define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
4974 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
4975 #define CAN_F8R2_FB30_Pos      (30U)
4976 #define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
4977 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
4978 #define CAN_F8R2_FB31_Pos      (31U)
4979 #define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
4980 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
4981 
4982 /*******************  Bit definition for CAN_F9R2 register  *******************/
4983 #define CAN_F9R2_FB0_Pos       (0U)
4984 #define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
4985 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
4986 #define CAN_F9R2_FB1_Pos       (1U)
4987 #define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
4988 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
4989 #define CAN_F9R2_FB2_Pos       (2U)
4990 #define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
4991 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
4992 #define CAN_F9R2_FB3_Pos       (3U)
4993 #define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
4994 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
4995 #define CAN_F9R2_FB4_Pos       (4U)
4996 #define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
4997 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
4998 #define CAN_F9R2_FB5_Pos       (5U)
4999 #define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
5000 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5001 #define CAN_F9R2_FB6_Pos       (6U)
5002 #define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
5003 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5004 #define CAN_F9R2_FB7_Pos       (7U)
5005 #define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
5006 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5007 #define CAN_F9R2_FB8_Pos       (8U)
5008 #define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
5009 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5010 #define CAN_F9R2_FB9_Pos       (9U)
5011 #define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
5012 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5013 #define CAN_F9R2_FB10_Pos      (10U)
5014 #define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
5015 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5016 #define CAN_F9R2_FB11_Pos      (11U)
5017 #define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
5018 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5019 #define CAN_F9R2_FB12_Pos      (12U)
5020 #define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
5021 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5022 #define CAN_F9R2_FB13_Pos      (13U)
5023 #define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
5024 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5025 #define CAN_F9R2_FB14_Pos      (14U)
5026 #define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
5027 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5028 #define CAN_F9R2_FB15_Pos      (15U)
5029 #define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
5030 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5031 #define CAN_F9R2_FB16_Pos      (16U)
5032 #define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
5033 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5034 #define CAN_F9R2_FB17_Pos      (17U)
5035 #define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
5036 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5037 #define CAN_F9R2_FB18_Pos      (18U)
5038 #define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
5039 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5040 #define CAN_F9R2_FB19_Pos      (19U)
5041 #define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5042 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5043 #define CAN_F9R2_FB20_Pos      (20U)
5044 #define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5045 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5046 #define CAN_F9R2_FB21_Pos      (21U)
5047 #define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5048 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5049 #define CAN_F9R2_FB22_Pos      (22U)
5050 #define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5051 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5052 #define CAN_F9R2_FB23_Pos      (23U)
5053 #define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5054 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5055 #define CAN_F9R2_FB24_Pos      (24U)
5056 #define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5057 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5058 #define CAN_F9R2_FB25_Pos      (25U)
5059 #define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5060 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5061 #define CAN_F9R2_FB26_Pos      (26U)
5062 #define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5063 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5064 #define CAN_F9R2_FB27_Pos      (27U)
5065 #define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5066 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5067 #define CAN_F9R2_FB28_Pos      (28U)
5068 #define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5069 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5070 #define CAN_F9R2_FB29_Pos      (29U)
5071 #define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5072 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5073 #define CAN_F9R2_FB30_Pos      (30U)
5074 #define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5075 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5076 #define CAN_F9R2_FB31_Pos      (31U)
5077 #define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5078 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5079 
5080 /*******************  Bit definition for CAN_F10R2 register  ******************/
5081 #define CAN_F10R2_FB0_Pos      (0U)
5082 #define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5083 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5084 #define CAN_F10R2_FB1_Pos      (1U)
5085 #define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5086 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5087 #define CAN_F10R2_FB2_Pos      (2U)
5088 #define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5089 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5090 #define CAN_F10R2_FB3_Pos      (3U)
5091 #define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5092 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5093 #define CAN_F10R2_FB4_Pos      (4U)
5094 #define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5095 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5096 #define CAN_F10R2_FB5_Pos      (5U)
5097 #define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5098 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5099 #define CAN_F10R2_FB6_Pos      (6U)
5100 #define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5101 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5102 #define CAN_F10R2_FB7_Pos      (7U)
5103 #define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5104 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5105 #define CAN_F10R2_FB8_Pos      (8U)
5106 #define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5107 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5108 #define CAN_F10R2_FB9_Pos      (9U)
5109 #define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5110 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5111 #define CAN_F10R2_FB10_Pos     (10U)
5112 #define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5113 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5114 #define CAN_F10R2_FB11_Pos     (11U)
5115 #define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5116 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5117 #define CAN_F10R2_FB12_Pos     (12U)
5118 #define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5119 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5120 #define CAN_F10R2_FB13_Pos     (13U)
5121 #define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5122 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5123 #define CAN_F10R2_FB14_Pos     (14U)
5124 #define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5125 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5126 #define CAN_F10R2_FB15_Pos     (15U)
5127 #define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5128 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5129 #define CAN_F10R2_FB16_Pos     (16U)
5130 #define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5131 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5132 #define CAN_F10R2_FB17_Pos     (17U)
5133 #define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5134 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5135 #define CAN_F10R2_FB18_Pos     (18U)
5136 #define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5137 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5138 #define CAN_F10R2_FB19_Pos     (19U)
5139 #define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5140 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5141 #define CAN_F10R2_FB20_Pos     (20U)
5142 #define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5143 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5144 #define CAN_F10R2_FB21_Pos     (21U)
5145 #define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5146 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5147 #define CAN_F10R2_FB22_Pos     (22U)
5148 #define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5149 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5150 #define CAN_F10R2_FB23_Pos     (23U)
5151 #define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5152 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5153 #define CAN_F10R2_FB24_Pos     (24U)
5154 #define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5155 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5156 #define CAN_F10R2_FB25_Pos     (25U)
5157 #define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5158 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5159 #define CAN_F10R2_FB26_Pos     (26U)
5160 #define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5161 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5162 #define CAN_F10R2_FB27_Pos     (27U)
5163 #define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5164 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5165 #define CAN_F10R2_FB28_Pos     (28U)
5166 #define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5167 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5168 #define CAN_F10R2_FB29_Pos     (29U)
5169 #define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5170 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5171 #define CAN_F10R2_FB30_Pos     (30U)
5172 #define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5173 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5174 #define CAN_F10R2_FB31_Pos     (31U)
5175 #define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5176 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5177 
5178 /*******************  Bit definition for CAN_F11R2 register  ******************/
5179 #define CAN_F11R2_FB0_Pos      (0U)
5180 #define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5181 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5182 #define CAN_F11R2_FB1_Pos      (1U)
5183 #define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5184 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5185 #define CAN_F11R2_FB2_Pos      (2U)
5186 #define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5187 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5188 #define CAN_F11R2_FB3_Pos      (3U)
5189 #define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5190 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5191 #define CAN_F11R2_FB4_Pos      (4U)
5192 #define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5193 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5194 #define CAN_F11R2_FB5_Pos      (5U)
5195 #define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5196 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5197 #define CAN_F11R2_FB6_Pos      (6U)
5198 #define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5199 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5200 #define CAN_F11R2_FB7_Pos      (7U)
5201 #define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5202 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
5203 #define CAN_F11R2_FB8_Pos      (8U)
5204 #define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
5205 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
5206 #define CAN_F11R2_FB9_Pos      (9U)
5207 #define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
5208 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
5209 #define CAN_F11R2_FB10_Pos     (10U)
5210 #define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
5211 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
5212 #define CAN_F11R2_FB11_Pos     (11U)
5213 #define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
5214 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
5215 #define CAN_F11R2_FB12_Pos     (12U)
5216 #define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
5217 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
5218 #define CAN_F11R2_FB13_Pos     (13U)
5219 #define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
5220 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
5221 #define CAN_F11R2_FB14_Pos     (14U)
5222 #define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
5223 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
5224 #define CAN_F11R2_FB15_Pos     (15U)
5225 #define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
5226 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
5227 #define CAN_F11R2_FB16_Pos     (16U)
5228 #define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
5229 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
5230 #define CAN_F11R2_FB17_Pos     (17U)
5231 #define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
5232 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
5233 #define CAN_F11R2_FB18_Pos     (18U)
5234 #define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
5235 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
5236 #define CAN_F11R2_FB19_Pos     (19U)
5237 #define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
5238 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
5239 #define CAN_F11R2_FB20_Pos     (20U)
5240 #define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
5241 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
5242 #define CAN_F11R2_FB21_Pos     (21U)
5243 #define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
5244 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
5245 #define CAN_F11R2_FB22_Pos     (22U)
5246 #define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
5247 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
5248 #define CAN_F11R2_FB23_Pos     (23U)
5249 #define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
5250 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
5251 #define CAN_F11R2_FB24_Pos     (24U)
5252 #define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
5253 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
5254 #define CAN_F11R2_FB25_Pos     (25U)
5255 #define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
5256 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
5257 #define CAN_F11R2_FB26_Pos     (26U)
5258 #define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
5259 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
5260 #define CAN_F11R2_FB27_Pos     (27U)
5261 #define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
5262 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
5263 #define CAN_F11R2_FB28_Pos     (28U)
5264 #define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
5265 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
5266 #define CAN_F11R2_FB29_Pos     (29U)
5267 #define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
5268 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
5269 #define CAN_F11R2_FB30_Pos     (30U)
5270 #define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
5271 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
5272 #define CAN_F11R2_FB31_Pos     (31U)
5273 #define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
5274 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
5275 
5276 /*******************  Bit definition for CAN_F12R2 register  ******************/
5277 #define CAN_F12R2_FB0_Pos      (0U)
5278 #define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
5279 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
5280 #define CAN_F12R2_FB1_Pos      (1U)
5281 #define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
5282 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
5283 #define CAN_F12R2_FB2_Pos      (2U)
5284 #define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
5285 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
5286 #define CAN_F12R2_FB3_Pos      (3U)
5287 #define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
5288 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
5289 #define CAN_F12R2_FB4_Pos      (4U)
5290 #define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
5291 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
5292 #define CAN_F12R2_FB5_Pos      (5U)
5293 #define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
5294 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
5295 #define CAN_F12R2_FB6_Pos      (6U)
5296 #define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
5297 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
5298 #define CAN_F12R2_FB7_Pos      (7U)
5299 #define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
5300 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
5301 #define CAN_F12R2_FB8_Pos      (8U)
5302 #define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
5303 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
5304 #define CAN_F12R2_FB9_Pos      (9U)
5305 #define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
5306 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
5307 #define CAN_F12R2_FB10_Pos     (10U)
5308 #define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
5309 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
5310 #define CAN_F12R2_FB11_Pos     (11U)
5311 #define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
5312 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
5313 #define CAN_F12R2_FB12_Pos     (12U)
5314 #define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
5315 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
5316 #define CAN_F12R2_FB13_Pos     (13U)
5317 #define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
5318 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
5319 #define CAN_F12R2_FB14_Pos     (14U)
5320 #define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
5321 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
5322 #define CAN_F12R2_FB15_Pos     (15U)
5323 #define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
5324 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
5325 #define CAN_F12R2_FB16_Pos     (16U)
5326 #define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
5327 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
5328 #define CAN_F12R2_FB17_Pos     (17U)
5329 #define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
5330 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
5331 #define CAN_F12R2_FB18_Pos     (18U)
5332 #define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
5333 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
5334 #define CAN_F12R2_FB19_Pos     (19U)
5335 #define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
5336 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
5337 #define CAN_F12R2_FB20_Pos     (20U)
5338 #define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
5339 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
5340 #define CAN_F12R2_FB21_Pos     (21U)
5341 #define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
5342 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
5343 #define CAN_F12R2_FB22_Pos     (22U)
5344 #define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
5345 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
5346 #define CAN_F12R2_FB23_Pos     (23U)
5347 #define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
5348 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
5349 #define CAN_F12R2_FB24_Pos     (24U)
5350 #define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
5351 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
5352 #define CAN_F12R2_FB25_Pos     (25U)
5353 #define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
5354 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
5355 #define CAN_F12R2_FB26_Pos     (26U)
5356 #define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
5357 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
5358 #define CAN_F12R2_FB27_Pos     (27U)
5359 #define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
5360 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
5361 #define CAN_F12R2_FB28_Pos     (28U)
5362 #define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
5363 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
5364 #define CAN_F12R2_FB29_Pos     (29U)
5365 #define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
5366 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
5367 #define CAN_F12R2_FB30_Pos     (30U)
5368 #define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
5369 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
5370 #define CAN_F12R2_FB31_Pos     (31U)
5371 #define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
5372 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
5373 
5374 /*******************  Bit definition for CAN_F13R2 register  ******************/
5375 #define CAN_F13R2_FB0_Pos      (0U)
5376 #define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
5377 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
5378 #define CAN_F13R2_FB1_Pos      (1U)
5379 #define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
5380 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
5381 #define CAN_F13R2_FB2_Pos      (2U)
5382 #define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
5383 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
5384 #define CAN_F13R2_FB3_Pos      (3U)
5385 #define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
5386 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
5387 #define CAN_F13R2_FB4_Pos      (4U)
5388 #define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
5389 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
5390 #define CAN_F13R2_FB5_Pos      (5U)
5391 #define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
5392 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
5393 #define CAN_F13R2_FB6_Pos      (6U)
5394 #define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
5395 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
5396 #define CAN_F13R2_FB7_Pos      (7U)
5397 #define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
5398 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
5399 #define CAN_F13R2_FB8_Pos      (8U)
5400 #define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
5401 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
5402 #define CAN_F13R2_FB9_Pos      (9U)
5403 #define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
5404 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
5405 #define CAN_F13R2_FB10_Pos     (10U)
5406 #define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
5407 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
5408 #define CAN_F13R2_FB11_Pos     (11U)
5409 #define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
5410 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
5411 #define CAN_F13R2_FB12_Pos     (12U)
5412 #define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
5413 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
5414 #define CAN_F13R2_FB13_Pos     (13U)
5415 #define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
5416 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
5417 #define CAN_F13R2_FB14_Pos     (14U)
5418 #define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
5419 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
5420 #define CAN_F13R2_FB15_Pos     (15U)
5421 #define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
5422 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
5423 #define CAN_F13R2_FB16_Pos     (16U)
5424 #define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
5425 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
5426 #define CAN_F13R2_FB17_Pos     (17U)
5427 #define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
5428 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
5429 #define CAN_F13R2_FB18_Pos     (18U)
5430 #define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
5431 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
5432 #define CAN_F13R2_FB19_Pos     (19U)
5433 #define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
5434 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
5435 #define CAN_F13R2_FB20_Pos     (20U)
5436 #define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
5437 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
5438 #define CAN_F13R2_FB21_Pos     (21U)
5439 #define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
5440 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
5441 #define CAN_F13R2_FB22_Pos     (22U)
5442 #define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
5443 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
5444 #define CAN_F13R2_FB23_Pos     (23U)
5445 #define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
5446 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
5447 #define CAN_F13R2_FB24_Pos     (24U)
5448 #define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
5449 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
5450 #define CAN_F13R2_FB25_Pos     (25U)
5451 #define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
5452 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
5453 #define CAN_F13R2_FB26_Pos     (26U)
5454 #define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
5455 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
5456 #define CAN_F13R2_FB27_Pos     (27U)
5457 #define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
5458 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
5459 #define CAN_F13R2_FB28_Pos     (28U)
5460 #define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
5461 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
5462 #define CAN_F13R2_FB29_Pos     (29U)
5463 #define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
5464 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
5465 #define CAN_F13R2_FB30_Pos     (30U)
5466 #define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
5467 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
5468 #define CAN_F13R2_FB31_Pos     (31U)
5469 #define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
5470 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
5471 
5472 /******************************************************************************/
5473 /*                                                                            */
5474 /*                          CRC calculation unit                              */
5475 /*                                                                            */
5476 /******************************************************************************/
5477 /*******************  Bit definition for CRC_DR register  *********************/
5478 #define CRC_DR_DR_Pos       (0U)
5479 #define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
5480 #define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
5481 
5482 
5483 /*******************  Bit definition for CRC_IDR register  ********************/
5484 #define CRC_IDR_IDR_Pos     (0U)
5485 #define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
5486 #define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
5487 
5488 
5489 /********************  Bit definition for CRC_CR register  ********************/
5490 #define CRC_CR_RESET_Pos    (0U)
5491 #define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
5492 #define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
5493 
5494 /******************************************************************************/
5495 /*                                                                            */
5496 /*                            Crypto Processor                                */
5497 /*                                                                            */
5498 /******************************************************************************/
5499 /******************* Bits definition for CRYP_CR register  ********************/
5500 #define CRYP_CR_ALGODIR_Pos              (2U)
5501 #define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)         /*!< 0x00000004 */
5502 #define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk
5503 
5504 #define CRYP_CR_ALGOMODE_Pos             (3U)
5505 #define CRYP_CR_ALGOMODE_Msk             (0x7UL << CRYP_CR_ALGOMODE_Pos)        /*!< 0x00000038 */
5506 #define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk
5507 #define CRYP_CR_ALGOMODE_0               (0x1UL << CRYP_CR_ALGOMODE_Pos)        /*!< 0x00000008 */
5508 #define CRYP_CR_ALGOMODE_1               (0x2UL << CRYP_CR_ALGOMODE_Pos)        /*!< 0x00000010 */
5509 #define CRYP_CR_ALGOMODE_2               (0x4UL << CRYP_CR_ALGOMODE_Pos)        /*!< 0x00000020 */
5510 #define CRYP_CR_ALGOMODE_TDES_ECB        0x00000000U
5511 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
5512 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5513 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
5514 #define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)
5515 #define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5516 #define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk
5517 #define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)
5518 #define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5519 #define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk
5520 #define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)
5521 #define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5522 #define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk
5523 #define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)
5524 #define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5525 #define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk
5526 #define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)
5527 #define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5528 #define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk
5529 #define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)
5530 #define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5531 #define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk
5532 
5533 #define CRYP_CR_DATATYPE_Pos             (6U)
5534 #define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x000000C0 */
5535 #define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk
5536 #define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */
5537 #define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */
5538 #define CRYP_CR_KEYSIZE_Pos              (8U)
5539 #define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000300 */
5540 #define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk
5541 #define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */
5542 #define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */
5543 #define CRYP_CR_FFLUSH_Pos               (14U)
5544 #define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)          /*!< 0x00004000 */
5545 #define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk
5546 #define CRYP_CR_CRYPEN_Pos               (15U)
5547 #define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)          /*!< 0x00008000 */
5548 #define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk
5549 /****************** Bits definition for CRYP_SR register  *********************/
5550 #define CRYP_SR_IFEM_Pos                 (0U)
5551 #define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)            /*!< 0x00000001 */
5552 #define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk
5553 #define CRYP_SR_IFNF_Pos                 (1U)
5554 #define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)            /*!< 0x00000002 */
5555 #define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk
5556 #define CRYP_SR_OFNE_Pos                 (2U)
5557 #define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)            /*!< 0x00000004 */
5558 #define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk
5559 #define CRYP_SR_OFFU_Pos                 (3U)
5560 #define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)            /*!< 0x00000008 */
5561 #define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk
5562 #define CRYP_SR_BUSY_Pos                 (4U)
5563 #define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)            /*!< 0x00000010 */
5564 #define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk
5565 /****************** Bits definition for CRYP_DMACR register  ******************/
5566 #define CRYP_DMACR_DIEN_Pos              (0U)
5567 #define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)         /*!< 0x00000001 */
5568 #define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk
5569 #define CRYP_DMACR_DOEN_Pos              (1U)
5570 #define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)         /*!< 0x00000002 */
5571 #define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk
5572 /*****************  Bits definition for CRYP_IMSCR register  ******************/
5573 #define CRYP_IMSCR_INIM_Pos              (0U)
5574 #define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)         /*!< 0x00000001 */
5575 #define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk
5576 #define CRYP_IMSCR_OUTIM_Pos             (1U)
5577 #define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)        /*!< 0x00000002 */
5578 #define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk
5579 /****************** Bits definition for CRYP_RISR register  *******************/
5580 #define CRYP_RISR_OUTRIS_Pos             (0U)
5581 #define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)        /*!< 0x00000001 */
5582 #define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk
5583 #define CRYP_RISR_INRIS_Pos              (1U)
5584 #define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)         /*!< 0x00000002 */
5585 #define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk
5586 /****************** Bits definition for CRYP_MISR register  *******************/
5587 #define CRYP_MISR_INMIS_Pos              (0U)
5588 #define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)         /*!< 0x00000001 */
5589 #define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk
5590 #define CRYP_MISR_OUTMIS_Pos             (1U)
5591 #define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)        /*!< 0x00000002 */
5592 #define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk
5593 
5594 /******************************************************************************/
5595 /*                                                                            */
5596 /*                      Digital to Analog Converter                           */
5597 /*                                                                            */
5598 /******************************************************************************/
5599 /********************  Bit definition for DAC_CR register  ********************/
5600 #define DAC_CR_EN1_Pos              (0U)
5601 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
5602 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
5603 #define DAC_CR_BOFF1_Pos            (1U)
5604 #define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
5605 #define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
5606 #define DAC_CR_TEN1_Pos             (2U)
5607 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
5608 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
5609 
5610 #define DAC_CR_TSEL1_Pos            (3U)
5611 #define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
5612 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5613 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
5614 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
5615 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
5616 
5617 #define DAC_CR_WAVE1_Pos            (6U)
5618 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
5619 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5620 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
5621 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
5622 
5623 #define DAC_CR_MAMP1_Pos            (8U)
5624 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
5625 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5626 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
5627 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
5628 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
5629 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
5630 
5631 #define DAC_CR_DMAEN1_Pos           (12U)
5632 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
5633 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
5634 #define DAC_CR_DMAUDRIE1_Pos        (13U)
5635 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
5636 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
5637 #define DAC_CR_EN2_Pos              (16U)
5638 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
5639 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
5640 #define DAC_CR_BOFF2_Pos            (17U)
5641 #define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
5642 #define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
5643 #define DAC_CR_TEN2_Pos             (18U)
5644 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
5645 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
5646 
5647 #define DAC_CR_TSEL2_Pos            (19U)
5648 #define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
5649 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5650 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
5651 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
5652 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
5653 
5654 #define DAC_CR_WAVE2_Pos            (22U)
5655 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
5656 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5657 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
5658 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
5659 
5660 #define DAC_CR_MAMP2_Pos            (24U)
5661 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
5662 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5663 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
5664 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
5665 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
5666 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
5667 
5668 #define DAC_CR_DMAEN2_Pos           (28U)
5669 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
5670 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
5671 #define DAC_CR_DMAUDRIE2_Pos        (29U)
5672 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
5673 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
5674 
5675 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
5676 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
5677 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
5678 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
5679 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
5680 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
5681 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
5682 
5683 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
5684 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
5685 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
5686 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5687 
5688 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
5689 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
5690 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5691 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5692 
5693 /******************  Bit definition for DAC_DHR8R1 register  ******************/
5694 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
5695 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
5696 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5697 
5698 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
5699 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
5700 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
5701 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5702 
5703 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
5704 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
5705 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
5706 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5707 
5708 /******************  Bit definition for DAC_DHR8R2 register  ******************/
5709 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
5710 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
5711 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5712 
5713 /*****************  Bit definition for DAC_DHR12RD register  ******************/
5714 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
5715 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
5716 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
5717 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
5718 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
5719 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
5720 
5721 /*****************  Bit definition for DAC_DHR12LD register  ******************/
5722 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
5723 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
5724 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
5725 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
5726 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
5727 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
5728 
5729 /******************  Bit definition for DAC_DHR8RD register  ******************/
5730 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
5731 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
5732 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
5733 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
5734 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
5735 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
5736 
5737 /*******************  Bit definition for DAC_DOR1 register  *******************/
5738 #define DAC_DOR1_DACC1DOR_Pos       (0U)
5739 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
5740 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
5741 
5742 /*******************  Bit definition for DAC_DOR2 register  *******************/
5743 #define DAC_DOR2_DACC2DOR_Pos       (0U)
5744 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
5745 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
5746 
5747 /********************  Bit definition for DAC_SR register  ********************/
5748 #define DAC_SR_DMAUDR1_Pos          (13U)
5749 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
5750 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
5751 #define DAC_SR_DMAUDR2_Pos          (29U)
5752 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
5753 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
5754 
5755 /******************************************************************************/
5756 /*                                                                            */
5757 /*                                 Debug MCU                                  */
5758 /*                                                                            */
5759 /******************************************************************************/
5760 
5761 /******************************************************************************/
5762 /*                                                                            */
5763 /*                                    DCMI                                    */
5764 /*                                                                            */
5765 /******************************************************************************/
5766 /********************  Bits definition for DCMI_CR register  ******************/
5767 #define DCMI_CR_CAPTURE_Pos        (0U)
5768 #define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
5769 #define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
5770 #define DCMI_CR_CM_Pos             (1U)
5771 #define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
5772 #define DCMI_CR_CM                 DCMI_CR_CM_Msk
5773 #define DCMI_CR_CROP_Pos           (2U)
5774 #define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
5775 #define DCMI_CR_CROP               DCMI_CR_CROP_Msk
5776 #define DCMI_CR_JPEG_Pos           (3U)
5777 #define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
5778 #define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
5779 #define DCMI_CR_ESS_Pos            (4U)
5780 #define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
5781 #define DCMI_CR_ESS                DCMI_CR_ESS_Msk
5782 #define DCMI_CR_PCKPOL_Pos         (5U)
5783 #define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
5784 #define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
5785 #define DCMI_CR_HSPOL_Pos          (6U)
5786 #define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
5787 #define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
5788 #define DCMI_CR_VSPOL_Pos          (7U)
5789 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
5790 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
5791 #define DCMI_CR_FCRC_0             0x00000100U
5792 #define DCMI_CR_FCRC_1             0x00000200U
5793 #define DCMI_CR_EDM_0              0x00000400U
5794 #define DCMI_CR_EDM_1              0x00000800U
5795 #define DCMI_CR_CRE_Pos            (12U)
5796 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                   /*!< 0x00001000 */
5797 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
5798 #define DCMI_CR_ENABLE_Pos         (14U)
5799 #define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
5800 #define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
5801 
5802 /********************  Bits definition for DCMI_SR register  ******************/
5803 #define DCMI_SR_HSYNC_Pos          (0U)
5804 #define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
5805 #define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
5806 #define DCMI_SR_VSYNC_Pos          (1U)
5807 #define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
5808 #define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
5809 #define DCMI_SR_FNE_Pos            (2U)
5810 #define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
5811 #define DCMI_SR_FNE                DCMI_SR_FNE_Msk
5812 
5813 /********************  Bits definition for DCMI_RIS register  *****************/
5814 #define DCMI_RIS_FRAME_RIS_Pos     (0U)
5815 #define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
5816 #define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
5817 #define DCMI_RIS_OVR_RIS_Pos       (1U)
5818 #define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
5819 #define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
5820 #define DCMI_RIS_ERR_RIS_Pos       (2U)
5821 #define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
5822 #define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
5823 #define DCMI_RIS_VSYNC_RIS_Pos     (3U)
5824 #define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
5825 #define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
5826 #define DCMI_RIS_LINE_RIS_Pos      (4U)
5827 #define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
5828 #define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
5829 /* Legacy defines */
5830 #define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
5831 #define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
5832 #define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
5833 #define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
5834 #define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
5835 
5836 /********************  Bits definition for DCMI_IER register  *****************/
5837 #define DCMI_IER_FRAME_IE_Pos      (0U)
5838 #define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
5839 #define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
5840 #define DCMI_IER_OVR_IE_Pos        (1U)
5841 #define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
5842 #define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
5843 #define DCMI_IER_ERR_IE_Pos        (2U)
5844 #define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
5845 #define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
5846 #define DCMI_IER_VSYNC_IE_Pos      (3U)
5847 #define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
5848 #define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
5849 #define DCMI_IER_LINE_IE_Pos       (4U)
5850 #define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
5851 #define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
5852 /* Legacy defines */
5853 #define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
5854 
5855 /********************  Bits definition for DCMI_MIS register  *****************/
5856 #define DCMI_MIS_FRAME_MIS_Pos     (0U)
5857 #define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
5858 #define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
5859 #define DCMI_MIS_OVR_MIS_Pos       (1U)
5860 #define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
5861 #define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
5862 #define DCMI_MIS_ERR_MIS_Pos       (2U)
5863 #define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
5864 #define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
5865 #define DCMI_MIS_VSYNC_MIS_Pos     (3U)
5866 #define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
5867 #define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
5868 #define DCMI_MIS_LINE_MIS_Pos      (4U)
5869 #define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
5870 #define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
5871 
5872 /* Legacy defines */
5873 #define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
5874 #define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
5875 #define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
5876 #define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
5877 #define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
5878 
5879 /********************  Bits definition for DCMI_ICR register  *****************/
5880 #define DCMI_ICR_FRAME_ISC_Pos     (0U)
5881 #define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
5882 #define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
5883 #define DCMI_ICR_OVR_ISC_Pos       (1U)
5884 #define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
5885 #define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
5886 #define DCMI_ICR_ERR_ISC_Pos       (2U)
5887 #define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
5888 #define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
5889 #define DCMI_ICR_VSYNC_ISC_Pos     (3U)
5890 #define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
5891 #define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
5892 #define DCMI_ICR_LINE_ISC_Pos      (4U)
5893 #define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
5894 #define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
5895 
5896 /* Legacy defines */
5897 #define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
5898 
5899 /********************  Bits definition for DCMI_ESCR register  ******************/
5900 #define DCMI_ESCR_FSC_Pos          (0U)
5901 #define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
5902 #define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
5903 #define DCMI_ESCR_LSC_Pos          (8U)
5904 #define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
5905 #define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
5906 #define DCMI_ESCR_LEC_Pos          (16U)
5907 #define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
5908 #define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
5909 #define DCMI_ESCR_FEC_Pos          (24U)
5910 #define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
5911 #define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
5912 
5913 /********************  Bits definition for DCMI_ESUR register  ******************/
5914 #define DCMI_ESUR_FSU_Pos          (0U)
5915 #define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
5916 #define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
5917 #define DCMI_ESUR_LSU_Pos          (8U)
5918 #define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
5919 #define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
5920 #define DCMI_ESUR_LEU_Pos          (16U)
5921 #define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
5922 #define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
5923 #define DCMI_ESUR_FEU_Pos          (24U)
5924 #define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
5925 #define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
5926 
5927 /********************  Bits definition for DCMI_CWSTRT register  ******************/
5928 #define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
5929 #define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
5930 #define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
5931 #define DCMI_CWSTRT_VST_Pos        (16U)
5932 #define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
5933 #define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
5934 
5935 /********************  Bits definition for DCMI_CWSIZE register  ******************/
5936 #define DCMI_CWSIZE_CAPCNT_Pos     (0U)
5937 #define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
5938 #define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
5939 #define DCMI_CWSIZE_VLINE_Pos      (16U)
5940 #define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
5941 #define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
5942 
5943 /********************  Bits definition for DCMI_DR register  ******************/
5944 #define DCMI_DR_BYTE0_Pos          (0U)
5945 #define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
5946 #define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
5947 #define DCMI_DR_BYTE1_Pos          (8U)
5948 #define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
5949 #define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
5950 #define DCMI_DR_BYTE2_Pos          (16U)
5951 #define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
5952 #define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
5953 #define DCMI_DR_BYTE3_Pos          (24U)
5954 #define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
5955 #define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
5956 
5957 /******************************************************************************/
5958 /*                                                                            */
5959 /*                             DMA Controller                                 */
5960 /*                                                                            */
5961 /******************************************************************************/
5962 /********************  Bits definition for DMA_SxCR register  *****************/
5963 #define DMA_SxCR_CHSEL_Pos       (25U)
5964 #define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
5965 #define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk
5966 #define DMA_SxCR_CHSEL_0         (0x1UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x02000000 */
5967 #define DMA_SxCR_CHSEL_1         (0x2UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x04000000 */
5968 #define DMA_SxCR_CHSEL_2         (0x4UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x08000000 */
5969 #define DMA_SxCR_MBURST_Pos      (23U)
5970 #define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
5971 #define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk
5972 #define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
5973 #define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
5974 #define DMA_SxCR_PBURST_Pos      (21U)
5975 #define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
5976 #define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk
5977 #define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
5978 #define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
5979 #define DMA_SxCR_CT_Pos          (19U)
5980 #define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
5981 #define DMA_SxCR_CT              DMA_SxCR_CT_Msk
5982 #define DMA_SxCR_DBM_Pos         (18U)
5983 #define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
5984 #define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk
5985 #define DMA_SxCR_PL_Pos          (16U)
5986 #define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
5987 #define DMA_SxCR_PL              DMA_SxCR_PL_Msk
5988 #define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
5989 #define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
5990 #define DMA_SxCR_PINCOS_Pos      (15U)
5991 #define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
5992 #define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk
5993 #define DMA_SxCR_MSIZE_Pos       (13U)
5994 #define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
5995 #define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk
5996 #define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
5997 #define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
5998 #define DMA_SxCR_PSIZE_Pos       (11U)
5999 #define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
6000 #define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk
6001 #define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
6002 #define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
6003 #define DMA_SxCR_MINC_Pos        (10U)
6004 #define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
6005 #define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk
6006 #define DMA_SxCR_PINC_Pos        (9U)
6007 #define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
6008 #define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk
6009 #define DMA_SxCR_CIRC_Pos        (8U)
6010 #define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
6011 #define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk
6012 #define DMA_SxCR_DIR_Pos         (6U)
6013 #define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
6014 #define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk
6015 #define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
6016 #define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
6017 #define DMA_SxCR_PFCTRL_Pos      (5U)
6018 #define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
6019 #define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk
6020 #define DMA_SxCR_TCIE_Pos        (4U)
6021 #define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
6022 #define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk
6023 #define DMA_SxCR_HTIE_Pos        (3U)
6024 #define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
6025 #define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk
6026 #define DMA_SxCR_TEIE_Pos        (2U)
6027 #define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
6028 #define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk
6029 #define DMA_SxCR_DMEIE_Pos       (1U)
6030 #define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
6031 #define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk
6032 #define DMA_SxCR_EN_Pos          (0U)
6033 #define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
6034 #define DMA_SxCR_EN              DMA_SxCR_EN_Msk
6035 
6036 /* Legacy defines */
6037 #define DMA_SxCR_ACK_Pos         (20U)
6038 #define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
6039 #define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk
6040 
6041 /********************  Bits definition for DMA_SxCNDTR register  **************/
6042 #define DMA_SxNDT_Pos            (0U)
6043 #define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
6044 #define DMA_SxNDT                DMA_SxNDT_Msk
6045 #define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
6046 #define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
6047 #define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
6048 #define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
6049 #define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
6050 #define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
6051 #define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
6052 #define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
6053 #define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
6054 #define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
6055 #define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
6056 #define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
6057 #define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
6058 #define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
6059 #define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
6060 #define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
6061 
6062 /********************  Bits definition for DMA_SxFCR register  ****************/
6063 #define DMA_SxFCR_FEIE_Pos       (7U)
6064 #define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
6065 #define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk
6066 #define DMA_SxFCR_FS_Pos         (3U)
6067 #define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
6068 #define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk
6069 #define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
6070 #define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
6071 #define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
6072 #define DMA_SxFCR_DMDIS_Pos      (2U)
6073 #define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
6074 #define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk
6075 #define DMA_SxFCR_FTH_Pos        (0U)
6076 #define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
6077 #define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk
6078 #define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
6079 #define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
6080 
6081 /********************  Bits definition for DMA_LISR register  *****************/
6082 #define DMA_LISR_TCIF3_Pos       (27U)
6083 #define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
6084 #define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk
6085 #define DMA_LISR_HTIF3_Pos       (26U)
6086 #define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
6087 #define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk
6088 #define DMA_LISR_TEIF3_Pos       (25U)
6089 #define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
6090 #define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk
6091 #define DMA_LISR_DMEIF3_Pos      (24U)
6092 #define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
6093 #define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk
6094 #define DMA_LISR_FEIF3_Pos       (22U)
6095 #define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
6096 #define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk
6097 #define DMA_LISR_TCIF2_Pos       (21U)
6098 #define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
6099 #define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk
6100 #define DMA_LISR_HTIF2_Pos       (20U)
6101 #define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
6102 #define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk
6103 #define DMA_LISR_TEIF2_Pos       (19U)
6104 #define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
6105 #define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk
6106 #define DMA_LISR_DMEIF2_Pos      (18U)
6107 #define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
6108 #define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk
6109 #define DMA_LISR_FEIF2_Pos       (16U)
6110 #define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
6111 #define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk
6112 #define DMA_LISR_TCIF1_Pos       (11U)
6113 #define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
6114 #define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk
6115 #define DMA_LISR_HTIF1_Pos       (10U)
6116 #define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
6117 #define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk
6118 #define DMA_LISR_TEIF1_Pos       (9U)
6119 #define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
6120 #define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk
6121 #define DMA_LISR_DMEIF1_Pos      (8U)
6122 #define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
6123 #define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk
6124 #define DMA_LISR_FEIF1_Pos       (6U)
6125 #define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
6126 #define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk
6127 #define DMA_LISR_TCIF0_Pos       (5U)
6128 #define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
6129 #define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk
6130 #define DMA_LISR_HTIF0_Pos       (4U)
6131 #define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
6132 #define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk
6133 #define DMA_LISR_TEIF0_Pos       (3U)
6134 #define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
6135 #define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk
6136 #define DMA_LISR_DMEIF0_Pos      (2U)
6137 #define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
6138 #define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk
6139 #define DMA_LISR_FEIF0_Pos       (0U)
6140 #define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
6141 #define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk
6142 
6143 /********************  Bits definition for DMA_HISR register  *****************/
6144 #define DMA_HISR_TCIF7_Pos       (27U)
6145 #define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
6146 #define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk
6147 #define DMA_HISR_HTIF7_Pos       (26U)
6148 #define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
6149 #define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk
6150 #define DMA_HISR_TEIF7_Pos       (25U)
6151 #define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
6152 #define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk
6153 #define DMA_HISR_DMEIF7_Pos      (24U)
6154 #define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
6155 #define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk
6156 #define DMA_HISR_FEIF7_Pos       (22U)
6157 #define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
6158 #define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk
6159 #define DMA_HISR_TCIF6_Pos       (21U)
6160 #define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
6161 #define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk
6162 #define DMA_HISR_HTIF6_Pos       (20U)
6163 #define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
6164 #define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk
6165 #define DMA_HISR_TEIF6_Pos       (19U)
6166 #define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
6167 #define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk
6168 #define DMA_HISR_DMEIF6_Pos      (18U)
6169 #define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
6170 #define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk
6171 #define DMA_HISR_FEIF6_Pos       (16U)
6172 #define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
6173 #define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk
6174 #define DMA_HISR_TCIF5_Pos       (11U)
6175 #define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
6176 #define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk
6177 #define DMA_HISR_HTIF5_Pos       (10U)
6178 #define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
6179 #define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk
6180 #define DMA_HISR_TEIF5_Pos       (9U)
6181 #define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
6182 #define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk
6183 #define DMA_HISR_DMEIF5_Pos      (8U)
6184 #define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
6185 #define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk
6186 #define DMA_HISR_FEIF5_Pos       (6U)
6187 #define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
6188 #define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk
6189 #define DMA_HISR_TCIF4_Pos       (5U)
6190 #define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
6191 #define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk
6192 #define DMA_HISR_HTIF4_Pos       (4U)
6193 #define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
6194 #define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk
6195 #define DMA_HISR_TEIF4_Pos       (3U)
6196 #define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
6197 #define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk
6198 #define DMA_HISR_DMEIF4_Pos      (2U)
6199 #define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
6200 #define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk
6201 #define DMA_HISR_FEIF4_Pos       (0U)
6202 #define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
6203 #define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk
6204 
6205 /********************  Bits definition for DMA_LIFCR register  ****************/
6206 #define DMA_LIFCR_CTCIF3_Pos     (27U)
6207 #define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
6208 #define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk
6209 #define DMA_LIFCR_CHTIF3_Pos     (26U)
6210 #define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
6211 #define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk
6212 #define DMA_LIFCR_CTEIF3_Pos     (25U)
6213 #define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
6214 #define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk
6215 #define DMA_LIFCR_CDMEIF3_Pos    (24U)
6216 #define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
6217 #define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk
6218 #define DMA_LIFCR_CFEIF3_Pos     (22U)
6219 #define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
6220 #define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk
6221 #define DMA_LIFCR_CTCIF2_Pos     (21U)
6222 #define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
6223 #define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk
6224 #define DMA_LIFCR_CHTIF2_Pos     (20U)
6225 #define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
6226 #define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk
6227 #define DMA_LIFCR_CTEIF2_Pos     (19U)
6228 #define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
6229 #define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk
6230 #define DMA_LIFCR_CDMEIF2_Pos    (18U)
6231 #define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
6232 #define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk
6233 #define DMA_LIFCR_CFEIF2_Pos     (16U)
6234 #define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
6235 #define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk
6236 #define DMA_LIFCR_CTCIF1_Pos     (11U)
6237 #define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
6238 #define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk
6239 #define DMA_LIFCR_CHTIF1_Pos     (10U)
6240 #define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
6241 #define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk
6242 #define DMA_LIFCR_CTEIF1_Pos     (9U)
6243 #define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
6244 #define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk
6245 #define DMA_LIFCR_CDMEIF1_Pos    (8U)
6246 #define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
6247 #define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk
6248 #define DMA_LIFCR_CFEIF1_Pos     (6U)
6249 #define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
6250 #define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk
6251 #define DMA_LIFCR_CTCIF0_Pos     (5U)
6252 #define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
6253 #define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk
6254 #define DMA_LIFCR_CHTIF0_Pos     (4U)
6255 #define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
6256 #define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk
6257 #define DMA_LIFCR_CTEIF0_Pos     (3U)
6258 #define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
6259 #define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk
6260 #define DMA_LIFCR_CDMEIF0_Pos    (2U)
6261 #define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
6262 #define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk
6263 #define DMA_LIFCR_CFEIF0_Pos     (0U)
6264 #define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
6265 #define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk
6266 
6267 /********************  Bits definition for DMA_HIFCR  register  ****************/
6268 #define DMA_HIFCR_CTCIF7_Pos     (27U)
6269 #define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
6270 #define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk
6271 #define DMA_HIFCR_CHTIF7_Pos     (26U)
6272 #define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
6273 #define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk
6274 #define DMA_HIFCR_CTEIF7_Pos     (25U)
6275 #define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
6276 #define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk
6277 #define DMA_HIFCR_CDMEIF7_Pos    (24U)
6278 #define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
6279 #define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk
6280 #define DMA_HIFCR_CFEIF7_Pos     (22U)
6281 #define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
6282 #define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk
6283 #define DMA_HIFCR_CTCIF6_Pos     (21U)
6284 #define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
6285 #define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk
6286 #define DMA_HIFCR_CHTIF6_Pos     (20U)
6287 #define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
6288 #define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk
6289 #define DMA_HIFCR_CTEIF6_Pos     (19U)
6290 #define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
6291 #define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk
6292 #define DMA_HIFCR_CDMEIF6_Pos    (18U)
6293 #define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
6294 #define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk
6295 #define DMA_HIFCR_CFEIF6_Pos     (16U)
6296 #define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
6297 #define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk
6298 #define DMA_HIFCR_CTCIF5_Pos     (11U)
6299 #define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
6300 #define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk
6301 #define DMA_HIFCR_CHTIF5_Pos     (10U)
6302 #define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
6303 #define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk
6304 #define DMA_HIFCR_CTEIF5_Pos     (9U)
6305 #define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
6306 #define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk
6307 #define DMA_HIFCR_CDMEIF5_Pos    (8U)
6308 #define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
6309 #define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk
6310 #define DMA_HIFCR_CFEIF5_Pos     (6U)
6311 #define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
6312 #define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk
6313 #define DMA_HIFCR_CTCIF4_Pos     (5U)
6314 #define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
6315 #define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk
6316 #define DMA_HIFCR_CHTIF4_Pos     (4U)
6317 #define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
6318 #define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk
6319 #define DMA_HIFCR_CTEIF4_Pos     (3U)
6320 #define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
6321 #define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk
6322 #define DMA_HIFCR_CDMEIF4_Pos    (2U)
6323 #define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
6324 #define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk
6325 #define DMA_HIFCR_CFEIF4_Pos     (0U)
6326 #define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
6327 #define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk
6328 
6329 /******************  Bit definition for DMA_SxPAR register  ********************/
6330 #define DMA_SxPAR_PA_Pos         (0U)
6331 #define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
6332 #define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
6333 
6334 /******************  Bit definition for DMA_SxM0AR register  ********************/
6335 #define DMA_SxM0AR_M0A_Pos       (0U)
6336 #define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
6337 #define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
6338 
6339 /******************  Bit definition for DMA_SxM1AR register  ********************/
6340 #define DMA_SxM1AR_M1A_Pos       (0U)
6341 #define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
6342 #define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
6343 
6344 /******************************************************************************/
6345 /*                                                                            */
6346 /*                    External Interrupt/Event Controller                     */
6347 /*                                                                            */
6348 /******************************************************************************/
6349 /*******************  Bit definition for EXTI_IMR register  *******************/
6350 #define EXTI_IMR_MR0_Pos          (0U)
6351 #define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
6352 #define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
6353 #define EXTI_IMR_MR1_Pos          (1U)
6354 #define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
6355 #define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
6356 #define EXTI_IMR_MR2_Pos          (2U)
6357 #define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
6358 #define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
6359 #define EXTI_IMR_MR3_Pos          (3U)
6360 #define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
6361 #define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
6362 #define EXTI_IMR_MR4_Pos          (4U)
6363 #define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
6364 #define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
6365 #define EXTI_IMR_MR5_Pos          (5U)
6366 #define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
6367 #define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
6368 #define EXTI_IMR_MR6_Pos          (6U)
6369 #define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
6370 #define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
6371 #define EXTI_IMR_MR7_Pos          (7U)
6372 #define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
6373 #define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
6374 #define EXTI_IMR_MR8_Pos          (8U)
6375 #define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
6376 #define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
6377 #define EXTI_IMR_MR9_Pos          (9U)
6378 #define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
6379 #define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
6380 #define EXTI_IMR_MR10_Pos         (10U)
6381 #define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
6382 #define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
6383 #define EXTI_IMR_MR11_Pos         (11U)
6384 #define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
6385 #define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
6386 #define EXTI_IMR_MR12_Pos         (12U)
6387 #define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
6388 #define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
6389 #define EXTI_IMR_MR13_Pos         (13U)
6390 #define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
6391 #define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
6392 #define EXTI_IMR_MR14_Pos         (14U)
6393 #define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
6394 #define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
6395 #define EXTI_IMR_MR15_Pos         (15U)
6396 #define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
6397 #define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
6398 #define EXTI_IMR_MR16_Pos         (16U)
6399 #define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
6400 #define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
6401 #define EXTI_IMR_MR17_Pos         (17U)
6402 #define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
6403 #define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
6404 #define EXTI_IMR_MR18_Pos         (18U)
6405 #define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
6406 #define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
6407 #define EXTI_IMR_MR19_Pos         (19U)
6408 #define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
6409 #define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
6410 #define EXTI_IMR_MR20_Pos         (20U)
6411 #define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
6412 #define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
6413 #define EXTI_IMR_MR21_Pos         (21U)
6414 #define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
6415 #define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
6416 #define EXTI_IMR_MR22_Pos         (22U)
6417 #define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
6418 #define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
6419 
6420 /* Reference Defines */
6421 #define  EXTI_IMR_IM0                        EXTI_IMR_MR0
6422 #define  EXTI_IMR_IM1                        EXTI_IMR_MR1
6423 #define  EXTI_IMR_IM2                        EXTI_IMR_MR2
6424 #define  EXTI_IMR_IM3                        EXTI_IMR_MR3
6425 #define  EXTI_IMR_IM4                        EXTI_IMR_MR4
6426 #define  EXTI_IMR_IM5                        EXTI_IMR_MR5
6427 #define  EXTI_IMR_IM6                        EXTI_IMR_MR6
6428 #define  EXTI_IMR_IM7                        EXTI_IMR_MR7
6429 #define  EXTI_IMR_IM8                        EXTI_IMR_MR8
6430 #define  EXTI_IMR_IM9                        EXTI_IMR_MR9
6431 #define  EXTI_IMR_IM10                       EXTI_IMR_MR10
6432 #define  EXTI_IMR_IM11                       EXTI_IMR_MR11
6433 #define  EXTI_IMR_IM12                       EXTI_IMR_MR12
6434 #define  EXTI_IMR_IM13                       EXTI_IMR_MR13
6435 #define  EXTI_IMR_IM14                       EXTI_IMR_MR14
6436 #define  EXTI_IMR_IM15                       EXTI_IMR_MR15
6437 #define  EXTI_IMR_IM16                       EXTI_IMR_MR16
6438 #define  EXTI_IMR_IM17                       EXTI_IMR_MR17
6439 #define  EXTI_IMR_IM18                       EXTI_IMR_MR18
6440 #define  EXTI_IMR_IM19                       EXTI_IMR_MR19
6441 #define  EXTI_IMR_IM20                       EXTI_IMR_MR20
6442 #define  EXTI_IMR_IM21                       EXTI_IMR_MR21
6443 #define  EXTI_IMR_IM22                       EXTI_IMR_MR22
6444 #define EXTI_IMR_IM_Pos           (0U)
6445 #define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
6446 #define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
6447 
6448 /*******************  Bit definition for EXTI_EMR register  *******************/
6449 #define EXTI_EMR_MR0_Pos          (0U)
6450 #define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
6451 #define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
6452 #define EXTI_EMR_MR1_Pos          (1U)
6453 #define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
6454 #define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
6455 #define EXTI_EMR_MR2_Pos          (2U)
6456 #define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
6457 #define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
6458 #define EXTI_EMR_MR3_Pos          (3U)
6459 #define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
6460 #define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
6461 #define EXTI_EMR_MR4_Pos          (4U)
6462 #define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
6463 #define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
6464 #define EXTI_EMR_MR5_Pos          (5U)
6465 #define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
6466 #define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
6467 #define EXTI_EMR_MR6_Pos          (6U)
6468 #define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
6469 #define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
6470 #define EXTI_EMR_MR7_Pos          (7U)
6471 #define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
6472 #define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
6473 #define EXTI_EMR_MR8_Pos          (8U)
6474 #define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
6475 #define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
6476 #define EXTI_EMR_MR9_Pos          (9U)
6477 #define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
6478 #define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
6479 #define EXTI_EMR_MR10_Pos         (10U)
6480 #define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
6481 #define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
6482 #define EXTI_EMR_MR11_Pos         (11U)
6483 #define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
6484 #define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
6485 #define EXTI_EMR_MR12_Pos         (12U)
6486 #define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
6487 #define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
6488 #define EXTI_EMR_MR13_Pos         (13U)
6489 #define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
6490 #define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
6491 #define EXTI_EMR_MR14_Pos         (14U)
6492 #define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
6493 #define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
6494 #define EXTI_EMR_MR15_Pos         (15U)
6495 #define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
6496 #define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
6497 #define EXTI_EMR_MR16_Pos         (16U)
6498 #define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
6499 #define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
6500 #define EXTI_EMR_MR17_Pos         (17U)
6501 #define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
6502 #define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
6503 #define EXTI_EMR_MR18_Pos         (18U)
6504 #define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
6505 #define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
6506 #define EXTI_EMR_MR19_Pos         (19U)
6507 #define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
6508 #define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
6509 #define EXTI_EMR_MR20_Pos         (20U)
6510 #define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
6511 #define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
6512 #define EXTI_EMR_MR21_Pos         (21U)
6513 #define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
6514 #define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
6515 #define EXTI_EMR_MR22_Pos         (22U)
6516 #define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
6517 #define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
6518 
6519 /* Reference Defines */
6520 #define  EXTI_EMR_EM0                        EXTI_EMR_MR0
6521 #define  EXTI_EMR_EM1                        EXTI_EMR_MR1
6522 #define  EXTI_EMR_EM2                        EXTI_EMR_MR2
6523 #define  EXTI_EMR_EM3                        EXTI_EMR_MR3
6524 #define  EXTI_EMR_EM4                        EXTI_EMR_MR4
6525 #define  EXTI_EMR_EM5                        EXTI_EMR_MR5
6526 #define  EXTI_EMR_EM6                        EXTI_EMR_MR6
6527 #define  EXTI_EMR_EM7                        EXTI_EMR_MR7
6528 #define  EXTI_EMR_EM8                        EXTI_EMR_MR8
6529 #define  EXTI_EMR_EM9                        EXTI_EMR_MR9
6530 #define  EXTI_EMR_EM10                       EXTI_EMR_MR10
6531 #define  EXTI_EMR_EM11                       EXTI_EMR_MR11
6532 #define  EXTI_EMR_EM12                       EXTI_EMR_MR12
6533 #define  EXTI_EMR_EM13                       EXTI_EMR_MR13
6534 #define  EXTI_EMR_EM14                       EXTI_EMR_MR14
6535 #define  EXTI_EMR_EM15                       EXTI_EMR_MR15
6536 #define  EXTI_EMR_EM16                       EXTI_EMR_MR16
6537 #define  EXTI_EMR_EM17                       EXTI_EMR_MR17
6538 #define  EXTI_EMR_EM18                       EXTI_EMR_MR18
6539 #define  EXTI_EMR_EM19                       EXTI_EMR_MR19
6540 #define  EXTI_EMR_EM20                       EXTI_EMR_MR20
6541 #define  EXTI_EMR_EM21                       EXTI_EMR_MR21
6542 #define  EXTI_EMR_EM22                       EXTI_EMR_MR22
6543 
6544 /******************  Bit definition for EXTI_RTSR register  *******************/
6545 #define EXTI_RTSR_TR0_Pos         (0U)
6546 #define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
6547 #define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
6548 #define EXTI_RTSR_TR1_Pos         (1U)
6549 #define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
6550 #define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
6551 #define EXTI_RTSR_TR2_Pos         (2U)
6552 #define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
6553 #define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
6554 #define EXTI_RTSR_TR3_Pos         (3U)
6555 #define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
6556 #define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
6557 #define EXTI_RTSR_TR4_Pos         (4U)
6558 #define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
6559 #define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
6560 #define EXTI_RTSR_TR5_Pos         (5U)
6561 #define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
6562 #define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
6563 #define EXTI_RTSR_TR6_Pos         (6U)
6564 #define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
6565 #define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
6566 #define EXTI_RTSR_TR7_Pos         (7U)
6567 #define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
6568 #define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
6569 #define EXTI_RTSR_TR8_Pos         (8U)
6570 #define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
6571 #define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
6572 #define EXTI_RTSR_TR9_Pos         (9U)
6573 #define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
6574 #define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
6575 #define EXTI_RTSR_TR10_Pos        (10U)
6576 #define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
6577 #define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
6578 #define EXTI_RTSR_TR11_Pos        (11U)
6579 #define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
6580 #define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
6581 #define EXTI_RTSR_TR12_Pos        (12U)
6582 #define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
6583 #define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
6584 #define EXTI_RTSR_TR13_Pos        (13U)
6585 #define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
6586 #define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
6587 #define EXTI_RTSR_TR14_Pos        (14U)
6588 #define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
6589 #define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
6590 #define EXTI_RTSR_TR15_Pos        (15U)
6591 #define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
6592 #define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
6593 #define EXTI_RTSR_TR16_Pos        (16U)
6594 #define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
6595 #define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
6596 #define EXTI_RTSR_TR17_Pos        (17U)
6597 #define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
6598 #define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
6599 #define EXTI_RTSR_TR18_Pos        (18U)
6600 #define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
6601 #define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
6602 #define EXTI_RTSR_TR19_Pos        (19U)
6603 #define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
6604 #define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
6605 #define EXTI_RTSR_TR20_Pos        (20U)
6606 #define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
6607 #define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
6608 #define EXTI_RTSR_TR21_Pos        (21U)
6609 #define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
6610 #define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
6611 #define EXTI_RTSR_TR22_Pos        (22U)
6612 #define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
6613 #define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
6614 
6615 /******************  Bit definition for EXTI_FTSR register  *******************/
6616 #define EXTI_FTSR_TR0_Pos         (0U)
6617 #define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
6618 #define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
6619 #define EXTI_FTSR_TR1_Pos         (1U)
6620 #define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
6621 #define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
6622 #define EXTI_FTSR_TR2_Pos         (2U)
6623 #define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
6624 #define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
6625 #define EXTI_FTSR_TR3_Pos         (3U)
6626 #define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
6627 #define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
6628 #define EXTI_FTSR_TR4_Pos         (4U)
6629 #define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
6630 #define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
6631 #define EXTI_FTSR_TR5_Pos         (5U)
6632 #define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
6633 #define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
6634 #define EXTI_FTSR_TR6_Pos         (6U)
6635 #define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
6636 #define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
6637 #define EXTI_FTSR_TR7_Pos         (7U)
6638 #define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
6639 #define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
6640 #define EXTI_FTSR_TR8_Pos         (8U)
6641 #define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
6642 #define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
6643 #define EXTI_FTSR_TR9_Pos         (9U)
6644 #define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
6645 #define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
6646 #define EXTI_FTSR_TR10_Pos        (10U)
6647 #define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
6648 #define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
6649 #define EXTI_FTSR_TR11_Pos        (11U)
6650 #define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
6651 #define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
6652 #define EXTI_FTSR_TR12_Pos        (12U)
6653 #define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
6654 #define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
6655 #define EXTI_FTSR_TR13_Pos        (13U)
6656 #define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
6657 #define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
6658 #define EXTI_FTSR_TR14_Pos        (14U)
6659 #define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
6660 #define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
6661 #define EXTI_FTSR_TR15_Pos        (15U)
6662 #define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
6663 #define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
6664 #define EXTI_FTSR_TR16_Pos        (16U)
6665 #define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
6666 #define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
6667 #define EXTI_FTSR_TR17_Pos        (17U)
6668 #define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
6669 #define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
6670 #define EXTI_FTSR_TR18_Pos        (18U)
6671 #define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
6672 #define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
6673 #define EXTI_FTSR_TR19_Pos        (19U)
6674 #define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
6675 #define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
6676 #define EXTI_FTSR_TR20_Pos        (20U)
6677 #define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
6678 #define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
6679 #define EXTI_FTSR_TR21_Pos        (21U)
6680 #define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
6681 #define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
6682 #define EXTI_FTSR_TR22_Pos        (22U)
6683 #define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
6684 #define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
6685 
6686 /******************  Bit definition for EXTI_SWIER register  ******************/
6687 #define EXTI_SWIER_SWIER0_Pos     (0U)
6688 #define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
6689 #define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
6690 #define EXTI_SWIER_SWIER1_Pos     (1U)
6691 #define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
6692 #define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
6693 #define EXTI_SWIER_SWIER2_Pos     (2U)
6694 #define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
6695 #define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
6696 #define EXTI_SWIER_SWIER3_Pos     (3U)
6697 #define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
6698 #define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
6699 #define EXTI_SWIER_SWIER4_Pos     (4U)
6700 #define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
6701 #define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
6702 #define EXTI_SWIER_SWIER5_Pos     (5U)
6703 #define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
6704 #define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
6705 #define EXTI_SWIER_SWIER6_Pos     (6U)
6706 #define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
6707 #define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
6708 #define EXTI_SWIER_SWIER7_Pos     (7U)
6709 #define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
6710 #define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
6711 #define EXTI_SWIER_SWIER8_Pos     (8U)
6712 #define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
6713 #define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
6714 #define EXTI_SWIER_SWIER9_Pos     (9U)
6715 #define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
6716 #define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
6717 #define EXTI_SWIER_SWIER10_Pos    (10U)
6718 #define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
6719 #define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
6720 #define EXTI_SWIER_SWIER11_Pos    (11U)
6721 #define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
6722 #define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
6723 #define EXTI_SWIER_SWIER12_Pos    (12U)
6724 #define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
6725 #define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
6726 #define EXTI_SWIER_SWIER13_Pos    (13U)
6727 #define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
6728 #define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
6729 #define EXTI_SWIER_SWIER14_Pos    (14U)
6730 #define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
6731 #define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
6732 #define EXTI_SWIER_SWIER15_Pos    (15U)
6733 #define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
6734 #define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
6735 #define EXTI_SWIER_SWIER16_Pos    (16U)
6736 #define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
6737 #define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
6738 #define EXTI_SWIER_SWIER17_Pos    (17U)
6739 #define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
6740 #define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
6741 #define EXTI_SWIER_SWIER18_Pos    (18U)
6742 #define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
6743 #define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
6744 #define EXTI_SWIER_SWIER19_Pos    (19U)
6745 #define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
6746 #define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
6747 #define EXTI_SWIER_SWIER20_Pos    (20U)
6748 #define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
6749 #define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
6750 #define EXTI_SWIER_SWIER21_Pos    (21U)
6751 #define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
6752 #define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
6753 #define EXTI_SWIER_SWIER22_Pos    (22U)
6754 #define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
6755 #define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
6756 
6757 /*******************  Bit definition for EXTI_PR register  ********************/
6758 #define EXTI_PR_PR0_Pos           (0U)
6759 #define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
6760 #define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
6761 #define EXTI_PR_PR1_Pos           (1U)
6762 #define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
6763 #define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
6764 #define EXTI_PR_PR2_Pos           (2U)
6765 #define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
6766 #define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
6767 #define EXTI_PR_PR3_Pos           (3U)
6768 #define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
6769 #define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
6770 #define EXTI_PR_PR4_Pos           (4U)
6771 #define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
6772 #define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
6773 #define EXTI_PR_PR5_Pos           (5U)
6774 #define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
6775 #define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
6776 #define EXTI_PR_PR6_Pos           (6U)
6777 #define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
6778 #define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
6779 #define EXTI_PR_PR7_Pos           (7U)
6780 #define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
6781 #define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
6782 #define EXTI_PR_PR8_Pos           (8U)
6783 #define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
6784 #define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
6785 #define EXTI_PR_PR9_Pos           (9U)
6786 #define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
6787 #define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
6788 #define EXTI_PR_PR10_Pos          (10U)
6789 #define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
6790 #define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
6791 #define EXTI_PR_PR11_Pos          (11U)
6792 #define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
6793 #define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
6794 #define EXTI_PR_PR12_Pos          (12U)
6795 #define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
6796 #define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
6797 #define EXTI_PR_PR13_Pos          (13U)
6798 #define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
6799 #define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
6800 #define EXTI_PR_PR14_Pos          (14U)
6801 #define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
6802 #define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
6803 #define EXTI_PR_PR15_Pos          (15U)
6804 #define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
6805 #define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
6806 #define EXTI_PR_PR16_Pos          (16U)
6807 #define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
6808 #define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
6809 #define EXTI_PR_PR17_Pos          (17U)
6810 #define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
6811 #define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
6812 #define EXTI_PR_PR18_Pos          (18U)
6813 #define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
6814 #define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
6815 #define EXTI_PR_PR19_Pos          (19U)
6816 #define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
6817 #define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
6818 #define EXTI_PR_PR20_Pos          (20U)
6819 #define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
6820 #define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
6821 #define EXTI_PR_PR21_Pos          (21U)
6822 #define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
6823 #define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
6824 #define EXTI_PR_PR22_Pos          (22U)
6825 #define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
6826 #define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
6827 
6828 /******************************************************************************/
6829 /*                                                                            */
6830 /*                                    FLASH                                   */
6831 /*                                                                            */
6832 /******************************************************************************/
6833 /*******************  Bits definition for FLASH_ACR register  *****************/
6834 #define FLASH_ACR_LATENCY_Pos          (0U)
6835 #define FLASH_ACR_LATENCY_Msk          (0xFUL << FLASH_ACR_LATENCY_Pos)         /*!< 0x0000000F */
6836 #define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
6837 #define FLASH_ACR_LATENCY_0WS          0x00000000U
6838 #define FLASH_ACR_LATENCY_1WS          0x00000001U
6839 #define FLASH_ACR_LATENCY_2WS          0x00000002U
6840 #define FLASH_ACR_LATENCY_3WS          0x00000003U
6841 #define FLASH_ACR_LATENCY_4WS          0x00000004U
6842 #define FLASH_ACR_LATENCY_5WS          0x00000005U
6843 #define FLASH_ACR_LATENCY_6WS          0x00000006U
6844 #define FLASH_ACR_LATENCY_7WS          0x00000007U
6845 
6846 #define FLASH_ACR_PRFTEN_Pos           (8U)
6847 #define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
6848 #define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk
6849 #define FLASH_ACR_ICEN_Pos             (9U)
6850 #define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
6851 #define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk
6852 #define FLASH_ACR_DCEN_Pos             (10U)
6853 #define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
6854 #define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk
6855 #define FLASH_ACR_ICRST_Pos            (11U)
6856 #define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
6857 #define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk
6858 #define FLASH_ACR_DCRST_Pos            (12U)
6859 #define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
6860 #define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk
6861 #define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)
6862 #define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
6863 #define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk
6864 #define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)
6865 #define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
6866 #define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk
6867 
6868 /*******************  Bits definition for FLASH_SR register  ******************/
6869 #define FLASH_SR_EOP_Pos               (0U)
6870 #define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
6871 #define FLASH_SR_EOP                   FLASH_SR_EOP_Msk
6872 #define FLASH_SR_SOP_Pos               (1U)
6873 #define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
6874 #define FLASH_SR_SOP                   FLASH_SR_SOP_Msk
6875 #define FLASH_SR_WRPERR_Pos            (4U)
6876 #define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
6877 #define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk
6878 #define FLASH_SR_PGAERR_Pos            (5U)
6879 #define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
6880 #define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk
6881 #define FLASH_SR_PGPERR_Pos            (6U)
6882 #define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
6883 #define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk
6884 #define FLASH_SR_PGSERR_Pos            (7U)
6885 #define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
6886 #define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk
6887 #define FLASH_SR_BSY_Pos               (16U)
6888 #define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
6889 #define FLASH_SR_BSY                   FLASH_SR_BSY_Msk
6890 
6891 /*******************  Bits definition for FLASH_CR register  ******************/
6892 #define FLASH_CR_PG_Pos                (0U)
6893 #define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
6894 #define FLASH_CR_PG                    FLASH_CR_PG_Msk
6895 #define FLASH_CR_SER_Pos               (1U)
6896 #define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
6897 #define FLASH_CR_SER                   FLASH_CR_SER_Msk
6898 #define FLASH_CR_MER_Pos               (2U)
6899 #define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
6900 #define FLASH_CR_MER                   FLASH_CR_MER_Msk
6901 #define FLASH_CR_SNB_Pos               (3U)
6902 #define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
6903 #define FLASH_CR_SNB                   FLASH_CR_SNB_Msk
6904 #define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
6905 #define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
6906 #define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
6907 #define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
6908 #define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
6909 #define FLASH_CR_PSIZE_Pos             (8U)
6910 #define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
6911 #define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk
6912 #define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
6913 #define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
6914 #define FLASH_CR_STRT_Pos              (16U)
6915 #define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
6916 #define FLASH_CR_STRT                  FLASH_CR_STRT_Msk
6917 #define FLASH_CR_EOPIE_Pos             (24U)
6918 #define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
6919 #define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk
6920 #define FLASH_CR_LOCK_Pos              (31U)
6921 #define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
6922 #define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk
6923 
6924 /*******************  Bits definition for FLASH_OPTCR register  ***************/
6925 #define FLASH_OPTCR_OPTLOCK_Pos        (0U)
6926 #define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
6927 #define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk
6928 #define FLASH_OPTCR_OPTSTRT_Pos        (1U)
6929 #define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
6930 #define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk
6931 #define FLASH_OPTCR_BOR_LEV_0          0x00000004U
6932 #define FLASH_OPTCR_BOR_LEV_1          0x00000008U
6933 #define FLASH_OPTCR_BOR_LEV_Pos        (2U)
6934 #define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
6935 #define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk
6936 
6937 #define FLASH_OPTCR_WDG_SW_Pos         (5U)
6938 #define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
6939 #define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk
6940 #define FLASH_OPTCR_nRST_STOP_Pos      (6U)
6941 #define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
6942 #define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk
6943 #define FLASH_OPTCR_nRST_STDBY_Pos     (7U)
6944 #define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
6945 #define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk
6946 #define FLASH_OPTCR_RDP_Pos            (8U)
6947 #define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
6948 #define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk
6949 #define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
6950 #define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
6951 #define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
6952 #define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
6953 #define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
6954 #define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
6955 #define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
6956 #define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
6957 #define FLASH_OPTCR_nWRP_Pos           (16U)
6958 #define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
6959 #define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk
6960 #define FLASH_OPTCR_nWRP_0             (0x001UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00010000 */
6961 #define FLASH_OPTCR_nWRP_1             (0x002UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00020000 */
6962 #define FLASH_OPTCR_nWRP_2             (0x004UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00040000 */
6963 #define FLASH_OPTCR_nWRP_3             (0x008UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00080000 */
6964 #define FLASH_OPTCR_nWRP_4             (0x010UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00100000 */
6965 #define FLASH_OPTCR_nWRP_5             (0x020UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00200000 */
6966 #define FLASH_OPTCR_nWRP_6             (0x040UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00400000 */
6967 #define FLASH_OPTCR_nWRP_7             (0x080UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x00800000 */
6968 #define FLASH_OPTCR_nWRP_8             (0x100UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x01000000 */
6969 #define FLASH_OPTCR_nWRP_9             (0x200UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x02000000 */
6970 #define FLASH_OPTCR_nWRP_10            (0x400UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x04000000 */
6971 #define FLASH_OPTCR_nWRP_11            (0x800UL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x08000000 */
6972 
6973 /******************************************************************************/
6974 /*                                                                            */
6975 /*                       Flexible Static Memory Controller                    */
6976 /*                                                                            */
6977 /******************************************************************************/
6978 /******************  Bit definition for FSMC_BCR1 register  *******************/
6979 #define FSMC_BCR1_MBKEN_Pos          (0U)
6980 #define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */
6981 #define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */
6982 #define FSMC_BCR1_MUXEN_Pos          (1U)
6983 #define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */
6984 #define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
6985 
6986 #define FSMC_BCR1_MTYP_Pos           (2U)
6987 #define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */
6988 #define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
6989 #define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */
6990 #define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */
6991 
6992 #define FSMC_BCR1_MWID_Pos           (4U)
6993 #define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */
6994 #define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
6995 #define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */
6996 #define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */
6997 
6998 #define FSMC_BCR1_FACCEN_Pos         (6U)
6999 #define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */
7000 #define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */
7001 #define FSMC_BCR1_BURSTEN_Pos        (8U)
7002 #define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */
7003 #define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */
7004 #define FSMC_BCR1_WAITPOL_Pos        (9U)
7005 #define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */
7006 #define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7007 #define FSMC_BCR1_WRAPMOD_Pos        (10U)
7008 #define FSMC_BCR1_WRAPMOD_Msk        (0x1UL << FSMC_BCR1_WRAPMOD_Pos)           /*!< 0x00000400 */
7009 #define FSMC_BCR1_WRAPMOD            FSMC_BCR1_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
7010 #define FSMC_BCR1_WAITCFG_Pos        (11U)
7011 #define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */
7012 #define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */
7013 #define FSMC_BCR1_WREN_Pos           (12U)
7014 #define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */
7015 #define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */
7016 #define FSMC_BCR1_WAITEN_Pos         (13U)
7017 #define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */
7018 #define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */
7019 #define FSMC_BCR1_EXTMOD_Pos         (14U)
7020 #define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */
7021 #define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */
7022 #define FSMC_BCR1_ASYNCWAIT_Pos      (15U)
7023 #define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7024 #define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7025 #define FSMC_BCR1_CBURSTRW_Pos       (19U)
7026 #define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */
7027 #define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */
7028 
7029 /******************  Bit definition for FSMC_BCR2 register  *******************/
7030 #define FSMC_BCR2_MBKEN_Pos          (0U)
7031 #define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */
7032 #define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */
7033 #define FSMC_BCR2_MUXEN_Pos          (1U)
7034 #define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */
7035 #define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
7036 
7037 #define FSMC_BCR2_MTYP_Pos           (2U)
7038 #define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */
7039 #define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
7040 #define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */
7041 #define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */
7042 
7043 #define FSMC_BCR2_MWID_Pos           (4U)
7044 #define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */
7045 #define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
7046 #define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */
7047 #define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */
7048 
7049 #define FSMC_BCR2_FACCEN_Pos         (6U)
7050 #define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */
7051 #define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */
7052 #define FSMC_BCR2_BURSTEN_Pos        (8U)
7053 #define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */
7054 #define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */
7055 #define FSMC_BCR2_WAITPOL_Pos        (9U)
7056 #define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */
7057 #define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7058 #define FSMC_BCR2_WRAPMOD_Pos        (10U)
7059 #define FSMC_BCR2_WRAPMOD_Msk        (0x1UL << FSMC_BCR2_WRAPMOD_Pos)           /*!< 0x00000400 */
7060 #define FSMC_BCR2_WRAPMOD            FSMC_BCR2_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
7061 #define FSMC_BCR2_WAITCFG_Pos        (11U)
7062 #define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */
7063 #define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */
7064 #define FSMC_BCR2_WREN_Pos           (12U)
7065 #define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */
7066 #define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */
7067 #define FSMC_BCR2_WAITEN_Pos         (13U)
7068 #define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */
7069 #define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */
7070 #define FSMC_BCR2_EXTMOD_Pos         (14U)
7071 #define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */
7072 #define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */
7073 #define FSMC_BCR2_ASYNCWAIT_Pos      (15U)
7074 #define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7075 #define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7076 #define FSMC_BCR2_CBURSTRW_Pos       (19U)
7077 #define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */
7078 #define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */
7079 
7080 /******************  Bit definition for FSMC_BCR3 register  *******************/
7081 #define FSMC_BCR3_MBKEN_Pos          (0U)
7082 #define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */
7083 #define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */
7084 #define FSMC_BCR3_MUXEN_Pos          (1U)
7085 #define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */
7086 #define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
7087 
7088 #define FSMC_BCR3_MTYP_Pos           (2U)
7089 #define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */
7090 #define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
7091 #define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */
7092 #define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */
7093 
7094 #define FSMC_BCR3_MWID_Pos           (4U)
7095 #define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */
7096 #define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
7097 #define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */
7098 #define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */
7099 
7100 #define FSMC_BCR3_FACCEN_Pos         (6U)
7101 #define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */
7102 #define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */
7103 #define FSMC_BCR3_BURSTEN_Pos        (8U)
7104 #define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */
7105 #define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */
7106 #define FSMC_BCR3_WAITPOL_Pos        (9U)
7107 #define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */
7108 #define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7109 #define FSMC_BCR3_WRAPMOD_Pos        (10U)
7110 #define FSMC_BCR3_WRAPMOD_Msk        (0x1UL << FSMC_BCR3_WRAPMOD_Pos)           /*!< 0x00000400 */
7111 #define FSMC_BCR3_WRAPMOD            FSMC_BCR3_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
7112 #define FSMC_BCR3_WAITCFG_Pos        (11U)
7113 #define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */
7114 #define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */
7115 #define FSMC_BCR3_WREN_Pos           (12U)
7116 #define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */
7117 #define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */
7118 #define FSMC_BCR3_WAITEN_Pos         (13U)
7119 #define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */
7120 #define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */
7121 #define FSMC_BCR3_EXTMOD_Pos         (14U)
7122 #define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */
7123 #define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */
7124 #define FSMC_BCR3_ASYNCWAIT_Pos      (15U)
7125 #define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7126 #define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7127 #define FSMC_BCR3_CBURSTRW_Pos       (19U)
7128 #define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */
7129 #define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */
7130 
7131 /******************  Bit definition for FSMC_BCR4 register  *******************/
7132 #define FSMC_BCR4_MBKEN_Pos          (0U)
7133 #define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */
7134 #define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */
7135 #define FSMC_BCR4_MUXEN_Pos          (1U)
7136 #define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */
7137 #define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
7138 
7139 #define FSMC_BCR4_MTYP_Pos           (2U)
7140 #define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */
7141 #define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
7142 #define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */
7143 #define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */
7144 
7145 #define FSMC_BCR4_MWID_Pos           (4U)
7146 #define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */
7147 #define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
7148 #define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */
7149 #define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */
7150 
7151 #define FSMC_BCR4_FACCEN_Pos         (6U)
7152 #define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */
7153 #define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */
7154 #define FSMC_BCR4_BURSTEN_Pos        (8U)
7155 #define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */
7156 #define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */
7157 #define FSMC_BCR4_WAITPOL_Pos        (9U)
7158 #define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */
7159 #define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
7160 #define FSMC_BCR4_WRAPMOD_Pos        (10U)
7161 #define FSMC_BCR4_WRAPMOD_Msk        (0x1UL << FSMC_BCR4_WRAPMOD_Pos)           /*!< 0x00000400 */
7162 #define FSMC_BCR4_WRAPMOD            FSMC_BCR4_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
7163 #define FSMC_BCR4_WAITCFG_Pos        (11U)
7164 #define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */
7165 #define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */
7166 #define FSMC_BCR4_WREN_Pos           (12U)
7167 #define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */
7168 #define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */
7169 #define FSMC_BCR4_WAITEN_Pos         (13U)
7170 #define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */
7171 #define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */
7172 #define FSMC_BCR4_EXTMOD_Pos         (14U)
7173 #define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */
7174 #define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */
7175 #define FSMC_BCR4_ASYNCWAIT_Pos      (15U)
7176 #define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */
7177 #define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
7178 #define FSMC_BCR4_CBURSTRW_Pos       (19U)
7179 #define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */
7180 #define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */
7181 
7182 /******************  Bit definition for FSMC_BTR1 register  ******************/
7183 #define FSMC_BTR1_ADDSET_Pos         (0U)
7184 #define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */
7185 #define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7186 #define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */
7187 #define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */
7188 #define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */
7189 #define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */
7190 
7191 #define FSMC_BTR1_ADDHLD_Pos         (4U)
7192 #define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */
7193 #define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7194 #define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */
7195 #define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */
7196 #define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */
7197 #define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */
7198 
7199 #define FSMC_BTR1_DATAST_Pos         (8U)
7200 #define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */
7201 #define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7202 #define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */
7203 #define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */
7204 #define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */
7205 #define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */
7206 #define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */
7207 #define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */
7208 #define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */
7209 #define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */
7210 
7211 #define FSMC_BTR1_BUSTURN_Pos        (16U)
7212 #define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */
7213 #define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7214 #define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */
7215 #define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */
7216 #define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */
7217 #define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */
7218 
7219 #define FSMC_BTR1_CLKDIV_Pos         (20U)
7220 #define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */
7221 #define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7222 #define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */
7223 #define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */
7224 #define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */
7225 #define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */
7226 
7227 #define FSMC_BTR1_DATLAT_Pos         (24U)
7228 #define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */
7229 #define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7230 #define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */
7231 #define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */
7232 #define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */
7233 #define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */
7234 
7235 #define FSMC_BTR1_ACCMOD_Pos         (28U)
7236 #define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */
7237 #define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7238 #define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */
7239 #define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */
7240 
7241 /******************  Bit definition for FSMC_BTR2 register  *******************/
7242 #define FSMC_BTR2_ADDSET_Pos         (0U)
7243 #define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */
7244 #define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7245 #define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */
7246 #define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */
7247 #define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */
7248 #define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */
7249 
7250 #define FSMC_BTR2_ADDHLD_Pos         (4U)
7251 #define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */
7252 #define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7253 #define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */
7254 #define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */
7255 #define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */
7256 #define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */
7257 
7258 #define FSMC_BTR2_DATAST_Pos         (8U)
7259 #define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */
7260 #define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7261 #define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */
7262 #define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */
7263 #define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */
7264 #define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */
7265 #define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */
7266 #define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */
7267 #define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */
7268 #define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */
7269 
7270 #define FSMC_BTR2_BUSTURN_Pos        (16U)
7271 #define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */
7272 #define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7273 #define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */
7274 #define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */
7275 #define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */
7276 #define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */
7277 
7278 #define FSMC_BTR2_CLKDIV_Pos         (20U)
7279 #define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */
7280 #define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7281 #define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */
7282 #define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */
7283 #define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */
7284 #define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */
7285 
7286 #define FSMC_BTR2_DATLAT_Pos         (24U)
7287 #define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */
7288 #define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7289 #define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */
7290 #define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */
7291 #define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */
7292 #define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */
7293 
7294 #define FSMC_BTR2_ACCMOD_Pos         (28U)
7295 #define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */
7296 #define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7297 #define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */
7298 #define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */
7299 
7300 /*******************  Bit definition for FSMC_BTR3 register  *******************/
7301 #define FSMC_BTR3_ADDSET_Pos         (0U)
7302 #define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */
7303 #define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7304 #define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */
7305 #define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */
7306 #define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */
7307 #define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */
7308 
7309 #define FSMC_BTR3_ADDHLD_Pos         (4U)
7310 #define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */
7311 #define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7312 #define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */
7313 #define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */
7314 #define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */
7315 #define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */
7316 
7317 #define FSMC_BTR3_DATAST_Pos         (8U)
7318 #define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */
7319 #define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7320 #define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */
7321 #define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */
7322 #define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */
7323 #define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */
7324 #define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */
7325 #define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */
7326 #define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */
7327 #define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */
7328 
7329 #define FSMC_BTR3_BUSTURN_Pos        (16U)
7330 #define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */
7331 #define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7332 #define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */
7333 #define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */
7334 #define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */
7335 #define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */
7336 
7337 #define FSMC_BTR3_CLKDIV_Pos         (20U)
7338 #define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */
7339 #define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7340 #define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */
7341 #define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */
7342 #define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */
7343 #define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */
7344 
7345 #define FSMC_BTR3_DATLAT_Pos         (24U)
7346 #define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */
7347 #define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7348 #define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */
7349 #define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */
7350 #define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */
7351 #define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */
7352 
7353 #define FSMC_BTR3_ACCMOD_Pos         (28U)
7354 #define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */
7355 #define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7356 #define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */
7357 #define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */
7358 
7359 /******************  Bit definition for FSMC_BTR4 register  *******************/
7360 #define FSMC_BTR4_ADDSET_Pos         (0U)
7361 #define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */
7362 #define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
7363 #define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */
7364 #define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */
7365 #define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */
7366 #define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */
7367 
7368 #define FSMC_BTR4_ADDHLD_Pos         (4U)
7369 #define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */
7370 #define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7371 #define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */
7372 #define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */
7373 #define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */
7374 #define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */
7375 
7376 #define FSMC_BTR4_DATAST_Pos         (8U)
7377 #define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */
7378 #define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
7379 #define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */
7380 #define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */
7381 #define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */
7382 #define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */
7383 #define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */
7384 #define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */
7385 #define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */
7386 #define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */
7387 
7388 #define FSMC_BTR4_BUSTURN_Pos        (16U)
7389 #define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */
7390 #define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
7391 #define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */
7392 #define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */
7393 #define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */
7394 #define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */
7395 
7396 #define FSMC_BTR4_CLKDIV_Pos         (20U)
7397 #define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */
7398 #define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
7399 #define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */
7400 #define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */
7401 #define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */
7402 #define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */
7403 
7404 #define FSMC_BTR4_DATLAT_Pos         (24U)
7405 #define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */
7406 #define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
7407 #define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */
7408 #define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */
7409 #define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */
7410 #define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */
7411 
7412 #define FSMC_BTR4_ACCMOD_Pos         (28U)
7413 #define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */
7414 #define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
7415 #define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */
7416 #define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */
7417 
7418 /******************  Bit definition for FSMC_BWTR1 register  ******************/
7419 #define FSMC_BWTR1_ADDSET_Pos        (0U)
7420 #define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */
7421 #define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7422 #define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */
7423 #define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */
7424 #define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */
7425 #define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */
7426 
7427 #define FSMC_BWTR1_ADDHLD_Pos        (4U)
7428 #define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */
7429 #define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7430 #define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */
7431 #define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */
7432 #define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */
7433 #define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */
7434 
7435 #define FSMC_BWTR1_DATAST_Pos        (8U)
7436 #define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */
7437 #define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
7438 #define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */
7439 #define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */
7440 #define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */
7441 #define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */
7442 #define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */
7443 #define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */
7444 #define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */
7445 #define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */
7446 
7447 #define FSMC_BWTR1_BUSTURN_Pos       (16U)
7448 #define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */
7449 #define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7450 #define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */
7451 #define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */
7452 #define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */
7453 #define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */
7454 
7455 #define FSMC_BWTR1_ACCMOD_Pos        (28U)
7456 #define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */
7457 #define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7458 #define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */
7459 #define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */
7460 
7461 /******************  Bit definition for FSMC_BWTR2 register  ******************/
7462 #define FSMC_BWTR2_ADDSET_Pos        (0U)
7463 #define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */
7464 #define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7465 #define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */
7466 #define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */
7467 #define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */
7468 #define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */
7469 
7470 #define FSMC_BWTR2_ADDHLD_Pos        (4U)
7471 #define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */
7472 #define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7473 #define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */
7474 #define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */
7475 #define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */
7476 #define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */
7477 
7478 #define FSMC_BWTR2_DATAST_Pos        (8U)
7479 #define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */
7480 #define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
7481 #define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */
7482 #define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */
7483 #define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */
7484 #define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */
7485 #define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */
7486 #define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */
7487 #define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */
7488 #define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */
7489 
7490 #define FSMC_BWTR2_BUSTURN_Pos       (16U)
7491 #define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */
7492 #define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7493 #define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */
7494 #define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */
7495 #define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */
7496 #define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */
7497 
7498 #define FSMC_BWTR2_ACCMOD_Pos        (28U)
7499 #define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */
7500 #define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7501 #define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */
7502 #define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */
7503 
7504 /******************  Bit definition for FSMC_BWTR3 register  ******************/
7505 #define FSMC_BWTR3_ADDSET_Pos        (0U)
7506 #define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */
7507 #define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7508 #define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */
7509 #define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */
7510 #define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */
7511 #define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */
7512 
7513 #define FSMC_BWTR3_ADDHLD_Pos        (4U)
7514 #define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */
7515 #define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7516 #define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */
7517 #define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */
7518 #define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */
7519 #define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */
7520 
7521 #define FSMC_BWTR3_DATAST_Pos        (8U)
7522 #define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */
7523 #define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
7524 #define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */
7525 #define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */
7526 #define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */
7527 #define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */
7528 #define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */
7529 #define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */
7530 #define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */
7531 #define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */
7532 
7533 #define FSMC_BWTR3_BUSTURN_Pos       (16U)
7534 #define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */
7535 #define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7536 #define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */
7537 #define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */
7538 #define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */
7539 #define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */
7540 
7541 #define FSMC_BWTR3_ACCMOD_Pos        (28U)
7542 #define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */
7543 #define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7544 #define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */
7545 #define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */
7546 
7547 /******************  Bit definition for FSMC_BWTR4 register  ******************/
7548 #define FSMC_BWTR4_ADDSET_Pos        (0U)
7549 #define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */
7550 #define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
7551 #define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */
7552 #define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */
7553 #define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */
7554 #define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */
7555 
7556 #define FSMC_BWTR4_ADDHLD_Pos        (4U)
7557 #define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */
7558 #define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
7559 #define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */
7560 #define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */
7561 #define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */
7562 #define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */
7563 
7564 #define FSMC_BWTR4_DATAST_Pos        (8U)
7565 #define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */
7566 #define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */
7567 #define FSMC_BWTR4_DATAST_0          (0x01UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00000100 */
7568 #define FSMC_BWTR4_DATAST_1          (0x02UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00000200 */
7569 #define FSMC_BWTR4_DATAST_2          (0x04UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00000400 */
7570 #define FSMC_BWTR4_DATAST_3          (0x08UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00000800 */
7571 #define FSMC_BWTR4_DATAST_4          (0x10UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00001000 */
7572 #define FSMC_BWTR4_DATAST_5          (0x20UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00002000 */
7573 #define FSMC_BWTR4_DATAST_6          (0x40UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00004000 */
7574 #define FSMC_BWTR4_DATAST_7          (0x80UL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x00008000 */
7575 
7576 #define FSMC_BWTR4_BUSTURN_Pos       (16U)
7577 #define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */
7578 #define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
7579 #define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */
7580 #define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */
7581 #define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */
7582 #define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */
7583 
7584 #define FSMC_BWTR4_ACCMOD_Pos        (28U)
7585 #define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */
7586 #define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
7587 #define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */
7588 #define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */
7589 
7590 /******************  Bit definition for FSMC_PCR2 register  *******************/
7591 #define FSMC_PCR2_PWAITEN_Pos        (1U)
7592 #define FSMC_PCR2_PWAITEN_Msk        (0x1UL << FSMC_PCR2_PWAITEN_Pos)           /*!< 0x00000002 */
7593 #define FSMC_PCR2_PWAITEN            FSMC_PCR2_PWAITEN_Msk                     /*!<Wait feature enable bit */
7594 #define FSMC_PCR2_PBKEN_Pos          (2U)
7595 #define FSMC_PCR2_PBKEN_Msk          (0x1UL << FSMC_PCR2_PBKEN_Pos)             /*!< 0x00000004 */
7596 #define FSMC_PCR2_PBKEN              FSMC_PCR2_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
7597 #define FSMC_PCR2_PTYP_Pos           (3U)
7598 #define FSMC_PCR2_PTYP_Msk           (0x1UL << FSMC_PCR2_PTYP_Pos)              /*!< 0x00000008 */
7599 #define FSMC_PCR2_PTYP               FSMC_PCR2_PTYP_Msk                        /*!<Memory type */
7600 
7601 #define FSMC_PCR2_PWID_Pos           (4U)
7602 #define FSMC_PCR2_PWID_Msk           (0x3UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000030 */
7603 #define FSMC_PCR2_PWID               FSMC_PCR2_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
7604 #define FSMC_PCR2_PWID_0             (0x1UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000010 */
7605 #define FSMC_PCR2_PWID_1             (0x2UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000020 */
7606 
7607 #define FSMC_PCR2_ECCEN_Pos          (6U)
7608 #define FSMC_PCR2_ECCEN_Msk          (0x1UL << FSMC_PCR2_ECCEN_Pos)             /*!< 0x00000040 */
7609 #define FSMC_PCR2_ECCEN              FSMC_PCR2_ECCEN_Msk                       /*!<ECC computation logic enable bit */
7610 
7611 #define FSMC_PCR2_TCLR_Pos           (9U)
7612 #define FSMC_PCR2_TCLR_Msk           (0xFUL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001E00 */
7613 #define FSMC_PCR2_TCLR               FSMC_PCR2_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
7614 #define FSMC_PCR2_TCLR_0             (0x1UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000200 */
7615 #define FSMC_PCR2_TCLR_1             (0x2UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000400 */
7616 #define FSMC_PCR2_TCLR_2             (0x4UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000800 */
7617 #define FSMC_PCR2_TCLR_3             (0x8UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001000 */
7618 
7619 #define FSMC_PCR2_TAR_Pos            (13U)
7620 #define FSMC_PCR2_TAR_Msk            (0xFUL << FSMC_PCR2_TAR_Pos)               /*!< 0x0001E000 */
7621 #define FSMC_PCR2_TAR                FSMC_PCR2_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
7622 #define FSMC_PCR2_TAR_0              (0x1UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00002000 */
7623 #define FSMC_PCR2_TAR_1              (0x2UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00004000 */
7624 #define FSMC_PCR2_TAR_2              (0x4UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00008000 */
7625 #define FSMC_PCR2_TAR_3              (0x8UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00010000 */
7626 
7627 #define FSMC_PCR2_ECCPS_Pos          (17U)
7628 #define FSMC_PCR2_ECCPS_Msk          (0x7UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x000E0000 */
7629 #define FSMC_PCR2_ECCPS              FSMC_PCR2_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size) */
7630 #define FSMC_PCR2_ECCPS_0            (0x1UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00020000 */
7631 #define FSMC_PCR2_ECCPS_1            (0x2UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00040000 */
7632 #define FSMC_PCR2_ECCPS_2            (0x4UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00080000 */
7633 
7634 /******************  Bit definition for FSMC_PCR3 register  *******************/
7635 #define FSMC_PCR3_PWAITEN_Pos        (1U)
7636 #define FSMC_PCR3_PWAITEN_Msk        (0x1UL << FSMC_PCR3_PWAITEN_Pos)           /*!< 0x00000002 */
7637 #define FSMC_PCR3_PWAITEN            FSMC_PCR3_PWAITEN_Msk                     /*!<Wait feature enable bit */
7638 #define FSMC_PCR3_PBKEN_Pos          (2U)
7639 #define FSMC_PCR3_PBKEN_Msk          (0x1UL << FSMC_PCR3_PBKEN_Pos)             /*!< 0x00000004 */
7640 #define FSMC_PCR3_PBKEN              FSMC_PCR3_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
7641 #define FSMC_PCR3_PTYP_Pos           (3U)
7642 #define FSMC_PCR3_PTYP_Msk           (0x1UL << FSMC_PCR3_PTYP_Pos)              /*!< 0x00000008 */
7643 #define FSMC_PCR3_PTYP               FSMC_PCR3_PTYP_Msk                        /*!<Memory type */
7644 
7645 #define FSMC_PCR3_PWID_Pos           (4U)
7646 #define FSMC_PCR3_PWID_Msk           (0x3UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000030 */
7647 #define FSMC_PCR3_PWID               FSMC_PCR3_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
7648 #define FSMC_PCR3_PWID_0             (0x1UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000010 */
7649 #define FSMC_PCR3_PWID_1             (0x2UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000020 */
7650 
7651 #define FSMC_PCR3_ECCEN_Pos          (6U)
7652 #define FSMC_PCR3_ECCEN_Msk          (0x1UL << FSMC_PCR3_ECCEN_Pos)             /*!< 0x00000040 */
7653 #define FSMC_PCR3_ECCEN              FSMC_PCR3_ECCEN_Msk                       /*!<ECC computation logic enable bit */
7654 
7655 #define FSMC_PCR3_TCLR_Pos           (9U)
7656 #define FSMC_PCR3_TCLR_Msk           (0xFUL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001E00 */
7657 #define FSMC_PCR3_TCLR               FSMC_PCR3_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
7658 #define FSMC_PCR3_TCLR_0             (0x1UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000200 */
7659 #define FSMC_PCR3_TCLR_1             (0x2UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000400 */
7660 #define FSMC_PCR3_TCLR_2             (0x4UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000800 */
7661 #define FSMC_PCR3_TCLR_3             (0x8UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001000 */
7662 
7663 #define FSMC_PCR3_TAR_Pos            (13U)
7664 #define FSMC_PCR3_TAR_Msk            (0xFUL << FSMC_PCR3_TAR_Pos)               /*!< 0x0001E000 */
7665 #define FSMC_PCR3_TAR                FSMC_PCR3_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
7666 #define FSMC_PCR3_TAR_0              (0x1UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00002000 */
7667 #define FSMC_PCR3_TAR_1              (0x2UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00004000 */
7668 #define FSMC_PCR3_TAR_2              (0x4UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00008000 */
7669 #define FSMC_PCR3_TAR_3              (0x8UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00010000 */
7670 
7671 #define FSMC_PCR3_ECCPS_Pos          (17U)
7672 #define FSMC_PCR3_ECCPS_Msk          (0x7UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x000E0000 */
7673 #define FSMC_PCR3_ECCPS              FSMC_PCR3_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */
7674 #define FSMC_PCR3_ECCPS_0            (0x1UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00020000 */
7675 #define FSMC_PCR3_ECCPS_1            (0x2UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00040000 */
7676 #define FSMC_PCR3_ECCPS_2            (0x4UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00080000 */
7677 
7678 /******************  Bit definition for FSMC_PCR4 register  *******************/
7679 #define FSMC_PCR4_PWAITEN_Pos        (1U)
7680 #define FSMC_PCR4_PWAITEN_Msk        (0x1UL << FSMC_PCR4_PWAITEN_Pos)           /*!< 0x00000002 */
7681 #define FSMC_PCR4_PWAITEN            FSMC_PCR4_PWAITEN_Msk                     /*!<Wait feature enable bit */
7682 #define FSMC_PCR4_PBKEN_Pos          (2U)
7683 #define FSMC_PCR4_PBKEN_Msk          (0x1UL << FSMC_PCR4_PBKEN_Pos)             /*!< 0x00000004 */
7684 #define FSMC_PCR4_PBKEN              FSMC_PCR4_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
7685 #define FSMC_PCR4_PTYP_Pos           (3U)
7686 #define FSMC_PCR4_PTYP_Msk           (0x1UL << FSMC_PCR4_PTYP_Pos)              /*!< 0x00000008 */
7687 #define FSMC_PCR4_PTYP               FSMC_PCR4_PTYP_Msk                        /*!<Memory type */
7688 
7689 #define FSMC_PCR4_PWID_Pos           (4U)
7690 #define FSMC_PCR4_PWID_Msk           (0x3UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000030 */
7691 #define FSMC_PCR4_PWID               FSMC_PCR4_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
7692 #define FSMC_PCR4_PWID_0             (0x1UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000010 */
7693 #define FSMC_PCR4_PWID_1             (0x2UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000020 */
7694 
7695 #define FSMC_PCR4_ECCEN_Pos          (6U)
7696 #define FSMC_PCR4_ECCEN_Msk          (0x1UL << FSMC_PCR4_ECCEN_Pos)             /*!< 0x00000040 */
7697 #define FSMC_PCR4_ECCEN              FSMC_PCR4_ECCEN_Msk                       /*!<ECC computation logic enable bit */
7698 
7699 #define FSMC_PCR4_TCLR_Pos           (9U)
7700 #define FSMC_PCR4_TCLR_Msk           (0xFUL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001E00 */
7701 #define FSMC_PCR4_TCLR               FSMC_PCR4_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
7702 #define FSMC_PCR4_TCLR_0             (0x1UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000200 */
7703 #define FSMC_PCR4_TCLR_1             (0x2UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000400 */
7704 #define FSMC_PCR4_TCLR_2             (0x4UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000800 */
7705 #define FSMC_PCR4_TCLR_3             (0x8UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001000 */
7706 
7707 #define FSMC_PCR4_TAR_Pos            (13U)
7708 #define FSMC_PCR4_TAR_Msk            (0xFUL << FSMC_PCR4_TAR_Pos)               /*!< 0x0001E000 */
7709 #define FSMC_PCR4_TAR                FSMC_PCR4_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
7710 #define FSMC_PCR4_TAR_0              (0x1UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00002000 */
7711 #define FSMC_PCR4_TAR_1              (0x2UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00004000 */
7712 #define FSMC_PCR4_TAR_2              (0x4UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00008000 */
7713 #define FSMC_PCR4_TAR_3              (0x8UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00010000 */
7714 
7715 #define FSMC_PCR4_ECCPS_Pos          (17U)
7716 #define FSMC_PCR4_ECCPS_Msk          (0x7UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x000E0000 */
7717 #define FSMC_PCR4_ECCPS              FSMC_PCR4_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */
7718 #define FSMC_PCR4_ECCPS_0            (0x1UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00020000 */
7719 #define FSMC_PCR4_ECCPS_1            (0x2UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00040000 */
7720 #define FSMC_PCR4_ECCPS_2            (0x4UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00080000 */
7721 
7722 /*******************  Bit definition for FSMC_SR2 register  *******************/
7723 #define FSMC_SR2_IRS_Pos             (0U)
7724 #define FSMC_SR2_IRS_Msk             (0x1UL << FSMC_SR2_IRS_Pos)                /*!< 0x00000001 */
7725 #define FSMC_SR2_IRS                 FSMC_SR2_IRS_Msk                          /*!<Interrupt Rising Edge status */
7726 #define FSMC_SR2_ILS_Pos             (1U)
7727 #define FSMC_SR2_ILS_Msk             (0x1UL << FSMC_SR2_ILS_Pos)                /*!< 0x00000002 */
7728 #define FSMC_SR2_ILS                 FSMC_SR2_ILS_Msk                          /*!<Interrupt Level status */
7729 #define FSMC_SR2_IFS_Pos             (2U)
7730 #define FSMC_SR2_IFS_Msk             (0x1UL << FSMC_SR2_IFS_Pos)                /*!< 0x00000004 */
7731 #define FSMC_SR2_IFS                 FSMC_SR2_IFS_Msk                          /*!<Interrupt Falling Edge status */
7732 #define FSMC_SR2_IREN_Pos            (3U)
7733 #define FSMC_SR2_IREN_Msk            (0x1UL << FSMC_SR2_IREN_Pos)               /*!< 0x00000008 */
7734 #define FSMC_SR2_IREN                FSMC_SR2_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit */
7735 #define FSMC_SR2_ILEN_Pos            (4U)
7736 #define FSMC_SR2_ILEN_Msk            (0x1UL << FSMC_SR2_ILEN_Pos)               /*!< 0x00000010 */
7737 #define FSMC_SR2_ILEN                FSMC_SR2_ILEN_Msk                         /*!<Interrupt Level detection Enable bit */
7738 #define FSMC_SR2_IFEN_Pos            (5U)
7739 #define FSMC_SR2_IFEN_Msk            (0x1UL << FSMC_SR2_IFEN_Pos)               /*!< 0x00000020 */
7740 #define FSMC_SR2_IFEN                FSMC_SR2_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
7741 #define FSMC_SR2_FEMPT_Pos           (6U)
7742 #define FSMC_SR2_FEMPT_Msk           (0x1UL << FSMC_SR2_FEMPT_Pos)              /*!< 0x00000040 */
7743 #define FSMC_SR2_FEMPT               FSMC_SR2_FEMPT_Msk                        /*!<FIFO empty */
7744 
7745 /*******************  Bit definition for FSMC_SR3 register  *******************/
7746 #define FSMC_SR3_IRS_Pos             (0U)
7747 #define FSMC_SR3_IRS_Msk             (0x1UL << FSMC_SR3_IRS_Pos)                /*!< 0x00000001 */
7748 #define FSMC_SR3_IRS                 FSMC_SR3_IRS_Msk                          /*!<Interrupt Rising Edge status */
7749 #define FSMC_SR3_ILS_Pos             (1U)
7750 #define FSMC_SR3_ILS_Msk             (0x1UL << FSMC_SR3_ILS_Pos)                /*!< 0x00000002 */
7751 #define FSMC_SR3_ILS                 FSMC_SR3_ILS_Msk                          /*!<Interrupt Level status */
7752 #define FSMC_SR3_IFS_Pos             (2U)
7753 #define FSMC_SR3_IFS_Msk             (0x1UL << FSMC_SR3_IFS_Pos)                /*!< 0x00000004 */
7754 #define FSMC_SR3_IFS                 FSMC_SR3_IFS_Msk                          /*!<Interrupt Falling Edge status */
7755 #define FSMC_SR3_IREN_Pos            (3U)
7756 #define FSMC_SR3_IREN_Msk            (0x1UL << FSMC_SR3_IREN_Pos)               /*!< 0x00000008 */
7757 #define FSMC_SR3_IREN                FSMC_SR3_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit */
7758 #define FSMC_SR3_ILEN_Pos            (4U)
7759 #define FSMC_SR3_ILEN_Msk            (0x1UL << FSMC_SR3_ILEN_Pos)               /*!< 0x00000010 */
7760 #define FSMC_SR3_ILEN                FSMC_SR3_ILEN_Msk                         /*!<Interrupt Level detection Enable bit */
7761 #define FSMC_SR3_IFEN_Pos            (5U)
7762 #define FSMC_SR3_IFEN_Msk            (0x1UL << FSMC_SR3_IFEN_Pos)               /*!< 0x00000020 */
7763 #define FSMC_SR3_IFEN                FSMC_SR3_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
7764 #define FSMC_SR3_FEMPT_Pos           (6U)
7765 #define FSMC_SR3_FEMPT_Msk           (0x1UL << FSMC_SR3_FEMPT_Pos)              /*!< 0x00000040 */
7766 #define FSMC_SR3_FEMPT               FSMC_SR3_FEMPT_Msk                        /*!<FIFO empty */
7767 
7768 /*******************  Bit definition for FSMC_SR4 register  *******************/
7769 #define FSMC_SR4_IRS_Pos             (0U)
7770 #define FSMC_SR4_IRS_Msk             (0x1UL << FSMC_SR4_IRS_Pos)                /*!< 0x00000001 */
7771 #define FSMC_SR4_IRS                 FSMC_SR4_IRS_Msk                          /*!<Interrupt Rising Edge status */
7772 #define FSMC_SR4_ILS_Pos             (1U)
7773 #define FSMC_SR4_ILS_Msk             (0x1UL << FSMC_SR4_ILS_Pos)                /*!< 0x00000002 */
7774 #define FSMC_SR4_ILS                 FSMC_SR4_ILS_Msk                          /*!<Interrupt Level status */
7775 #define FSMC_SR4_IFS_Pos             (2U)
7776 #define FSMC_SR4_IFS_Msk             (0x1UL << FSMC_SR4_IFS_Pos)                /*!< 0x00000004 */
7777 #define FSMC_SR4_IFS                 FSMC_SR4_IFS_Msk                          /*!<Interrupt Falling Edge status */
7778 #define FSMC_SR4_IREN_Pos            (3U)
7779 #define FSMC_SR4_IREN_Msk            (0x1UL << FSMC_SR4_IREN_Pos)               /*!< 0x00000008 */
7780 #define FSMC_SR4_IREN                FSMC_SR4_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit */
7781 #define FSMC_SR4_ILEN_Pos            (4U)
7782 #define FSMC_SR4_ILEN_Msk            (0x1UL << FSMC_SR4_ILEN_Pos)               /*!< 0x00000010 */
7783 #define FSMC_SR4_ILEN                FSMC_SR4_ILEN_Msk                         /*!<Interrupt Level detection Enable bit */
7784 #define FSMC_SR4_IFEN_Pos            (5U)
7785 #define FSMC_SR4_IFEN_Msk            (0x1UL << FSMC_SR4_IFEN_Pos)               /*!< 0x00000020 */
7786 #define FSMC_SR4_IFEN                FSMC_SR4_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
7787 #define FSMC_SR4_FEMPT_Pos           (6U)
7788 #define FSMC_SR4_FEMPT_Msk           (0x1UL << FSMC_SR4_FEMPT_Pos)              /*!< 0x00000040 */
7789 #define FSMC_SR4_FEMPT               FSMC_SR4_FEMPT_Msk                        /*!<FIFO empty */
7790 
7791 /******************  Bit definition for FSMC_PMEM2 register  ******************/
7792 #define FSMC_PMEM2_MEMSET2_Pos       (0U)
7793 #define FSMC_PMEM2_MEMSET2_Msk       (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x000000FF */
7794 #define FSMC_PMEM2_MEMSET2           FSMC_PMEM2_MEMSET2_Msk                    /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
7795 #define FSMC_PMEM2_MEMSET2_0         (0x01UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000001 */
7796 #define FSMC_PMEM2_MEMSET2_1         (0x02UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000002 */
7797 #define FSMC_PMEM2_MEMSET2_2         (0x04UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000004 */
7798 #define FSMC_PMEM2_MEMSET2_3         (0x08UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000008 */
7799 #define FSMC_PMEM2_MEMSET2_4         (0x10UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000010 */
7800 #define FSMC_PMEM2_MEMSET2_5         (0x20UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000020 */
7801 #define FSMC_PMEM2_MEMSET2_6         (0x40UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000040 */
7802 #define FSMC_PMEM2_MEMSET2_7         (0x80UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000080 */
7803 
7804 #define FSMC_PMEM2_MEMWAIT2_Pos      (8U)
7805 #define FSMC_PMEM2_MEMWAIT2_Msk      (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x0000FF00 */
7806 #define FSMC_PMEM2_MEMWAIT2          FSMC_PMEM2_MEMWAIT2_Msk                   /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
7807 #define FSMC_PMEM2_MEMWAIT2_0        (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000100 */
7808 #define FSMC_PMEM2_MEMWAIT2_1        (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000200 */
7809 #define FSMC_PMEM2_MEMWAIT2_2        (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000400 */
7810 #define FSMC_PMEM2_MEMWAIT2_3        (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000800 */
7811 #define FSMC_PMEM2_MEMWAIT2_4        (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00001000 */
7812 #define FSMC_PMEM2_MEMWAIT2_5        (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00002000 */
7813 #define FSMC_PMEM2_MEMWAIT2_6        (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00004000 */
7814 #define FSMC_PMEM2_MEMWAIT2_7        (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00008000 */
7815 
7816 #define FSMC_PMEM2_MEMHOLD2_Pos      (16U)
7817 #define FSMC_PMEM2_MEMHOLD2_Msk      (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00FF0000 */
7818 #define FSMC_PMEM2_MEMHOLD2          FSMC_PMEM2_MEMHOLD2_Msk                   /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
7819 #define FSMC_PMEM2_MEMHOLD2_0        (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00010000 */
7820 #define FSMC_PMEM2_MEMHOLD2_1        (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00020000 */
7821 #define FSMC_PMEM2_MEMHOLD2_2        (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00040000 */
7822 #define FSMC_PMEM2_MEMHOLD2_3        (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00080000 */
7823 #define FSMC_PMEM2_MEMHOLD2_4        (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00100000 */
7824 #define FSMC_PMEM2_MEMHOLD2_5        (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00200000 */
7825 #define FSMC_PMEM2_MEMHOLD2_6        (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00400000 */
7826 #define FSMC_PMEM2_MEMHOLD2_7        (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00800000 */
7827 
7828 #define FSMC_PMEM2_MEMHIZ2_Pos       (24U)
7829 #define FSMC_PMEM2_MEMHIZ2_Msk       (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0xFF000000 */
7830 #define FSMC_PMEM2_MEMHIZ2           FSMC_PMEM2_MEMHIZ2_Msk                    /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
7831 #define FSMC_PMEM2_MEMHIZ2_0         (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x01000000 */
7832 #define FSMC_PMEM2_MEMHIZ2_1         (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x02000000 */
7833 #define FSMC_PMEM2_MEMHIZ2_2         (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x04000000 */
7834 #define FSMC_PMEM2_MEMHIZ2_3         (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x08000000 */
7835 #define FSMC_PMEM2_MEMHIZ2_4         (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x10000000 */
7836 #define FSMC_PMEM2_MEMHIZ2_5         (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x20000000 */
7837 #define FSMC_PMEM2_MEMHIZ2_6         (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x40000000 */
7838 #define FSMC_PMEM2_MEMHIZ2_7         (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x80000000 */
7839 
7840 /******************  Bit definition for FSMC_PMEM3 register  ******************/
7841 #define FSMC_PMEM3_MEMSET3_Pos       (0U)
7842 #define FSMC_PMEM3_MEMSET3_Msk       (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x000000FF */
7843 #define FSMC_PMEM3_MEMSET3           FSMC_PMEM3_MEMSET3_Msk                    /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
7844 #define FSMC_PMEM3_MEMSET3_0         (0x01UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000001 */
7845 #define FSMC_PMEM3_MEMSET3_1         (0x02UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000002 */
7846 #define FSMC_PMEM3_MEMSET3_2         (0x04UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000004 */
7847 #define FSMC_PMEM3_MEMSET3_3         (0x08UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000008 */
7848 #define FSMC_PMEM3_MEMSET3_4         (0x10UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000010 */
7849 #define FSMC_PMEM3_MEMSET3_5         (0x20UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000020 */
7850 #define FSMC_PMEM3_MEMSET3_6         (0x40UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000040 */
7851 #define FSMC_PMEM3_MEMSET3_7         (0x80UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000080 */
7852 
7853 #define FSMC_PMEM3_MEMWAIT3_Pos      (8U)
7854 #define FSMC_PMEM3_MEMWAIT3_Msk      (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x0000FF00 */
7855 #define FSMC_PMEM3_MEMWAIT3          FSMC_PMEM3_MEMWAIT3_Msk                   /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
7856 #define FSMC_PMEM3_MEMWAIT3_0        (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000100 */
7857 #define FSMC_PMEM3_MEMWAIT3_1        (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000200 */
7858 #define FSMC_PMEM3_MEMWAIT3_2        (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000400 */
7859 #define FSMC_PMEM3_MEMWAIT3_3        (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000800 */
7860 #define FSMC_PMEM3_MEMWAIT3_4        (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00001000 */
7861 #define FSMC_PMEM3_MEMWAIT3_5        (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00002000 */
7862 #define FSMC_PMEM3_MEMWAIT3_6        (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00004000 */
7863 #define FSMC_PMEM3_MEMWAIT3_7        (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00008000 */
7864 
7865 #define FSMC_PMEM3_MEMHOLD3_Pos      (16U)
7866 #define FSMC_PMEM3_MEMHOLD3_Msk      (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00FF0000 */
7867 #define FSMC_PMEM3_MEMHOLD3          FSMC_PMEM3_MEMHOLD3_Msk                   /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
7868 #define FSMC_PMEM3_MEMHOLD3_0        (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00010000 */
7869 #define FSMC_PMEM3_MEMHOLD3_1        (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00020000 */
7870 #define FSMC_PMEM3_MEMHOLD3_2        (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00040000 */
7871 #define FSMC_PMEM3_MEMHOLD3_3        (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00080000 */
7872 #define FSMC_PMEM3_MEMHOLD3_4        (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00100000 */
7873 #define FSMC_PMEM3_MEMHOLD3_5        (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00200000 */
7874 #define FSMC_PMEM3_MEMHOLD3_6        (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00400000 */
7875 #define FSMC_PMEM3_MEMHOLD3_7        (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00800000 */
7876 
7877 #define FSMC_PMEM3_MEMHIZ3_Pos       (24U)
7878 #define FSMC_PMEM3_MEMHIZ3_Msk       (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0xFF000000 */
7879 #define FSMC_PMEM3_MEMHIZ3           FSMC_PMEM3_MEMHIZ3_Msk                    /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
7880 #define FSMC_PMEM3_MEMHIZ3_0         (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x01000000 */
7881 #define FSMC_PMEM3_MEMHIZ3_1         (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x02000000 */
7882 #define FSMC_PMEM3_MEMHIZ3_2         (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x04000000 */
7883 #define FSMC_PMEM3_MEMHIZ3_3         (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x08000000 */
7884 #define FSMC_PMEM3_MEMHIZ3_4         (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x10000000 */
7885 #define FSMC_PMEM3_MEMHIZ3_5         (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x20000000 */
7886 #define FSMC_PMEM3_MEMHIZ3_6         (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x40000000 */
7887 #define FSMC_PMEM3_MEMHIZ3_7         (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x80000000 */
7888 
7889 /******************  Bit definition for FSMC_PMEM4 register  ******************/
7890 #define FSMC_PMEM4_MEMSET4_Pos       (0U)
7891 #define FSMC_PMEM4_MEMSET4_Msk       (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x000000FF */
7892 #define FSMC_PMEM4_MEMSET4           FSMC_PMEM4_MEMSET4_Msk                    /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
7893 #define FSMC_PMEM4_MEMSET4_0         (0x01UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000001 */
7894 #define FSMC_PMEM4_MEMSET4_1         (0x02UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000002 */
7895 #define FSMC_PMEM4_MEMSET4_2         (0x04UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000004 */
7896 #define FSMC_PMEM4_MEMSET4_3         (0x08UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000008 */
7897 #define FSMC_PMEM4_MEMSET4_4         (0x10UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000010 */
7898 #define FSMC_PMEM4_MEMSET4_5         (0x20UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000020 */
7899 #define FSMC_PMEM4_MEMSET4_6         (0x40UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000040 */
7900 #define FSMC_PMEM4_MEMSET4_7         (0x80UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000080 */
7901 
7902 #define FSMC_PMEM4_MEMWAIT4_Pos      (8U)
7903 #define FSMC_PMEM4_MEMWAIT4_Msk      (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x0000FF00 */
7904 #define FSMC_PMEM4_MEMWAIT4          FSMC_PMEM4_MEMWAIT4_Msk                   /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
7905 #define FSMC_PMEM4_MEMWAIT4_0        (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000100 */
7906 #define FSMC_PMEM4_MEMWAIT4_1        (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000200 */
7907 #define FSMC_PMEM4_MEMWAIT4_2        (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000400 */
7908 #define FSMC_PMEM4_MEMWAIT4_3        (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000800 */
7909 #define FSMC_PMEM4_MEMWAIT4_4        (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00001000 */
7910 #define FSMC_PMEM4_MEMWAIT4_5        (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00002000 */
7911 #define FSMC_PMEM4_MEMWAIT4_6        (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00004000 */
7912 #define FSMC_PMEM4_MEMWAIT4_7        (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00008000 */
7913 
7914 #define FSMC_PMEM4_MEMHOLD4_Pos      (16U)
7915 #define FSMC_PMEM4_MEMHOLD4_Msk      (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00FF0000 */
7916 #define FSMC_PMEM4_MEMHOLD4          FSMC_PMEM4_MEMHOLD4_Msk                   /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
7917 #define FSMC_PMEM4_MEMHOLD4_0        (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00010000 */
7918 #define FSMC_PMEM4_MEMHOLD4_1        (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00020000 */
7919 #define FSMC_PMEM4_MEMHOLD4_2        (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00040000 */
7920 #define FSMC_PMEM4_MEMHOLD4_3        (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00080000 */
7921 #define FSMC_PMEM4_MEMHOLD4_4        (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00100000 */
7922 #define FSMC_PMEM4_MEMHOLD4_5        (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00200000 */
7923 #define FSMC_PMEM4_MEMHOLD4_6        (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00400000 */
7924 #define FSMC_PMEM4_MEMHOLD4_7        (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00800000 */
7925 
7926 #define FSMC_PMEM4_MEMHIZ4_Pos       (24U)
7927 #define FSMC_PMEM4_MEMHIZ4_Msk       (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0xFF000000 */
7928 #define FSMC_PMEM4_MEMHIZ4           FSMC_PMEM4_MEMHIZ4_Msk                    /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
7929 #define FSMC_PMEM4_MEMHIZ4_0         (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x01000000 */
7930 #define FSMC_PMEM4_MEMHIZ4_1         (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x02000000 */
7931 #define FSMC_PMEM4_MEMHIZ4_2         (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x04000000 */
7932 #define FSMC_PMEM4_MEMHIZ4_3         (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x08000000 */
7933 #define FSMC_PMEM4_MEMHIZ4_4         (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x10000000 */
7934 #define FSMC_PMEM4_MEMHIZ4_5         (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x20000000 */
7935 #define FSMC_PMEM4_MEMHIZ4_6         (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x40000000 */
7936 #define FSMC_PMEM4_MEMHIZ4_7         (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x80000000 */
7937 
7938 /******************  Bit definition for FSMC_PATT2 register  ******************/
7939 #define FSMC_PATT2_ATTSET2_Pos       (0U)
7940 #define FSMC_PATT2_ATTSET2_Msk       (0xFFUL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x000000FF */
7941 #define FSMC_PATT2_ATTSET2           FSMC_PATT2_ATTSET2_Msk                    /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
7942 #define FSMC_PATT2_ATTSET2_0         (0x01UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000001 */
7943 #define FSMC_PATT2_ATTSET2_1         (0x02UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000002 */
7944 #define FSMC_PATT2_ATTSET2_2         (0x04UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000004 */
7945 #define FSMC_PATT2_ATTSET2_3         (0x08UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000008 */
7946 #define FSMC_PATT2_ATTSET2_4         (0x10UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000010 */
7947 #define FSMC_PATT2_ATTSET2_5         (0x20UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000020 */
7948 #define FSMC_PATT2_ATTSET2_6         (0x40UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000040 */
7949 #define FSMC_PATT2_ATTSET2_7         (0x80UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000080 */
7950 
7951 #define FSMC_PATT2_ATTWAIT2_Pos      (8U)
7952 #define FSMC_PATT2_ATTWAIT2_Msk      (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x0000FF00 */
7953 #define FSMC_PATT2_ATTWAIT2          FSMC_PATT2_ATTWAIT2_Msk                   /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
7954 #define FSMC_PATT2_ATTWAIT2_0        (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000100 */
7955 #define FSMC_PATT2_ATTWAIT2_1        (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000200 */
7956 #define FSMC_PATT2_ATTWAIT2_2        (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000400 */
7957 #define FSMC_PATT2_ATTWAIT2_3        (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000800 */
7958 #define FSMC_PATT2_ATTWAIT2_4        (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00001000 */
7959 #define FSMC_PATT2_ATTWAIT2_5        (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00002000 */
7960 #define FSMC_PATT2_ATTWAIT2_6        (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00004000 */
7961 #define FSMC_PATT2_ATTWAIT2_7        (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00008000 */
7962 
7963 #define FSMC_PATT2_ATTHOLD2_Pos      (16U)
7964 #define FSMC_PATT2_ATTHOLD2_Msk      (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00FF0000 */
7965 #define FSMC_PATT2_ATTHOLD2          FSMC_PATT2_ATTHOLD2_Msk                   /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
7966 #define FSMC_PATT2_ATTHOLD2_0        (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00010000 */
7967 #define FSMC_PATT2_ATTHOLD2_1        (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00020000 */
7968 #define FSMC_PATT2_ATTHOLD2_2        (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00040000 */
7969 #define FSMC_PATT2_ATTHOLD2_3        (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00080000 */
7970 #define FSMC_PATT2_ATTHOLD2_4        (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00100000 */
7971 #define FSMC_PATT2_ATTHOLD2_5        (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00200000 */
7972 #define FSMC_PATT2_ATTHOLD2_6        (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00400000 */
7973 #define FSMC_PATT2_ATTHOLD2_7        (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00800000 */
7974 
7975 #define FSMC_PATT2_ATTHIZ2_Pos       (24U)
7976 #define FSMC_PATT2_ATTHIZ2_Msk       (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0xFF000000 */
7977 #define FSMC_PATT2_ATTHIZ2           FSMC_PATT2_ATTHIZ2_Msk                    /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
7978 #define FSMC_PATT2_ATTHIZ2_0         (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x01000000 */
7979 #define FSMC_PATT2_ATTHIZ2_1         (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x02000000 */
7980 #define FSMC_PATT2_ATTHIZ2_2         (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x04000000 */
7981 #define FSMC_PATT2_ATTHIZ2_3         (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x08000000 */
7982 #define FSMC_PATT2_ATTHIZ2_4         (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x10000000 */
7983 #define FSMC_PATT2_ATTHIZ2_5         (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x20000000 */
7984 #define FSMC_PATT2_ATTHIZ2_6         (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x40000000 */
7985 #define FSMC_PATT2_ATTHIZ2_7         (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x80000000 */
7986 
7987 /******************  Bit definition for FSMC_PATT3 register  ******************/
7988 #define FSMC_PATT3_ATTSET3_Pos       (0U)
7989 #define FSMC_PATT3_ATTSET3_Msk       (0xFFUL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x000000FF */
7990 #define FSMC_PATT3_ATTSET3           FSMC_PATT3_ATTSET3_Msk                    /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
7991 #define FSMC_PATT3_ATTSET3_0         (0x01UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000001 */
7992 #define FSMC_PATT3_ATTSET3_1         (0x02UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000002 */
7993 #define FSMC_PATT3_ATTSET3_2         (0x04UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000004 */
7994 #define FSMC_PATT3_ATTSET3_3         (0x08UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000008 */
7995 #define FSMC_PATT3_ATTSET3_4         (0x10UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000010 */
7996 #define FSMC_PATT3_ATTSET3_5         (0x20UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000020 */
7997 #define FSMC_PATT3_ATTSET3_6         (0x40UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000040 */
7998 #define FSMC_PATT3_ATTSET3_7         (0x80UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000080 */
7999 
8000 #define FSMC_PATT3_ATTWAIT3_Pos      (8U)
8001 #define FSMC_PATT3_ATTWAIT3_Msk      (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x0000FF00 */
8002 #define FSMC_PATT3_ATTWAIT3          FSMC_PATT3_ATTWAIT3_Msk                   /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
8003 #define FSMC_PATT3_ATTWAIT3_0        (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000100 */
8004 #define FSMC_PATT3_ATTWAIT3_1        (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000200 */
8005 #define FSMC_PATT3_ATTWAIT3_2        (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000400 */
8006 #define FSMC_PATT3_ATTWAIT3_3        (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000800 */
8007 #define FSMC_PATT3_ATTWAIT3_4        (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00001000 */
8008 #define FSMC_PATT3_ATTWAIT3_5        (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00002000 */
8009 #define FSMC_PATT3_ATTWAIT3_6        (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00004000 */
8010 #define FSMC_PATT3_ATTWAIT3_7        (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00008000 */
8011 
8012 #define FSMC_PATT3_ATTHOLD3_Pos      (16U)
8013 #define FSMC_PATT3_ATTHOLD3_Msk      (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00FF0000 */
8014 #define FSMC_PATT3_ATTHOLD3          FSMC_PATT3_ATTHOLD3_Msk                   /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
8015 #define FSMC_PATT3_ATTHOLD3_0        (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00010000 */
8016 #define FSMC_PATT3_ATTHOLD3_1        (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00020000 */
8017 #define FSMC_PATT3_ATTHOLD3_2        (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00040000 */
8018 #define FSMC_PATT3_ATTHOLD3_3        (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00080000 */
8019 #define FSMC_PATT3_ATTHOLD3_4        (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00100000 */
8020 #define FSMC_PATT3_ATTHOLD3_5        (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00200000 */
8021 #define FSMC_PATT3_ATTHOLD3_6        (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00400000 */
8022 #define FSMC_PATT3_ATTHOLD3_7        (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00800000 */
8023 
8024 #define FSMC_PATT3_ATTHIZ3_Pos       (24U)
8025 #define FSMC_PATT3_ATTHIZ3_Msk       (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0xFF000000 */
8026 #define FSMC_PATT3_ATTHIZ3           FSMC_PATT3_ATTHIZ3_Msk                    /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
8027 #define FSMC_PATT3_ATTHIZ3_0         (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x01000000 */
8028 #define FSMC_PATT3_ATTHIZ3_1         (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x02000000 */
8029 #define FSMC_PATT3_ATTHIZ3_2         (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x04000000 */
8030 #define FSMC_PATT3_ATTHIZ3_3         (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x08000000 */
8031 #define FSMC_PATT3_ATTHIZ3_4         (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x10000000 */
8032 #define FSMC_PATT3_ATTHIZ3_5         (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x20000000 */
8033 #define FSMC_PATT3_ATTHIZ3_6         (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x40000000 */
8034 #define FSMC_PATT3_ATTHIZ3_7         (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x80000000 */
8035 
8036 /******************  Bit definition for FSMC_PATT4 register  ******************/
8037 #define FSMC_PATT4_ATTSET4_Pos       (0U)
8038 #define FSMC_PATT4_ATTSET4_Msk       (0xFFUL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x000000FF */
8039 #define FSMC_PATT4_ATTSET4           FSMC_PATT4_ATTSET4_Msk                    /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
8040 #define FSMC_PATT4_ATTSET4_0         (0x01UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000001 */
8041 #define FSMC_PATT4_ATTSET4_1         (0x02UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000002 */
8042 #define FSMC_PATT4_ATTSET4_2         (0x04UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000004 */
8043 #define FSMC_PATT4_ATTSET4_3         (0x08UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000008 */
8044 #define FSMC_PATT4_ATTSET4_4         (0x10UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000010 */
8045 #define FSMC_PATT4_ATTSET4_5         (0x20UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000020 */
8046 #define FSMC_PATT4_ATTSET4_6         (0x40UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000040 */
8047 #define FSMC_PATT4_ATTSET4_7         (0x80UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000080 */
8048 
8049 #define FSMC_PATT4_ATTWAIT4_Pos      (8U)
8050 #define FSMC_PATT4_ATTWAIT4_Msk      (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x0000FF00 */
8051 #define FSMC_PATT4_ATTWAIT4          FSMC_PATT4_ATTWAIT4_Msk                   /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
8052 #define FSMC_PATT4_ATTWAIT4_0        (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000100 */
8053 #define FSMC_PATT4_ATTWAIT4_1        (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000200 */
8054 #define FSMC_PATT4_ATTWAIT4_2        (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000400 */
8055 #define FSMC_PATT4_ATTWAIT4_3        (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000800 */
8056 #define FSMC_PATT4_ATTWAIT4_4        (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00001000 */
8057 #define FSMC_PATT4_ATTWAIT4_5        (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00002000 */
8058 #define FSMC_PATT4_ATTWAIT4_6        (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00004000 */
8059 #define FSMC_PATT4_ATTWAIT4_7        (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00008000 */
8060 
8061 #define FSMC_PATT4_ATTHOLD4_Pos      (16U)
8062 #define FSMC_PATT4_ATTHOLD4_Msk      (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00FF0000 */
8063 #define FSMC_PATT4_ATTHOLD4          FSMC_PATT4_ATTHOLD4_Msk                   /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
8064 #define FSMC_PATT4_ATTHOLD4_0        (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00010000 */
8065 #define FSMC_PATT4_ATTHOLD4_1        (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00020000 */
8066 #define FSMC_PATT4_ATTHOLD4_2        (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00040000 */
8067 #define FSMC_PATT4_ATTHOLD4_3        (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00080000 */
8068 #define FSMC_PATT4_ATTHOLD4_4        (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00100000 */
8069 #define FSMC_PATT4_ATTHOLD4_5        (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00200000 */
8070 #define FSMC_PATT4_ATTHOLD4_6        (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00400000 */
8071 #define FSMC_PATT4_ATTHOLD4_7        (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00800000 */
8072 
8073 #define FSMC_PATT4_ATTHIZ4_Pos       (24U)
8074 #define FSMC_PATT4_ATTHIZ4_Msk       (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0xFF000000 */
8075 #define FSMC_PATT4_ATTHIZ4           FSMC_PATT4_ATTHIZ4_Msk                    /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
8076 #define FSMC_PATT4_ATTHIZ4_0         (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x01000000 */
8077 #define FSMC_PATT4_ATTHIZ4_1         (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x02000000 */
8078 #define FSMC_PATT4_ATTHIZ4_2         (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x04000000 */
8079 #define FSMC_PATT4_ATTHIZ4_3         (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x08000000 */
8080 #define FSMC_PATT4_ATTHIZ4_4         (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x10000000 */
8081 #define FSMC_PATT4_ATTHIZ4_5         (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x20000000 */
8082 #define FSMC_PATT4_ATTHIZ4_6         (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x40000000 */
8083 #define FSMC_PATT4_ATTHIZ4_7         (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x80000000 */
8084 
8085 /******************  Bit definition for FSMC_PIO4 register  *******************/
8086 #define FSMC_PIO4_IOSET4_Pos         (0U)
8087 #define FSMC_PIO4_IOSET4_Msk         (0xFFUL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x000000FF */
8088 #define FSMC_PIO4_IOSET4             FSMC_PIO4_IOSET4_Msk                      /*!<IOSET4[7:0] bits (I/O 4 setup time) */
8089 #define FSMC_PIO4_IOSET4_0           (0x01UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000001 */
8090 #define FSMC_PIO4_IOSET4_1           (0x02UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000002 */
8091 #define FSMC_PIO4_IOSET4_2           (0x04UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000004 */
8092 #define FSMC_PIO4_IOSET4_3           (0x08UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000008 */
8093 #define FSMC_PIO4_IOSET4_4           (0x10UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000010 */
8094 #define FSMC_PIO4_IOSET4_5           (0x20UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000020 */
8095 #define FSMC_PIO4_IOSET4_6           (0x40UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000040 */
8096 #define FSMC_PIO4_IOSET4_7           (0x80UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000080 */
8097 
8098 #define FSMC_PIO4_IOWAIT4_Pos        (8U)
8099 #define FSMC_PIO4_IOWAIT4_Msk        (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x0000FF00 */
8100 #define FSMC_PIO4_IOWAIT4            FSMC_PIO4_IOWAIT4_Msk                     /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
8101 #define FSMC_PIO4_IOWAIT4_0          (0x01UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000100 */
8102 #define FSMC_PIO4_IOWAIT4_1          (0x02UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000200 */
8103 #define FSMC_PIO4_IOWAIT4_2          (0x04UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000400 */
8104 #define FSMC_PIO4_IOWAIT4_3          (0x08UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000800 */
8105 #define FSMC_PIO4_IOWAIT4_4          (0x10UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00001000 */
8106 #define FSMC_PIO4_IOWAIT4_5          (0x20UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00002000 */
8107 #define FSMC_PIO4_IOWAIT4_6          (0x40UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00004000 */
8108 #define FSMC_PIO4_IOWAIT4_7          (0x80UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00008000 */
8109 
8110 #define FSMC_PIO4_IOHOLD4_Pos        (16U)
8111 #define FSMC_PIO4_IOHOLD4_Msk        (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00FF0000 */
8112 #define FSMC_PIO4_IOHOLD4            FSMC_PIO4_IOHOLD4_Msk                     /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
8113 #define FSMC_PIO4_IOHOLD4_0          (0x01UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00010000 */
8114 #define FSMC_PIO4_IOHOLD4_1          (0x02UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00020000 */
8115 #define FSMC_PIO4_IOHOLD4_2          (0x04UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00040000 */
8116 #define FSMC_PIO4_IOHOLD4_3          (0x08UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00080000 */
8117 #define FSMC_PIO4_IOHOLD4_4          (0x10UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00100000 */
8118 #define FSMC_PIO4_IOHOLD4_5          (0x20UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00200000 */
8119 #define FSMC_PIO4_IOHOLD4_6          (0x40UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00400000 */
8120 #define FSMC_PIO4_IOHOLD4_7          (0x80UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00800000 */
8121 
8122 #define FSMC_PIO4_IOHIZ4_Pos         (24U)
8123 #define FSMC_PIO4_IOHIZ4_Msk         (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0xFF000000 */
8124 #define FSMC_PIO4_IOHIZ4             FSMC_PIO4_IOHIZ4_Msk                      /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
8125 #define FSMC_PIO4_IOHIZ4_0           (0x01UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x01000000 */
8126 #define FSMC_PIO4_IOHIZ4_1           (0x02UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x02000000 */
8127 #define FSMC_PIO4_IOHIZ4_2           (0x04UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x04000000 */
8128 #define FSMC_PIO4_IOHIZ4_3           (0x08UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x08000000 */
8129 #define FSMC_PIO4_IOHIZ4_4           (0x10UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x10000000 */
8130 #define FSMC_PIO4_IOHIZ4_5           (0x20UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x20000000 */
8131 #define FSMC_PIO4_IOHIZ4_6           (0x40UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x40000000 */
8132 #define FSMC_PIO4_IOHIZ4_7           (0x80UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x80000000 */
8133 
8134 /******************  Bit definition for FSMC_ECCR2 register  ******************/
8135 #define FSMC_ECCR2_ECC2_Pos          (0U)
8136 #define FSMC_ECCR2_ECC2_Msk          (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)      /*!< 0xFFFFFFFF */
8137 #define FSMC_ECCR2_ECC2              FSMC_ECCR2_ECC2_Msk                       /*!<ECC result */
8138 
8139 /******************  Bit definition for FSMC_ECCR3 register  ******************/
8140 #define FSMC_ECCR3_ECC3_Pos          (0U)
8141 #define FSMC_ECCR3_ECC3_Msk          (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)      /*!< 0xFFFFFFFF */
8142 #define FSMC_ECCR3_ECC3              FSMC_ECCR3_ECC3_Msk                       /*!<ECC result */
8143 
8144 /******************************************************************************/
8145 /*                                                                            */
8146 /*                            General Purpose I/O                             */
8147 /*                                                                            */
8148 /******************************************************************************/
8149 /******************  Bits definition for GPIO_MODER register  *****************/
8150 #define GPIO_MODER_MODE0                    0x00000003U
8151 #define GPIO_MODER_MODE0_0                  0x00000001U
8152 #define GPIO_MODER_MODE0_1                  0x00000002U
8153 #define GPIO_MODER_MODE1                    0x0000000CU
8154 #define GPIO_MODER_MODE1_0                  0x00000004U
8155 #define GPIO_MODER_MODE1_1                  0x00000008U
8156 #define GPIO_MODER_MODE2                    0x00000030U
8157 #define GPIO_MODER_MODE2_0                  0x00000010U
8158 #define GPIO_MODER_MODE2_1                  0x00000020U
8159 #define GPIO_MODER_MODE3                    0x000000C0U
8160 #define GPIO_MODER_MODE3_0                  0x00000040U
8161 #define GPIO_MODER_MODE3_1                  0x00000080U
8162 #define GPIO_MODER_MODE4                    0x00000300U
8163 #define GPIO_MODER_MODE4_0                  0x00000100U
8164 #define GPIO_MODER_MODE4_1                  0x00000200U
8165 #define GPIO_MODER_MODE5                    0x00000C00U
8166 #define GPIO_MODER_MODE5_0                  0x00000400U
8167 #define GPIO_MODER_MODE5_1                  0x00000800U
8168 #define GPIO_MODER_MODE6                    0x00003000U
8169 #define GPIO_MODER_MODE6_0                  0x00001000U
8170 #define GPIO_MODER_MODE6_1                  0x00002000U
8171 #define GPIO_MODER_MODE7                    0x0000C000U
8172 #define GPIO_MODER_MODE7_0                  0x00004000U
8173 #define GPIO_MODER_MODE7_1                  0x00008000U
8174 #define GPIO_MODER_MODE8                    0x00030000U
8175 #define GPIO_MODER_MODE8_0                  0x00010000U
8176 #define GPIO_MODER_MODE8_1                  0x00020000U
8177 #define GPIO_MODER_MODE9                    0x000C0000U
8178 #define GPIO_MODER_MODE9_0                  0x00040000U
8179 #define GPIO_MODER_MODE9_1                  0x00080000U
8180 #define GPIO_MODER_MODE10                   0x00300000U
8181 #define GPIO_MODER_MODE10_0                 0x00100000U
8182 #define GPIO_MODER_MODE10_1                 0x00200000U
8183 #define GPIO_MODER_MODE11                   0x00C00000U
8184 #define GPIO_MODER_MODE11_0                 0x00400000U
8185 #define GPIO_MODER_MODE11_1                 0x00800000U
8186 #define GPIO_MODER_MODE12                   0x03000000U
8187 #define GPIO_MODER_MODE12_0                 0x01000000U
8188 #define GPIO_MODER_MODE12_1                 0x02000000U
8189 #define GPIO_MODER_MODE13                   0x0C000000U
8190 #define GPIO_MODER_MODE13_0                 0x04000000U
8191 #define GPIO_MODER_MODE13_1                 0x08000000U
8192 #define GPIO_MODER_MODE14                   0x30000000U
8193 #define GPIO_MODER_MODE14_0                 0x10000000U
8194 #define GPIO_MODER_MODE14_1                 0x20000000U
8195 #define GPIO_MODER_MODE15                   0xC0000000U
8196 #define GPIO_MODER_MODE15_0                 0x40000000U
8197 #define GPIO_MODER_MODE15_1                 0x80000000U
8198 
8199 /* Legacy defines */
8200 #define GPIO_MODER_MODER0_Pos       (0U)
8201 #define GPIO_MODER_MODER0_Msk       (0x3UL << GPIO_MODER_MODER0_Pos)            /*!< 0x00000003 */
8202 #define GPIO_MODER_MODER0           GPIO_MODER_MODER0_Msk
8203 #define GPIO_MODER_MODER0_0         (0x1UL << GPIO_MODER_MODER0_Pos)            /*!< 0x00000001 */
8204 #define GPIO_MODER_MODER0_1         (0x2UL << GPIO_MODER_MODER0_Pos)            /*!< 0x00000002 */
8205 #define GPIO_MODER_MODER1_Pos       (2U)
8206 #define GPIO_MODER_MODER1_Msk       (0x3UL << GPIO_MODER_MODER1_Pos)            /*!< 0x0000000C */
8207 #define GPIO_MODER_MODER1           GPIO_MODER_MODER1_Msk
8208 #define GPIO_MODER_MODER1_0         (0x1UL << GPIO_MODER_MODER1_Pos)            /*!< 0x00000004 */
8209 #define GPIO_MODER_MODER1_1         (0x2UL << GPIO_MODER_MODER1_Pos)            /*!< 0x00000008 */
8210 #define GPIO_MODER_MODER2_Pos       (4U)
8211 #define GPIO_MODER_MODER2_Msk       (0x3UL << GPIO_MODER_MODER2_Pos)            /*!< 0x00000030 */
8212 #define GPIO_MODER_MODER2           GPIO_MODER_MODER2_Msk
8213 #define GPIO_MODER_MODER2_0         (0x1UL << GPIO_MODER_MODER2_Pos)            /*!< 0x00000010 */
8214 #define GPIO_MODER_MODER2_1         (0x2UL << GPIO_MODER_MODER2_Pos)            /*!< 0x00000020 */
8215 #define GPIO_MODER_MODER3_Pos       (6U)
8216 #define GPIO_MODER_MODER3_Msk       (0x3UL << GPIO_MODER_MODER3_Pos)            /*!< 0x000000C0 */
8217 #define GPIO_MODER_MODER3           GPIO_MODER_MODER3_Msk
8218 #define GPIO_MODER_MODER3_0         (0x1UL << GPIO_MODER_MODER3_Pos)            /*!< 0x00000040 */
8219 #define GPIO_MODER_MODER3_1         (0x2UL << GPIO_MODER_MODER3_Pos)            /*!< 0x00000080 */
8220 #define GPIO_MODER_MODER4_Pos       (8U)
8221 #define GPIO_MODER_MODER4_Msk       (0x3UL << GPIO_MODER_MODER4_Pos)            /*!< 0x00000300 */
8222 #define GPIO_MODER_MODER4           GPIO_MODER_MODER4_Msk
8223 #define GPIO_MODER_MODER4_0         (0x1UL << GPIO_MODER_MODER4_Pos)            /*!< 0x00000100 */
8224 #define GPIO_MODER_MODER4_1         (0x2UL << GPIO_MODER_MODER4_Pos)            /*!< 0x00000200 */
8225 #define GPIO_MODER_MODER5_Pos       (10U)
8226 #define GPIO_MODER_MODER5_Msk       (0x3UL << GPIO_MODER_MODER5_Pos)            /*!< 0x00000C00 */
8227 #define GPIO_MODER_MODER5           GPIO_MODER_MODER5_Msk
8228 #define GPIO_MODER_MODER5_0         (0x1UL << GPIO_MODER_MODER5_Pos)            /*!< 0x00000400 */
8229 #define GPIO_MODER_MODER5_1         (0x2UL << GPIO_MODER_MODER5_Pos)            /*!< 0x00000800 */
8230 #define GPIO_MODER_MODER6_Pos       (12U)
8231 #define GPIO_MODER_MODER6_Msk       (0x3UL << GPIO_MODER_MODER6_Pos)            /*!< 0x00003000 */
8232 #define GPIO_MODER_MODER6           GPIO_MODER_MODER6_Msk
8233 #define GPIO_MODER_MODER6_0         (0x1UL << GPIO_MODER_MODER6_Pos)            /*!< 0x00001000 */
8234 #define GPIO_MODER_MODER6_1         (0x2UL << GPIO_MODER_MODER6_Pos)            /*!< 0x00002000 */
8235 #define GPIO_MODER_MODER7_Pos       (14U)
8236 #define GPIO_MODER_MODER7_Msk       (0x3UL << GPIO_MODER_MODER7_Pos)            /*!< 0x0000C000 */
8237 #define GPIO_MODER_MODER7           GPIO_MODER_MODER7_Msk
8238 #define GPIO_MODER_MODER7_0         (0x1UL << GPIO_MODER_MODER7_Pos)            /*!< 0x00004000 */
8239 #define GPIO_MODER_MODER7_1         (0x2UL << GPIO_MODER_MODER7_Pos)            /*!< 0x00008000 */
8240 #define GPIO_MODER_MODER8_Pos       (16U)
8241 #define GPIO_MODER_MODER8_Msk       (0x3UL << GPIO_MODER_MODER8_Pos)            /*!< 0x00030000 */
8242 #define GPIO_MODER_MODER8           GPIO_MODER_MODER8_Msk
8243 #define GPIO_MODER_MODER8_0         (0x1UL << GPIO_MODER_MODER8_Pos)            /*!< 0x00010000 */
8244 #define GPIO_MODER_MODER8_1         (0x2UL << GPIO_MODER_MODER8_Pos)            /*!< 0x00020000 */
8245 #define GPIO_MODER_MODER9_Pos       (18U)
8246 #define GPIO_MODER_MODER9_Msk       (0x3UL << GPIO_MODER_MODER9_Pos)            /*!< 0x000C0000 */
8247 #define GPIO_MODER_MODER9           GPIO_MODER_MODER9_Msk
8248 #define GPIO_MODER_MODER9_0         (0x1UL << GPIO_MODER_MODER9_Pos)            /*!< 0x00040000 */
8249 #define GPIO_MODER_MODER9_1         (0x2UL << GPIO_MODER_MODER9_Pos)            /*!< 0x00080000 */
8250 #define GPIO_MODER_MODER10_Pos      (20U)
8251 #define GPIO_MODER_MODER10_Msk      (0x3UL << GPIO_MODER_MODER10_Pos)           /*!< 0x00300000 */
8252 #define GPIO_MODER_MODER10          GPIO_MODER_MODER10_Msk
8253 #define GPIO_MODER_MODER10_0        (0x1UL << GPIO_MODER_MODER10_Pos)           /*!< 0x00100000 */
8254 #define GPIO_MODER_MODER10_1        (0x2UL << GPIO_MODER_MODER10_Pos)           /*!< 0x00200000 */
8255 #define GPIO_MODER_MODER11_Pos      (22U)
8256 #define GPIO_MODER_MODER11_Msk      (0x3UL << GPIO_MODER_MODER11_Pos)           /*!< 0x00C00000 */
8257 #define GPIO_MODER_MODER11          GPIO_MODER_MODER11_Msk
8258 #define GPIO_MODER_MODER11_0        (0x1UL << GPIO_MODER_MODER11_Pos)           /*!< 0x00400000 */
8259 #define GPIO_MODER_MODER11_1        (0x2UL << GPIO_MODER_MODER11_Pos)           /*!< 0x00800000 */
8260 #define GPIO_MODER_MODER12_Pos      (24U)
8261 #define GPIO_MODER_MODER12_Msk      (0x3UL << GPIO_MODER_MODER12_Pos)           /*!< 0x03000000 */
8262 #define GPIO_MODER_MODER12          GPIO_MODER_MODER12_Msk
8263 #define GPIO_MODER_MODER12_0        (0x1UL << GPIO_MODER_MODER12_Pos)           /*!< 0x01000000 */
8264 #define GPIO_MODER_MODER12_1        (0x2UL << GPIO_MODER_MODER12_Pos)           /*!< 0x02000000 */
8265 #define GPIO_MODER_MODER13_Pos      (26U)
8266 #define GPIO_MODER_MODER13_Msk      (0x3UL << GPIO_MODER_MODER13_Pos)           /*!< 0x0C000000 */
8267 #define GPIO_MODER_MODER13          GPIO_MODER_MODER13_Msk
8268 #define GPIO_MODER_MODER13_0        (0x1UL << GPIO_MODER_MODER13_Pos)           /*!< 0x04000000 */
8269 #define GPIO_MODER_MODER13_1        (0x2UL << GPIO_MODER_MODER13_Pos)           /*!< 0x08000000 */
8270 #define GPIO_MODER_MODER14_Pos      (28U)
8271 #define GPIO_MODER_MODER14_Msk      (0x3UL << GPIO_MODER_MODER14_Pos)           /*!< 0x30000000 */
8272 #define GPIO_MODER_MODER14          GPIO_MODER_MODER14_Msk
8273 #define GPIO_MODER_MODER14_0        (0x1UL << GPIO_MODER_MODER14_Pos)           /*!< 0x10000000 */
8274 #define GPIO_MODER_MODER14_1        (0x2UL << GPIO_MODER_MODER14_Pos)           /*!< 0x20000000 */
8275 #define GPIO_MODER_MODER15_Pos      (30U)
8276 #define GPIO_MODER_MODER15_Msk      (0x3UL << GPIO_MODER_MODER15_Pos)           /*!< 0xC0000000 */
8277 #define GPIO_MODER_MODER15          GPIO_MODER_MODER15_Msk
8278 #define GPIO_MODER_MODER15_0        (0x1UL << GPIO_MODER_MODER15_Pos)           /*!< 0x40000000 */
8279 #define GPIO_MODER_MODER15_1        (0x2UL << GPIO_MODER_MODER15_Pos)           /*!< 0x80000000 */
8280 
8281 /******************  Bits definition for GPIO_OTYPER register  ****************/
8282 #define GPIO_OTYPER_OT0                     0x00000001U
8283 #define GPIO_OTYPER_OT1                     0x00000002U
8284 #define GPIO_OTYPER_OT2                     0x00000004U
8285 #define GPIO_OTYPER_OT3                     0x00000008U
8286 #define GPIO_OTYPER_OT4                     0x00000010U
8287 #define GPIO_OTYPER_OT5                     0x00000020U
8288 #define GPIO_OTYPER_OT6                     0x00000040U
8289 #define GPIO_OTYPER_OT7                     0x00000080U
8290 #define GPIO_OTYPER_OT8                     0x00000100U
8291 #define GPIO_OTYPER_OT9                     0x00000200U
8292 #define GPIO_OTYPER_OT10                    0x00000400U
8293 #define GPIO_OTYPER_OT11                    0x00000800U
8294 #define GPIO_OTYPER_OT12                    0x00001000U
8295 #define GPIO_OTYPER_OT13                    0x00002000U
8296 #define GPIO_OTYPER_OT14                    0x00004000U
8297 #define GPIO_OTYPER_OT15                    0x00008000U
8298 
8299 /* Legacy defines */
8300 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
8301 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
8302 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
8303 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
8304 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
8305 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
8306 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
8307 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
8308 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
8309 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
8310 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
8311 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
8312 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
8313 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
8314 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
8315 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
8316 
8317 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
8318 #define GPIO_OSPEEDR_OSPEED0                0x00000003U
8319 #define GPIO_OSPEEDR_OSPEED0_0              0x00000001U
8320 #define GPIO_OSPEEDR_OSPEED0_1              0x00000002U
8321 #define GPIO_OSPEEDR_OSPEED1                0x0000000CU
8322 #define GPIO_OSPEEDR_OSPEED1_0              0x00000004U
8323 #define GPIO_OSPEEDR_OSPEED1_1              0x00000008U
8324 #define GPIO_OSPEEDR_OSPEED2                0x00000030U
8325 #define GPIO_OSPEEDR_OSPEED2_0              0x00000010U
8326 #define GPIO_OSPEEDR_OSPEED2_1              0x00000020U
8327 #define GPIO_OSPEEDR_OSPEED3                0x000000C0U
8328 #define GPIO_OSPEEDR_OSPEED3_0              0x00000040U
8329 #define GPIO_OSPEEDR_OSPEED3_1              0x00000080U
8330 #define GPIO_OSPEEDR_OSPEED4                0x00000300U
8331 #define GPIO_OSPEEDR_OSPEED4_0              0x00000100U
8332 #define GPIO_OSPEEDR_OSPEED4_1              0x00000200U
8333 #define GPIO_OSPEEDR_OSPEED5                0x00000C00U
8334 #define GPIO_OSPEEDR_OSPEED5_0              0x00000400U
8335 #define GPIO_OSPEEDR_OSPEED5_1              0x00000800U
8336 #define GPIO_OSPEEDR_OSPEED6                0x00003000U
8337 #define GPIO_OSPEEDR_OSPEED6_0              0x00001000U
8338 #define GPIO_OSPEEDR_OSPEED6_1              0x00002000U
8339 #define GPIO_OSPEEDR_OSPEED7                0x0000C000U
8340 #define GPIO_OSPEEDR_OSPEED7_0              0x00004000U
8341 #define GPIO_OSPEEDR_OSPEED7_1              0x00008000U
8342 #define GPIO_OSPEEDR_OSPEED8                0x00030000U
8343 #define GPIO_OSPEEDR_OSPEED8_0              0x00010000U
8344 #define GPIO_OSPEEDR_OSPEED8_1              0x00020000U
8345 #define GPIO_OSPEEDR_OSPEED9                0x000C0000U
8346 #define GPIO_OSPEEDR_OSPEED9_0              0x00040000U
8347 #define GPIO_OSPEEDR_OSPEED9_1              0x00080000U
8348 #define GPIO_OSPEEDR_OSPEED10               0x00300000U
8349 #define GPIO_OSPEEDR_OSPEED10_0             0x00100000U
8350 #define GPIO_OSPEEDR_OSPEED10_1             0x00200000U
8351 #define GPIO_OSPEEDR_OSPEED11               0x00C00000U
8352 #define GPIO_OSPEEDR_OSPEED11_0             0x00400000U
8353 #define GPIO_OSPEEDR_OSPEED11_1             0x00800000U
8354 #define GPIO_OSPEEDR_OSPEED12               0x03000000U
8355 #define GPIO_OSPEEDR_OSPEED12_0             0x01000000U
8356 #define GPIO_OSPEEDR_OSPEED12_1             0x02000000U
8357 #define GPIO_OSPEEDR_OSPEED13               0x0C000000U
8358 #define GPIO_OSPEEDR_OSPEED13_0             0x04000000U
8359 #define GPIO_OSPEEDR_OSPEED13_1             0x08000000U
8360 #define GPIO_OSPEEDR_OSPEED14               0x30000000U
8361 #define GPIO_OSPEEDR_OSPEED14_0             0x10000000U
8362 #define GPIO_OSPEEDR_OSPEED14_1             0x20000000U
8363 #define GPIO_OSPEEDR_OSPEED15               0xC0000000U
8364 #define GPIO_OSPEEDR_OSPEED15_0             0x40000000U
8365 #define GPIO_OSPEEDR_OSPEED15_1             0x80000000U
8366 
8367 /* Legacy defines */
8368 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
8369 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
8370 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
8371 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
8372 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
8373 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
8374 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
8375 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
8376 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
8377 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
8378 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
8379 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
8380 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
8381 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
8382 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
8383 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
8384 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
8385 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
8386 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
8387 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
8388 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
8389 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
8390 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
8391 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
8392 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
8393 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
8394 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
8395 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
8396 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
8397 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
8398 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
8399 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
8400 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
8401 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
8402 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
8403 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
8404 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
8405 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
8406 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
8407 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
8408 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
8409 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
8410 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
8411 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
8412 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
8413 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
8414 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
8415 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
8416 
8417 /******************  Bits definition for GPIO_PUPDR register  *****************/
8418 #define GPIO_PUPDR_PUPD0                    0x00000003U
8419 #define GPIO_PUPDR_PUPD0_0                  0x00000001U
8420 #define GPIO_PUPDR_PUPD0_1                  0x00000002U
8421 #define GPIO_PUPDR_PUPD1                    0x0000000CU
8422 #define GPIO_PUPDR_PUPD1_0                  0x00000004U
8423 #define GPIO_PUPDR_PUPD1_1                  0x00000008U
8424 #define GPIO_PUPDR_PUPD2                    0x00000030U
8425 #define GPIO_PUPDR_PUPD2_0                  0x00000010U
8426 #define GPIO_PUPDR_PUPD2_1                  0x00000020U
8427 #define GPIO_PUPDR_PUPD3                    0x000000C0U
8428 #define GPIO_PUPDR_PUPD3_0                  0x00000040U
8429 #define GPIO_PUPDR_PUPD3_1                  0x00000080U
8430 #define GPIO_PUPDR_PUPD4                    0x00000300U
8431 #define GPIO_PUPDR_PUPD4_0                  0x00000100U
8432 #define GPIO_PUPDR_PUPD4_1                  0x00000200U
8433 #define GPIO_PUPDR_PUPD5                    0x00000C00U
8434 #define GPIO_PUPDR_PUPD5_0                  0x00000400U
8435 #define GPIO_PUPDR_PUPD5_1                  0x00000800U
8436 #define GPIO_PUPDR_PUPD6                    0x00003000U
8437 #define GPIO_PUPDR_PUPD6_0                  0x00001000U
8438 #define GPIO_PUPDR_PUPD6_1                  0x00002000U
8439 #define GPIO_PUPDR_PUPD7                    0x0000C000U
8440 #define GPIO_PUPDR_PUPD7_0                  0x00004000U
8441 #define GPIO_PUPDR_PUPD7_1                  0x00008000U
8442 #define GPIO_PUPDR_PUPD8                    0x00030000U
8443 #define GPIO_PUPDR_PUPD8_0                  0x00010000U
8444 #define GPIO_PUPDR_PUPD8_1                  0x00020000U
8445 #define GPIO_PUPDR_PUPD9                    0x000C0000U
8446 #define GPIO_PUPDR_PUPD9_0                  0x00040000U
8447 #define GPIO_PUPDR_PUPD9_1                  0x00080000U
8448 #define GPIO_PUPDR_PUPD10                   0x00300000U
8449 #define GPIO_PUPDR_PUPD10_0                 0x00100000U
8450 #define GPIO_PUPDR_PUPD10_1                 0x00200000U
8451 #define GPIO_PUPDR_PUPD11                   0x00C00000U
8452 #define GPIO_PUPDR_PUPD11_0                 0x00400000U
8453 #define GPIO_PUPDR_PUPD11_1                 0x00800000U
8454 #define GPIO_PUPDR_PUPD12                   0x03000000U
8455 #define GPIO_PUPDR_PUPD12_0                 0x01000000U
8456 #define GPIO_PUPDR_PUPD12_1                 0x02000000U
8457 #define GPIO_PUPDR_PUPD13                   0x0C000000U
8458 #define GPIO_PUPDR_PUPD13_0                 0x04000000U
8459 #define GPIO_PUPDR_PUPD13_1                 0x08000000U
8460 #define GPIO_PUPDR_PUPD14                   0x30000000U
8461 #define GPIO_PUPDR_PUPD14_0                 0x10000000U
8462 #define GPIO_PUPDR_PUPD14_1                 0x20000000U
8463 #define GPIO_PUPDR_PUPD15                   0xC0000000U
8464 #define GPIO_PUPDR_PUPD15_0                 0x40000000U
8465 #define GPIO_PUPDR_PUPD15_1                 0x80000000U
8466 
8467 /* Legacy defines */
8468 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
8469 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
8470 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
8471 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
8472 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
8473 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
8474 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
8475 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
8476 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
8477 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
8478 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
8479 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
8480 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
8481 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
8482 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
8483 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
8484 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
8485 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
8486 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
8487 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
8488 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
8489 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
8490 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
8491 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
8492 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
8493 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
8494 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
8495 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
8496 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
8497 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
8498 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
8499 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
8500 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
8501 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
8502 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
8503 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
8504 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
8505 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
8506 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
8507 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
8508 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
8509 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
8510 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
8511 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
8512 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
8513 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
8514 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
8515 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
8516 
8517 /******************  Bits definition for GPIO_IDR register  *******************/
8518 #define GPIO_IDR_ID0                        0x00000001U
8519 #define GPIO_IDR_ID1                        0x00000002U
8520 #define GPIO_IDR_ID2                        0x00000004U
8521 #define GPIO_IDR_ID3                        0x00000008U
8522 #define GPIO_IDR_ID4                        0x00000010U
8523 #define GPIO_IDR_ID5                        0x00000020U
8524 #define GPIO_IDR_ID6                        0x00000040U
8525 #define GPIO_IDR_ID7                        0x00000080U
8526 #define GPIO_IDR_ID8                        0x00000100U
8527 #define GPIO_IDR_ID9                        0x00000200U
8528 #define GPIO_IDR_ID10                       0x00000400U
8529 #define GPIO_IDR_ID11                       0x00000800U
8530 #define GPIO_IDR_ID12                       0x00001000U
8531 #define GPIO_IDR_ID13                       0x00002000U
8532 #define GPIO_IDR_ID14                       0x00004000U
8533 #define GPIO_IDR_ID15                       0x00008000U
8534 
8535 /* Legacy defines */
8536 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
8537 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
8538 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
8539 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
8540 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
8541 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
8542 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
8543 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
8544 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
8545 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
8546 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
8547 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
8548 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
8549 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
8550 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
8551 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
8552 
8553 /******************  Bits definition for GPIO_ODR register  *******************/
8554 #define GPIO_ODR_OD0                        0x00000001U
8555 #define GPIO_ODR_OD1                        0x00000002U
8556 #define GPIO_ODR_OD2                        0x00000004U
8557 #define GPIO_ODR_OD3                        0x00000008U
8558 #define GPIO_ODR_OD4                        0x00000010U
8559 #define GPIO_ODR_OD5                        0x00000020U
8560 #define GPIO_ODR_OD6                        0x00000040U
8561 #define GPIO_ODR_OD7                        0x00000080U
8562 #define GPIO_ODR_OD8                        0x00000100U
8563 #define GPIO_ODR_OD9                        0x00000200U
8564 #define GPIO_ODR_OD10                       0x00000400U
8565 #define GPIO_ODR_OD11                       0x00000800U
8566 #define GPIO_ODR_OD12                       0x00001000U
8567 #define GPIO_ODR_OD13                       0x00002000U
8568 #define GPIO_ODR_OD14                       0x00004000U
8569 #define GPIO_ODR_OD15                       0x00008000U
8570 
8571 /* Legacy defines */
8572 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
8573 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
8574 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
8575 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
8576 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
8577 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
8578 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
8579 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
8580 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
8581 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
8582 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
8583 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
8584 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
8585 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
8586 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
8587 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
8588 
8589 /******************  Bits definition for GPIO_BSRR register  ******************/
8590 #define GPIO_BSRR_BS0                       0x00000001U
8591 #define GPIO_BSRR_BS1                       0x00000002U
8592 #define GPIO_BSRR_BS2                       0x00000004U
8593 #define GPIO_BSRR_BS3                       0x00000008U
8594 #define GPIO_BSRR_BS4                       0x00000010U
8595 #define GPIO_BSRR_BS5                       0x00000020U
8596 #define GPIO_BSRR_BS6                       0x00000040U
8597 #define GPIO_BSRR_BS7                       0x00000080U
8598 #define GPIO_BSRR_BS8                       0x00000100U
8599 #define GPIO_BSRR_BS9                       0x00000200U
8600 #define GPIO_BSRR_BS10                      0x00000400U
8601 #define GPIO_BSRR_BS11                      0x00000800U
8602 #define GPIO_BSRR_BS12                      0x00001000U
8603 #define GPIO_BSRR_BS13                      0x00002000U
8604 #define GPIO_BSRR_BS14                      0x00004000U
8605 #define GPIO_BSRR_BS15                      0x00008000U
8606 #define GPIO_BSRR_BR0                       0x00010000U
8607 #define GPIO_BSRR_BR1                       0x00020000U
8608 #define GPIO_BSRR_BR2                       0x00040000U
8609 #define GPIO_BSRR_BR3                       0x00080000U
8610 #define GPIO_BSRR_BR4                       0x00100000U
8611 #define GPIO_BSRR_BR5                       0x00200000U
8612 #define GPIO_BSRR_BR6                       0x00400000U
8613 #define GPIO_BSRR_BR7                       0x00800000U
8614 #define GPIO_BSRR_BR8                       0x01000000U
8615 #define GPIO_BSRR_BR9                       0x02000000U
8616 #define GPIO_BSRR_BR10                      0x04000000U
8617 #define GPIO_BSRR_BR11                      0x08000000U
8618 #define GPIO_BSRR_BR12                      0x10000000U
8619 #define GPIO_BSRR_BR13                      0x20000000U
8620 #define GPIO_BSRR_BR14                      0x40000000U
8621 #define GPIO_BSRR_BR15                      0x80000000U
8622 
8623 /* Legacy defines */
8624 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
8625 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
8626 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
8627 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
8628 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
8629 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
8630 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
8631 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
8632 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
8633 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
8634 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
8635 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
8636 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
8637 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
8638 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
8639 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
8640 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
8641 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
8642 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
8643 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
8644 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
8645 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
8646 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
8647 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
8648 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
8649 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
8650 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
8651 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
8652 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
8653 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
8654 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
8655 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
8656 
8657 /****************** Bit definition for GPIO_LCKR register *********************/
8658 #define GPIO_LCKR_LCK0_Pos          (0U)
8659 #define GPIO_LCKR_LCK0_Msk          (0x1UL << GPIO_LCKR_LCK0_Pos)               /*!< 0x00000001 */
8660 #define GPIO_LCKR_LCK0              GPIO_LCKR_LCK0_Msk
8661 #define GPIO_LCKR_LCK1_Pos          (1U)
8662 #define GPIO_LCKR_LCK1_Msk          (0x1UL << GPIO_LCKR_LCK1_Pos)               /*!< 0x00000002 */
8663 #define GPIO_LCKR_LCK1              GPIO_LCKR_LCK1_Msk
8664 #define GPIO_LCKR_LCK2_Pos          (2U)
8665 #define GPIO_LCKR_LCK2_Msk          (0x1UL << GPIO_LCKR_LCK2_Pos)               /*!< 0x00000004 */
8666 #define GPIO_LCKR_LCK2              GPIO_LCKR_LCK2_Msk
8667 #define GPIO_LCKR_LCK3_Pos          (3U)
8668 #define GPIO_LCKR_LCK3_Msk          (0x1UL << GPIO_LCKR_LCK3_Pos)               /*!< 0x00000008 */
8669 #define GPIO_LCKR_LCK3              GPIO_LCKR_LCK3_Msk
8670 #define GPIO_LCKR_LCK4_Pos          (4U)
8671 #define GPIO_LCKR_LCK4_Msk          (0x1UL << GPIO_LCKR_LCK4_Pos)               /*!< 0x00000010 */
8672 #define GPIO_LCKR_LCK4              GPIO_LCKR_LCK4_Msk
8673 #define GPIO_LCKR_LCK5_Pos          (5U)
8674 #define GPIO_LCKR_LCK5_Msk          (0x1UL << GPIO_LCKR_LCK5_Pos)               /*!< 0x00000020 */
8675 #define GPIO_LCKR_LCK5              GPIO_LCKR_LCK5_Msk
8676 #define GPIO_LCKR_LCK6_Pos          (6U)
8677 #define GPIO_LCKR_LCK6_Msk          (0x1UL << GPIO_LCKR_LCK6_Pos)               /*!< 0x00000040 */
8678 #define GPIO_LCKR_LCK6              GPIO_LCKR_LCK6_Msk
8679 #define GPIO_LCKR_LCK7_Pos          (7U)
8680 #define GPIO_LCKR_LCK7_Msk          (0x1UL << GPIO_LCKR_LCK7_Pos)               /*!< 0x00000080 */
8681 #define GPIO_LCKR_LCK7              GPIO_LCKR_LCK7_Msk
8682 #define GPIO_LCKR_LCK8_Pos          (8U)
8683 #define GPIO_LCKR_LCK8_Msk          (0x1UL << GPIO_LCKR_LCK8_Pos)               /*!< 0x00000100 */
8684 #define GPIO_LCKR_LCK8              GPIO_LCKR_LCK8_Msk
8685 #define GPIO_LCKR_LCK9_Pos          (9U)
8686 #define GPIO_LCKR_LCK9_Msk          (0x1UL << GPIO_LCKR_LCK9_Pos)               /*!< 0x00000200 */
8687 #define GPIO_LCKR_LCK9              GPIO_LCKR_LCK9_Msk
8688 #define GPIO_LCKR_LCK10_Pos         (10U)
8689 #define GPIO_LCKR_LCK10_Msk         (0x1UL << GPIO_LCKR_LCK10_Pos)              /*!< 0x00000400 */
8690 #define GPIO_LCKR_LCK10             GPIO_LCKR_LCK10_Msk
8691 #define GPIO_LCKR_LCK11_Pos         (11U)
8692 #define GPIO_LCKR_LCK11_Msk         (0x1UL << GPIO_LCKR_LCK11_Pos)              /*!< 0x00000800 */
8693 #define GPIO_LCKR_LCK11             GPIO_LCKR_LCK11_Msk
8694 #define GPIO_LCKR_LCK12_Pos         (12U)
8695 #define GPIO_LCKR_LCK12_Msk         (0x1UL << GPIO_LCKR_LCK12_Pos)              /*!< 0x00001000 */
8696 #define GPIO_LCKR_LCK12             GPIO_LCKR_LCK12_Msk
8697 #define GPIO_LCKR_LCK13_Pos         (13U)
8698 #define GPIO_LCKR_LCK13_Msk         (0x1UL << GPIO_LCKR_LCK13_Pos)              /*!< 0x00002000 */
8699 #define GPIO_LCKR_LCK13             GPIO_LCKR_LCK13_Msk
8700 #define GPIO_LCKR_LCK14_Pos         (14U)
8701 #define GPIO_LCKR_LCK14_Msk         (0x1UL << GPIO_LCKR_LCK14_Pos)              /*!< 0x00004000 */
8702 #define GPIO_LCKR_LCK14             GPIO_LCKR_LCK14_Msk
8703 #define GPIO_LCKR_LCK15_Pos         (15U)
8704 #define GPIO_LCKR_LCK15_Msk         (0x1UL << GPIO_LCKR_LCK15_Pos)              /*!< 0x00008000 */
8705 #define GPIO_LCKR_LCK15             GPIO_LCKR_LCK15_Msk
8706 #define GPIO_LCKR_LCKK_Pos          (16U)
8707 #define GPIO_LCKR_LCKK_Msk          (0x1UL << GPIO_LCKR_LCKK_Pos)               /*!< 0x00010000 */
8708 #define GPIO_LCKR_LCKK              GPIO_LCKR_LCKK_Msk
8709 
8710 /****************** Bit definition for GPIO_AFRL register *********************/
8711 #define GPIO_AFRL_AFSEL0                    0x0000000FU
8712 #define GPIO_AFRL_AFSEL0_0                  0x00000001U
8713 #define GPIO_AFRL_AFSEL0_1                  0x00000002U
8714 #define GPIO_AFRL_AFSEL0_2                  0x00000004U
8715 #define GPIO_AFRL_AFSEL0_3                  0x00000008U
8716 #define GPIO_AFRL_AFSEL1                    0x000000F0U
8717 #define GPIO_AFRL_AFSEL1_0                  0x00000010U
8718 #define GPIO_AFRL_AFSEL1_1                  0x00000020U
8719 #define GPIO_AFRL_AFSEL1_2                  0x00000040U
8720 #define GPIO_AFRL_AFSEL1_3                  0x00000080U
8721 #define GPIO_AFRL_AFSEL2                    0x00000F00U
8722 #define GPIO_AFRL_AFSEL2_0                  0x00000100U
8723 #define GPIO_AFRL_AFSEL2_1                  0x00000200U
8724 #define GPIO_AFRL_AFSEL2_2                  0x00000400U
8725 #define GPIO_AFRL_AFSEL2_3                  0x00000800U
8726 #define GPIO_AFRL_AFSEL3                    0x0000F000U
8727 #define GPIO_AFRL_AFSEL3_0                  0x00001000U
8728 #define GPIO_AFRL_AFSEL3_1                  0x00002000U
8729 #define GPIO_AFRL_AFSEL3_2                  0x00004000U
8730 #define GPIO_AFRL_AFSEL3_3                  0x00008000U
8731 #define GPIO_AFRL_AFSEL4                    0x000F0000U
8732 #define GPIO_AFRL_AFSEL4_0                  0x00010000U
8733 #define GPIO_AFRL_AFSEL4_1                  0x00020000U
8734 #define GPIO_AFRL_AFSEL4_2                  0x00040000U
8735 #define GPIO_AFRL_AFSEL4_3                  0x00080000U
8736 #define GPIO_AFRL_AFSEL5                    0x00F00000U
8737 #define GPIO_AFRL_AFSEL5_0                  0x00100000U
8738 #define GPIO_AFRL_AFSEL5_1                  0x00200000U
8739 #define GPIO_AFRL_AFSEL5_2                  0x00400000U
8740 #define GPIO_AFRL_AFSEL5_3                  0x00800000U
8741 #define GPIO_AFRL_AFSEL6                    0x0F000000U
8742 #define GPIO_AFRL_AFSEL6_0                  0x01000000U
8743 #define GPIO_AFRL_AFSEL6_1                  0x02000000U
8744 #define GPIO_AFRL_AFSEL6_2                  0x04000000U
8745 #define GPIO_AFRL_AFSEL6_3                  0x08000000U
8746 #define GPIO_AFRL_AFSEL7                    0xF0000000U
8747 #define GPIO_AFRL_AFSEL7_0                  0x10000000U
8748 #define GPIO_AFRL_AFSEL7_1                  0x20000000U
8749 #define GPIO_AFRL_AFSEL7_2                  0x40000000U
8750 #define GPIO_AFRL_AFSEL7_3                  0x80000000U
8751 
8752 /* Legacy defines */
8753 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
8754 #define GPIO_AFRL_AFRL0_0                    GPIO_AFRL_AFSEL0_0
8755 #define GPIO_AFRL_AFRL0_1                    GPIO_AFRL_AFSEL0_1
8756 #define GPIO_AFRL_AFRL0_2                    GPIO_AFRL_AFSEL0_2
8757 #define GPIO_AFRL_AFRL0_3                    GPIO_AFRL_AFSEL0_3
8758 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
8759 #define GPIO_AFRL_AFRL1_0                    GPIO_AFRL_AFSEL1_0
8760 #define GPIO_AFRL_AFRL1_1                    GPIO_AFRL_AFSEL1_1
8761 #define GPIO_AFRL_AFRL1_2                    GPIO_AFRL_AFSEL1_2
8762 #define GPIO_AFRL_AFRL1_3                    GPIO_AFRL_AFSEL1_3
8763 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
8764 #define GPIO_AFRL_AFRL2_0                    GPIO_AFRL_AFSEL2_0
8765 #define GPIO_AFRL_AFRL2_1                    GPIO_AFRL_AFSEL2_1
8766 #define GPIO_AFRL_AFRL2_2                    GPIO_AFRL_AFSEL2_2
8767 #define GPIO_AFRL_AFRL2_3                    GPIO_AFRL_AFSEL2_3
8768 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
8769 #define GPIO_AFRL_AFRL3_0                    GPIO_AFRL_AFSEL3_0
8770 #define GPIO_AFRL_AFRL3_1                    GPIO_AFRL_AFSEL3_1
8771 #define GPIO_AFRL_AFRL3_2                    GPIO_AFRL_AFSEL3_2
8772 #define GPIO_AFRL_AFRL3_3                    GPIO_AFRL_AFSEL3_3
8773 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
8774 #define GPIO_AFRL_AFRL4_0                    GPIO_AFRL_AFSEL4_0
8775 #define GPIO_AFRL_AFRL4_1                    GPIO_AFRL_AFSEL4_1
8776 #define GPIO_AFRL_AFRL4_2                    GPIO_AFRL_AFSEL4_2
8777 #define GPIO_AFRL_AFRL4_3                    GPIO_AFRL_AFSEL4_3
8778 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
8779 #define GPIO_AFRL_AFRL5_0                    GPIO_AFRL_AFSEL5_0
8780 #define GPIO_AFRL_AFRL5_1                    GPIO_AFRL_AFSEL5_1
8781 #define GPIO_AFRL_AFRL5_2                    GPIO_AFRL_AFSEL5_2
8782 #define GPIO_AFRL_AFRL5_3                    GPIO_AFRL_AFSEL5_3
8783 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
8784 #define GPIO_AFRL_AFRL6_0                    GPIO_AFRL_AFSEL6_0
8785 #define GPIO_AFRL_AFRL6_1                    GPIO_AFRL_AFSEL6_1
8786 #define GPIO_AFRL_AFRL6_2                    GPIO_AFRL_AFSEL6_2
8787 #define GPIO_AFRL_AFRL6_3                    GPIO_AFRL_AFSEL6_3
8788 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
8789 #define GPIO_AFRL_AFRL7_0                    GPIO_AFRL_AFSEL7_0
8790 #define GPIO_AFRL_AFRL7_1                    GPIO_AFRL_AFSEL7_1
8791 #define GPIO_AFRL_AFRL7_2                    GPIO_AFRL_AFSEL7_2
8792 #define GPIO_AFRL_AFRL7_3                    GPIO_AFRL_AFSEL7_3
8793 
8794 /****************** Bit definition for GPIO_AFRH register *********************/
8795 #define GPIO_AFRH_AFSEL8                    0x0000000FU
8796 #define GPIO_AFRH_AFSEL8_0                  0x00000001U
8797 #define GPIO_AFRH_AFSEL8_1                  0x00000002U
8798 #define GPIO_AFRH_AFSEL8_2                  0x00000004U
8799 #define GPIO_AFRH_AFSEL8_3                  0x00000008U
8800 #define GPIO_AFRH_AFSEL9                    0x000000F0U
8801 #define GPIO_AFRH_AFSEL9_0                  0x00000010U
8802 #define GPIO_AFRH_AFSEL9_1                  0x00000020U
8803 #define GPIO_AFRH_AFSEL9_2                  0x00000040U
8804 #define GPIO_AFRH_AFSEL9_3                  0x00000080U
8805 #define GPIO_AFRH_AFSEL10                   0x00000F00U
8806 #define GPIO_AFRH_AFSEL10_0                 0x00000100U
8807 #define GPIO_AFRH_AFSEL10_1                 0x00000200U
8808 #define GPIO_AFRH_AFSEL10_2                 0x00000400U
8809 #define GPIO_AFRH_AFSEL10_3                 0x00000800U
8810 #define GPIO_AFRH_AFSEL11                   0x0000F000U
8811 #define GPIO_AFRH_AFSEL11_0                 0x00001000U
8812 #define GPIO_AFRH_AFSEL11_1                 0x00002000U
8813 #define GPIO_AFRH_AFSEL11_2                 0x00004000U
8814 #define GPIO_AFRH_AFSEL11_3                 0x00008000U
8815 #define GPIO_AFRH_AFSEL12                   0x000F0000U
8816 #define GPIO_AFRH_AFSEL12_0                 0x00010000U
8817 #define GPIO_AFRH_AFSEL12_1                 0x00020000U
8818 #define GPIO_AFRH_AFSEL12_2                 0x00040000U
8819 #define GPIO_AFRH_AFSEL12_3                 0x00080000U
8820 #define GPIO_AFRH_AFSEL13                   0x00F00000U
8821 #define GPIO_AFRH_AFSEL13_0                 0x00100000U
8822 #define GPIO_AFRH_AFSEL13_1                 0x00200000U
8823 #define GPIO_AFRH_AFSEL13_2                 0x00400000U
8824 #define GPIO_AFRH_AFSEL13_3                 0x00800000U
8825 #define GPIO_AFRH_AFSEL14                   0x0F000000U
8826 #define GPIO_AFRH_AFSEL14_0                 0x01000000U
8827 #define GPIO_AFRH_AFSEL14_1                 0x02000000U
8828 #define GPIO_AFRH_AFSEL14_2                 0x04000000U
8829 #define GPIO_AFRH_AFSEL14_3                 0x08000000U
8830 #define GPIO_AFRH_AFSEL15                   0xF0000000U
8831 #define GPIO_AFRH_AFSEL15_0                 0x10000000U
8832 #define GPIO_AFRH_AFSEL15_1                 0x20000000U
8833 #define GPIO_AFRH_AFSEL15_2                 0x40000000U
8834 #define GPIO_AFRH_AFSEL15_3                 0x80000000U
8835 
8836 /* Legacy defines */
8837 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
8838 #define GPIO_AFRH_AFRH0_0                    GPIO_AFRH_AFSEL8_0
8839 #define GPIO_AFRH_AFRH0_1                    GPIO_AFRH_AFSEL8_1
8840 #define GPIO_AFRH_AFRH0_2                    GPIO_AFRH_AFSEL8_2
8841 #define GPIO_AFRH_AFRH0_3                    GPIO_AFRH_AFSEL8_3
8842 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
8843 #define GPIO_AFRH_AFRH1_0                    GPIO_AFRH_AFSEL9_0
8844 #define GPIO_AFRH_AFRH1_1                    GPIO_AFRH_AFSEL9_1
8845 #define GPIO_AFRH_AFRH1_2                    GPIO_AFRH_AFSEL9_2
8846 #define GPIO_AFRH_AFRH1_3                    GPIO_AFRH_AFSEL9_3
8847 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
8848 #define GPIO_AFRH_AFRH2_0                    GPIO_AFRH_AFSEL10_0
8849 #define GPIO_AFRH_AFRH2_1                    GPIO_AFRH_AFSEL10_1
8850 #define GPIO_AFRH_AFRH2_2                    GPIO_AFRH_AFSEL10_2
8851 #define GPIO_AFRH_AFRH2_3                    GPIO_AFRH_AFSEL10_3
8852 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
8853 #define GPIO_AFRH_AFRH3_0                    GPIO_AFRH_AFSEL11_0
8854 #define GPIO_AFRH_AFRH3_1                    GPIO_AFRH_AFSEL11_1
8855 #define GPIO_AFRH_AFRH3_2                    GPIO_AFRH_AFSEL11_2
8856 #define GPIO_AFRH_AFRH3_3                    GPIO_AFRH_AFSEL11_3
8857 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
8858 #define GPIO_AFRH_AFRH4_0                    GPIO_AFRH_AFSEL12_0
8859 #define GPIO_AFRH_AFRH4_1                    GPIO_AFRH_AFSEL12_1
8860 #define GPIO_AFRH_AFRH4_2                    GPIO_AFRH_AFSEL12_2
8861 #define GPIO_AFRH_AFRH4_3                    GPIO_AFRH_AFSEL12_3
8862 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
8863 #define GPIO_AFRH_AFRH5_0                    GPIO_AFRH_AFSEL13_0
8864 #define GPIO_AFRH_AFRH5_1                    GPIO_AFRH_AFSEL13_1
8865 #define GPIO_AFRH_AFRH5_2                    GPIO_AFRH_AFSEL13_2
8866 #define GPIO_AFRH_AFRH5_3                    GPIO_AFRH_AFSEL13_3
8867 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
8868 #define GPIO_AFRH_AFRH6_0                    GPIO_AFRH_AFSEL14_0
8869 #define GPIO_AFRH_AFRH6_1                    GPIO_AFRH_AFSEL14_1
8870 #define GPIO_AFRH_AFRH6_2                    GPIO_AFRH_AFSEL14_2
8871 #define GPIO_AFRH_AFRH6_3                    GPIO_AFRH_AFSEL14_3
8872 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
8873 #define GPIO_AFRH_AFRH7_0                    GPIO_AFRH_AFSEL15_0
8874 #define GPIO_AFRH_AFRH7_1                    GPIO_AFRH_AFSEL15_1
8875 #define GPIO_AFRH_AFRH7_2                    GPIO_AFRH_AFSEL15_2
8876 #define GPIO_AFRH_AFRH7_3                    GPIO_AFRH_AFSEL15_3
8877 
8878 
8879 /******************************************************************************/
8880 /*                                                                            */
8881 /*                                    HASH                                    */
8882 /*                                                                            */
8883 /******************************************************************************/
8884 /******************  Bits definition for HASH_CR register  ********************/
8885 #define HASH_CR_INIT_Pos          (2U)
8886 #define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                   /*!< 0x00000004 */
8887 #define HASH_CR_INIT              HASH_CR_INIT_Msk
8888 #define HASH_CR_DMAE_Pos          (3U)
8889 #define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                   /*!< 0x00000008 */
8890 #define HASH_CR_DMAE              HASH_CR_DMAE_Msk
8891 #define HASH_CR_DATATYPE_Pos      (4U)
8892 #define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000030 */
8893 #define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk
8894 #define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */
8895 #define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */
8896 #define HASH_CR_MODE_Pos          (6U)
8897 #define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                   /*!< 0x00000040 */
8898 #define HASH_CR_MODE              HASH_CR_MODE_Msk
8899 #define HASH_CR_ALGO_Pos          (7U)
8900 #define HASH_CR_ALGO_Msk          (0x1UL << HASH_CR_ALGO_Pos)                   /*!< 0x00000080 */
8901 #define HASH_CR_ALGO              HASH_CR_ALGO_Msk
8902 #define HASH_CR_ALGO_0            (0x1UL << HASH_CR_ALGO_Pos)                   /*!< 0x00000080 */
8903 #define HASH_CR_NBW_Pos           (8U)
8904 #define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                    /*!< 0x00000F00 */
8905 #define HASH_CR_NBW               HASH_CR_NBW_Msk
8906 #define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */
8907 #define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */
8908 #define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */
8909 #define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */
8910 #define HASH_CR_DINNE_Pos         (12U)
8911 #define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                  /*!< 0x00001000 */
8912 #define HASH_CR_DINNE             HASH_CR_DINNE_Msk
8913 #define HASH_CR_LKEY_Pos          (16U)
8914 #define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                   /*!< 0x00010000 */
8915 #define HASH_CR_LKEY              HASH_CR_LKEY_Msk
8916 
8917 /******************  Bits definition for HASH_STR register  *******************/
8918 #define HASH_STR_NBLW_Pos         (0U)
8919 #define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                 /*!< 0x0000001F */
8920 #define HASH_STR_NBLW             HASH_STR_NBLW_Msk
8921 #define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */
8922 #define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */
8923 #define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */
8924 #define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */
8925 #define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */
8926 #define HASH_STR_DCAL_Pos         (8U)
8927 #define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                  /*!< 0x00000100 */
8928 #define HASH_STR_DCAL             HASH_STR_DCAL_Msk
8929 /* Aliases for HASH_STR register */
8930 #define HASH_STR_NBW                         HASH_STR_NBLW
8931 #define HASH_STR_NBW_0                       HASH_STR_NBLW_0
8932 #define HASH_STR_NBW_1                       HASH_STR_NBLW_1
8933 #define HASH_STR_NBW_2                       HASH_STR_NBLW_2
8934 #define HASH_STR_NBW_3                       HASH_STR_NBLW_3
8935 #define HASH_STR_NBW_4                       HASH_STR_NBLW_4
8936 
8937 
8938 /******************  Bits definition for HASH_IMR register  *******************/
8939 #define HASH_IMR_DINIE_Pos        (0U)
8940 #define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                 /*!< 0x00000001 */
8941 #define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk
8942 #define HASH_IMR_DCIE_Pos         (1U)
8943 #define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                  /*!< 0x00000002 */
8944 #define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk
8945 /* Aliases for HASH_IMR register */
8946 #define HASH_IMR_DINIM                       HASH_IMR_DINIE
8947 #define HASH_IMR_DCIM                        HASH_IMR_DCIE
8948 
8949 
8950 /******************  Bits definition for HASH_SR register  ********************/
8951 #define HASH_SR_DINIS_Pos         (0U)
8952 #define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                  /*!< 0x00000001 */
8953 #define HASH_SR_DINIS             HASH_SR_DINIS_Msk
8954 #define HASH_SR_DCIS_Pos          (1U)
8955 #define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                   /*!< 0x00000002 */
8956 #define HASH_SR_DCIS              HASH_SR_DCIS_Msk
8957 #define HASH_SR_DMAS_Pos          (2U)
8958 #define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                   /*!< 0x00000004 */
8959 #define HASH_SR_DMAS              HASH_SR_DMAS_Msk
8960 #define HASH_SR_BUSY_Pos          (3U)
8961 #define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                   /*!< 0x00000008 */
8962 #define HASH_SR_BUSY              HASH_SR_BUSY_Msk
8963 
8964 /******************************************************************************/
8965 /*                                                                            */
8966 /*                      Inter-integrated Circuit Interface                    */
8967 /*                                                                            */
8968 /******************************************************************************/
8969 /*******************  Bit definition for I2C_CR1 register  ********************/
8970 #define I2C_CR1_PE_Pos            (0U)
8971 #define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
8972 #define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
8973 #define I2C_CR1_SMBUS_Pos         (1U)
8974 #define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
8975 #define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
8976 #define I2C_CR1_SMBTYPE_Pos       (3U)
8977 #define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
8978 #define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
8979 #define I2C_CR1_ENARP_Pos         (4U)
8980 #define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
8981 #define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
8982 #define I2C_CR1_ENPEC_Pos         (5U)
8983 #define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
8984 #define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
8985 #define I2C_CR1_ENGC_Pos          (6U)
8986 #define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
8987 #define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
8988 #define I2C_CR1_NOSTRETCH_Pos     (7U)
8989 #define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
8990 #define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)  */
8991 #define I2C_CR1_START_Pos         (8U)
8992 #define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
8993 #define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
8994 #define I2C_CR1_STOP_Pos          (9U)
8995 #define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
8996 #define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
8997 #define I2C_CR1_ACK_Pos           (10U)
8998 #define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
8999 #define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
9000 #define I2C_CR1_POS_Pos           (11U)
9001 #define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
9002 #define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
9003 #define I2C_CR1_PEC_Pos           (12U)
9004 #define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
9005 #define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
9006 #define I2C_CR1_ALERT_Pos         (13U)
9007 #define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
9008 #define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
9009 #define I2C_CR1_SWRST_Pos         (15U)
9010 #define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
9011 #define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
9012 
9013 /*******************  Bit definition for I2C_CR2 register  ********************/
9014 #define I2C_CR2_FREQ_Pos          (0U)
9015 #define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
9016 #define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
9017 #define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
9018 #define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
9019 #define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
9020 #define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
9021 #define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
9022 #define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
9023 
9024 #define I2C_CR2_ITERREN_Pos       (8U)
9025 #define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
9026 #define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
9027 #define I2C_CR2_ITEVTEN_Pos       (9U)
9028 #define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
9029 #define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
9030 #define I2C_CR2_ITBUFEN_Pos       (10U)
9031 #define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
9032 #define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
9033 #define I2C_CR2_DMAEN_Pos         (11U)
9034 #define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
9035 #define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
9036 #define I2C_CR2_LAST_Pos          (12U)
9037 #define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
9038 #define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
9039 
9040 /*******************  Bit definition for I2C_OAR1 register  *******************/
9041 #define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
9042 #define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
9043 
9044 #define I2C_OAR1_ADD0_Pos         (0U)
9045 #define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
9046 #define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
9047 #define I2C_OAR1_ADD1_Pos         (1U)
9048 #define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
9049 #define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
9050 #define I2C_OAR1_ADD2_Pos         (2U)
9051 #define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
9052 #define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
9053 #define I2C_OAR1_ADD3_Pos         (3U)
9054 #define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
9055 #define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
9056 #define I2C_OAR1_ADD4_Pos         (4U)
9057 #define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
9058 #define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
9059 #define I2C_OAR1_ADD5_Pos         (5U)
9060 #define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
9061 #define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
9062 #define I2C_OAR1_ADD6_Pos         (6U)
9063 #define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
9064 #define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
9065 #define I2C_OAR1_ADD7_Pos         (7U)
9066 #define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
9067 #define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
9068 #define I2C_OAR1_ADD8_Pos         (8U)
9069 #define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
9070 #define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
9071 #define I2C_OAR1_ADD9_Pos         (9U)
9072 #define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
9073 #define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
9074 
9075 #define I2C_OAR1_ADDMODE_Pos      (15U)
9076 #define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
9077 #define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
9078 
9079 /*******************  Bit definition for I2C_OAR2 register  *******************/
9080 #define I2C_OAR2_ENDUAL_Pos       (0U)
9081 #define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
9082 #define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
9083 #define I2C_OAR2_ADD2_Pos         (1U)
9084 #define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
9085 #define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
9086 
9087 /********************  Bit definition for I2C_DR register  ********************/
9088 #define I2C_DR_DR_Pos             (0U)
9089 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
9090 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
9091 
9092 /*******************  Bit definition for I2C_SR1 register  ********************/
9093 #define I2C_SR1_SB_Pos            (0U)
9094 #define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
9095 #define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                  */
9096 #define I2C_SR1_ADDR_Pos          (1U)
9097 #define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
9098 #define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
9099 #define I2C_SR1_BTF_Pos           (2U)
9100 #define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
9101 #define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
9102 #define I2C_SR1_ADD10_Pos         (3U)
9103 #define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
9104 #define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)         */
9105 #define I2C_SR1_STOPF_Pos         (4U)
9106 #define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
9107 #define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)              */
9108 #define I2C_SR1_RXNE_Pos          (6U)
9109 #define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
9110 #define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)      */
9111 #define I2C_SR1_TXE_Pos           (7U)
9112 #define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
9113 #define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)       */
9114 #define I2C_SR1_BERR_Pos          (8U)
9115 #define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
9116 #define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
9117 #define I2C_SR1_ARLO_Pos          (9U)
9118 #define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
9119 #define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)           */
9120 #define I2C_SR1_AF_Pos            (10U)
9121 #define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
9122 #define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
9123 #define I2C_SR1_OVR_Pos           (11U)
9124 #define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
9125 #define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
9126 #define I2C_SR1_PECERR_Pos        (12U)
9127 #define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
9128 #define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
9129 #define I2C_SR1_TIMEOUT_Pos       (14U)
9130 #define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
9131 #define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
9132 #define I2C_SR1_SMBALERT_Pos      (15U)
9133 #define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
9134 #define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
9135 
9136 /*******************  Bit definition for I2C_SR2 register  ********************/
9137 #define I2C_SR2_MSL_Pos           (0U)
9138 #define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
9139 #define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                              */
9140 #define I2C_SR2_BUSY_Pos          (1U)
9141 #define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
9142 #define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                  */
9143 #define I2C_SR2_TRA_Pos           (2U)
9144 #define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
9145 #define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                      */
9146 #define I2C_SR2_GENCALL_Pos       (4U)
9147 #define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
9148 #define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)  */
9149 #define I2C_SR2_SMBDEFAULT_Pos    (5U)
9150 #define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
9151 #define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode) */
9152 #define I2C_SR2_SMBHOST_Pos       (6U)
9153 #define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
9154 #define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)     */
9155 #define I2C_SR2_DUALF_Pos         (7U)
9156 #define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
9157 #define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)             */
9158 #define I2C_SR2_PEC_Pos           (8U)
9159 #define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
9160 #define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register            */
9161 
9162 /*******************  Bit definition for I2C_CCR register  ********************/
9163 #define I2C_CCR_CCR_Pos           (0U)
9164 #define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
9165 #define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
9166 #define I2C_CCR_DUTY_Pos          (14U)
9167 #define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
9168 #define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
9169 #define I2C_CCR_FS_Pos            (15U)
9170 #define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
9171 #define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
9172 
9173 /******************  Bit definition for I2C_TRISE register  *******************/
9174 #define I2C_TRISE_TRISE_Pos       (0U)
9175 #define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
9176 #define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
9177 
9178 /******************************************************************************/
9179 /*                                                                            */
9180 /*                           Independent WATCHDOG                             */
9181 /*                                                                            */
9182 /******************************************************************************/
9183 /*******************  Bit definition for IWDG_KR register  ********************/
9184 #define IWDG_KR_KEY_Pos     (0U)
9185 #define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
9186 #define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h) */
9187 
9188 /*******************  Bit definition for IWDG_PR register  ********************/
9189 #define IWDG_PR_PR_Pos      (0U)
9190 #define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
9191 #define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider) */
9192 #define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x00000001 */
9193 #define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x00000002 */
9194 #define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x00000004 */
9195 
9196 /*******************  Bit definition for IWDG_RLR register  *******************/
9197 #define IWDG_RLR_RL_Pos     (0U)
9198 #define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
9199 #define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value */
9200 
9201 /*******************  Bit definition for IWDG_SR register  ********************/
9202 #define IWDG_SR_PVU_Pos     (0U)
9203 #define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
9204 #define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update */
9205 #define IWDG_SR_RVU_Pos     (1U)
9206 #define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
9207 #define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
9208 
9209 /******************************************************************************/
9210 /*                                                                            */
9211 /*                             Power Control                                  */
9212 /*                                                                            */
9213 /******************************************************************************/
9214 /********************  Bit definition for PWR_CR register  ********************/
9215 #define PWR_CR_LPDS_Pos        (0U)
9216 #define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
9217 #define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
9218 #define PWR_CR_PDDS_Pos        (1U)
9219 #define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
9220 #define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
9221 #define PWR_CR_CWUF_Pos        (2U)
9222 #define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
9223 #define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
9224 #define PWR_CR_CSBF_Pos        (3U)
9225 #define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
9226 #define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
9227 #define PWR_CR_PVDE_Pos        (4U)
9228 #define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
9229 #define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
9230 
9231 #define PWR_CR_PLS_Pos         (5U)
9232 #define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
9233 #define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
9234 #define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
9235 #define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
9236 #define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
9237 
9238 /*!< PVD level configuration */
9239 #define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
9240 #define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
9241 #define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
9242 #define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
9243 #define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
9244 #define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
9245 #define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
9246 #define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
9247 
9248 #define PWR_CR_DBP_Pos         (8U)
9249 #define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
9250 #define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
9251 #define PWR_CR_FPDS_Pos        (9U)
9252 #define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
9253 #define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
9254 
9255 /*******************  Bit definition for PWR_CSR register  ********************/
9256 #define PWR_CSR_WUF_Pos        (0U)
9257 #define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
9258 #define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
9259 #define PWR_CSR_SBF_Pos        (1U)
9260 #define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
9261 #define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
9262 #define PWR_CSR_PVDO_Pos       (2U)
9263 #define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
9264 #define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
9265 #define PWR_CSR_BRR_Pos        (3U)
9266 #define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
9267 #define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
9268 #define PWR_CSR_EWUP_Pos       (8U)
9269 #define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
9270 #define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
9271 #define PWR_CSR_BRE_Pos        (9U)
9272 #define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
9273 #define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
9274 
9275 /******************************************************************************/
9276 /*                                                                            */
9277 /*                         Reset and Clock Control                            */
9278 /*                                                                            */
9279 /******************************************************************************/
9280 /********************  Bit definition for RCC_CR register  ********************/
9281 #define RCC_CR_HSION_Pos                   (0U)
9282 #define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
9283 #define RCC_CR_HSION                       RCC_CR_HSION_Msk
9284 #define RCC_CR_HSIRDY_Pos                  (1U)
9285 #define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
9286 #define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk
9287 
9288 #define RCC_CR_HSITRIM_Pos                 (3U)
9289 #define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
9290 #define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk
9291 #define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
9292 #define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
9293 #define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
9294 #define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
9295 #define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
9296 
9297 #define RCC_CR_HSICAL_Pos                  (8U)
9298 #define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
9299 #define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk
9300 #define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
9301 #define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
9302 #define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
9303 #define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
9304 #define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
9305 #define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
9306 #define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
9307 #define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
9308 
9309 #define RCC_CR_HSEON_Pos                   (16U)
9310 #define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
9311 #define RCC_CR_HSEON                       RCC_CR_HSEON_Msk
9312 #define RCC_CR_HSERDY_Pos                  (17U)
9313 #define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
9314 #define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk
9315 #define RCC_CR_HSEBYP_Pos                  (18U)
9316 #define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
9317 #define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk
9318 #define RCC_CR_CSSON_Pos                   (19U)
9319 #define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
9320 #define RCC_CR_CSSON                       RCC_CR_CSSON_Msk
9321 #define RCC_CR_PLLON_Pos                   (24U)
9322 #define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
9323 #define RCC_CR_PLLON                       RCC_CR_PLLON_Msk
9324 #define RCC_CR_PLLRDY_Pos                  (25U)
9325 #define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
9326 #define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk
9327 #define RCC_CR_PLLI2SON_Pos                (26U)
9328 #define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
9329 #define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk
9330 #define RCC_CR_PLLI2SRDY_Pos               (27U)
9331 #define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
9332 #define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk
9333 
9334 /********************  Bit definition for RCC_PLLCFGR register  ***************/
9335 #define RCC_PLLCFGR_PLLM_Pos               (0U)
9336 #define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
9337 #define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk
9338 #define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
9339 #define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
9340 #define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
9341 #define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
9342 #define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
9343 #define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
9344 
9345 #define RCC_PLLCFGR_PLLN_Pos               (6U)
9346 #define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
9347 #define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk
9348 #define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
9349 #define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
9350 #define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
9351 #define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
9352 #define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
9353 #define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
9354 #define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
9355 #define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
9356 #define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
9357 
9358 #define RCC_PLLCFGR_PLLP_Pos               (16U)
9359 #define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
9360 #define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk
9361 #define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
9362 #define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
9363 
9364 #define RCC_PLLCFGR_PLLSRC_Pos             (22U)
9365 #define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
9366 #define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk
9367 #define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)
9368 #define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
9369 #define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk
9370 #define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U
9371 
9372 #define RCC_PLLCFGR_PLLQ_Pos               (24U)
9373 #define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
9374 #define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk
9375 #define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
9376 #define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
9377 #define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
9378 #define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
9379 
9380 /********************  Bit definition for RCC_CFGR register  ******************/
9381 /*!< SW configuration */
9382 #define RCC_CFGR_SW_Pos                    (0U)
9383 #define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
9384 #define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
9385 #define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
9386 #define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
9387 
9388 #define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
9389 #define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
9390 #define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
9391 
9392 /*!< SWS configuration */
9393 #define RCC_CFGR_SWS_Pos                   (2U)
9394 #define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
9395 #define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
9396 #define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
9397 #define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
9398 
9399 #define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock */
9400 #define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock */
9401 #define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock */
9402 
9403 /*!< HPRE configuration */
9404 #define RCC_CFGR_HPRE_Pos                  (4U)
9405 #define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
9406 #define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
9407 #define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
9408 #define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
9409 #define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
9410 #define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
9411 
9412 #define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided */
9413 #define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2 */
9414 #define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4 */
9415 #define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8 */
9416 #define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16 */
9417 #define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64 */
9418 #define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
9419 #define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
9420 #define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
9421 
9422 /*!< PPRE1 configuration */
9423 #define RCC_CFGR_PPRE1_Pos                 (10U)
9424 #define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
9425 #define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
9426 #define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
9427 #define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
9428 #define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
9429 
9430 #define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided */
9431 #define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2 */
9432 #define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4 */
9433 #define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8 */
9434 #define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
9435 
9436 /*!< PPRE2 configuration */
9437 #define RCC_CFGR_PPRE2_Pos                 (13U)
9438 #define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
9439 #define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
9440 #define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
9441 #define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
9442 #define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
9443 
9444 #define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided */
9445 #define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2 */
9446 #define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4 */
9447 #define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8 */
9448 #define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
9449 
9450 /*!< RTCPRE configuration */
9451 #define RCC_CFGR_RTCPRE_Pos                (16U)
9452 #define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
9453 #define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk
9454 #define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
9455 #define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
9456 #define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
9457 #define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
9458 #define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
9459 
9460 /*!< MCO1 configuration */
9461 #define RCC_CFGR_MCO1_Pos                  (21U)
9462 #define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
9463 #define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk
9464 #define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
9465 #define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
9466 
9467 #define RCC_CFGR_I2SSRC_Pos                (23U)
9468 #define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
9469 #define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk
9470 
9471 #define RCC_CFGR_MCO1PRE_Pos               (24U)
9472 #define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
9473 #define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk
9474 #define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
9475 #define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
9476 #define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
9477 
9478 #define RCC_CFGR_MCO2PRE_Pos               (27U)
9479 #define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
9480 #define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk
9481 #define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
9482 #define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
9483 #define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
9484 
9485 #define RCC_CFGR_MCO2_Pos                  (30U)
9486 #define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
9487 #define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk
9488 #define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
9489 #define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
9490 
9491 /********************  Bit definition for RCC_CIR register  *******************/
9492 #define RCC_CIR_LSIRDYF_Pos                (0U)
9493 #define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
9494 #define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk
9495 #define RCC_CIR_LSERDYF_Pos                (1U)
9496 #define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
9497 #define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk
9498 #define RCC_CIR_HSIRDYF_Pos                (2U)
9499 #define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
9500 #define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk
9501 #define RCC_CIR_HSERDYF_Pos                (3U)
9502 #define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
9503 #define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk
9504 #define RCC_CIR_PLLRDYF_Pos                (4U)
9505 #define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
9506 #define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk
9507 #define RCC_CIR_PLLI2SRDYF_Pos             (5U)
9508 #define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
9509 #define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk
9510 
9511 #define RCC_CIR_CSSF_Pos                   (7U)
9512 #define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
9513 #define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk
9514 #define RCC_CIR_LSIRDYIE_Pos               (8U)
9515 #define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
9516 #define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk
9517 #define RCC_CIR_LSERDYIE_Pos               (9U)
9518 #define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
9519 #define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk
9520 #define RCC_CIR_HSIRDYIE_Pos               (10U)
9521 #define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
9522 #define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk
9523 #define RCC_CIR_HSERDYIE_Pos               (11U)
9524 #define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
9525 #define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk
9526 #define RCC_CIR_PLLRDYIE_Pos               (12U)
9527 #define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
9528 #define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk
9529 #define RCC_CIR_PLLI2SRDYIE_Pos            (13U)
9530 #define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
9531 #define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk
9532 
9533 #define RCC_CIR_LSIRDYC_Pos                (16U)
9534 #define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
9535 #define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk
9536 #define RCC_CIR_LSERDYC_Pos                (17U)
9537 #define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
9538 #define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk
9539 #define RCC_CIR_HSIRDYC_Pos                (18U)
9540 #define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
9541 #define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk
9542 #define RCC_CIR_HSERDYC_Pos                (19U)
9543 #define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
9544 #define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk
9545 #define RCC_CIR_PLLRDYC_Pos                (20U)
9546 #define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
9547 #define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk
9548 #define RCC_CIR_PLLI2SRDYC_Pos             (21U)
9549 #define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
9550 #define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk
9551 
9552 #define RCC_CIR_CSSC_Pos                   (23U)
9553 #define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
9554 #define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk
9555 
9556 /********************  Bit definition for RCC_AHB1RSTR register  **************/
9557 #define RCC_AHB1RSTR_GPIOARST_Pos          (0U)
9558 #define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
9559 #define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk
9560 #define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)
9561 #define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
9562 #define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk
9563 #define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)
9564 #define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
9565 #define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk
9566 #define RCC_AHB1RSTR_GPIODRST_Pos          (3U)
9567 #define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
9568 #define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk
9569 #define RCC_AHB1RSTR_GPIOERST_Pos          (4U)
9570 #define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
9571 #define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk
9572 #define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)
9573 #define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
9574 #define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk
9575 #define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)
9576 #define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
9577 #define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk
9578 #define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)
9579 #define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
9580 #define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk
9581 #define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)
9582 #define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
9583 #define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk
9584 #define RCC_AHB1RSTR_CRCRST_Pos            (12U)
9585 #define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
9586 #define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk
9587 #define RCC_AHB1RSTR_DMA1RST_Pos           (21U)
9588 #define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
9589 #define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk
9590 #define RCC_AHB1RSTR_DMA2RST_Pos           (22U)
9591 #define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
9592 #define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk
9593 #define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)
9594 #define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
9595 #define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk
9596 #define RCC_AHB1RSTR_OTGHRST_Pos           (29U)
9597 #define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
9598 #define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk
9599 
9600 /********************  Bit definition for RCC_AHB2RSTR register  **************/
9601 #define RCC_AHB2RSTR_DCMIRST_Pos           (0U)
9602 #define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
9603 #define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk
9604 #define RCC_AHB2RSTR_CRYPRST_Pos           (4U)
9605 #define RCC_AHB2RSTR_CRYPRST_Msk           (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)  /*!< 0x00000010 */
9606 #define RCC_AHB2RSTR_CRYPRST               RCC_AHB2RSTR_CRYPRST_Msk
9607 #define RCC_AHB2RSTR_HASHRST_Pos           (5U)
9608 #define RCC_AHB2RSTR_HASHRST_Msk           (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)  /*!< 0x00000020 */
9609 #define RCC_AHB2RSTR_HASHRST               RCC_AHB2RSTR_HASHRST_Msk
9610 /* maintained for legacy purpose */
9611 #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST
9612 #define RCC_AHB2RSTR_RNGRST_Pos            (6U)
9613 #define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
9614 #define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk
9615 #define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)
9616 #define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
9617 #define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk
9618 
9619 /********************  Bit definition for RCC_AHB3RSTR register  **************/
9620 
9621 #define RCC_AHB3RSTR_FSMCRST_Pos           (0U)
9622 #define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */
9623 #define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk
9624 
9625 /********************  Bit definition for RCC_APB1RSTR register  **************/
9626 #define RCC_APB1RSTR_TIM2RST_Pos           (0U)
9627 #define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
9628 #define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk
9629 #define RCC_APB1RSTR_TIM3RST_Pos           (1U)
9630 #define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
9631 #define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk
9632 #define RCC_APB1RSTR_TIM4RST_Pos           (2U)
9633 #define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
9634 #define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk
9635 #define RCC_APB1RSTR_TIM5RST_Pos           (3U)
9636 #define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
9637 #define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk
9638 #define RCC_APB1RSTR_TIM6RST_Pos           (4U)
9639 #define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
9640 #define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk
9641 #define RCC_APB1RSTR_TIM7RST_Pos           (5U)
9642 #define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
9643 #define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk
9644 #define RCC_APB1RSTR_TIM12RST_Pos          (6U)
9645 #define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
9646 #define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk
9647 #define RCC_APB1RSTR_TIM13RST_Pos          (7U)
9648 #define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
9649 #define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk
9650 #define RCC_APB1RSTR_TIM14RST_Pos          (8U)
9651 #define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
9652 #define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk
9653 #define RCC_APB1RSTR_WWDGRST_Pos           (11U)
9654 #define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
9655 #define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk
9656 #define RCC_APB1RSTR_SPI2RST_Pos           (14U)
9657 #define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
9658 #define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk
9659 #define RCC_APB1RSTR_SPI3RST_Pos           (15U)
9660 #define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
9661 #define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk
9662 #define RCC_APB1RSTR_USART2RST_Pos         (17U)
9663 #define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
9664 #define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk
9665 #define RCC_APB1RSTR_USART3RST_Pos         (18U)
9666 #define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
9667 #define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk
9668 #define RCC_APB1RSTR_UART4RST_Pos          (19U)
9669 #define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
9670 #define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk
9671 #define RCC_APB1RSTR_UART5RST_Pos          (20U)
9672 #define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
9673 #define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk
9674 #define RCC_APB1RSTR_I2C1RST_Pos           (21U)
9675 #define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
9676 #define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk
9677 #define RCC_APB1RSTR_I2C2RST_Pos           (22U)
9678 #define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
9679 #define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk
9680 #define RCC_APB1RSTR_I2C3RST_Pos           (23U)
9681 #define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
9682 #define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk
9683 #define RCC_APB1RSTR_CAN1RST_Pos           (25U)
9684 #define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
9685 #define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk
9686 #define RCC_APB1RSTR_CAN2RST_Pos           (26U)
9687 #define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
9688 #define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk
9689 #define RCC_APB1RSTR_PWRRST_Pos            (28U)
9690 #define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
9691 #define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk
9692 #define RCC_APB1RSTR_DACRST_Pos            (29U)
9693 #define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
9694 #define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk
9695 
9696 /********************  Bit definition for RCC_APB2RSTR register  **************/
9697 #define RCC_APB2RSTR_TIM1RST_Pos           (0U)
9698 #define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
9699 #define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk
9700 #define RCC_APB2RSTR_TIM8RST_Pos           (1U)
9701 #define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
9702 #define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk
9703 #define RCC_APB2RSTR_USART1RST_Pos         (4U)
9704 #define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
9705 #define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk
9706 #define RCC_APB2RSTR_USART6RST_Pos         (5U)
9707 #define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
9708 #define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk
9709 #define RCC_APB2RSTR_ADCRST_Pos            (8U)
9710 #define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
9711 #define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk
9712 #define RCC_APB2RSTR_SDIORST_Pos           (11U)
9713 #define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
9714 #define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk
9715 #define RCC_APB2RSTR_SPI1RST_Pos           (12U)
9716 #define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
9717 #define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk
9718 #define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)
9719 #define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
9720 #define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk
9721 #define RCC_APB2RSTR_TIM9RST_Pos           (16U)
9722 #define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
9723 #define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk
9724 #define RCC_APB2RSTR_TIM10RST_Pos          (17U)
9725 #define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
9726 #define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk
9727 #define RCC_APB2RSTR_TIM11RST_Pos          (18U)
9728 #define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
9729 #define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk
9730 
9731 /* Old SPI1RST bit definition, maintained for legacy purpose */
9732 #define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
9733 
9734 /********************  Bit definition for RCC_AHB1ENR register  ***************/
9735 #define RCC_AHB1ENR_GPIOAEN_Pos            (0U)
9736 #define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
9737 #define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk
9738 #define RCC_AHB1ENR_GPIOBEN_Pos            (1U)
9739 #define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
9740 #define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk
9741 #define RCC_AHB1ENR_GPIOCEN_Pos            (2U)
9742 #define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
9743 #define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk
9744 #define RCC_AHB1ENR_GPIODEN_Pos            (3U)
9745 #define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
9746 #define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk
9747 #define RCC_AHB1ENR_GPIOEEN_Pos            (4U)
9748 #define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
9749 #define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk
9750 #define RCC_AHB1ENR_GPIOFEN_Pos            (5U)
9751 #define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
9752 #define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk
9753 #define RCC_AHB1ENR_GPIOGEN_Pos            (6U)
9754 #define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
9755 #define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk
9756 #define RCC_AHB1ENR_GPIOHEN_Pos            (7U)
9757 #define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
9758 #define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk
9759 #define RCC_AHB1ENR_GPIOIEN_Pos            (8U)
9760 #define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
9761 #define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk
9762 #define RCC_AHB1ENR_CRCEN_Pos              (12U)
9763 #define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
9764 #define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk
9765 #define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)
9766 #define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
9767 #define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk
9768 #define RCC_AHB1ENR_DMA1EN_Pos             (21U)
9769 #define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
9770 #define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk
9771 #define RCC_AHB1ENR_DMA2EN_Pos             (22U)
9772 #define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
9773 #define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk
9774 
9775 #define RCC_AHB1ENR_ETHMACEN_Pos           (25U)
9776 #define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
9777 #define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk
9778 #define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)
9779 #define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
9780 #define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk
9781 #define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)
9782 #define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
9783 #define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk
9784 #define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)
9785 #define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
9786 #define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk
9787 #define RCC_AHB1ENR_OTGHSEN_Pos            (29U)
9788 #define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
9789 #define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk
9790 #define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)
9791 #define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
9792 #define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk
9793 
9794 /********************  Bit definition for RCC_AHB2ENR register  ***************/
9795 #define RCC_AHB2ENR_DCMIEN_Pos             (0U)
9796 #define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
9797 #define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk
9798 #define RCC_AHB2ENR_CRYPEN_Pos             (4U)
9799 #define RCC_AHB2ENR_CRYPEN_Msk             (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)    /*!< 0x00000010 */
9800 #define RCC_AHB2ENR_CRYPEN                 RCC_AHB2ENR_CRYPEN_Msk
9801 #define RCC_AHB2ENR_HASHEN_Pos             (5U)
9802 #define RCC_AHB2ENR_HASHEN_Msk             (0x1UL << RCC_AHB2ENR_HASHEN_Pos)    /*!< 0x00000020 */
9803 #define RCC_AHB2ENR_HASHEN                 RCC_AHB2ENR_HASHEN_Msk
9804 #define RCC_AHB2ENR_RNGEN_Pos              (6U)
9805 #define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
9806 #define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk
9807 #define RCC_AHB2ENR_OTGFSEN_Pos            (7U)
9808 #define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
9809 #define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk
9810 
9811 /********************  Bit definition for RCC_AHB3ENR register  ***************/
9812 
9813 #define RCC_AHB3ENR_FSMCEN_Pos             (0U)
9814 #define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */
9815 #define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk
9816 
9817 /********************  Bit definition for RCC_APB1ENR register  ***************/
9818 #define RCC_APB1ENR_TIM2EN_Pos             (0U)
9819 #define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
9820 #define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk
9821 #define RCC_APB1ENR_TIM3EN_Pos             (1U)
9822 #define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
9823 #define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk
9824 #define RCC_APB1ENR_TIM4EN_Pos             (2U)
9825 #define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
9826 #define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk
9827 #define RCC_APB1ENR_TIM5EN_Pos             (3U)
9828 #define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
9829 #define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk
9830 #define RCC_APB1ENR_TIM6EN_Pos             (4U)
9831 #define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
9832 #define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk
9833 #define RCC_APB1ENR_TIM7EN_Pos             (5U)
9834 #define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
9835 #define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk
9836 #define RCC_APB1ENR_TIM12EN_Pos            (6U)
9837 #define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
9838 #define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk
9839 #define RCC_APB1ENR_TIM13EN_Pos            (7U)
9840 #define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
9841 #define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk
9842 #define RCC_APB1ENR_TIM14EN_Pos            (8U)
9843 #define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
9844 #define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk
9845 #define RCC_APB1ENR_WWDGEN_Pos             (11U)
9846 #define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
9847 #define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk
9848 #define RCC_APB1ENR_SPI2EN_Pos             (14U)
9849 #define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
9850 #define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk
9851 #define RCC_APB1ENR_SPI3EN_Pos             (15U)
9852 #define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
9853 #define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk
9854 #define RCC_APB1ENR_USART2EN_Pos           (17U)
9855 #define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
9856 #define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk
9857 #define RCC_APB1ENR_USART3EN_Pos           (18U)
9858 #define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
9859 #define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk
9860 #define RCC_APB1ENR_UART4EN_Pos            (19U)
9861 #define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
9862 #define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk
9863 #define RCC_APB1ENR_UART5EN_Pos            (20U)
9864 #define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
9865 #define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk
9866 #define RCC_APB1ENR_I2C1EN_Pos             (21U)
9867 #define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
9868 #define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk
9869 #define RCC_APB1ENR_I2C2EN_Pos             (22U)
9870 #define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
9871 #define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk
9872 #define RCC_APB1ENR_I2C3EN_Pos             (23U)
9873 #define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
9874 #define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk
9875 #define RCC_APB1ENR_CAN1EN_Pos             (25U)
9876 #define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
9877 #define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk
9878 #define RCC_APB1ENR_CAN2EN_Pos             (26U)
9879 #define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
9880 #define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk
9881 #define RCC_APB1ENR_PWREN_Pos              (28U)
9882 #define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
9883 #define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk
9884 #define RCC_APB1ENR_DACEN_Pos              (29U)
9885 #define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
9886 #define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk
9887 
9888 /********************  Bit definition for RCC_APB2ENR register  ***************/
9889 #define RCC_APB2ENR_TIM1EN_Pos             (0U)
9890 #define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
9891 #define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk
9892 #define RCC_APB2ENR_TIM8EN_Pos             (1U)
9893 #define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
9894 #define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk
9895 #define RCC_APB2ENR_USART1EN_Pos           (4U)
9896 #define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
9897 #define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk
9898 #define RCC_APB2ENR_USART6EN_Pos           (5U)
9899 #define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
9900 #define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk
9901 #define RCC_APB2ENR_ADC1EN_Pos             (8U)
9902 #define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
9903 #define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk
9904 #define RCC_APB2ENR_ADC2EN_Pos             (9U)
9905 #define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
9906 #define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk
9907 #define RCC_APB2ENR_ADC3EN_Pos             (10U)
9908 #define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
9909 #define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk
9910 #define RCC_APB2ENR_SDIOEN_Pos             (11U)
9911 #define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
9912 #define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk
9913 #define RCC_APB2ENR_SPI1EN_Pos             (12U)
9914 #define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
9915 #define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk
9916 #define RCC_APB2ENR_SYSCFGEN_Pos           (14U)
9917 #define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
9918 #define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk
9919 #define RCC_APB2ENR_TIM9EN_Pos             (16U)
9920 #define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
9921 #define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk
9922 #define RCC_APB2ENR_TIM10EN_Pos            (17U)
9923 #define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
9924 #define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk
9925 #define RCC_APB2ENR_TIM11EN_Pos            (18U)
9926 #define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
9927 #define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk
9928 
9929 /********************  Bit definition for RCC_AHB1LPENR register  *************/
9930 #define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)
9931 #define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
9932 #define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk
9933 #define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)
9934 #define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
9935 #define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk
9936 #define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)
9937 #define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
9938 #define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk
9939 #define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)
9940 #define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
9941 #define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk
9942 #define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)
9943 #define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
9944 #define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk
9945 #define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)
9946 #define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
9947 #define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk
9948 #define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)
9949 #define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
9950 #define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk
9951 #define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)
9952 #define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
9953 #define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk
9954 #define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)
9955 #define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
9956 #define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk
9957 #define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)
9958 #define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
9959 #define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk
9960 #define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)
9961 #define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
9962 #define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk
9963 #define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)
9964 #define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
9965 #define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk
9966 #define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)
9967 #define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
9968 #define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk
9969 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)
9970 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
9971 #define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk
9972 #define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)
9973 #define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
9974 #define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk
9975 #define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)
9976 #define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
9977 #define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk
9978 #define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)
9979 #define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
9980 #define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk
9981 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)
9982 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
9983 #define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk
9984 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)
9985 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
9986 #define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk
9987 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)
9988 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
9989 #define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
9990 #define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)
9991 #define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
9992 #define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk
9993 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)
9994 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
9995 #define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk
9996 
9997 /********************  Bit definition for RCC_AHB2LPENR register  *************/
9998 #define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)
9999 #define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
10000 #define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk
10001 #define RCC_AHB2LPENR_CRYPLPEN_Pos         (4U)
10002 #define RCC_AHB2LPENR_CRYPLPEN_Msk         (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
10003 #define RCC_AHB2LPENR_CRYPLPEN             RCC_AHB2LPENR_CRYPLPEN_Msk
10004 #define RCC_AHB2LPENR_HASHLPEN_Pos         (5U)
10005 #define RCC_AHB2LPENR_HASHLPEN_Msk         (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
10006 #define RCC_AHB2LPENR_HASHLPEN             RCC_AHB2LPENR_HASHLPEN_Msk
10007 #define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)
10008 #define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
10009 #define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk
10010 #define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)
10011 #define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
10012 #define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk
10013 
10014 /********************  Bit definition for RCC_AHB3LPENR register  *************/
10015 
10016 #define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)
10017 #define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
10018 #define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk
10019 
10020 /********************  Bit definition for RCC_APB1LPENR register  *************/
10021 #define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)
10022 #define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
10023 #define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk
10024 #define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)
10025 #define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
10026 #define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk
10027 #define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)
10028 #define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
10029 #define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk
10030 #define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)
10031 #define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
10032 #define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk
10033 #define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)
10034 #define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
10035 #define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk
10036 #define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)
10037 #define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
10038 #define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk
10039 #define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)
10040 #define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
10041 #define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk
10042 #define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)
10043 #define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
10044 #define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk
10045 #define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)
10046 #define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
10047 #define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk
10048 #define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)
10049 #define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
10050 #define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk
10051 #define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)
10052 #define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
10053 #define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk
10054 #define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)
10055 #define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
10056 #define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk
10057 #define RCC_APB1LPENR_USART2LPEN_Pos       (17U)
10058 #define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
10059 #define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk
10060 #define RCC_APB1LPENR_USART3LPEN_Pos       (18U)
10061 #define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
10062 #define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk
10063 #define RCC_APB1LPENR_UART4LPEN_Pos        (19U)
10064 #define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
10065 #define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk
10066 #define RCC_APB1LPENR_UART5LPEN_Pos        (20U)
10067 #define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
10068 #define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk
10069 #define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)
10070 #define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
10071 #define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk
10072 #define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)
10073 #define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
10074 #define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk
10075 #define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)
10076 #define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
10077 #define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk
10078 #define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)
10079 #define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
10080 #define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk
10081 #define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)
10082 #define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
10083 #define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk
10084 #define RCC_APB1LPENR_PWRLPEN_Pos          (28U)
10085 #define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
10086 #define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk
10087 #define RCC_APB1LPENR_DACLPEN_Pos          (29U)
10088 #define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
10089 #define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk
10090 
10091 /********************  Bit definition for RCC_APB2LPENR register  *************/
10092 #define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)
10093 #define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
10094 #define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk
10095 #define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)
10096 #define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
10097 #define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk
10098 #define RCC_APB2LPENR_USART1LPEN_Pos       (4U)
10099 #define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
10100 #define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk
10101 #define RCC_APB2LPENR_USART6LPEN_Pos       (5U)
10102 #define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
10103 #define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk
10104 #define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)
10105 #define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
10106 #define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk
10107 #define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)
10108 #define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
10109 #define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk
10110 #define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)
10111 #define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
10112 #define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk
10113 #define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)
10114 #define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
10115 #define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk
10116 #define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)
10117 #define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
10118 #define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk
10119 #define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)
10120 #define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
10121 #define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk
10122 #define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)
10123 #define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
10124 #define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk
10125 #define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)
10126 #define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
10127 #define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk
10128 #define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)
10129 #define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
10130 #define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk
10131 
10132 /********************  Bit definition for RCC_BDCR register  ******************/
10133 #define RCC_BDCR_LSEON_Pos                 (0U)
10134 #define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
10135 #define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk
10136 #define RCC_BDCR_LSERDY_Pos                (1U)
10137 #define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
10138 #define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk
10139 #define RCC_BDCR_LSEBYP_Pos                (2U)
10140 #define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
10141 #define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk
10142 
10143 #define RCC_BDCR_RTCSEL_Pos                (8U)
10144 #define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
10145 #define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk
10146 #define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
10147 #define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
10148 
10149 #define RCC_BDCR_RTCEN_Pos                 (15U)
10150 #define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
10151 #define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk
10152 #define RCC_BDCR_BDRST_Pos                 (16U)
10153 #define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
10154 #define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk
10155 
10156 /********************  Bit definition for RCC_CSR register  *******************/
10157 #define RCC_CSR_LSION_Pos                  (0U)
10158 #define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
10159 #define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
10160 #define RCC_CSR_LSIRDY_Pos                 (1U)
10161 #define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
10162 #define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
10163 #define RCC_CSR_RMVF_Pos                   (24U)
10164 #define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
10165 #define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk
10166 #define RCC_CSR_BORRSTF_Pos                (25U)
10167 #define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
10168 #define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk
10169 #define RCC_CSR_PINRSTF_Pos                (26U)
10170 #define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
10171 #define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
10172 #define RCC_CSR_PORRSTF_Pos                (27U)
10173 #define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
10174 #define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk
10175 #define RCC_CSR_SFTRSTF_Pos                (28U)
10176 #define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
10177 #define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk
10178 #define RCC_CSR_IWDGRSTF_Pos               (29U)
10179 #define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
10180 #define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
10181 #define RCC_CSR_WWDGRSTF_Pos               (30U)
10182 #define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
10183 #define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk
10184 #define RCC_CSR_LPWRRSTF_Pos               (31U)
10185 #define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
10186 #define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
10187 /* Legacy defines */
10188 #define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
10189 #define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
10190 
10191 /********************  Bit definition for RCC_SSCGR register  *****************/
10192 #define RCC_SSCGR_MODPER_Pos               (0U)
10193 #define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
10194 #define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk
10195 #define RCC_SSCGR_INCSTEP_Pos              (13U)
10196 #define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
10197 #define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk
10198 #define RCC_SSCGR_SPREADSEL_Pos            (30U)
10199 #define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
10200 #define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk
10201 #define RCC_SSCGR_SSCGEN_Pos               (31U)
10202 #define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
10203 #define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk
10204 
10205 /********************  Bit definition for RCC_PLLI2SCFGR register  ************/
10206 #define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)
10207 #define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
10208 #define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk
10209 #define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
10210 #define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
10211 #define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
10212 #define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
10213 #define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
10214 #define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
10215 #define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
10216 #define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
10217 #define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
10218 
10219 #define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)
10220 #define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
10221 #define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk
10222 #define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
10223 #define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
10224 #define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
10225 
10226 /******************************************************************************/
10227 /*                                                                            */
10228 /*                                    RNG                                     */
10229 /*                                                                            */
10230 /******************************************************************************/
10231 /********************  Bits definition for RNG_CR register  *******************/
10232 #define RNG_CR_RNGEN_Pos    (2U)
10233 #define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
10234 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
10235 #define RNG_CR_IE_Pos       (3U)
10236 #define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
10237 #define RNG_CR_IE           RNG_CR_IE_Msk
10238 
10239 /********************  Bits definition for RNG_SR register  *******************/
10240 #define RNG_SR_DRDY_Pos     (0U)
10241 #define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
10242 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
10243 #define RNG_SR_CECS_Pos     (1U)
10244 #define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
10245 #define RNG_SR_CECS         RNG_SR_CECS_Msk
10246 #define RNG_SR_SECS_Pos     (2U)
10247 #define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
10248 #define RNG_SR_SECS         RNG_SR_SECS_Msk
10249 #define RNG_SR_CEIS_Pos     (5U)
10250 #define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
10251 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
10252 #define RNG_SR_SEIS_Pos     (6U)
10253 #define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
10254 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
10255 
10256 /******************************************************************************/
10257 /*                                                                            */
10258 /*                           Real-Time Clock (RTC)                            */
10259 /*                                                                            */
10260 /******************************************************************************/
10261 /********************  Bits definition for RTC_TR register  *******************/
10262 #define RTC_TR_PM_Pos                 (22U)
10263 #define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
10264 #define RTC_TR_PM                     RTC_TR_PM_Msk
10265 #define RTC_TR_HT_Pos                 (20U)
10266 #define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
10267 #define RTC_TR_HT                     RTC_TR_HT_Msk
10268 #define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
10269 #define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
10270 #define RTC_TR_HU_Pos                 (16U)
10271 #define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
10272 #define RTC_TR_HU                     RTC_TR_HU_Msk
10273 #define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
10274 #define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
10275 #define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
10276 #define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
10277 #define RTC_TR_MNT_Pos                (12U)
10278 #define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
10279 #define RTC_TR_MNT                    RTC_TR_MNT_Msk
10280 #define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
10281 #define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
10282 #define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
10283 #define RTC_TR_MNU_Pos                (8U)
10284 #define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
10285 #define RTC_TR_MNU                    RTC_TR_MNU_Msk
10286 #define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
10287 #define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
10288 #define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
10289 #define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
10290 #define RTC_TR_ST_Pos                 (4U)
10291 #define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
10292 #define RTC_TR_ST                     RTC_TR_ST_Msk
10293 #define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
10294 #define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
10295 #define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
10296 #define RTC_TR_SU_Pos                 (0U)
10297 #define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
10298 #define RTC_TR_SU                     RTC_TR_SU_Msk
10299 #define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
10300 #define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
10301 #define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
10302 #define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
10303 
10304 /********************  Bits definition for RTC_DR register  *******************/
10305 #define RTC_DR_YT_Pos                 (20U)
10306 #define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
10307 #define RTC_DR_YT                     RTC_DR_YT_Msk
10308 #define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
10309 #define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
10310 #define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
10311 #define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
10312 #define RTC_DR_YU_Pos                 (16U)
10313 #define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
10314 #define RTC_DR_YU                     RTC_DR_YU_Msk
10315 #define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
10316 #define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
10317 #define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
10318 #define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
10319 #define RTC_DR_WDU_Pos                (13U)
10320 #define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
10321 #define RTC_DR_WDU                    RTC_DR_WDU_Msk
10322 #define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
10323 #define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
10324 #define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
10325 #define RTC_DR_MT_Pos                 (12U)
10326 #define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
10327 #define RTC_DR_MT                     RTC_DR_MT_Msk
10328 #define RTC_DR_MU_Pos                 (8U)
10329 #define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
10330 #define RTC_DR_MU                     RTC_DR_MU_Msk
10331 #define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
10332 #define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
10333 #define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
10334 #define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
10335 #define RTC_DR_DT_Pos                 (4U)
10336 #define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
10337 #define RTC_DR_DT                     RTC_DR_DT_Msk
10338 #define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
10339 #define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
10340 #define RTC_DR_DU_Pos                 (0U)
10341 #define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
10342 #define RTC_DR_DU                     RTC_DR_DU_Msk
10343 #define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
10344 #define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
10345 #define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
10346 #define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
10347 
10348 /********************  Bits definition for RTC_CR register  *******************/
10349 #define RTC_CR_COE_Pos                (23U)
10350 #define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
10351 #define RTC_CR_COE                    RTC_CR_COE_Msk
10352 #define RTC_CR_OSEL_Pos               (21U)
10353 #define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
10354 #define RTC_CR_OSEL                   RTC_CR_OSEL_Msk
10355 #define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
10356 #define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
10357 #define RTC_CR_POL_Pos                (20U)
10358 #define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
10359 #define RTC_CR_POL                    RTC_CR_POL_Msk
10360 #define RTC_CR_BKP_Pos                 (18U)
10361 #define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
10362 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
10363 #define RTC_CR_SUB1H_Pos              (17U)
10364 #define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
10365 #define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk
10366 #define RTC_CR_ADD1H_Pos              (16U)
10367 #define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
10368 #define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk
10369 #define RTC_CR_TSIE_Pos               (15U)
10370 #define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
10371 #define RTC_CR_TSIE                   RTC_CR_TSIE_Msk
10372 #define RTC_CR_WUTIE_Pos              (14U)
10373 #define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
10374 #define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk
10375 #define RTC_CR_ALRBIE_Pos             (13U)
10376 #define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
10377 #define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk
10378 #define RTC_CR_ALRAIE_Pos             (12U)
10379 #define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
10380 #define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk
10381 #define RTC_CR_TSE_Pos                (11U)
10382 #define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
10383 #define RTC_CR_TSE                    RTC_CR_TSE_Msk
10384 #define RTC_CR_WUTE_Pos               (10U)
10385 #define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
10386 #define RTC_CR_WUTE                   RTC_CR_WUTE_Msk
10387 #define RTC_CR_ALRBE_Pos              (9U)
10388 #define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
10389 #define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk
10390 #define RTC_CR_ALRAE_Pos              (8U)
10391 #define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
10392 #define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk
10393 #define RTC_CR_DCE_Pos                (7U)
10394 #define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
10395 #define RTC_CR_DCE                    RTC_CR_DCE_Msk
10396 #define RTC_CR_FMT_Pos                (6U)
10397 #define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
10398 #define RTC_CR_FMT                    RTC_CR_FMT_Msk
10399 #define RTC_CR_REFCKON_Pos            (4U)
10400 #define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
10401 #define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk
10402 #define RTC_CR_TSEDGE_Pos             (3U)
10403 #define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
10404 #define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk
10405 #define RTC_CR_WUCKSEL_Pos            (0U)
10406 #define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
10407 #define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk
10408 #define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
10409 #define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
10410 #define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
10411 
10412 /* Legacy defines */
10413 #define RTC_CR_BCK                     RTC_CR_BKP
10414 
10415 /********************  Bits definition for RTC_ISR register  ******************/
10416 #define RTC_ISR_TAMP1F_Pos            (13U)
10417 #define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
10418 #define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk
10419 #define RTC_ISR_TSOVF_Pos             (12U)
10420 #define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
10421 #define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk
10422 #define RTC_ISR_TSF_Pos               (11U)
10423 #define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
10424 #define RTC_ISR_TSF                   RTC_ISR_TSF_Msk
10425 #define RTC_ISR_WUTF_Pos              (10U)
10426 #define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
10427 #define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk
10428 #define RTC_ISR_ALRBF_Pos             (9U)
10429 #define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
10430 #define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk
10431 #define RTC_ISR_ALRAF_Pos             (8U)
10432 #define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
10433 #define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk
10434 #define RTC_ISR_INIT_Pos              (7U)
10435 #define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
10436 #define RTC_ISR_INIT                  RTC_ISR_INIT_Msk
10437 #define RTC_ISR_INITF_Pos             (6U)
10438 #define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
10439 #define RTC_ISR_INITF                 RTC_ISR_INITF_Msk
10440 #define RTC_ISR_RSF_Pos               (5U)
10441 #define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
10442 #define RTC_ISR_RSF                   RTC_ISR_RSF_Msk
10443 #define RTC_ISR_INITS_Pos             (4U)
10444 #define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
10445 #define RTC_ISR_INITS                 RTC_ISR_INITS_Msk
10446 #define RTC_ISR_WUTWF_Pos             (2U)
10447 #define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
10448 #define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk
10449 #define RTC_ISR_ALRBWF_Pos            (1U)
10450 #define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
10451 #define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk
10452 #define RTC_ISR_ALRAWF_Pos            (0U)
10453 #define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
10454 #define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk
10455 
10456 /********************  Bits definition for RTC_PRER register  *****************/
10457 #define RTC_PRER_PREDIV_A_Pos         (16U)
10458 #define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
10459 #define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk
10460 #define RTC_PRER_PREDIV_S_Pos         (0U)
10461 #define RTC_PRER_PREDIV_S_Msk         (0x1FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00001FFF */
10462 #define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk
10463 
10464 /********************  Bits definition for RTC_WUTR register  *****************/
10465 #define RTC_WUTR_WUT_Pos              (0U)
10466 #define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
10467 #define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk
10468 
10469 /********************  Bits definition for RTC_CALIBR register  ***************/
10470 #define RTC_CALIBR_DCS_Pos            (7U)
10471 #define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
10472 #define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk
10473 #define RTC_CALIBR_DC_Pos             (0U)
10474 #define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
10475 #define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk
10476 
10477 /********************  Bits definition for RTC_ALRMAR register  ***************/
10478 #define RTC_ALRMAR_MSK4_Pos           (31U)
10479 #define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
10480 #define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk
10481 #define RTC_ALRMAR_WDSEL_Pos          (30U)
10482 #define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
10483 #define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk
10484 #define RTC_ALRMAR_DT_Pos             (28U)
10485 #define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
10486 #define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk
10487 #define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
10488 #define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
10489 #define RTC_ALRMAR_DU_Pos             (24U)
10490 #define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
10491 #define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk
10492 #define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
10493 #define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
10494 #define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
10495 #define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
10496 #define RTC_ALRMAR_MSK3_Pos           (23U)
10497 #define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
10498 #define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk
10499 #define RTC_ALRMAR_PM_Pos             (22U)
10500 #define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
10501 #define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk
10502 #define RTC_ALRMAR_HT_Pos             (20U)
10503 #define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
10504 #define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk
10505 #define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
10506 #define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
10507 #define RTC_ALRMAR_HU_Pos             (16U)
10508 #define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
10509 #define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk
10510 #define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
10511 #define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
10512 #define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
10513 #define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
10514 #define RTC_ALRMAR_MSK2_Pos           (15U)
10515 #define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
10516 #define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk
10517 #define RTC_ALRMAR_MNT_Pos            (12U)
10518 #define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
10519 #define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk
10520 #define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
10521 #define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
10522 #define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
10523 #define RTC_ALRMAR_MNU_Pos            (8U)
10524 #define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
10525 #define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk
10526 #define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
10527 #define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
10528 #define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
10529 #define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
10530 #define RTC_ALRMAR_MSK1_Pos           (7U)
10531 #define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
10532 #define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk
10533 #define RTC_ALRMAR_ST_Pos             (4U)
10534 #define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
10535 #define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk
10536 #define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
10537 #define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
10538 #define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
10539 #define RTC_ALRMAR_SU_Pos             (0U)
10540 #define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
10541 #define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk
10542 #define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
10543 #define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
10544 #define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
10545 #define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
10546 
10547 /********************  Bits definition for RTC_ALRMBR register  ***************/
10548 #define RTC_ALRMBR_MSK4_Pos           (31U)
10549 #define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
10550 #define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk
10551 #define RTC_ALRMBR_WDSEL_Pos          (30U)
10552 #define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
10553 #define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk
10554 #define RTC_ALRMBR_DT_Pos             (28U)
10555 #define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
10556 #define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk
10557 #define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
10558 #define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
10559 #define RTC_ALRMBR_DU_Pos             (24U)
10560 #define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
10561 #define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk
10562 #define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
10563 #define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
10564 #define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
10565 #define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
10566 #define RTC_ALRMBR_MSK3_Pos           (23U)
10567 #define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
10568 #define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk
10569 #define RTC_ALRMBR_PM_Pos             (22U)
10570 #define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
10571 #define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk
10572 #define RTC_ALRMBR_HT_Pos             (20U)
10573 #define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
10574 #define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk
10575 #define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
10576 #define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
10577 #define RTC_ALRMBR_HU_Pos             (16U)
10578 #define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
10579 #define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk
10580 #define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
10581 #define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
10582 #define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
10583 #define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
10584 #define RTC_ALRMBR_MSK2_Pos           (15U)
10585 #define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
10586 #define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk
10587 #define RTC_ALRMBR_MNT_Pos            (12U)
10588 #define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
10589 #define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk
10590 #define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
10591 #define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
10592 #define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
10593 #define RTC_ALRMBR_MNU_Pos            (8U)
10594 #define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
10595 #define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk
10596 #define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
10597 #define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
10598 #define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
10599 #define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
10600 #define RTC_ALRMBR_MSK1_Pos           (7U)
10601 #define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
10602 #define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk
10603 #define RTC_ALRMBR_ST_Pos             (4U)
10604 #define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
10605 #define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk
10606 #define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
10607 #define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
10608 #define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
10609 #define RTC_ALRMBR_SU_Pos             (0U)
10610 #define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
10611 #define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk
10612 #define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
10613 #define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
10614 #define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
10615 #define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
10616 
10617 /********************  Bits definition for RTC_WPR register  ******************/
10618 #define RTC_WPR_KEY_Pos               (0U)
10619 #define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
10620 #define RTC_WPR_KEY                   RTC_WPR_KEY_Msk
10621 
10622 /********************  Bits definition for RTC_TSTR register  *****************/
10623 #define RTC_TSTR_PM_Pos               (22U)
10624 #define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
10625 #define RTC_TSTR_PM                   RTC_TSTR_PM_Msk
10626 #define RTC_TSTR_HT_Pos               (20U)
10627 #define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
10628 #define RTC_TSTR_HT                   RTC_TSTR_HT_Msk
10629 #define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
10630 #define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
10631 #define RTC_TSTR_HU_Pos               (16U)
10632 #define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
10633 #define RTC_TSTR_HU                   RTC_TSTR_HU_Msk
10634 #define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
10635 #define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
10636 #define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
10637 #define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
10638 #define RTC_TSTR_MNT_Pos              (12U)
10639 #define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
10640 #define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk
10641 #define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
10642 #define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
10643 #define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
10644 #define RTC_TSTR_MNU_Pos              (8U)
10645 #define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
10646 #define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk
10647 #define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
10648 #define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
10649 #define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
10650 #define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
10651 #define RTC_TSTR_ST_Pos               (4U)
10652 #define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
10653 #define RTC_TSTR_ST                   RTC_TSTR_ST_Msk
10654 #define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
10655 #define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
10656 #define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
10657 #define RTC_TSTR_SU_Pos               (0U)
10658 #define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
10659 #define RTC_TSTR_SU                   RTC_TSTR_SU_Msk
10660 #define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
10661 #define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
10662 #define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
10663 #define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
10664 
10665 /********************  Bits definition for RTC_TSDR register  *****************/
10666 #define RTC_TSDR_WDU_Pos              (13U)
10667 #define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
10668 #define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk
10669 #define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
10670 #define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
10671 #define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
10672 #define RTC_TSDR_MT_Pos               (12U)
10673 #define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
10674 #define RTC_TSDR_MT                   RTC_TSDR_MT_Msk
10675 #define RTC_TSDR_MU_Pos               (8U)
10676 #define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
10677 #define RTC_TSDR_MU                   RTC_TSDR_MU_Msk
10678 #define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
10679 #define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
10680 #define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
10681 #define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
10682 #define RTC_TSDR_DT_Pos               (4U)
10683 #define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
10684 #define RTC_TSDR_DT                   RTC_TSDR_DT_Msk
10685 #define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
10686 #define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
10687 #define RTC_TSDR_DU_Pos               (0U)
10688 #define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
10689 #define RTC_TSDR_DU                   RTC_TSDR_DU_Msk
10690 #define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
10691 #define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
10692 #define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
10693 #define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
10694 
10695 /********************  Bits definition for RTC_TAFCR register  ****************/
10696 #define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)
10697 #define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
10698 #define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk
10699 #define RTC_TAFCR_TSINSEL_Pos         (17U)
10700 #define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
10701 #define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk
10702 #define RTC_TAFCR_TAMP1INSEL_Pos      (16U)
10703 #define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
10704 #define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk
10705 #define RTC_TAFCR_TAMPIE_Pos          (2U)
10706 #define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
10707 #define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk
10708 #define RTC_TAFCR_TAMP1TRG_Pos        (1U)
10709 #define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
10710 #define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk
10711 #define RTC_TAFCR_TAMP1E_Pos          (0U)
10712 #define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
10713 #define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk
10714 
10715 /* Legacy defines */
10716 #define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
10717 
10718 /********************  Bits definition for RTC_BKP0R register  ****************/
10719 #define RTC_BKP0R_Pos                 (0U)
10720 #define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
10721 #define RTC_BKP0R                     RTC_BKP0R_Msk
10722 
10723 /********************  Bits definition for RTC_BKP1R register  ****************/
10724 #define RTC_BKP1R_Pos                 (0U)
10725 #define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
10726 #define RTC_BKP1R                     RTC_BKP1R_Msk
10727 
10728 /********************  Bits definition for RTC_BKP2R register  ****************/
10729 #define RTC_BKP2R_Pos                 (0U)
10730 #define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
10731 #define RTC_BKP2R                     RTC_BKP2R_Msk
10732 
10733 /********************  Bits definition for RTC_BKP3R register  ****************/
10734 #define RTC_BKP3R_Pos                 (0U)
10735 #define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
10736 #define RTC_BKP3R                     RTC_BKP3R_Msk
10737 
10738 /********************  Bits definition for RTC_BKP4R register  ****************/
10739 #define RTC_BKP4R_Pos                 (0U)
10740 #define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
10741 #define RTC_BKP4R                     RTC_BKP4R_Msk
10742 
10743 /********************  Bits definition for RTC_BKP5R register  ****************/
10744 #define RTC_BKP5R_Pos                 (0U)
10745 #define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
10746 #define RTC_BKP5R                     RTC_BKP5R_Msk
10747 
10748 /********************  Bits definition for RTC_BKP6R register  ****************/
10749 #define RTC_BKP6R_Pos                 (0U)
10750 #define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
10751 #define RTC_BKP6R                     RTC_BKP6R_Msk
10752 
10753 /********************  Bits definition for RTC_BKP7R register  ****************/
10754 #define RTC_BKP7R_Pos                 (0U)
10755 #define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
10756 #define RTC_BKP7R                     RTC_BKP7R_Msk
10757 
10758 /********************  Bits definition for RTC_BKP8R register  ****************/
10759 #define RTC_BKP8R_Pos                 (0U)
10760 #define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
10761 #define RTC_BKP8R                     RTC_BKP8R_Msk
10762 
10763 /********************  Bits definition for RTC_BKP9R register  ****************/
10764 #define RTC_BKP9R_Pos                 (0U)
10765 #define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
10766 #define RTC_BKP9R                     RTC_BKP9R_Msk
10767 
10768 /********************  Bits definition for RTC_BKP10R register  ***************/
10769 #define RTC_BKP10R_Pos                (0U)
10770 #define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
10771 #define RTC_BKP10R                    RTC_BKP10R_Msk
10772 
10773 /********************  Bits definition for RTC_BKP11R register  ***************/
10774 #define RTC_BKP11R_Pos                (0U)
10775 #define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
10776 #define RTC_BKP11R                    RTC_BKP11R_Msk
10777 
10778 /********************  Bits definition for RTC_BKP12R register  ***************/
10779 #define RTC_BKP12R_Pos                (0U)
10780 #define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
10781 #define RTC_BKP12R                    RTC_BKP12R_Msk
10782 
10783 /********************  Bits definition for RTC_BKP13R register  ***************/
10784 #define RTC_BKP13R_Pos                (0U)
10785 #define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
10786 #define RTC_BKP13R                    RTC_BKP13R_Msk
10787 
10788 /********************  Bits definition for RTC_BKP14R register  ***************/
10789 #define RTC_BKP14R_Pos                (0U)
10790 #define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
10791 #define RTC_BKP14R                    RTC_BKP14R_Msk
10792 
10793 /********************  Bits definition for RTC_BKP15R register  ***************/
10794 #define RTC_BKP15R_Pos                (0U)
10795 #define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
10796 #define RTC_BKP15R                    RTC_BKP15R_Msk
10797 
10798 /********************  Bits definition for RTC_BKP16R register  ***************/
10799 #define RTC_BKP16R_Pos                (0U)
10800 #define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
10801 #define RTC_BKP16R                    RTC_BKP16R_Msk
10802 
10803 /********************  Bits definition for RTC_BKP17R register  ***************/
10804 #define RTC_BKP17R_Pos                (0U)
10805 #define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
10806 #define RTC_BKP17R                    RTC_BKP17R_Msk
10807 
10808 /********************  Bits definition for RTC_BKP18R register  ***************/
10809 #define RTC_BKP18R_Pos                (0U)
10810 #define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
10811 #define RTC_BKP18R                    RTC_BKP18R_Msk
10812 
10813 /********************  Bits definition for RTC_BKP19R register  ***************/
10814 #define RTC_BKP19R_Pos                (0U)
10815 #define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
10816 #define RTC_BKP19R                    RTC_BKP19R_Msk
10817 
10818 /******************** Number of backup registers ******************************/
10819 #define RTC_BKP_NUMBER                       0x000000014U
10820 
10821 /******************************************************************************/
10822 /*                                                                            */
10823 /*                          SD host Interface                                 */
10824 /*                                                                            */
10825 /******************************************************************************/
10826 /******************  Bit definition for SDIO_POWER register  ******************/
10827 #define SDIO_POWER_PWRCTRL_Pos         (0U)
10828 #define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
10829 #define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
10830 #define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000001 */
10831 #define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000002 */
10832 
10833 /******************  Bit definition for SDIO_CLKCR register  ******************/
10834 #define SDIO_CLKCR_CLKDIV_Pos          (0U)
10835 #define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
10836 #define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor */
10837 #define SDIO_CLKCR_CLKEN_Pos           (8U)
10838 #define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
10839 #define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit */
10840 #define SDIO_CLKCR_PWRSAV_Pos          (9U)
10841 #define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
10842 #define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit */
10843 #define SDIO_CLKCR_BYPASS_Pos          (10U)
10844 #define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
10845 #define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
10846 
10847 #define SDIO_CLKCR_WIDBUS_Pos          (11U)
10848 #define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
10849 #define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
10850 #define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00000800 */
10851 #define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001000 */
10852 
10853 #define SDIO_CLKCR_NEGEDGE_Pos         (13U)
10854 #define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
10855 #define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
10856 #define SDIO_CLKCR_HWFC_EN_Pos         (14U)
10857 #define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
10858 #define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable */
10859 
10860 /*******************  Bit definition for SDIO_ARG register  *******************/
10861 #define SDIO_ARG_CMDARG_Pos            (0U)
10862 #define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
10863 #define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
10864 
10865 /*******************  Bit definition for SDIO_CMD register  *******************/
10866 #define SDIO_CMD_CMDINDEX_Pos          (0U)
10867 #define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
10868 #define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index */
10869 
10870 #define SDIO_CMD_WAITRESP_Pos          (6U)
10871 #define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
10872 #define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
10873 #define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x00000040 */
10874 #define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x00000080 */
10875 
10876 #define SDIO_CMD_WAITINT_Pos           (8U)
10877 #define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
10878 #define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request */
10879 #define SDIO_CMD_WAITPEND_Pos          (9U)
10880 #define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
10881 #define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
10882 #define SDIO_CMD_CPSMEN_Pos            (10U)
10883 #define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
10884 #define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit */
10885 #define SDIO_CMD_SDIOSUSPEND_Pos       (11U)
10886 #define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
10887 #define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command */
10888 #define SDIO_CMD_ENCMDCOMPL_Pos        (12U)
10889 #define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */
10890 #define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion */
10891 #define SDIO_CMD_NIEN_Pos              (13U)
10892 #define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */
10893 #define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable */
10894 #define SDIO_CMD_CEATACMD_Pos          (14U)
10895 #define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */
10896 #define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command */
10897 
10898 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
10899 #define SDIO_RESPCMD_RESPCMD_Pos       (0U)
10900 #define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
10901 #define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
10902 
10903 /******************  Bit definition for SDIO_RESP0 register  ******************/
10904 #define SDIO_RESP0_CARDSTATUS0_Pos     (0U)
10905 #define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
10906 #define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
10907 
10908 /******************  Bit definition for SDIO_RESP1 register  ******************/
10909 #define SDIO_RESP1_CARDSTATUS1_Pos     (0U)
10910 #define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
10911 #define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
10912 
10913 /******************  Bit definition for SDIO_RESP2 register  ******************/
10914 #define SDIO_RESP2_CARDSTATUS2_Pos     (0U)
10915 #define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
10916 #define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
10917 
10918 /******************  Bit definition for SDIO_RESP3 register  ******************/
10919 #define SDIO_RESP3_CARDSTATUS3_Pos     (0U)
10920 #define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
10921 #define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
10922 
10923 /******************  Bit definition for SDIO_RESP4 register  ******************/
10924 #define SDIO_RESP4_CARDSTATUS4_Pos     (0U)
10925 #define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
10926 #define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
10927 
10928 /******************  Bit definition for SDIO_DTIMER register  *****************/
10929 #define SDIO_DTIMER_DATATIME_Pos       (0U)
10930 #define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
10931 #define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
10932 
10933 /******************  Bit definition for SDIO_DLEN register  *******************/
10934 #define SDIO_DLEN_DATALENGTH_Pos       (0U)
10935 #define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
10936 #define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
10937 
10938 /******************  Bit definition for SDIO_DCTRL register  ******************/
10939 #define SDIO_DCTRL_DTEN_Pos            (0U)
10940 #define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
10941 #define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit */
10942 #define SDIO_DCTRL_DTDIR_Pos           (1U)
10943 #define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
10944 #define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
10945 #define SDIO_DCTRL_DTMODE_Pos          (2U)
10946 #define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
10947 #define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection */
10948 #define SDIO_DCTRL_DMAEN_Pos           (3U)
10949 #define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
10950 #define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit */
10951 
10952 #define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)
10953 #define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
10954 #define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
10955 #define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x00000010 */
10956 #define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x00000020 */
10957 #define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x00000040 */
10958 #define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x00000080 */
10959 
10960 #define SDIO_DCTRL_RWSTART_Pos         (8U)
10961 #define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
10962 #define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start */
10963 #define SDIO_DCTRL_RWSTOP_Pos          (9U)
10964 #define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
10965 #define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop */
10966 #define SDIO_DCTRL_RWMOD_Pos           (10U)
10967 #define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
10968 #define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode */
10969 #define SDIO_DCTRL_SDIOEN_Pos          (11U)
10970 #define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
10971 #define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
10972 
10973 /******************  Bit definition for SDIO_DCOUNT register  *****************/
10974 #define SDIO_DCOUNT_DATACOUNT_Pos      (0U)
10975 #define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
10976 #define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
10977 
10978 /******************  Bit definition for SDIO_STA register  ********************/
10979 #define SDIO_STA_CCRCFAIL_Pos          (0U)
10980 #define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
10981 #define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
10982 #define SDIO_STA_DCRCFAIL_Pos          (1U)
10983 #define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
10984 #define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
10985 #define SDIO_STA_CTIMEOUT_Pos          (2U)
10986 #define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
10987 #define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
10988 #define SDIO_STA_DTIMEOUT_Pos          (3U)
10989 #define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
10990 #define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
10991 #define SDIO_STA_TXUNDERR_Pos          (4U)
10992 #define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
10993 #define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
10994 #define SDIO_STA_RXOVERR_Pos           (5U)
10995 #define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
10996 #define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
10997 #define SDIO_STA_CMDREND_Pos           (6U)
10998 #define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
10999 #define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
11000 #define SDIO_STA_CMDSENT_Pos           (7U)
11001 #define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
11002 #define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
11003 #define SDIO_STA_DATAEND_Pos           (8U)
11004 #define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
11005 #define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
11006 #define SDIO_STA_STBITERR_Pos          (9U)
11007 #define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */
11008 #define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */
11009 #define SDIO_STA_DBCKEND_Pos           (10U)
11010 #define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
11011 #define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
11012 #define SDIO_STA_CMDACT_Pos            (11U)
11013 #define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
11014 #define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
11015 #define SDIO_STA_TXACT_Pos             (12U)
11016 #define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
11017 #define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
11018 #define SDIO_STA_RXACT_Pos             (13U)
11019 #define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
11020 #define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
11021 #define SDIO_STA_TXFIFOHE_Pos          (14U)
11022 #define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
11023 #define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
11024 #define SDIO_STA_RXFIFOHF_Pos          (15U)
11025 #define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
11026 #define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
11027 #define SDIO_STA_TXFIFOF_Pos           (16U)
11028 #define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
11029 #define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
11030 #define SDIO_STA_RXFIFOF_Pos           (17U)
11031 #define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
11032 #define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
11033 #define SDIO_STA_TXFIFOE_Pos           (18U)
11034 #define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
11035 #define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
11036 #define SDIO_STA_RXFIFOE_Pos           (19U)
11037 #define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
11038 #define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
11039 #define SDIO_STA_TXDAVL_Pos            (20U)
11040 #define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
11041 #define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
11042 #define SDIO_STA_RXDAVL_Pos            (21U)
11043 #define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
11044 #define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
11045 #define SDIO_STA_SDIOIT_Pos            (22U)
11046 #define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
11047 #define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
11048 #define SDIO_STA_CEATAEND_Pos          (23U)
11049 #define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */
11050 #define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */
11051 
11052 /*******************  Bit definition for SDIO_ICR register  *******************/
11053 #define SDIO_ICR_CCRCFAILC_Pos         (0U)
11054 #define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
11055 #define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
11056 #define SDIO_ICR_DCRCFAILC_Pos         (1U)
11057 #define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
11058 #define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
11059 #define SDIO_ICR_CTIMEOUTC_Pos         (2U)
11060 #define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
11061 #define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
11062 #define SDIO_ICR_DTIMEOUTC_Pos         (3U)
11063 #define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
11064 #define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
11065 #define SDIO_ICR_TXUNDERRC_Pos         (4U)
11066 #define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
11067 #define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
11068 #define SDIO_ICR_RXOVERRC_Pos          (5U)
11069 #define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
11070 #define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
11071 #define SDIO_ICR_CMDRENDC_Pos          (6U)
11072 #define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
11073 #define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
11074 #define SDIO_ICR_CMDSENTC_Pos          (7U)
11075 #define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
11076 #define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
11077 #define SDIO_ICR_DATAENDC_Pos          (8U)
11078 #define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
11079 #define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
11080 #define SDIO_ICR_STBITERRC_Pos         (9U)
11081 #define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */
11082 #define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */
11083 #define SDIO_ICR_DBCKENDC_Pos          (10U)
11084 #define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
11085 #define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
11086 #define SDIO_ICR_SDIOITC_Pos           (22U)
11087 #define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
11088 #define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
11089 #define SDIO_ICR_CEATAENDC_Pos         (23U)
11090 #define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */
11091 #define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */
11092 
11093 /******************  Bit definition for SDIO_MASK register  *******************/
11094 #define SDIO_MASK_CCRCFAILIE_Pos       (0U)
11095 #define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
11096 #define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
11097 #define SDIO_MASK_DCRCFAILIE_Pos       (1U)
11098 #define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
11099 #define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
11100 #define SDIO_MASK_CTIMEOUTIE_Pos       (2U)
11101 #define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
11102 #define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
11103 #define SDIO_MASK_DTIMEOUTIE_Pos       (3U)
11104 #define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
11105 #define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
11106 #define SDIO_MASK_TXUNDERRIE_Pos       (4U)
11107 #define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
11108 #define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
11109 #define SDIO_MASK_RXOVERRIE_Pos        (5U)
11110 #define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
11111 #define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
11112 #define SDIO_MASK_CMDRENDIE_Pos        (6U)
11113 #define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
11114 #define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
11115 #define SDIO_MASK_CMDSENTIE_Pos        (7U)
11116 #define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
11117 #define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
11118 #define SDIO_MASK_DATAENDIE_Pos        (8U)
11119 #define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
11120 #define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
11121 #define SDIO_MASK_STBITERRIE_Pos       (9U)
11122 #define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */
11123 #define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */
11124 #define SDIO_MASK_DBCKENDIE_Pos        (10U)
11125 #define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
11126 #define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
11127 #define SDIO_MASK_CMDACTIE_Pos         (11U)
11128 #define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
11129 #define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
11130 #define SDIO_MASK_TXACTIE_Pos          (12U)
11131 #define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
11132 #define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
11133 #define SDIO_MASK_RXACTIE_Pos          (13U)
11134 #define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
11135 #define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
11136 #define SDIO_MASK_TXFIFOHEIE_Pos       (14U)
11137 #define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
11138 #define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
11139 #define SDIO_MASK_RXFIFOHFIE_Pos       (15U)
11140 #define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
11141 #define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
11142 #define SDIO_MASK_TXFIFOFIE_Pos        (16U)
11143 #define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
11144 #define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
11145 #define SDIO_MASK_RXFIFOFIE_Pos        (17U)
11146 #define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
11147 #define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
11148 #define SDIO_MASK_TXFIFOEIE_Pos        (18U)
11149 #define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
11150 #define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
11151 #define SDIO_MASK_RXFIFOEIE_Pos        (19U)
11152 #define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
11153 #define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
11154 #define SDIO_MASK_TXDAVLIE_Pos         (20U)
11155 #define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
11156 #define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
11157 #define SDIO_MASK_RXDAVLIE_Pos         (21U)
11158 #define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
11159 #define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
11160 #define SDIO_MASK_SDIOITIE_Pos         (22U)
11161 #define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
11162 #define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
11163 #define SDIO_MASK_CEATAENDIE_Pos       (23U)
11164 #define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */
11165 #define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */
11166 
11167 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
11168 #define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)
11169 #define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
11170 #define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
11171 
11172 /******************  Bit definition for SDIO_FIFO register  *******************/
11173 #define SDIO_FIFO_FIFODATA_Pos         (0U)
11174 #define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
11175 #define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
11176 
11177 /******************************************************************************/
11178 /*                                                                            */
11179 /*                        Serial Peripheral Interface                         */
11180 /*                                                                            */
11181 /******************************************************************************/
11182 /*******************  Bit definition for SPI_CR1 register  ********************/
11183 #define SPI_CR1_CPHA_Pos            (0U)
11184 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
11185 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
11186 #define SPI_CR1_CPOL_Pos            (1U)
11187 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
11188 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
11189 #define SPI_CR1_MSTR_Pos            (2U)
11190 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
11191 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
11192 
11193 #define SPI_CR1_BR_Pos              (3U)
11194 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
11195 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
11196 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
11197 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
11198 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
11199 
11200 #define SPI_CR1_SPE_Pos             (6U)
11201 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
11202 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
11203 #define SPI_CR1_LSBFIRST_Pos        (7U)
11204 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
11205 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
11206 #define SPI_CR1_SSI_Pos             (8U)
11207 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
11208 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
11209 #define SPI_CR1_SSM_Pos             (9U)
11210 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
11211 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
11212 #define SPI_CR1_RXONLY_Pos          (10U)
11213 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
11214 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
11215 #define SPI_CR1_DFF_Pos             (11U)
11216 #define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
11217 #define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
11218 #define SPI_CR1_CRCNEXT_Pos         (12U)
11219 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
11220 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
11221 #define SPI_CR1_CRCEN_Pos           (13U)
11222 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
11223 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
11224 #define SPI_CR1_BIDIOE_Pos          (14U)
11225 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
11226 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
11227 #define SPI_CR1_BIDIMODE_Pos        (15U)
11228 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
11229 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
11230 
11231 /*******************  Bit definition for SPI_CR2 register  ********************/
11232 #define SPI_CR2_RXDMAEN_Pos         (0U)
11233 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
11234 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
11235 #define SPI_CR2_TXDMAEN_Pos         (1U)
11236 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
11237 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
11238 #define SPI_CR2_SSOE_Pos            (2U)
11239 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
11240 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
11241 #define SPI_CR2_FRF_Pos             (4U)
11242 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
11243 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
11244 #define SPI_CR2_ERRIE_Pos           (5U)
11245 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
11246 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
11247 #define SPI_CR2_RXNEIE_Pos          (6U)
11248 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
11249 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
11250 #define SPI_CR2_TXEIE_Pos           (7U)
11251 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
11252 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
11253 
11254 /********************  Bit definition for SPI_SR register  ********************/
11255 #define SPI_SR_RXNE_Pos             (0U)
11256 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
11257 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
11258 #define SPI_SR_TXE_Pos              (1U)
11259 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
11260 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
11261 #define SPI_SR_CHSIDE_Pos           (2U)
11262 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
11263 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
11264 #define SPI_SR_UDR_Pos              (3U)
11265 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
11266 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
11267 #define SPI_SR_CRCERR_Pos           (4U)
11268 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
11269 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
11270 #define SPI_SR_MODF_Pos             (5U)
11271 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
11272 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
11273 #define SPI_SR_OVR_Pos              (6U)
11274 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
11275 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
11276 #define SPI_SR_BSY_Pos              (7U)
11277 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
11278 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
11279 #define SPI_SR_FRE_Pos              (8U)
11280 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
11281 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
11282 
11283 /********************  Bit definition for SPI_DR register  ********************/
11284 #define SPI_DR_DR_Pos               (0U)
11285 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
11286 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
11287 
11288 /*******************  Bit definition for SPI_CRCPR register  ******************/
11289 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
11290 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
11291 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
11292 
11293 /******************  Bit definition for SPI_RXCRCR register  ******************/
11294 #define SPI_RXCRCR_RXCRC_Pos        (0U)
11295 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
11296 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
11297 
11298 /******************  Bit definition for SPI_TXCRCR register  ******************/
11299 #define SPI_TXCRCR_TXCRC_Pos        (0U)
11300 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
11301 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
11302 
11303 /******************  Bit definition for SPI_I2SCFGR register  *****************/
11304 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
11305 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
11306 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
11307 
11308 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
11309 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
11310 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
11311 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
11312 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
11313 
11314 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
11315 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
11316 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
11317 
11318 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
11319 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
11320 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
11321 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
11322 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
11323 
11324 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
11325 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
11326 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
11327 
11328 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
11329 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
11330 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
11331 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
11332 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
11333 
11334 #define SPI_I2SCFGR_I2SE_Pos        (10U)
11335 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
11336 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
11337 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
11338 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
11339 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
11340 
11341 /******************  Bit definition for SPI_I2SPR register  *******************/
11342 #define SPI_I2SPR_I2SDIV_Pos        (0U)
11343 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
11344 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
11345 #define SPI_I2SPR_ODD_Pos           (8U)
11346 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
11347 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
11348 #define SPI_I2SPR_MCKOE_Pos         (9U)
11349 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
11350 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
11351 
11352 /******************************************************************************/
11353 /*                                                                            */
11354 /*                                 SYSCFG                                     */
11355 /*                                                                            */
11356 /******************************************************************************/
11357 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
11358 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
11359 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
11360 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!<SYSCFG_Memory Remap Config */
11361 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
11362 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
11363 /******************  Bit definition for SYSCFG_PMC register  ******************/
11364 #define SYSCFG_PMC_MII_RMII_SEL_Pos     (23U)
11365 #define SYSCFG_PMC_MII_RMII_SEL_Msk     (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)  /*!< 0x00800000 */
11366 #define SYSCFG_PMC_MII_RMII_SEL         SYSCFG_PMC_MII_RMII_SEL_Msk            /*!<Ethernet PHY interface selection */
11367 
11368 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
11369 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
11370 #define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
11371 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
11372 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
11373 #define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
11374 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
11375 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
11376 #define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
11377 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
11378 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
11379 #define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
11380 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
11381 /**
11382   * @brief   EXTI0 configuration
11383   */
11384 #define SYSCFG_EXTICR1_EXTI0_PA         0x00000000U                            /*!<PA[0] pin */
11385 #define SYSCFG_EXTICR1_EXTI0_PB         0x00000001U                            /*!<PB[0] pin */
11386 #define SYSCFG_EXTICR1_EXTI0_PC         0x00000002U                            /*!<PC[0] pin */
11387 #define SYSCFG_EXTICR1_EXTI0_PD         0x00000003U                            /*!<PD[0] pin */
11388 #define SYSCFG_EXTICR1_EXTI0_PE         0x00000004U                            /*!<PE[0] pin */
11389 #define SYSCFG_EXTICR1_EXTI0_PF         0x00000005U                            /*!<PF[0] pin */
11390 #define SYSCFG_EXTICR1_EXTI0_PG         0x00000006U                            /*!<PG[0] pin */
11391 #define SYSCFG_EXTICR1_EXTI0_PH         0x00000007U                            /*!<PH[0] pin */
11392 #define SYSCFG_EXTICR1_EXTI0_PI         0x00000008U                            /*!<PI[0] pin */
11393 /**
11394   * @brief   EXTI1 configuration
11395   */
11396 #define SYSCFG_EXTICR1_EXTI1_PA         0x00000000U                            /*!<PA[1] pin */
11397 #define SYSCFG_EXTICR1_EXTI1_PB         0x00000010U                            /*!<PB[1] pin */
11398 #define SYSCFG_EXTICR1_EXTI1_PC         0x00000020U                            /*!<PC[1] pin */
11399 #define SYSCFG_EXTICR1_EXTI1_PD         0x00000030U                            /*!<PD[1] pin */
11400 #define SYSCFG_EXTICR1_EXTI1_PE         0x00000040U                            /*!<PE[1] pin */
11401 #define SYSCFG_EXTICR1_EXTI1_PF         0x00000050U                            /*!<PF[1] pin */
11402 #define SYSCFG_EXTICR1_EXTI1_PG         0x00000060U                            /*!<PG[1] pin */
11403 #define SYSCFG_EXTICR1_EXTI1_PH         0x00000070U                            /*!<PH[1] pin */
11404 #define SYSCFG_EXTICR1_EXTI1_PI         0x00000080U                            /*!<PI[1] pin */
11405 /**
11406   * @brief   EXTI2 configuration
11407   */
11408 #define SYSCFG_EXTICR1_EXTI2_PA         0x00000000U                            /*!<PA[2] pin */
11409 #define SYSCFG_EXTICR1_EXTI2_PB         0x00000100U                            /*!<PB[2] pin */
11410 #define SYSCFG_EXTICR1_EXTI2_PC         0x00000200U                            /*!<PC[2] pin */
11411 #define SYSCFG_EXTICR1_EXTI2_PD         0x00000300U                            /*!<PD[2] pin */
11412 #define SYSCFG_EXTICR1_EXTI2_PE         0x00000400U                            /*!<PE[2] pin */
11413 #define SYSCFG_EXTICR1_EXTI2_PF         0x00000500U                            /*!<PF[2] pin */
11414 #define SYSCFG_EXTICR1_EXTI2_PG         0x00000600U                            /*!<PG[2] pin */
11415 #define SYSCFG_EXTICR1_EXTI2_PH         0x00000700U                            /*!<PH[2] pin */
11416 #define SYSCFG_EXTICR1_EXTI2_PI         0x00000800U                            /*!<PI[2] pin */
11417 /**
11418   * @brief   EXTI3 configuration
11419   */
11420 #define SYSCFG_EXTICR1_EXTI3_PA         0x00000000U                            /*!<PA[3] pin */
11421 #define SYSCFG_EXTICR1_EXTI3_PB         0x00001000U                            /*!<PB[3] pin */
11422 #define SYSCFG_EXTICR1_EXTI3_PC         0x00002000U                            /*!<PC[3] pin */
11423 #define SYSCFG_EXTICR1_EXTI3_PD         0x00003000U                            /*!<PD[3] pin */
11424 #define SYSCFG_EXTICR1_EXTI3_PE         0x00004000U                            /*!<PE[3] pin */
11425 #define SYSCFG_EXTICR1_EXTI3_PF         0x00005000U                            /*!<PF[3] pin */
11426 #define SYSCFG_EXTICR1_EXTI3_PG         0x00006000U                            /*!<PG[3] pin */
11427 #define SYSCFG_EXTICR1_EXTI3_PH         0x00007000U                            /*!<PH[3] pin */
11428 #define SYSCFG_EXTICR1_EXTI3_PI         0x00008000U                            /*!<PI[3] pin */
11429 
11430 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
11431 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
11432 #define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
11433 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
11434 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
11435 #define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
11436 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
11437 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
11438 #define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
11439 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
11440 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
11441 #define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
11442 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
11443 /**
11444   * @brief   EXTI4 configuration
11445   */
11446 #define SYSCFG_EXTICR2_EXTI4_PA         0x00000000U                            /*!<PA[4] pin */
11447 #define SYSCFG_EXTICR2_EXTI4_PB         0x00000001U                            /*!<PB[4] pin */
11448 #define SYSCFG_EXTICR2_EXTI4_PC         0x00000002U                            /*!<PC[4] pin */
11449 #define SYSCFG_EXTICR2_EXTI4_PD         0x00000003U                            /*!<PD[4] pin */
11450 #define SYSCFG_EXTICR2_EXTI4_PE         0x00000004U                            /*!<PE[4] pin */
11451 #define SYSCFG_EXTICR2_EXTI4_PF         0x00000005U                            /*!<PF[4] pin */
11452 #define SYSCFG_EXTICR2_EXTI4_PG         0x00000006U                            /*!<PG[4] pin */
11453 #define SYSCFG_EXTICR2_EXTI4_PH         0x00000007U                            /*!<PH[4] pin */
11454 #define SYSCFG_EXTICR2_EXTI4_PI         0x00000008U                            /*!<PI[4] pin */
11455 /**
11456   * @brief   EXTI5 configuration
11457   */
11458 #define SYSCFG_EXTICR2_EXTI5_PA         0x00000000U                            /*!<PA[5] pin */
11459 #define SYSCFG_EXTICR2_EXTI5_PB         0x00000010U                            /*!<PB[5] pin */
11460 #define SYSCFG_EXTICR2_EXTI5_PC         0x00000020U                            /*!<PC[5] pin */
11461 #define SYSCFG_EXTICR2_EXTI5_PD         0x00000030U                            /*!<PD[5] pin */
11462 #define SYSCFG_EXTICR2_EXTI5_PE         0x00000040U                            /*!<PE[5] pin */
11463 #define SYSCFG_EXTICR2_EXTI5_PF         0x00000050U                            /*!<PF[5] pin */
11464 #define SYSCFG_EXTICR2_EXTI5_PG         0x00000060U                            /*!<PG[5] pin */
11465 #define SYSCFG_EXTICR2_EXTI5_PH         0x00000070U                            /*!<PH[5] pin */
11466 #define SYSCFG_EXTICR2_EXTI5_PI         0x00000080U                            /*!<PI[5] pin */
11467 /**
11468   * @brief   EXTI6 configuration
11469   */
11470 #define SYSCFG_EXTICR2_EXTI6_PA         0x00000000U                            /*!<PA[6] pin */
11471 #define SYSCFG_EXTICR2_EXTI6_PB         0x00000100U                            /*!<PB[6] pin */
11472 #define SYSCFG_EXTICR2_EXTI6_PC         0x00000200U                            /*!<PC[6] pin */
11473 #define SYSCFG_EXTICR2_EXTI6_PD         0x00000300U                            /*!<PD[6] pin */
11474 #define SYSCFG_EXTICR2_EXTI6_PE         0x00000400U                            /*!<PE[6] pin */
11475 #define SYSCFG_EXTICR2_EXTI6_PF         0x00000500U                            /*!<PF[6] pin */
11476 #define SYSCFG_EXTICR2_EXTI6_PG         0x00000600U                            /*!<PG[6] pin */
11477 #define SYSCFG_EXTICR2_EXTI6_PH         0x00000700U                            /*!<PH[6] pin */
11478 #define SYSCFG_EXTICR2_EXTI6_PI         0x00000800U                            /*!<PI[6] pin */
11479 /**
11480   * @brief   EXTI7 configuration
11481   */
11482 #define SYSCFG_EXTICR2_EXTI7_PA         0x00000000U                            /*!<PA[7] pin */
11483 #define SYSCFG_EXTICR2_EXTI7_PB         0x00001000U                            /*!<PB[7] pin */
11484 #define SYSCFG_EXTICR2_EXTI7_PC         0x00002000U                            /*!<PC[7] pin */
11485 #define SYSCFG_EXTICR2_EXTI7_PD         0x00003000U                            /*!<PD[7] pin */
11486 #define SYSCFG_EXTICR2_EXTI7_PE         0x00004000U                            /*!<PE[7] pin */
11487 #define SYSCFG_EXTICR2_EXTI7_PF         0x00005000U                            /*!<PF[7] pin */
11488 #define SYSCFG_EXTICR2_EXTI7_PG         0x00006000U                            /*!<PG[7] pin */
11489 #define SYSCFG_EXTICR2_EXTI7_PH         0x00007000U                            /*!<PH[7] pin */
11490 #define SYSCFG_EXTICR2_EXTI7_PI         0x00008000U                            /*!<PI[7] pin */
11491 
11492 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
11493 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
11494 #define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
11495 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
11496 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
11497 #define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
11498 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
11499 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
11500 #define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
11501 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
11502 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
11503 #define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
11504 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
11505 
11506 /**
11507   * @brief   EXTI8 configuration
11508   */
11509 #define SYSCFG_EXTICR3_EXTI8_PA         0x00000000U                            /*!<PA[8] pin */
11510 #define SYSCFG_EXTICR3_EXTI8_PB         0x00000001U                            /*!<PB[8] pin */
11511 #define SYSCFG_EXTICR3_EXTI8_PC         0x00000002U                            /*!<PC[8] pin */
11512 #define SYSCFG_EXTICR3_EXTI8_PD         0x00000003U                            /*!<PD[8] pin */
11513 #define SYSCFG_EXTICR3_EXTI8_PE         0x00000004U                            /*!<PE[8] pin */
11514 #define SYSCFG_EXTICR3_EXTI8_PF         0x00000005U                            /*!<PF[8] pin */
11515 #define SYSCFG_EXTICR3_EXTI8_PG         0x00000006U                            /*!<PG[8] pin */
11516 #define SYSCFG_EXTICR3_EXTI8_PH         0x00000007U                            /*!<PH[8] pin */
11517 #define SYSCFG_EXTICR3_EXTI8_PI         0x00000008U                            /*!<PI[8] pin */
11518 /**
11519   * @brief   EXTI9 configuration
11520   */
11521 #define SYSCFG_EXTICR3_EXTI9_PA         0x00000000U                            /*!<PA[9] pin */
11522 #define SYSCFG_EXTICR3_EXTI9_PB         0x00000010U                            /*!<PB[9] pin */
11523 #define SYSCFG_EXTICR3_EXTI9_PC         0x00000020U                            /*!<PC[9] pin */
11524 #define SYSCFG_EXTICR3_EXTI9_PD         0x00000030U                            /*!<PD[9] pin */
11525 #define SYSCFG_EXTICR3_EXTI9_PE         0x00000040U                            /*!<PE[9] pin */
11526 #define SYSCFG_EXTICR3_EXTI9_PF         0x00000050U                            /*!<PF[9] pin */
11527 #define SYSCFG_EXTICR3_EXTI9_PG         0x00000060U                            /*!<PG[9] pin */
11528 #define SYSCFG_EXTICR3_EXTI9_PH         0x00000070U                            /*!<PH[9] pin */
11529 #define SYSCFG_EXTICR3_EXTI9_PI         0x00000080U                            /*!<PI[9] pin */
11530 /**
11531   * @brief   EXTI10 configuration
11532   */
11533 #define SYSCFG_EXTICR3_EXTI10_PA        0x00000000U                            /*!<PA[10] pin */
11534 #define SYSCFG_EXTICR3_EXTI10_PB        0x00000100U                            /*!<PB[10] pin */
11535 #define SYSCFG_EXTICR3_EXTI10_PC        0x00000200U                            /*!<PC[10] pin */
11536 #define SYSCFG_EXTICR3_EXTI10_PD        0x00000300U                            /*!<PD[10] pin */
11537 #define SYSCFG_EXTICR3_EXTI10_PE        0x00000400U                            /*!<PE[10] pin */
11538 #define SYSCFG_EXTICR3_EXTI10_PF        0x00000500U                            /*!<PF[10] pin */
11539 #define SYSCFG_EXTICR3_EXTI10_PG        0x00000600U                            /*!<PG[10] pin */
11540 #define SYSCFG_EXTICR3_EXTI10_PH        0x00000700U                            /*!<PH[10] pin */
11541 #define SYSCFG_EXTICR3_EXTI10_PI        0x00000800U                            /*!<PI[10] pin */
11542 /**
11543   * @brief   EXTI11 configuration
11544   */
11545 #define SYSCFG_EXTICR3_EXTI11_PA        0x00000000U                            /*!<PA[11] pin */
11546 #define SYSCFG_EXTICR3_EXTI11_PB        0x00001000U                            /*!<PB[11] pin */
11547 #define SYSCFG_EXTICR3_EXTI11_PC        0x00002000U                            /*!<PC[11] pin */
11548 #define SYSCFG_EXTICR3_EXTI11_PD        0x00003000U                            /*!<PD[11] pin */
11549 #define SYSCFG_EXTICR3_EXTI11_PE        0x00004000U                            /*!<PE[11] pin */
11550 #define SYSCFG_EXTICR3_EXTI11_PF        0x00005000U                            /*!<PF[11] pin */
11551 #define SYSCFG_EXTICR3_EXTI11_PG        0x00006000U                            /*!<PG[11] pin */
11552 #define SYSCFG_EXTICR3_EXTI11_PH        0x00007000U                            /*!<PH[11] pin */
11553 #define SYSCFG_EXTICR3_EXTI11_PI        0x00008000U                            /*!<PI[11] pin */
11554 
11555 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
11556 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
11557 #define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
11558 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
11559 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
11560 #define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
11561 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
11562 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
11563 #define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
11564 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
11565 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
11566 #define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
11567 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
11568 /**
11569   * @brief   EXTI12 configuration
11570   */
11571 #define SYSCFG_EXTICR4_EXTI12_PA        0x00000000U                            /*!<PA[12] pin */
11572 #define SYSCFG_EXTICR4_EXTI12_PB        0x00000001U                            /*!<PB[12] pin */
11573 #define SYSCFG_EXTICR4_EXTI12_PC        0x00000002U                            /*!<PC[12] pin */
11574 #define SYSCFG_EXTICR4_EXTI12_PD        0x00000003U                            /*!<PD[12] pin */
11575 #define SYSCFG_EXTICR4_EXTI12_PE        0x00000004U                            /*!<PE[12] pin */
11576 #define SYSCFG_EXTICR4_EXTI12_PF        0x00000005U                            /*!<PF[12] pin */
11577 #define SYSCFG_EXTICR4_EXTI12_PG        0x00000006U                            /*!<PG[12] pin */
11578 #define SYSCFG_EXTICR3_EXTI12_PH        0x00000007U                            /*!<PH[12] pin */
11579 /**
11580   * @brief   EXTI13 configuration
11581   */
11582 #define SYSCFG_EXTICR4_EXTI13_PA        0x00000000U                            /*!<PA[13] pin */
11583 #define SYSCFG_EXTICR4_EXTI13_PB        0x00000010U                            /*!<PB[13] pin */
11584 #define SYSCFG_EXTICR4_EXTI13_PC        0x00000020U                            /*!<PC[13] pin */
11585 #define SYSCFG_EXTICR4_EXTI13_PD        0x00000030U                            /*!<PD[13] pin */
11586 #define SYSCFG_EXTICR4_EXTI13_PE        0x00000040U                            /*!<PE[13] pin */
11587 #define SYSCFG_EXTICR4_EXTI13_PF        0x00000050U                            /*!<PF[13] pin */
11588 #define SYSCFG_EXTICR4_EXTI13_PG        0x00000060U                            /*!<PG[13] pin */
11589 #define SYSCFG_EXTICR3_EXTI13_PH        0x00000070U                            /*!<PH[13] pin */
11590 /**
11591   * @brief   EXTI14 configuration
11592   */
11593 #define SYSCFG_EXTICR4_EXTI14_PA        0x00000000U                            /*!<PA[14] pin */
11594 #define SYSCFG_EXTICR4_EXTI14_PB        0x00000100U                            /*!<PB[14] pin */
11595 #define SYSCFG_EXTICR4_EXTI14_PC        0x00000200U                            /*!<PC[14] pin */
11596 #define SYSCFG_EXTICR4_EXTI14_PD        0x00000300U                            /*!<PD[14] pin */
11597 #define SYSCFG_EXTICR4_EXTI14_PE        0x00000400U                            /*!<PE[14] pin */
11598 #define SYSCFG_EXTICR4_EXTI14_PF        0x00000500U                            /*!<PF[14] pin */
11599 #define SYSCFG_EXTICR4_EXTI14_PG        0x00000600U                            /*!<PG[14] pin */
11600 #define SYSCFG_EXTICR3_EXTI14_PH        0x00000700U                            /*!<PH[14] pin */
11601 /**
11602   * @brief   EXTI15 configuration
11603   */
11604 #define SYSCFG_EXTICR4_EXTI15_PA        0x00000000U                            /*!<PA[15] pin */
11605 #define SYSCFG_EXTICR4_EXTI15_PB        0x00001000U                            /*!<PB[15] pin */
11606 #define SYSCFG_EXTICR4_EXTI15_PC        0x00002000U                            /*!<PC[15] pin */
11607 #define SYSCFG_EXTICR4_EXTI15_PD        0x00003000U                            /*!<PD[15] pin */
11608 #define SYSCFG_EXTICR4_EXTI15_PE        0x00004000U                            /*!<PE[15] pin */
11609 #define SYSCFG_EXTICR4_EXTI15_PF        0x00005000U                            /*!<PF[15] pin */
11610 #define SYSCFG_EXTICR4_EXTI15_PG        0x00006000U                            /*!<PG[15] pin */
11611 #define SYSCFG_EXTICR3_EXTI15_PH        0x00007000U                            /*!<PH[15] pin */
11612 
11613 /******************  Bit definition for SYSCFG_CMPCR register  ****************/
11614 #define SYSCFG_CMPCR_CMP_PD_Pos         (0U)
11615 #define SYSCFG_CMPCR_CMP_PD_Msk         (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)      /*!< 0x00000001 */
11616 #define SYSCFG_CMPCR_CMP_PD             SYSCFG_CMPCR_CMP_PD_Msk                /*!<Compensation cell ready flag */
11617 #define SYSCFG_CMPCR_READY_Pos          (8U)
11618 #define SYSCFG_CMPCR_READY_Msk          (0x1UL << SYSCFG_CMPCR_READY_Pos)       /*!< 0x00000100 */
11619 #define SYSCFG_CMPCR_READY              SYSCFG_CMPCR_READY_Msk                 /*!<Compensation cell power-down */
11620 
11621 /******************************************************************************/
11622 /*                                                                            */
11623 /*                                    TIM                                     */
11624 /*                                                                            */
11625 /******************************************************************************/
11626 /*******************  Bit definition for TIM_CR1 register  ********************/
11627 #define TIM_CR1_CEN_Pos           (0U)
11628 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
11629 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
11630 #define TIM_CR1_UDIS_Pos          (1U)
11631 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
11632 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
11633 #define TIM_CR1_URS_Pos           (2U)
11634 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
11635 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
11636 #define TIM_CR1_OPM_Pos           (3U)
11637 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
11638 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
11639 #define TIM_CR1_DIR_Pos           (4U)
11640 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
11641 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
11642 
11643 #define TIM_CR1_CMS_Pos           (5U)
11644 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
11645 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
11646 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
11647 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
11648 
11649 #define TIM_CR1_ARPE_Pos          (7U)
11650 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
11651 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
11652 
11653 #define TIM_CR1_CKD_Pos           (8U)
11654 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
11655 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
11656 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
11657 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
11658 
11659 /*******************  Bit definition for TIM_CR2 register  ********************/
11660 #define TIM_CR2_CCPC_Pos          (0U)
11661 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
11662 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
11663 #define TIM_CR2_CCUS_Pos          (2U)
11664 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
11665 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
11666 #define TIM_CR2_CCDS_Pos          (3U)
11667 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
11668 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
11669 
11670 #define TIM_CR2_MMS_Pos           (4U)
11671 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
11672 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
11673 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
11674 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
11675 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
11676 
11677 #define TIM_CR2_TI1S_Pos          (7U)
11678 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
11679 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
11680 #define TIM_CR2_OIS1_Pos          (8U)
11681 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
11682 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
11683 #define TIM_CR2_OIS1N_Pos         (9U)
11684 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
11685 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
11686 #define TIM_CR2_OIS2_Pos          (10U)
11687 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
11688 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
11689 #define TIM_CR2_OIS2N_Pos         (11U)
11690 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
11691 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
11692 #define TIM_CR2_OIS3_Pos          (12U)
11693 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
11694 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
11695 #define TIM_CR2_OIS3N_Pos         (13U)
11696 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
11697 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
11698 #define TIM_CR2_OIS4_Pos          (14U)
11699 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
11700 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
11701 
11702 /*******************  Bit definition for TIM_SMCR register  *******************/
11703 #define TIM_SMCR_SMS_Pos          (0U)
11704 #define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
11705 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
11706 #define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000001 */
11707 #define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000002 */
11708 #define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000004 */
11709 
11710 #define TIM_SMCR_TS_Pos           (4U)
11711 #define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
11712 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
11713 #define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
11714 #define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
11715 #define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
11716 
11717 #define TIM_SMCR_MSM_Pos          (7U)
11718 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
11719 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
11720 
11721 #define TIM_SMCR_ETF_Pos          (8U)
11722 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
11723 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
11724 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
11725 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
11726 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
11727 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
11728 
11729 #define TIM_SMCR_ETPS_Pos         (12U)
11730 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
11731 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
11732 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
11733 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
11734 
11735 #define TIM_SMCR_ECE_Pos          (14U)
11736 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
11737 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
11738 #define TIM_SMCR_ETP_Pos          (15U)
11739 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
11740 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
11741 
11742 /*******************  Bit definition for TIM_DIER register  *******************/
11743 #define TIM_DIER_UIE_Pos          (0U)
11744 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
11745 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
11746 #define TIM_DIER_CC1IE_Pos        (1U)
11747 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
11748 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
11749 #define TIM_DIER_CC2IE_Pos        (2U)
11750 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
11751 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
11752 #define TIM_DIER_CC3IE_Pos        (3U)
11753 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
11754 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
11755 #define TIM_DIER_CC4IE_Pos        (4U)
11756 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
11757 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
11758 #define TIM_DIER_COMIE_Pos        (5U)
11759 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
11760 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
11761 #define TIM_DIER_TIE_Pos          (6U)
11762 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
11763 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
11764 #define TIM_DIER_BIE_Pos          (7U)
11765 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
11766 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
11767 #define TIM_DIER_UDE_Pos          (8U)
11768 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
11769 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
11770 #define TIM_DIER_CC1DE_Pos        (9U)
11771 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
11772 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
11773 #define TIM_DIER_CC2DE_Pos        (10U)
11774 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
11775 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
11776 #define TIM_DIER_CC3DE_Pos        (11U)
11777 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
11778 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
11779 #define TIM_DIER_CC4DE_Pos        (12U)
11780 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
11781 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
11782 #define TIM_DIER_COMDE_Pos        (13U)
11783 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
11784 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
11785 #define TIM_DIER_TDE_Pos          (14U)
11786 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
11787 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
11788 
11789 /********************  Bit definition for TIM_SR register  ********************/
11790 #define TIM_SR_UIF_Pos            (0U)
11791 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
11792 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
11793 #define TIM_SR_CC1IF_Pos          (1U)
11794 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
11795 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
11796 #define TIM_SR_CC2IF_Pos          (2U)
11797 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
11798 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
11799 #define TIM_SR_CC3IF_Pos          (3U)
11800 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
11801 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
11802 #define TIM_SR_CC4IF_Pos          (4U)
11803 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
11804 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
11805 #define TIM_SR_COMIF_Pos          (5U)
11806 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
11807 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
11808 #define TIM_SR_TIF_Pos            (6U)
11809 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
11810 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
11811 #define TIM_SR_BIF_Pos            (7U)
11812 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
11813 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
11814 #define TIM_SR_CC1OF_Pos          (9U)
11815 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
11816 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
11817 #define TIM_SR_CC2OF_Pos          (10U)
11818 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
11819 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
11820 #define TIM_SR_CC3OF_Pos          (11U)
11821 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
11822 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
11823 #define TIM_SR_CC4OF_Pos          (12U)
11824 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
11825 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
11826 
11827 /*******************  Bit definition for TIM_EGR register  ********************/
11828 #define TIM_EGR_UG_Pos            (0U)
11829 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
11830 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
11831 #define TIM_EGR_CC1G_Pos          (1U)
11832 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
11833 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
11834 #define TIM_EGR_CC2G_Pos          (2U)
11835 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
11836 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
11837 #define TIM_EGR_CC3G_Pos          (3U)
11838 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
11839 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
11840 #define TIM_EGR_CC4G_Pos          (4U)
11841 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
11842 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
11843 #define TIM_EGR_COMG_Pos          (5U)
11844 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
11845 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
11846 #define TIM_EGR_TG_Pos            (6U)
11847 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
11848 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
11849 #define TIM_EGR_BG_Pos            (7U)
11850 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
11851 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
11852 
11853 /******************  Bit definition for TIM_CCMR1 register  *******************/
11854 #define TIM_CCMR1_CC1S_Pos        (0U)
11855 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
11856 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
11857 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
11858 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
11859 
11860 #define TIM_CCMR1_OC1FE_Pos       (2U)
11861 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
11862 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
11863 #define TIM_CCMR1_OC1PE_Pos       (3U)
11864 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
11865 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
11866 
11867 #define TIM_CCMR1_OC1M_Pos        (4U)
11868 #define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
11869 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
11870 #define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000010 */
11871 #define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000020 */
11872 #define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000040 */
11873 
11874 #define TIM_CCMR1_OC1CE_Pos       (7U)
11875 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
11876 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
11877 
11878 #define TIM_CCMR1_CC2S_Pos        (8U)
11879 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
11880 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
11881 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
11882 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
11883 
11884 #define TIM_CCMR1_OC2FE_Pos       (10U)
11885 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
11886 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
11887 #define TIM_CCMR1_OC2PE_Pos       (11U)
11888 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
11889 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
11890 
11891 #define TIM_CCMR1_OC2M_Pos        (12U)
11892 #define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
11893 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
11894 #define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00001000 */
11895 #define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00002000 */
11896 #define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00004000 */
11897 
11898 #define TIM_CCMR1_OC2CE_Pos       (15U)
11899 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
11900 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
11901 
11902 /*----------------------------------------------------------------------------*/
11903 
11904 #define TIM_CCMR1_IC1PSC_Pos      (2U)
11905 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
11906 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
11907 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
11908 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
11909 
11910 #define TIM_CCMR1_IC1F_Pos        (4U)
11911 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
11912 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
11913 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
11914 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
11915 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
11916 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
11917 
11918 #define TIM_CCMR1_IC2PSC_Pos      (10U)
11919 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
11920 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
11921 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
11922 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
11923 
11924 #define TIM_CCMR1_IC2F_Pos        (12U)
11925 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
11926 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
11927 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
11928 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
11929 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
11930 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
11931 
11932 /******************  Bit definition for TIM_CCMR2 register  *******************/
11933 #define TIM_CCMR2_CC3S_Pos        (0U)
11934 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
11935 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
11936 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
11937 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
11938 
11939 #define TIM_CCMR2_OC3FE_Pos       (2U)
11940 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
11941 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
11942 #define TIM_CCMR2_OC3PE_Pos       (3U)
11943 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
11944 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
11945 
11946 #define TIM_CCMR2_OC3M_Pos        (4U)
11947 #define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
11948 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
11949 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
11950 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
11951 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
11952 
11953 #define TIM_CCMR2_OC3CE_Pos       (7U)
11954 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
11955 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
11956 
11957 #define TIM_CCMR2_CC4S_Pos        (8U)
11958 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
11959 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
11960 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
11961 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
11962 
11963 #define TIM_CCMR2_OC4FE_Pos       (10U)
11964 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
11965 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
11966 #define TIM_CCMR2_OC4PE_Pos       (11U)
11967 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
11968 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
11969 
11970 #define TIM_CCMR2_OC4M_Pos        (12U)
11971 #define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
11972 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
11973 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
11974 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
11975 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
11976 
11977 #define TIM_CCMR2_OC4CE_Pos       (15U)
11978 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
11979 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
11980 
11981 /*----------------------------------------------------------------------------*/
11982 
11983 #define TIM_CCMR2_IC3PSC_Pos      (2U)
11984 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
11985 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
11986 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
11987 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
11988 
11989 #define TIM_CCMR2_IC3F_Pos        (4U)
11990 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
11991 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
11992 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
11993 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
11994 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
11995 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
11996 
11997 #define TIM_CCMR2_IC4PSC_Pos      (10U)
11998 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
11999 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
12000 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
12001 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
12002 
12003 #define TIM_CCMR2_IC4F_Pos        (12U)
12004 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
12005 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
12006 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
12007 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
12008 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
12009 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
12010 
12011 /*******************  Bit definition for TIM_CCER register  *******************/
12012 #define TIM_CCER_CC1E_Pos         (0U)
12013 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
12014 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
12015 #define TIM_CCER_CC1P_Pos         (1U)
12016 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
12017 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
12018 #define TIM_CCER_CC1NE_Pos        (2U)
12019 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
12020 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
12021 #define TIM_CCER_CC1NP_Pos        (3U)
12022 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
12023 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
12024 #define TIM_CCER_CC2E_Pos         (4U)
12025 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
12026 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
12027 #define TIM_CCER_CC2P_Pos         (5U)
12028 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
12029 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
12030 #define TIM_CCER_CC2NE_Pos        (6U)
12031 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
12032 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
12033 #define TIM_CCER_CC2NP_Pos        (7U)
12034 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
12035 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
12036 #define TIM_CCER_CC3E_Pos         (8U)
12037 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
12038 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
12039 #define TIM_CCER_CC3P_Pos         (9U)
12040 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
12041 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
12042 #define TIM_CCER_CC3NE_Pos        (10U)
12043 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
12044 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
12045 #define TIM_CCER_CC3NP_Pos        (11U)
12046 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
12047 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
12048 #define TIM_CCER_CC4E_Pos         (12U)
12049 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
12050 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
12051 #define TIM_CCER_CC4P_Pos         (13U)
12052 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
12053 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
12054 #define TIM_CCER_CC4NP_Pos        (15U)
12055 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
12056 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
12057 
12058 /*******************  Bit definition for TIM_CNT register  ********************/
12059 #define TIM_CNT_CNT_Pos           (0U)
12060 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
12061 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
12062 
12063 /*******************  Bit definition for TIM_PSC register  ********************/
12064 #define TIM_PSC_PSC_Pos           (0U)
12065 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
12066 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
12067 
12068 /*******************  Bit definition for TIM_ARR register  ********************/
12069 #define TIM_ARR_ARR_Pos           (0U)
12070 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
12071 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
12072 
12073 /*******************  Bit definition for TIM_RCR register  ********************/
12074 #define TIM_RCR_REP_Pos           (0U)
12075 #define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
12076 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
12077 
12078 /*******************  Bit definition for TIM_CCR1 register  *******************/
12079 #define TIM_CCR1_CCR1_Pos         (0U)
12080 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
12081 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
12082 
12083 /*******************  Bit definition for TIM_CCR2 register  *******************/
12084 #define TIM_CCR2_CCR2_Pos         (0U)
12085 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
12086 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
12087 
12088 /*******************  Bit definition for TIM_CCR3 register  *******************/
12089 #define TIM_CCR3_CCR3_Pos         (0U)
12090 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
12091 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
12092 
12093 /*******************  Bit definition for TIM_CCR4 register  *******************/
12094 #define TIM_CCR4_CCR4_Pos         (0U)
12095 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
12096 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
12097 
12098 /*******************  Bit definition for TIM_BDTR register  *******************/
12099 #define TIM_BDTR_DTG_Pos          (0U)
12100 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
12101 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12102 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
12103 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
12104 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
12105 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
12106 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
12107 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
12108 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
12109 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
12110 
12111 #define TIM_BDTR_LOCK_Pos         (8U)
12112 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
12113 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
12114 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
12115 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
12116 
12117 #define TIM_BDTR_OSSI_Pos         (10U)
12118 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
12119 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
12120 #define TIM_BDTR_OSSR_Pos         (11U)
12121 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
12122 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
12123 #define TIM_BDTR_BKE_Pos          (12U)
12124 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
12125 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable */
12126 #define TIM_BDTR_BKP_Pos          (13U)
12127 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
12128 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity */
12129 #define TIM_BDTR_AOE_Pos          (14U)
12130 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
12131 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
12132 #define TIM_BDTR_MOE_Pos          (15U)
12133 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
12134 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
12135 
12136 /*******************  Bit definition for TIM_DCR register  ********************/
12137 #define TIM_DCR_DBA_Pos           (0U)
12138 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
12139 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
12140 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
12141 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
12142 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
12143 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
12144 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
12145 
12146 #define TIM_DCR_DBL_Pos           (8U)
12147 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
12148 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
12149 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
12150 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
12151 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
12152 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
12153 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
12154 
12155 /*******************  Bit definition for TIM_DMAR register  *******************/
12156 #define TIM_DMAR_DMAB_Pos         (0U)
12157 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
12158 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
12159 
12160 /*******************  Bit definition for TIM_OR register  *********************/
12161 #define TIM_OR_TI1_RMP_Pos        (0U)
12162 #define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
12163 #define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
12164 #define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
12165 #define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
12166 #define TIM_OR_TI4_RMP_Pos        (6U)
12167 #define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
12168 #define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
12169 #define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x00000040 */
12170 #define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x00000080 */
12171 #define TIM_OR_ITR1_RMP_Pos       (10U)
12172 #define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
12173 #define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
12174 #define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000400 */
12175 #define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000800 */
12176 
12177 /******************************************************************************/
12178 /*                                                                            */
12179 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
12180 /*                                                                            */
12181 /******************************************************************************/
12182 /*******************  Bit definition for USART_SR register  *******************/
12183 #define USART_SR_PE_Pos               (0U)
12184 #define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
12185 #define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error */
12186 #define USART_SR_FE_Pos               (1U)
12187 #define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
12188 #define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error */
12189 #define USART_SR_NE_Pos               (2U)
12190 #define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
12191 #define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag */
12192 #define USART_SR_ORE_Pos              (3U)
12193 #define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
12194 #define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error */
12195 #define USART_SR_IDLE_Pos             (4U)
12196 #define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
12197 #define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected */
12198 #define USART_SR_RXNE_Pos             (5U)
12199 #define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
12200 #define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
12201 #define USART_SR_TC_Pos               (6U)
12202 #define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
12203 #define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete */
12204 #define USART_SR_TXE_Pos              (7U)
12205 #define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
12206 #define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
12207 #define USART_SR_LBD_Pos              (8U)
12208 #define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
12209 #define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag */
12210 #define USART_SR_CTS_Pos              (9U)
12211 #define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
12212 #define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag */
12213 
12214 /*******************  Bit definition for USART_DR register  *******************/
12215 #define USART_DR_DR_Pos               (0U)
12216 #define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
12217 #define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
12218 
12219 /******************  Bit definition for USART_BRR register  *******************/
12220 #define USART_BRR_DIV_Fraction_Pos    (0U)
12221 #define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
12222 #define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
12223 #define USART_BRR_DIV_Mantissa_Pos    (4U)
12224 #define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
12225 #define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
12226 
12227 /******************  Bit definition for USART_CR1 register  *******************/
12228 #define USART_CR1_SBK_Pos             (0U)
12229 #define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
12230 #define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break */
12231 #define USART_CR1_RWU_Pos             (1U)
12232 #define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
12233 #define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup */
12234 #define USART_CR1_RE_Pos              (2U)
12235 #define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
12236 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable */
12237 #define USART_CR1_TE_Pos              (3U)
12238 #define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
12239 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable */
12240 #define USART_CR1_IDLEIE_Pos          (4U)
12241 #define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
12242 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable */
12243 #define USART_CR1_RXNEIE_Pos          (5U)
12244 #define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
12245 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable */
12246 #define USART_CR1_TCIE_Pos            (6U)
12247 #define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
12248 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
12249 #define USART_CR1_TXEIE_Pos           (7U)
12250 #define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
12251 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<PE Interrupt Enable */
12252 #define USART_CR1_PEIE_Pos            (8U)
12253 #define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
12254 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable */
12255 #define USART_CR1_PS_Pos              (9U)
12256 #define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
12257 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection */
12258 #define USART_CR1_PCE_Pos             (10U)
12259 #define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
12260 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable */
12261 #define USART_CR1_WAKE_Pos            (11U)
12262 #define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
12263 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method */
12264 #define USART_CR1_M_Pos               (12U)
12265 #define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
12266 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length */
12267 #define USART_CR1_UE_Pos              (13U)
12268 #define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
12269 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable */
12270 #define USART_CR1_OVER8_Pos           (15U)
12271 #define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
12272 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable */
12273 
12274 /******************  Bit definition for USART_CR2 register  *******************/
12275 #define USART_CR2_ADD_Pos             (0U)
12276 #define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
12277 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node */
12278 #define USART_CR2_LBDL_Pos            (5U)
12279 #define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
12280 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length */
12281 #define USART_CR2_LBDIE_Pos           (6U)
12282 #define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
12283 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
12284 #define USART_CR2_LBCL_Pos            (8U)
12285 #define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
12286 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse */
12287 #define USART_CR2_CPHA_Pos            (9U)
12288 #define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
12289 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase */
12290 #define USART_CR2_CPOL_Pos            (10U)
12291 #define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
12292 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity */
12293 #define USART_CR2_CLKEN_Pos           (11U)
12294 #define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
12295 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable */
12296 
12297 #define USART_CR2_STOP_Pos            (12U)
12298 #define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
12299 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
12300 #define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
12301 #define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
12302 
12303 #define USART_CR2_LINEN_Pos           (14U)
12304 #define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
12305 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
12306 
12307 /******************  Bit definition for USART_CR3 register  *******************/
12308 #define USART_CR3_EIE_Pos             (0U)
12309 #define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
12310 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable */
12311 #define USART_CR3_IREN_Pos            (1U)
12312 #define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
12313 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable */
12314 #define USART_CR3_IRLP_Pos            (2U)
12315 #define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
12316 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power */
12317 #define USART_CR3_HDSEL_Pos           (3U)
12318 #define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
12319 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection */
12320 #define USART_CR3_NACK_Pos            (4U)
12321 #define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
12322 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable */
12323 #define USART_CR3_SCEN_Pos            (5U)
12324 #define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
12325 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable */
12326 #define USART_CR3_DMAR_Pos            (6U)
12327 #define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
12328 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver */
12329 #define USART_CR3_DMAT_Pos            (7U)
12330 #define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
12331 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter */
12332 #define USART_CR3_RTSE_Pos            (8U)
12333 #define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
12334 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable */
12335 #define USART_CR3_CTSE_Pos            (9U)
12336 #define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
12337 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable */
12338 #define USART_CR3_CTSIE_Pos           (10U)
12339 #define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
12340 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable */
12341 #define USART_CR3_ONEBIT_Pos          (11U)
12342 #define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
12343 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
12344 
12345 /******************  Bit definition for USART_GTPR register  ******************/
12346 #define USART_GTPR_PSC_Pos            (0U)
12347 #define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
12348 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
12349 #define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x00000001 */
12350 #define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x00000002 */
12351 #define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x00000004 */
12352 #define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x00000008 */
12353 #define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x00000010 */
12354 #define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x00000020 */
12355 #define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x00000040 */
12356 #define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x00000080 */
12357 
12358 #define USART_GTPR_GT_Pos             (8U)
12359 #define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
12360 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
12361 
12362 /******************************************************************************/
12363 /*                                                                            */
12364 /*                            Window WATCHDOG                                 */
12365 /*                                                                            */
12366 /******************************************************************************/
12367 /*******************  Bit definition for WWDG_CR register  ********************/
12368 #define WWDG_CR_T_Pos           (0U)
12369 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
12370 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
12371 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
12372 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
12373 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
12374 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
12375 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
12376 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
12377 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
12378 
12379 /* Legacy defines */
12380 #define  WWDG_CR_T0                          WWDG_CR_T_0
12381 #define  WWDG_CR_T1                          WWDG_CR_T_1
12382 #define  WWDG_CR_T2                          WWDG_CR_T_2
12383 #define  WWDG_CR_T3                          WWDG_CR_T_3
12384 #define  WWDG_CR_T4                          WWDG_CR_T_4
12385 #define  WWDG_CR_T5                          WWDG_CR_T_5
12386 #define  WWDG_CR_T6                          WWDG_CR_T_6
12387 #define WWDG_CR_WDGA_Pos        (7U)
12388 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
12389 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
12390 
12391 /*******************  Bit definition for WWDG_CFR register  *******************/
12392 #define WWDG_CFR_W_Pos          (0U)
12393 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
12394 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
12395 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
12396 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
12397 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
12398 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
12399 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
12400 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
12401 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
12402 
12403 /* Legacy defines */
12404 #define  WWDG_CFR_W0                         WWDG_CFR_W_0
12405 #define  WWDG_CFR_W1                         WWDG_CFR_W_1
12406 #define  WWDG_CFR_W2                         WWDG_CFR_W_2
12407 #define  WWDG_CFR_W3                         WWDG_CFR_W_3
12408 #define  WWDG_CFR_W4                         WWDG_CFR_W_4
12409 #define  WWDG_CFR_W5                         WWDG_CFR_W_5
12410 #define  WWDG_CFR_W6                         WWDG_CFR_W_6
12411 
12412 #define WWDG_CFR_WDGTB_Pos      (7U)
12413 #define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
12414 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
12415 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
12416 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
12417 
12418 /* Legacy defines */
12419 #define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
12420 #define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
12421 
12422 #define WWDG_CFR_EWI_Pos        (9U)
12423 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
12424 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
12425 
12426 /*******************  Bit definition for WWDG_SR register  ********************/
12427 #define WWDG_SR_EWIF_Pos        (0U)
12428 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
12429 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
12430 
12431 /******************************************************************************/
12432 /*                                                                            */
12433 /*                                DBG                                         */
12434 /*                                                                            */
12435 /******************************************************************************/
12436 /********************  Bit definition for DBGMCU_IDCODE register  *************/
12437 #define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)
12438 #define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
12439 #define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk
12440 #define DBGMCU_IDCODE_REV_ID_Pos                     (16U)
12441 #define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
12442 #define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk
12443 
12444 /********************  Bit definition for DBGMCU_CR register  *****************/
12445 #define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)
12446 #define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
12447 #define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk
12448 #define DBGMCU_CR_DBG_STOP_Pos                       (1U)
12449 #define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
12450 #define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk
12451 #define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)
12452 #define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
12453 #define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk
12454 #define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)
12455 #define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
12456 #define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk
12457 
12458 #define DBGMCU_CR_TRACE_MODE_Pos                     (6U)
12459 #define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
12460 #define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk
12461 #define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
12462 #define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
12463 
12464 /********************  Bit definition for DBGMCU_APB1_FZ register  ************/
12465 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)
12466 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
12467 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
12468 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)
12469 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
12470 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
12471 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)
12472 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
12473 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
12474 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)
12475 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
12476 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
12477 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)
12478 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
12479 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
12480 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)
12481 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
12482 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
12483 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)
12484 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
12485 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
12486 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)
12487 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
12488 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
12489 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)
12490 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
12491 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
12492 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)
12493 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
12494 #define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
12495 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)
12496 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
12497 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
12498 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)
12499 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
12500 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
12501 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)
12502 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
12503 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
12504 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)
12505 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
12506 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
12507 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)
12508 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
12509 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
12510 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)
12511 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
12512 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
12513 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)
12514 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
12515 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
12516 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
12517 #define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
12518 
12519 /********************  Bit definition for DBGMCU_APB2_FZ register  ************/
12520 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)
12521 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
12522 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
12523 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)
12524 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
12525 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
12526 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)
12527 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
12528 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
12529 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)
12530 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
12531 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
12532 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)
12533 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
12534 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
12535 
12536 /******************************************************************************/
12537 /*                                                                            */
12538 /*                Ethernet MAC Registers bits definitions                     */
12539 /*                                                                            */
12540 /******************************************************************************/
12541 /* Bit definition for Ethernet MAC Control Register register */
12542 #define ETH_MACCR_WD_Pos                              (23U)
12543 #define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
12544 #define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
12545 #define ETH_MACCR_JD_Pos                              (22U)
12546 #define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
12547 #define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
12548 #define ETH_MACCR_IFG_Pos                             (17U)
12549 #define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
12550 #define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
12551 #define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
12552 #define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
12553 #define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
12554 #define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
12555 #define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
12556 #define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
12557 #define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
12558 #define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
12559 #define ETH_MACCR_CSD_Pos                             (16U)
12560 #define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
12561 #define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
12562 #define ETH_MACCR_FES_Pos                             (14U)
12563 #define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
12564 #define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
12565 #define ETH_MACCR_ROD_Pos                             (13U)
12566 #define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
12567 #define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
12568 #define ETH_MACCR_LM_Pos                              (12U)
12569 #define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
12570 #define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
12571 #define ETH_MACCR_DM_Pos                              (11U)
12572 #define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
12573 #define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
12574 #define ETH_MACCR_IPCO_Pos                            (10U)
12575 #define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
12576 #define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
12577 #define ETH_MACCR_RD_Pos                              (9U)
12578 #define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
12579 #define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
12580 #define ETH_MACCR_APCS_Pos                            (7U)
12581 #define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
12582 #define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
12583 #define ETH_MACCR_BL_Pos                              (5U)
12584 #define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
12585 #define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
12586                                                        a transmission attempt during retries after a collision: 0 =< r <2^k */
12587 #define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
12588 #define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
12589 #define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
12590 #define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */
12591 #define ETH_MACCR_DC_Pos                              (4U)
12592 #define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
12593 #define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
12594 #define ETH_MACCR_TE_Pos                              (3U)
12595 #define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
12596 #define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
12597 #define ETH_MACCR_RE_Pos                              (2U)
12598 #define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
12599 #define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
12600 
12601 /* Bit definition for Ethernet MAC Frame Filter Register */
12602 #define ETH_MACFFR_RA_Pos                             (31U)
12603 #define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
12604 #define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
12605 #define ETH_MACFFR_HPF_Pos                            (10U)
12606 #define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
12607 #define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
12608 #define ETH_MACFFR_SAF_Pos                            (9U)
12609 #define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
12610 #define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
12611 #define ETH_MACFFR_SAIF_Pos                           (8U)
12612 #define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
12613 #define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */
12614 #define ETH_MACFFR_PCF_Pos                            (6U)
12615 #define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
12616 #define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
12617 #define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)
12618 #define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
12619 #define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
12620 #define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)
12621 #define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
12622 #define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
12623 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)
12624 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
12625 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
12626 #define ETH_MACFFR_BFD_Pos                            (5U)
12627 #define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
12628 #define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */
12629 #define ETH_MACFFR_PAM_Pos                            (4U)
12630 #define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
12631 #define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
12632 #define ETH_MACFFR_DAIF_Pos                           (3U)
12633 #define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
12634 #define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
12635 #define ETH_MACFFR_HM_Pos                             (2U)
12636 #define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
12637 #define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */
12638 #define ETH_MACFFR_HU_Pos                             (1U)
12639 #define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
12640 #define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
12641 #define ETH_MACFFR_PM_Pos                             (0U)
12642 #define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
12643 #define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
12644 
12645 /* Bit definition for Ethernet MAC Hash Table High Register */
12646 #define ETH_MACHTHR_HTH_Pos                           (0U)
12647 #define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
12648 #define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
12649 
12650 /* Bit definition for Ethernet MAC Hash Table Low Register */
12651 #define ETH_MACHTLR_HTL_Pos                           (0U)
12652 #define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
12653 #define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
12654 
12655 /* Bit definition for Ethernet MAC MII Address Register */
12656 #define ETH_MACMIIAR_PA_Pos                           (11U)
12657 #define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
12658 #define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
12659 #define ETH_MACMIIAR_MR_Pos                           (6U)
12660 #define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
12661 #define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
12662 #define ETH_MACMIIAR_CR_Pos                           (2U)
12663 #define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
12664 #define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
12665 #define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
12666 #define ETH_MACMIIAR_CR_Div62_Pos                     (2U)
12667 #define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
12668 #define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-120 MHz; MDC clock= HCLK/62 */
12669 #define ETH_MACMIIAR_CR_Div16_Pos                     (3U)
12670 #define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
12671 #define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
12672 #define ETH_MACMIIAR_CR_Div26_Pos                     (2U)
12673 #define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
12674 #define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/42 */
12675 #define ETH_MACMIIAR_MW_Pos                           (1U)
12676 #define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
12677 #define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
12678 #define ETH_MACMIIAR_MB_Pos                           (0U)
12679 #define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
12680 #define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy */
12681 
12682 /* Bit definition for Ethernet MAC MII Data Register */
12683 #define ETH_MACMIIDR_MD_Pos                           (0U)
12684 #define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
12685 #define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
12686 
12687 /* Bit definition for Ethernet MAC Flow Control Register */
12688 #define ETH_MACFCR_PT_Pos                             (16U)
12689 #define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
12690 #define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
12691 #define ETH_MACFCR_ZQPD_Pos                           (7U)
12692 #define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
12693 #define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
12694 #define ETH_MACFCR_PLT_Pos                            (4U)
12695 #define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
12696 #define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
12697 #define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times */
12698 #define ETH_MACFCR_PLT_Minus28_Pos                    (4U)
12699 #define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
12700 #define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
12701 #define ETH_MACFCR_PLT_Minus144_Pos                   (5U)
12702 #define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
12703 #define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
12704 #define ETH_MACFCR_PLT_Minus256_Pos                   (4U)
12705 #define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
12706 #define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
12707 #define ETH_MACFCR_UPFD_Pos                           (3U)
12708 #define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
12709 #define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
12710 #define ETH_MACFCR_RFCE_Pos                           (2U)
12711 #define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
12712 #define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
12713 #define ETH_MACFCR_TFCE_Pos                           (1U)
12714 #define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
12715 #define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
12716 #define ETH_MACFCR_FCBBPA_Pos                         (0U)
12717 #define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
12718 #define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
12719 
12720 /* Bit definition for Ethernet MAC VLAN Tag Register */
12721 #define ETH_MACVLANTR_VLANTC_Pos                      (16U)
12722 #define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
12723 #define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
12724 #define ETH_MACVLANTR_VLANTI_Pos                      (0U)
12725 #define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
12726 #define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
12727 
12728 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
12729 #define ETH_MACRWUFFR_D_Pos                           (0U)
12730 #define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
12731 #define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
12732 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
12733    Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
12734 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
12735    Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
12736    Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
12737    Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
12738    Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
12739                               RSVD - Filter1 Command - RSVD - Filter0 Command
12740    Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
12741    Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
12742    Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
12743 
12744 /* Bit definition for Ethernet MAC PMT Control and Status Register */
12745 #define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)
12746 #define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
12747 #define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
12748 #define ETH_MACPMTCSR_GU_Pos                          (9U)
12749 #define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
12750 #define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast */
12751 #define ETH_MACPMTCSR_WFR_Pos                         (6U)
12752 #define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
12753 #define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received */
12754 #define ETH_MACPMTCSR_MPR_Pos                         (5U)
12755 #define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
12756 #define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received */
12757 #define ETH_MACPMTCSR_WFE_Pos                         (2U)
12758 #define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
12759 #define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable */
12760 #define ETH_MACPMTCSR_MPE_Pos                         (1U)
12761 #define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
12762 #define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable */
12763 #define ETH_MACPMTCSR_PD_Pos                          (0U)
12764 #define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
12765 #define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down */
12766 
12767 /* Bit definition for Ethernet MAC debug Register */
12768 #define ETH_MACDBGR_TFF_Pos                           (25U)
12769 #define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
12770 #define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
12771 #define ETH_MACDBGR_TFNE_Pos                          (24U)
12772 #define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
12773 #define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
12774 #define ETH_MACDBGR_TFWA_Pos                          (22U)
12775 #define ETH_MACDBGR_TFWA_Msk                          (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
12776 #define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */
12777 #define ETH_MACDBGR_TFRS_Pos                          (20U)
12778 #define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
12779 #define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
12780 #define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)
12781 #define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
12782 #define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
12783 #define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)
12784 #define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
12785 #define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
12786 #define ETH_MACDBGR_TFRS_READ_Pos                     (20U)
12787 #define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
12788 #define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
12789 #define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
12790 #define ETH_MACDBGR_MTP_Pos                           (19U)
12791 #define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
12792 #define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
12793 #define ETH_MACDBGR_MTFCS_Pos                         (17U)
12794 #define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
12795 #define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
12796 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)
12797 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
12798 #define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
12799 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)
12800 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
12801 #define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
12802 #define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)
12803 #define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
12804 #define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
12805 #define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
12806 #define ETH_MACDBGR_MMTEA_Pos                         (16U)
12807 #define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
12808 #define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
12809 #define ETH_MACDBGR_RFFL_Pos                          (8U)
12810 #define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
12811 #define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
12812 #define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)
12813 #define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
12814 #define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
12815 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)
12816 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
12817 #define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
12818 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)
12819 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
12820 #define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
12821 #define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
12822 #define ETH_MACDBGR_RFRCS_Pos                         (5U)
12823 #define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
12824 #define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
12825 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)
12826 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
12827 #define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
12828 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)
12829 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
12830 #define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
12831 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)
12832 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
12833 #define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
12834 #define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
12835 #define ETH_MACDBGR_RFWRA_Pos                         (4U)
12836 #define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
12837 #define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
12838 #define ETH_MACDBGR_MSFRWCS_Pos                       (1U)
12839 #define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
12840 #define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
12841 #define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
12842 #define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
12843 #define ETH_MACDBGR_MMRPEA_Pos                        (0U)
12844 #define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
12845 #define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
12846 
12847 /* Bit definition for Ethernet MAC Status Register */
12848 #define ETH_MACSR_TSTS_Pos                            (9U)
12849 #define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
12850 #define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
12851 #define ETH_MACSR_MMCTS_Pos                           (6U)
12852 #define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
12853 #define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status */
12854 #define ETH_MACSR_MMMCRS_Pos                          (5U)
12855 #define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
12856 #define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status */
12857 #define ETH_MACSR_MMCS_Pos                            (4U)
12858 #define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
12859 #define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status */
12860 #define ETH_MACSR_PMTS_Pos                            (3U)
12861 #define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
12862 #define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status */
12863 
12864 /* Bit definition for Ethernet MAC Interrupt Mask Register */
12865 #define ETH_MACIMR_TSTIM_Pos                          (9U)
12866 #define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
12867 #define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
12868 #define ETH_MACIMR_PMTIM_Pos                          (3U)
12869 #define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
12870 #define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask */
12871 
12872 /* Bit definition for Ethernet MAC Address0 High Register */
12873 #define ETH_MACA0HR_MACA0H_Pos                        (0U)
12874 #define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
12875 #define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
12876 
12877 /* Bit definition for Ethernet MAC Address0 Low Register */
12878 #define ETH_MACA0LR_MACA0L_Pos                        (0U)
12879 #define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
12880 #define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
12881 
12882 /* Bit definition for Ethernet MAC Address1 High Register */
12883 #define ETH_MACA1HR_AE_Pos                            (31U)
12884 #define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
12885 #define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
12886 #define ETH_MACA1HR_SA_Pos                            (30U)
12887 #define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
12888 #define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
12889 #define ETH_MACA1HR_MBC_Pos                           (24U)
12890 #define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
12891 #define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
12892 #define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
12893 #define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */
12894 #define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
12895 #define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
12896 #define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */
12897 #define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0] */
12898 #define ETH_MACA1HR_MACA1H_Pos                        (0U)
12899 #define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
12900 #define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
12901 
12902 /* Bit definition for Ethernet MAC Address1 Low Register */
12903 #define ETH_MACA1LR_MACA1L_Pos                        (0U)
12904 #define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
12905 #define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
12906 
12907 /* Bit definition for Ethernet MAC Address2 High Register */
12908 #define ETH_MACA2HR_AE_Pos                            (31U)
12909 #define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
12910 #define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
12911 #define ETH_MACA2HR_SA_Pos                            (30U)
12912 #define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
12913 #define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
12914 #define ETH_MACA2HR_MBC_Pos                           (24U)
12915 #define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
12916 #define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
12917 #define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
12918 #define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */
12919 #define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
12920 #define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
12921 #define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */
12922 #define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70] */
12923 #define ETH_MACA2HR_MACA2H_Pos                        (0U)
12924 #define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
12925 #define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
12926 
12927 /* Bit definition for Ethernet MAC Address2 Low Register */
12928 #define ETH_MACA2LR_MACA2L_Pos                        (0U)
12929 #define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
12930 #define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
12931 
12932 /* Bit definition for Ethernet MAC Address3 High Register */
12933 #define ETH_MACA3HR_AE_Pos                            (31U)
12934 #define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
12935 #define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
12936 #define ETH_MACA3HR_SA_Pos                            (30U)
12937 #define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
12938 #define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
12939 #define ETH_MACA3HR_MBC_Pos                           (24U)
12940 #define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
12941 #define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
12942 #define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
12943 #define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0] */
12944 #define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
12945 #define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
12946 #define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8] */
12947 #define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70] */
12948 #define ETH_MACA3HR_MACA3H_Pos                        (0U)
12949 #define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
12950 #define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
12951 
12952 /* Bit definition for Ethernet MAC Address3 Low Register */
12953 #define ETH_MACA3LR_MACA3L_Pos                        (0U)
12954 #define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
12955 #define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
12956 
12957 /******************************************************************************/
12958 /*                Ethernet MMC Registers bits definition                      */
12959 /******************************************************************************/
12960 
12961 /* Bit definition for Ethernet MMC Control Register */
12962 #define ETH_MMCCR_MCFHP_Pos                           (5U)
12963 #define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
12964 #define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
12965 #define ETH_MMCCR_MCP_Pos                             (4U)
12966 #define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
12967 #define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset */
12968 #define ETH_MMCCR_MCF_Pos                             (3U)
12969 #define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
12970 #define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze */
12971 #define ETH_MMCCR_ROR_Pos                             (2U)
12972 #define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
12973 #define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read */
12974 #define ETH_MMCCR_CSR_Pos                             (1U)
12975 #define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
12976 #define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover */
12977 #define ETH_MMCCR_CR_Pos                              (0U)
12978 #define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
12979 #define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset */
12980 
12981 /* Bit definition for Ethernet MMC Receive Interrupt Register */
12982 #define ETH_MMCRIR_RGUFS_Pos                          (17U)
12983 #define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
12984 #define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
12985 #define ETH_MMCRIR_RFAES_Pos                          (6U)
12986 #define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
12987 #define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
12988 #define ETH_MMCRIR_RFCES_Pos                          (5U)
12989 #define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
12990 #define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
12991 
12992 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
12993 #define ETH_MMCTIR_TGFS_Pos                           (21U)
12994 #define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
12995 #define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
12996 #define ETH_MMCTIR_TGFMSCS_Pos                        (15U)
12997 #define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
12998 #define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
12999 #define ETH_MMCTIR_TGFSCS_Pos                         (14U)
13000 #define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
13001 #define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
13002 
13003 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
13004 #define ETH_MMCRIMR_RGUFM_Pos                         (17U)
13005 #define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
13006 #define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
13007 #define ETH_MMCRIMR_RFAEM_Pos                         (6U)
13008 #define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
13009 #define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when Rx alignment error counter reaches half the maximum value */
13010 #define ETH_MMCRIMR_RFCEM_Pos                         (5U)
13011 #define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
13012 #define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
13013 
13014 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
13015 #define ETH_MMCTIMR_TGFM_Pos                          (21U)
13016 #define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
13017 #define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
13018 #define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)
13019 #define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
13020 #define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
13021 #define ETH_MMCTIMR_TGFSCM_Pos                        (14U)
13022 #define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
13023 #define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
13024 
13025 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
13026 #define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)
13027 #define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
13028 #define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
13029 
13030 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
13031 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)
13032 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
13033 #define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
13034 
13035 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
13036 #define ETH_MMCTGFCR_TGFC_Pos                         (0U)
13037 #define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
13038 #define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
13039 
13040 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
13041 #define ETH_MMCRFCECR_RFCEC_Pos                       (0U)
13042 #define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
13043 #define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
13044 
13045 /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
13046 #define ETH_MMCRFAECR_RFAEC_Pos                       (0U)
13047 #define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
13048 #define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
13049 
13050 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
13051 #define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)
13052 #define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
13053 #define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
13054 
13055 /******************************************************************************/
13056 /*               Ethernet PTP Registers bits definition                       */
13057 /******************************************************************************/
13058 
13059 /* Bit definition for Ethernet PTP Time Stamp Control Register */
13060 #define ETH_PTPTSCR_TSCNT_Pos                         (16U)
13061 #define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
13062 #define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
13063 #define ETH_PTPTSSR_TSSMRME_Pos                       (15U)
13064 #define ETH_PTPTSSR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
13065 #define ETH_PTPTSSR_TSSMRME                           ETH_PTPTSSR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
13066 #define ETH_PTPTSSR_TSSEME_Pos                        (14U)
13067 #define ETH_PTPTSSR_TSSEME_Msk                        (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
13068 #define ETH_PTPTSSR_TSSEME                            ETH_PTPTSSR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
13069 #define ETH_PTPTSSR_TSSIPV4FE_Pos                     (13U)
13070 #define ETH_PTPTSSR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
13071 #define ETH_PTPTSSR_TSSIPV4FE                         ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
13072 #define ETH_PTPTSSR_TSSIPV6FE_Pos                     (12U)
13073 #define ETH_PTPTSSR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
13074 #define ETH_PTPTSSR_TSSIPV6FE                         ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
13075 #define ETH_PTPTSSR_TSSPTPOEFE_Pos                    (11U)
13076 #define ETH_PTPTSSR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
13077 #define ETH_PTPTSSR_TSSPTPOEFE                        ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
13078 #define ETH_PTPTSSR_TSPTPPSV2E_Pos                    (10U)
13079 #define ETH_PTPTSSR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
13080 #define ETH_PTPTSSR_TSPTPPSV2E                        ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
13081 #define ETH_PTPTSSR_TSSSR_Pos                         (9U)
13082 #define ETH_PTPTSSR_TSSSR_Msk                         (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
13083 #define ETH_PTPTSSR_TSSSR                             ETH_PTPTSSR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
13084 #define ETH_PTPTSSR_TSSARFE_Pos                       (8U)
13085 #define ETH_PTPTSSR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
13086 #define ETH_PTPTSSR_TSSARFE                           ETH_PTPTSSR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
13087 
13088 #define ETH_PTPTSCR_TSARU_Pos                         (5U)
13089 #define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
13090 #define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
13091 #define ETH_PTPTSCR_TSITE_Pos                         (4U)
13092 #define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
13093 #define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
13094 #define ETH_PTPTSCR_TSSTU_Pos                         (3U)
13095 #define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
13096 #define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
13097 #define ETH_PTPTSCR_TSSTI_Pos                         (2U)
13098 #define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
13099 #define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
13100 #define ETH_PTPTSCR_TSFCU_Pos                         (1U)
13101 #define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
13102 #define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
13103 #define ETH_PTPTSCR_TSE_Pos                           (0U)
13104 #define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
13105 #define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
13106 
13107 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
13108 #define ETH_PTPSSIR_STSSI_Pos                         (0U)
13109 #define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
13110 #define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
13111 
13112 /* Bit definition for Ethernet PTP Time Stamp High Register */
13113 #define ETH_PTPTSHR_STS_Pos                           (0U)
13114 #define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
13115 #define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
13116 
13117 /* Bit definition for Ethernet PTP Time Stamp Low Register */
13118 #define ETH_PTPTSLR_STPNS_Pos                         (31U)
13119 #define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
13120 #define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
13121 #define ETH_PTPTSLR_STSS_Pos                          (0U)
13122 #define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
13123 #define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
13124 
13125 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
13126 #define ETH_PTPTSHUR_TSUS_Pos                         (0U)
13127 #define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
13128 #define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
13129 
13130 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
13131 #define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)
13132 #define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
13133 #define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
13134 #define ETH_PTPTSLUR_TSUSS_Pos                        (0U)
13135 #define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
13136 #define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
13137 
13138 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
13139 #define ETH_PTPTSAR_TSA_Pos                           (0U)
13140 #define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
13141 #define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
13142 
13143 /* Bit definition for Ethernet PTP Target Time High Register */
13144 #define ETH_PTPTTHR_TTSH_Pos                          (0U)
13145 #define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
13146 #define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
13147 
13148 /* Bit definition for Ethernet PTP Target Time Low Register */
13149 #define ETH_PTPTTLR_TTSL_Pos                          (0U)
13150 #define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
13151 #define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
13152 
13153 /* Bit definition for Ethernet PTP Time Stamp Status Register */
13154 #define ETH_PTPTSSR_TSTTR_Pos                         (5U)
13155 #define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
13156 #define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
13157 #define ETH_PTPTSSR_TSSO_Pos                          (4U)
13158 #define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
13159 #define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
13160 
13161 /******************************************************************************/
13162 /*                 Ethernet DMA Registers bits definition                     */
13163 /******************************************************************************/
13164 
13165 /* Bit definition for Ethernet DMA Bus Mode Register */
13166 #define ETH_DMABMR_AAB_Pos                            (25U)
13167 #define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
13168 #define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
13169 #define ETH_DMABMR_FPM_Pos                            (24U)
13170 #define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
13171 #define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
13172 #define ETH_DMABMR_USP_Pos                            (23U)
13173 #define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
13174 #define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
13175 #define ETH_DMABMR_RDP_Pos                            (17U)
13176 #define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
13177 #define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
13178 #define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
13179 #define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
13180 #define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13181 #define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13182 #define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13183 #define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13184 #define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
13185 #define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
13186 #define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
13187 #define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
13188 #define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
13189 #define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
13190 #define ETH_DMABMR_FB_Pos                             (16U)
13191 #define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
13192 #define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
13193 #define ETH_DMABMR_RTPR_Pos                           (14U)
13194 #define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
13195 #define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
13196 #define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
13197 #define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
13198 #define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
13199 #define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */
13200 #define ETH_DMABMR_PBL_Pos                            (8U)
13201 #define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
13202 #define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
13203 #define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
13204 #define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
13205 #define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13206 #define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13207 #define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13208 #define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13209 #define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
13210 #define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
13211 #define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
13212 #define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
13213 #define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
13214 #define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
13215 #define ETH_DMABMR_EDE_Pos                            (7U)
13216 #define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
13217 #define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
13218 #define ETH_DMABMR_DSL_Pos                            (2U)
13219 #define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
13220 #define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
13221 #define ETH_DMABMR_DA_Pos                             (1U)
13222 #define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
13223 #define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
13224 #define ETH_DMABMR_SR_Pos                             (0U)
13225 #define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
13226 #define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
13227 
13228 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
13229 #define ETH_DMATPDR_TPD_Pos                           (0U)
13230 #define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
13231 #define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
13232 
13233 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
13234 #define ETH_DMARPDR_RPD_Pos                           (0U)
13235 #define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
13236 #define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
13237 
13238 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
13239 #define ETH_DMARDLAR_SRL_Pos                          (0U)
13240 #define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
13241 #define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
13242 
13243 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
13244 #define ETH_DMATDLAR_STL_Pos                          (0U)
13245 #define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
13246 #define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
13247 
13248 /* Bit definition for Ethernet DMA Status Register */
13249 #define ETH_DMASR_TSTS_Pos                            (29U)
13250 #define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
13251 #define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
13252 #define ETH_DMASR_PMTS_Pos                            (28U)
13253 #define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
13254 #define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
13255 #define ETH_DMASR_MMCS_Pos                            (27U)
13256 #define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
13257 #define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
13258 #define ETH_DMASR_EBS_Pos                             (23U)
13259 #define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
13260 #define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
13261   /* combination with EBS[2:0] for GetFlagStatus function */
13262 #define ETH_DMASR_EBS_DescAccess_Pos                  (25U)
13263 #define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
13264 #define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
13265 #define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)
13266 #define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
13267 #define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
13268 #define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)
13269 #define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
13270 #define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
13271 #define ETH_DMASR_TPS_Pos                             (20U)
13272 #define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
13273 #define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
13274 #define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
13275 #define ETH_DMASR_TPS_Fetching_Pos                    (20U)
13276 #define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
13277 #define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
13278 #define ETH_DMASR_TPS_Waiting_Pos                     (21U)
13279 #define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
13280 #define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
13281 #define ETH_DMASR_TPS_Reading_Pos                     (20U)
13282 #define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
13283 #define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
13284 #define ETH_DMASR_TPS_Suspended_Pos                   (21U)
13285 #define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
13286 #define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
13287 #define ETH_DMASR_TPS_Closing_Pos                     (20U)
13288 #define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
13289 #define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
13290 #define ETH_DMASR_RPS_Pos                             (17U)
13291 #define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
13292 #define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
13293 #define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
13294 #define ETH_DMASR_RPS_Fetching_Pos                    (17U)
13295 #define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
13296 #define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
13297 #define ETH_DMASR_RPS_Waiting_Pos                     (17U)
13298 #define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
13299 #define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
13300 #define ETH_DMASR_RPS_Suspended_Pos                   (19U)
13301 #define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
13302 #define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
13303 #define ETH_DMASR_RPS_Closing_Pos                     (17U)
13304 #define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
13305 #define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
13306 #define ETH_DMASR_RPS_Queuing_Pos                     (17U)
13307 #define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
13308 #define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
13309 #define ETH_DMASR_NIS_Pos                             (16U)
13310 #define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
13311 #define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
13312 #define ETH_DMASR_AIS_Pos                             (15U)
13313 #define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
13314 #define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
13315 #define ETH_DMASR_ERS_Pos                             (14U)
13316 #define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
13317 #define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
13318 #define ETH_DMASR_FBES_Pos                            (13U)
13319 #define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
13320 #define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
13321 #define ETH_DMASR_ETS_Pos                             (10U)
13322 #define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
13323 #define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
13324 #define ETH_DMASR_RWTS_Pos                            (9U)
13325 #define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
13326 #define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
13327 #define ETH_DMASR_RPSS_Pos                            (8U)
13328 #define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
13329 #define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
13330 #define ETH_DMASR_RBUS_Pos                            (7U)
13331 #define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
13332 #define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
13333 #define ETH_DMASR_RS_Pos                              (6U)
13334 #define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
13335 #define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
13336 #define ETH_DMASR_TUS_Pos                             (5U)
13337 #define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
13338 #define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
13339 #define ETH_DMASR_ROS_Pos                             (4U)
13340 #define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
13341 #define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
13342 #define ETH_DMASR_TJTS_Pos                            (3U)
13343 #define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
13344 #define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
13345 #define ETH_DMASR_TBUS_Pos                            (2U)
13346 #define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
13347 #define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
13348 #define ETH_DMASR_TPSS_Pos                            (1U)
13349 #define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
13350 #define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
13351 #define ETH_DMASR_TS_Pos                              (0U)
13352 #define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
13353 #define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
13354 
13355 /* Bit definition for Ethernet DMA Operation Mode Register */
13356 #define ETH_DMAOMR_DTCEFD_Pos                         (26U)
13357 #define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
13358 #define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
13359 #define ETH_DMAOMR_RSF_Pos                            (25U)
13360 #define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
13361 #define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
13362 #define ETH_DMAOMR_DFRF_Pos                           (24U)
13363 #define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
13364 #define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
13365 #define ETH_DMAOMR_TSF_Pos                            (21U)
13366 #define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
13367 #define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
13368 #define ETH_DMAOMR_FTF_Pos                            (20U)
13369 #define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
13370 #define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
13371 #define ETH_DMAOMR_TTC_Pos                            (14U)
13372 #define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
13373 #define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
13374 #define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
13375 #define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
13376 #define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
13377 #define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
13378 #define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
13379 #define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
13380 #define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
13381 #define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
13382 #define ETH_DMAOMR_ST_Pos                             (13U)
13383 #define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
13384 #define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
13385 #define ETH_DMAOMR_FEF_Pos                            (7U)
13386 #define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
13387 #define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
13388 #define ETH_DMAOMR_FUGF_Pos                           (6U)
13389 #define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
13390 #define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
13391 #define ETH_DMAOMR_RTC_Pos                            (3U)
13392 #define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
13393 #define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
13394 #define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
13395 #define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
13396 #define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
13397 #define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
13398 #define ETH_DMAOMR_OSF_Pos                            (2U)
13399 #define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
13400 #define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
13401 #define ETH_DMAOMR_SR_Pos                             (1U)
13402 #define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
13403 #define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
13404 
13405 /* Bit definition for Ethernet DMA Interrupt Enable Register */
13406 #define ETH_DMAIER_NISE_Pos                           (16U)
13407 #define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
13408 #define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
13409 #define ETH_DMAIER_AISE_Pos                           (15U)
13410 #define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
13411 #define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
13412 #define ETH_DMAIER_ERIE_Pos                           (14U)
13413 #define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
13414 #define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
13415 #define ETH_DMAIER_FBEIE_Pos                          (13U)
13416 #define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
13417 #define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
13418 #define ETH_DMAIER_ETIE_Pos                           (10U)
13419 #define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
13420 #define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
13421 #define ETH_DMAIER_RWTIE_Pos                          (9U)
13422 #define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
13423 #define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
13424 #define ETH_DMAIER_RPSIE_Pos                          (8U)
13425 #define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
13426 #define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
13427 #define ETH_DMAIER_RBUIE_Pos                          (7U)
13428 #define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
13429 #define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
13430 #define ETH_DMAIER_RIE_Pos                            (6U)
13431 #define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
13432 #define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
13433 #define ETH_DMAIER_TUIE_Pos                           (5U)
13434 #define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
13435 #define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
13436 #define ETH_DMAIER_ROIE_Pos                           (4U)
13437 #define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
13438 #define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
13439 #define ETH_DMAIER_TJTIE_Pos                          (3U)
13440 #define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
13441 #define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
13442 #define ETH_DMAIER_TBUIE_Pos                          (2U)
13443 #define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
13444 #define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
13445 #define ETH_DMAIER_TPSIE_Pos                          (1U)
13446 #define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
13447 #define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
13448 #define ETH_DMAIER_TIE_Pos                            (0U)
13449 #define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
13450 #define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
13451 
13452 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
13453 #define ETH_DMAMFBOCR_OFOC_Pos                        (28U)
13454 #define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
13455 #define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
13456 #define ETH_DMAMFBOCR_MFA_Pos                         (17U)
13457 #define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
13458 #define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
13459 #define ETH_DMAMFBOCR_OMFC_Pos                        (16U)
13460 #define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
13461 #define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
13462 #define ETH_DMAMFBOCR_MFC_Pos                         (0U)
13463 #define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
13464 #define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
13465 
13466 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
13467 #define ETH_DMACHTDR_HTDAP_Pos                        (0U)
13468 #define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
13469 #define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
13470 
13471 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
13472 #define ETH_DMACHRDR_HRDAP_Pos                        (0U)
13473 #define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
13474 #define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
13475 
13476 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
13477 #define ETH_DMACHTBAR_HTBAP_Pos                       (0U)
13478 #define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
13479 #define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
13480 
13481 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
13482 #define ETH_DMACHRBAR_HRBAP_Pos                       (0U)
13483 #define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
13484 #define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
13485 
13486 /******************************************************************************/
13487 /*                                                                            */
13488 /*                                       USB_OTG			                        */
13489 /*                                                                            */
13490 /******************************************************************************/
13491 /********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
13492 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
13493 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
13494 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
13495 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
13496 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
13497 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
13498 #define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
13499 #define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
13500 #define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
13501 #define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
13502 #define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
13503 #define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
13504 #define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
13505 #define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
13506 #define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
13507 #define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
13508 #define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
13509 #define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
13510 #define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
13511 #define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
13512 #define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
13513 #define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
13514 #define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
13515 #define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
13516 #define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
13517 #define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
13518 #define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid */
13519 #define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)
13520 #define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
13521 #define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */
13522 
13523 /********************  Bit definition for USB_OTG_HCFG register  ********************/
13524 
13525 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
13526 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
13527 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */
13528 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
13529 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
13530 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
13531 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
13532 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
13533 
13534 /********************  Bit definition for USB_OTG_DCFG register  ********************/
13535 
13536 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
13537 #define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
13538 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
13539 #define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
13540 #define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
13541 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
13542 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
13543 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
13544 
13545 #define USB_OTG_DCFG_DAD_Pos                     (4U)
13546 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
13547 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
13548 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
13549 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
13550 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
13551 #define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
13552 #define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
13553 #define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
13554 #define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
13555 
13556 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
13557 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
13558 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
13559 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
13560 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
13561 
13562 #define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
13563 #define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
13564 #define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
13565 
13566 #define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
13567 #define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
13568 #define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
13569 
13570 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
13571 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
13572 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
13573 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
13574 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
13575 
13576 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
13577 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
13578 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
13579 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
13580 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
13581 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
13582 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
13583 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
13584 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
13585 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
13586 
13587 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
13588 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
13589 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
13590 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */
13591 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
13592 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
13593 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */
13594 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
13595 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
13596 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
13597 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
13598 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
13599 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */
13600 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
13601 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
13602 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */
13603 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
13604 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
13605 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */
13606 
13607 /********************  Bit definition for USB_OTG_DCTL register  ********************/
13608 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
13609 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
13610 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
13611 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
13612 #define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
13613 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */
13614 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
13615 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
13616 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */
13617 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
13618 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
13619 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */
13620 
13621 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
13622 #define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
13623 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
13624 #define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
13625 #define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
13626 #define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
13627 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
13628 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
13629 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */
13630 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
13631 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
13632 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */
13633 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
13634 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
13635 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */
13636 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
13637 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
13638 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */
13639 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
13640 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
13641 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
13642 
13643 /********************  Bit definition for USB_OTG_HFIR register  ********************/
13644 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
13645 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
13646 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
13647 
13648 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
13649 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
13650 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
13651 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */
13652 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
13653 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
13654 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
13655 
13656 /********************  Bit definition for USB_OTG_DSTS register  ********************/
13657 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
13658 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
13659 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */
13660 
13661 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
13662 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
13663 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
13664 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
13665 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
13666 #define USB_OTG_DSTS_EERR_Pos                    (3U)
13667 #define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
13668 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */
13669 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
13670 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
13671 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
13672 
13673 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
13674 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
13675 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
13676 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
13677 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
13678 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
13679 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
13680 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
13681 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
13682 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
13683 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
13684 #define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
13685 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
13686 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
13687 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
13688 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
13689 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
13690 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
13691 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
13692 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
13693 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
13694 
13695 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
13696 
13697 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
13698 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
13699 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
13700 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
13701 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
13702 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
13703 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
13704 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
13705 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
13706 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
13707 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
13708 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
13709 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
13710 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
13711 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
13712 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
13713 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
13714 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
13715 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
13716 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
13717 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
13718 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
13719 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
13720 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
13721 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
13722 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
13723 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
13724 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */
13725 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
13726 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
13727 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */
13728 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
13729 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
13730 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */
13731 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
13732 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
13733 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
13734 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
13735 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
13736 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
13737 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
13738 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
13739 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
13740 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
13741 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
13742 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */
13743 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
13744 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
13745 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */
13746 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
13747 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
13748 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */
13749 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
13750 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
13751 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */
13752 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
13753 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
13754 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */
13755 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
13756 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
13757 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */
13758 
13759 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
13760 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
13761 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
13762 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */
13763 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
13764 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
13765 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */
13766 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
13767 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
13768 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
13769 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
13770 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
13771 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */
13772 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
13773 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
13774 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */
13775 
13776 
13777 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
13778 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
13779 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
13780 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
13781 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
13782 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
13783 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
13784 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
13785 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
13786 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
13787 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
13788 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
13789 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
13790 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
13791 
13792 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
13793 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
13794 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13795 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
13796 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
13797 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
13798 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
13799 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
13800 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
13801 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
13802 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
13803 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
13804 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
13805 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
13806 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
13807 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */
13808 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
13809 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
13810 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */
13811 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
13812 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
13813 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */
13814 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
13815 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
13816 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */
13817 
13818 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
13819 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
13820 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
13821 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */
13822 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
13823 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
13824 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
13825 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
13826 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
13827 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
13828 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
13829 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
13830 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
13831 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
13832 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
13833 
13834 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
13835 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
13836 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
13837 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
13838 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
13839 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
13840 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
13841 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
13842 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
13843 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
13844 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
13845 
13846 /********************  Bit definition for USB_OTG_HAINT register  ********************/
13847 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
13848 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
13849 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
13850 
13851 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
13852 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
13853 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
13854 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
13855 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
13856 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
13857 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
13858 #define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
13859 #define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
13860 #define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
13861 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
13862 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
13863 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */
13864 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
13865 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
13866 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
13867 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
13868 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
13869 #define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
13870 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
13871 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
13872 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */
13873 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
13874 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
13875 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */
13876 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
13877 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
13878 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */
13879 #define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
13880 #define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
13881 #define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
13882 #define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
13883 #define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
13884 #define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
13885 #define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
13886 #define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
13887 #define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
13888 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
13889 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
13890 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
13891 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */
13892 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
13893 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
13894 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */
13895 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
13896 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
13897 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */
13898 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
13899 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
13900 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */
13901 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
13902 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
13903 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */
13904 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
13905 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
13906 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */
13907 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
13908 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
13909 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */
13910 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
13911 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
13912 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
13913 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
13914 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
13915 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */
13916 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
13917 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
13918 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */
13919 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
13920 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
13921 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */
13922 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
13923 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
13924 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */
13925 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
13926 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
13927 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */
13928 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
13929 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
13930 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */
13931 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
13932 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
13933 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */
13934 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
13935 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
13936 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */
13937 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
13938 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
13939 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */
13940 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
13941 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
13942 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
13943 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
13944 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
13945 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
13946 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
13947 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
13948 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */
13949 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
13950 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
13951 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */
13952 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
13953 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
13954 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */
13955 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
13956 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
13957 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */
13958 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
13959 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
13960 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */
13961 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
13962 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
13963 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
13964 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
13965 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
13966 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */
13967 
13968 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
13969 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
13970 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
13971 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */
13972 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
13973 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
13974 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */
13975 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
13976 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
13977 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */
13978 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
13979 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
13980 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */
13981 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
13982 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
13983 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */
13984 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
13985 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
13986 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
13987 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
13988 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
13989 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
13990 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
13991 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
13992 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */
13993 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
13994 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
13995 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */
13996 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
13997 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
13998 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */
13999 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
14000 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
14001 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */
14002 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
14003 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
14004 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */
14005 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
14006 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
14007 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */
14008 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
14009 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
14010 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */
14011 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
14012 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
14013 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */
14014 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
14015 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
14016 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */
14017 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
14018 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
14019 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
14020 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
14021 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
14022 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
14023 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
14024 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
14025 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */
14026 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
14027 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
14028 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */
14029 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
14030 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
14031 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */
14032 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
14033 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
14034 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */
14035 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
14036 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
14037 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */
14038 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
14039 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
14040 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */
14041 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
14042 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
14043 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
14044 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
14045 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
14046 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */
14047 
14048 /********************  Bit definition for USB_OTG_DAINT register  ********************/
14049 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
14050 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
14051 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */
14052 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
14053 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
14054 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
14055 
14056 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
14057 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
14058 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
14059 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
14060 
14061 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
14062 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
14063 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
14064 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */
14065 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
14066 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
14067 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
14068 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
14069 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
14070 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
14071 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
14072 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
14073 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
14074 
14075 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
14076 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
14077 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
14078 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
14079 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
14080 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
14081 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
14082 
14083 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
14084 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
14085 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
14086 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
14087 
14088 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
14089 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
14090 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
14091 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
14092 
14093 /********************  Bit definition for OTG register  ********************/
14094 #define USB_OTG_NPTXFSA_Pos                      (0U)
14095 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
14096 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
14097 #define USB_OTG_NPTXFD_Pos                       (16U)
14098 #define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
14099 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
14100 #define USB_OTG_TX0FSA_Pos                       (0U)
14101 #define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
14102 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
14103 #define USB_OTG_TX0FD_Pos                        (16U)
14104 #define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
14105 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
14106 
14107 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
14108 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
14109 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
14110 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
14111 
14112 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
14113 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
14114 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
14115 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
14116 
14117 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
14118 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
14119 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
14120 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
14121 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
14122 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
14123 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
14124 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
14125 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
14126 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
14127 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
14128 
14129 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
14130 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
14131 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
14132 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
14133 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
14134 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
14135 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
14136 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
14137 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
14138 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
14139 
14140 /********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
14141 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
14142 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
14143 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
14144 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
14145 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
14146 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
14147 
14148 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
14149 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
14150 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
14151 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
14152 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
14153 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
14154 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
14155 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
14156 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
14157 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
14158 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
14159 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
14160 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
14161 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
14162 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
14163 
14164 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
14165 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
14166 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
14167 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
14168 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
14169 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
14170 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
14171 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
14172 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
14173 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
14174 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
14175 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
14176 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
14177 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
14178 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
14179 
14180 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
14181 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
14182 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
14183 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
14184 
14185 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
14186 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
14187 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
14188 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
14189 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
14190 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
14191 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
14192 
14193 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
14194 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
14195 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
14196 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
14197 #define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)
14198 #define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
14199 #define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface */
14200 #define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)
14201 #define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
14202 #define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */
14203 #define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)
14204 #define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
14205 #define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */
14206 #define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)
14207 #define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
14208 #define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */
14209 #define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)
14210 #define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
14211 #define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option */
14212 
14213 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
14214 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
14215 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
14216 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
14217 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
14218 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
14219 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
14220 
14221 /********************  Bit definition for USB_OTG_CID register  ********************/
14222 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
14223 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
14224 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
14225 
14226 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
14227 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
14228 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14229 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
14230 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
14231 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14232 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14233 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
14234 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14235 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
14236 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
14237 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14238 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14239 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
14240 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14241 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14242 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
14243 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14244 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14245 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
14246 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14247 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
14248 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
14249 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14250 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
14251 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
14252 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14253 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
14254 
14255 /********************  Bit definition for USB_OTG_HPRT register  ********************/
14256 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
14257 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
14258 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */
14259 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
14260 #define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
14261 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */
14262 #define USB_OTG_HPRT_PENA_Pos                    (2U)
14263 #define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
14264 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */
14265 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
14266 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
14267 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
14268 #define USB_OTG_HPRT_POCA_Pos                    (4U)
14269 #define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
14270 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */
14271 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
14272 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
14273 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */
14274 #define USB_OTG_HPRT_PRES_Pos                    (6U)
14275 #define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
14276 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */
14277 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
14278 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
14279 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */
14280 #define USB_OTG_HPRT_PRST_Pos                    (8U)
14281 #define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
14282 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */
14283 
14284 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
14285 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
14286 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
14287 #define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
14288 #define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
14289 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
14290 #define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
14291 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
14292 
14293 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
14294 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
14295 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
14296 #define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
14297 #define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
14298 #define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
14299 #define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
14300 
14301 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
14302 #define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
14303 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
14304 #define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
14305 #define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
14306 
14307 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
14308 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
14309 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
14310 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
14311 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
14312 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
14313 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
14314 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
14315 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
14316 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
14317 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
14318 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
14319 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
14320 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
14321 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
14322 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
14323 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
14324 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
14325 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
14326 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
14327 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
14328 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
14329 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
14330 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
14331 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
14332 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
14333 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
14334 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
14335 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
14336 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
14337 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
14338 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
14339 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
14340 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
14341 
14342 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
14343 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
14344 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
14345 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
14346 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
14347 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
14348 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
14349 
14350 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
14351 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
14352 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14353 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
14354 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
14355 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14356 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
14357 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
14358 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
14359 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
14360 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
14361 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14362 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
14363 
14364 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
14365 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14366 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
14367 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14368 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14369 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
14370 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
14371 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
14372 
14373 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
14374 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
14375 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
14376 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
14377 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
14378 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
14379 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
14380 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
14381 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
14382 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
14383 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
14384 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
14385 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
14386 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
14387 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14388 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
14389 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
14390 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14391 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
14392 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
14393 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14394 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
14395 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
14396 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
14397 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
14398 
14399 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
14400 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
14401 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
14402 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
14403 
14404 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
14405 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
14406 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
14407 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
14408 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
14409 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
14410 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
14411 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
14412 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
14413 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
14414 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
14415 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
14416 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
14417 
14418 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
14419 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
14420 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
14421 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
14422 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
14423 
14424 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
14425 #define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
14426 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
14427 #define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
14428 #define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
14429 
14430 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
14431 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
14432 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
14433 #define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
14434 #define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
14435 #define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
14436 #define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
14437 #define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
14438 #define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
14439 #define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
14440 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
14441 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
14442 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
14443 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
14444 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
14445 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
14446 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
14447 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
14448 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
14449 
14450 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
14451 
14452 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
14453 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
14454 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
14455 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
14456 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
14457 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
14458 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
14459 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
14460 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
14461 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
14462 
14463 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
14464 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
14465 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
14466 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
14467 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
14468 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
14469 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
14470 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
14471 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
14472 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
14473 
14474 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
14475 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
14476 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
14477 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
14478 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
14479 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
14480 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
14481 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
14482 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
14483 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
14484 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
14485 
14486 /********************  Bit definition for USB_OTG_HCINT register  ********************/
14487 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
14488 #define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
14489 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
14490 #define USB_OTG_HCINT_CHH_Pos                    (1U)
14491 #define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
14492 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
14493 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
14494 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
14495 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
14496 #define USB_OTG_HCINT_STALL_Pos                  (3U)
14497 #define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
14498 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
14499 #define USB_OTG_HCINT_NAK_Pos                    (4U)
14500 #define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
14501 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
14502 #define USB_OTG_HCINT_ACK_Pos                    (5U)
14503 #define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
14504 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
14505 #define USB_OTG_HCINT_NYET_Pos                   (6U)
14506 #define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
14507 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
14508 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
14509 #define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
14510 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
14511 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
14512 #define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
14513 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
14514 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
14515 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
14516 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
14517 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
14518 #define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
14519 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
14520 
14521 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
14522 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
14523 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
14524 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
14525 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
14526 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
14527 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
14528 #define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
14529 #define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
14530 #define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
14531 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
14532 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
14533 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
14534 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
14535 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
14536 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
14537 #define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
14538 #define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
14539 #define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
14540 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
14541 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
14542 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
14543 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
14544 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
14545 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
14546 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
14547 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
14548 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
14549 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
14550 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
14551 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
14552 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
14553 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
14554 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
14555 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
14556 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
14557 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
14558 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
14559 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
14560 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
14561 
14562 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
14563 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
14564 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
14565 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
14566 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
14567 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
14568 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
14569 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
14570 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
14571 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
14572 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
14573 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
14574 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
14575 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
14576 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
14577 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
14578 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
14579 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
14580 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
14581 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
14582 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
14583 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
14584 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
14585 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
14586 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
14587 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
14588 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
14589 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
14590 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
14591 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
14592 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
14593 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
14594 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
14595 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
14596 
14597 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
14598 
14599 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
14600 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14601 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
14602 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
14603 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14604 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
14605 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
14606 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
14607 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
14608 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
14609 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
14610 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14611 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
14612 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
14613 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14614 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
14615 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
14616 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
14617 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
14618 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
14619 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
14620 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
14621 #define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
14622 #define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
14623 
14624 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
14625 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
14626 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14627 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
14628 
14629 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
14630 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
14631 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
14632 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
14633 
14634 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
14635 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
14636 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
14637 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
14638 
14639 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
14640 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
14641 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
14642 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
14643 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
14644 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
14645 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
14646 
14647 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
14648 
14649 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
14650 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
14651 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
14652 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
14653 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
14654 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
14655 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
14656 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
14657 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
14658 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
14659 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
14660 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
14661 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
14662 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
14663 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
14664 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
14665 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
14666 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
14667 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
14668 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
14669 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
14670 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
14671 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
14672 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
14673 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
14674 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
14675 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
14676 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
14677 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
14678 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
14679 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
14680 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
14681 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
14682 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
14683 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
14684 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
14685 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
14686 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
14687 
14688 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
14689 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
14690 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
14691 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
14692 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
14693 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
14694 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
14695 #define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
14696 #define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
14697 #define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
14698 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
14699 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
14700 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
14701 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
14702 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
14703 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
14704 #define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
14705 #define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
14706 #define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
14707 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
14708 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
14709 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
14710 #define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
14711 #define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
14712 #define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
14713 #define USB_OTG_DOEPINT_NAK_Pos                  (13U)
14714 #define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
14715 #define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
14716 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
14717 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
14718 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
14719 #define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
14720 #define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
14721 #define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
14722 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
14723 
14724 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
14725 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
14726 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
14727 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
14728 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
14729 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
14730 
14731 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
14732 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
14733 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
14734 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
14735 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
14736 
14737 /********************  Bit definition for PCGCCTL register  ********************/
14738 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
14739 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
14740 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
14741 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
14742 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
14743 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
14744 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
14745 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
14746 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
14747 
14748 /* Legacy define */
14749 /********************  Bit definition for OTG register  ********************/
14750 #define USB_OTG_CHNUM_Pos                        (0U)
14751 #define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
14752 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
14753 #define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
14754 #define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
14755 #define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
14756 #define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
14757 #define USB_OTG_BCNT_Pos                         (4U)
14758 #define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
14759 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
14760 
14761 #define USB_OTG_DPID_Pos                         (15U)
14762 #define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
14763 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
14764 #define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
14765 #define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
14766 
14767 #define USB_OTG_PKTSTS_Pos                       (17U)
14768 #define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
14769 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
14770 #define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
14771 #define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
14772 #define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
14773 #define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
14774 
14775 #define USB_OTG_EPNUM_Pos                        (0U)
14776 #define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
14777 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
14778 #define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
14779 #define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
14780 #define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
14781 #define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
14782 
14783 #define USB_OTG_FRMNUM_Pos                       (21U)
14784 #define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
14785 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
14786 #define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
14787 #define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
14788 #define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
14789 #define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
14790 /**
14791   * @}
14792   */
14793 
14794 /**
14795   * @}
14796   */
14797 
14798 /** @addtogroup Exported_macros
14799   * @{
14800   */
14801 
14802 /******************************* ADC Instances ********************************/
14803 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
14804                                        ((INSTANCE) == ADC2) || \
14805                                        ((INSTANCE) == ADC3))
14806 
14807 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14808 
14809 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
14810 
14811 /******************************* CAN Instances ********************************/
14812 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
14813                                        ((INSTANCE) == CAN2))
14814 
14815 /******************************* CRC Instances ********************************/
14816 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
14817 
14818 /******************************* DAC Instances ********************************/
14819 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
14820 
14821 /******************************* DCMI Instances *******************************/
14822 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
14823 
14824 /******************************** DMA Instances *******************************/
14825 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
14826                                               ((INSTANCE) == DMA1_Stream1) || \
14827                                               ((INSTANCE) == DMA1_Stream2) || \
14828                                               ((INSTANCE) == DMA1_Stream3) || \
14829                                               ((INSTANCE) == DMA1_Stream4) || \
14830                                               ((INSTANCE) == DMA1_Stream5) || \
14831                                               ((INSTANCE) == DMA1_Stream6) || \
14832                                               ((INSTANCE) == DMA1_Stream7) || \
14833                                               ((INSTANCE) == DMA2_Stream0) || \
14834                                               ((INSTANCE) == DMA2_Stream1) || \
14835                                               ((INSTANCE) == DMA2_Stream2) || \
14836                                               ((INSTANCE) == DMA2_Stream3) || \
14837                                               ((INSTANCE) == DMA2_Stream4) || \
14838                                               ((INSTANCE) == DMA2_Stream5) || \
14839                                               ((INSTANCE) == DMA2_Stream6) || \
14840                                               ((INSTANCE) == DMA2_Stream7))
14841 
14842 /******************************* GPIO Instances *******************************/
14843 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
14844                                         ((INSTANCE) == GPIOB) || \
14845                                         ((INSTANCE) == GPIOC) || \
14846                                         ((INSTANCE) == GPIOD) || \
14847                                         ((INSTANCE) == GPIOE) || \
14848                                         ((INSTANCE) == GPIOF) || \
14849                                         ((INSTANCE) == GPIOG) || \
14850                                         ((INSTANCE) == GPIOH) || \
14851                                         ((INSTANCE) == GPIOI))
14852 
14853 /**************************** GPIO Alternate Function Instances ***************/
14854 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
14855 
14856 /******************************** I2C Instances *******************************/
14857 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
14858                                        ((INSTANCE) == I2C2) || \
14859                                        ((INSTANCE) == I2C3))
14860 
14861 /******************************* SMBUS Instances ******************************/
14862 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
14863 
14864 /******************************** I2S Instances *******************************/
14865 #define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
14866                                         ((INSTANCE) == SPI3))
14867 
14868 /******************************* RNG Instances ********************************/
14869 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
14870 
14871 /****************************** RTC Instances *********************************/
14872 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
14873 
14874 /******************************** SPI Instances *******************************/
14875 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
14876                                        ((INSTANCE) == SPI2) || \
14877                                        ((INSTANCE) == SPI3))
14878 
14879 /****************** TIM Instances : All supported instances *******************/
14880 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
14881                                    ((INSTANCE) == TIM2)   || \
14882                                    ((INSTANCE) == TIM3)   || \
14883                                    ((INSTANCE) == TIM4)   || \
14884                                    ((INSTANCE) == TIM5)   || \
14885                                    ((INSTANCE) == TIM6)   || \
14886                                    ((INSTANCE) == TIM7)   || \
14887                                    ((INSTANCE) == TIM8)   || \
14888                                    ((INSTANCE) == TIM9)   || \
14889                                    ((INSTANCE) == TIM10)  || \
14890                                    ((INSTANCE) == TIM11)  || \
14891                                    ((INSTANCE) == TIM12)  || \
14892                                    ((INSTANCE) == TIM13)  || \
14893                                    ((INSTANCE) == TIM14))
14894 
14895 /************* TIM Instances : at least 1 capture/compare channel *************/
14896 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
14897                                          ((INSTANCE) == TIM2)  || \
14898                                          ((INSTANCE) == TIM3)  || \
14899                                          ((INSTANCE) == TIM4)  || \
14900                                          ((INSTANCE) == TIM5)  || \
14901                                          ((INSTANCE) == TIM8)  || \
14902                                          ((INSTANCE) == TIM9)  || \
14903                                          ((INSTANCE) == TIM10) || \
14904                                          ((INSTANCE) == TIM11) || \
14905                                          ((INSTANCE) == TIM12) || \
14906                                          ((INSTANCE) == TIM13) || \
14907                                          ((INSTANCE) == TIM14))
14908 
14909 /************ TIM Instances : at least 2 capture/compare channels *************/
14910 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14911                                        ((INSTANCE) == TIM2) || \
14912                                        ((INSTANCE) == TIM3) || \
14913                                        ((INSTANCE) == TIM4) || \
14914                                        ((INSTANCE) == TIM5) || \
14915                                        ((INSTANCE) == TIM8) || \
14916                                        ((INSTANCE) == TIM9) || \
14917                                        ((INSTANCE) == TIM12))
14918 
14919 /************ TIM Instances : at least 3 capture/compare channels *************/
14920 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
14921                                          ((INSTANCE) == TIM2) || \
14922                                          ((INSTANCE) == TIM3) || \
14923                                          ((INSTANCE) == TIM4) || \
14924                                          ((INSTANCE) == TIM5) || \
14925                                          ((INSTANCE) == TIM8))
14926 
14927 /************ TIM Instances : at least 4 capture/compare channels *************/
14928 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14929                                        ((INSTANCE) == TIM2) || \
14930                                        ((INSTANCE) == TIM3) || \
14931                                        ((INSTANCE) == TIM4) || \
14932                                        ((INSTANCE) == TIM5) || \
14933                                        ((INSTANCE) == TIM8))
14934 
14935 /******************** TIM Instances : Advanced-control timers *****************/
14936 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14937                                             ((INSTANCE) == TIM8))
14938 
14939 /******************* TIM Instances : Timer input XOR function *****************/
14940 #define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
14941                                          ((INSTANCE) == TIM2) || \
14942                                          ((INSTANCE) == TIM3) || \
14943                                          ((INSTANCE) == TIM4) || \
14944                                          ((INSTANCE) == TIM5) || \
14945                                          ((INSTANCE) == TIM8))
14946 
14947 /****************** TIM Instances : DMA requests generation (UDE) *************/
14948 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14949                                        ((INSTANCE) == TIM2) || \
14950                                        ((INSTANCE) == TIM3) || \
14951                                        ((INSTANCE) == TIM4) || \
14952                                        ((INSTANCE) == TIM5) || \
14953                                        ((INSTANCE) == TIM6) || \
14954                                        ((INSTANCE) == TIM7) || \
14955                                        ((INSTANCE) == TIM8))
14956 
14957 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
14958 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14959                                           ((INSTANCE) == TIM2) || \
14960                                           ((INSTANCE) == TIM3) || \
14961                                           ((INSTANCE) == TIM4) || \
14962                                           ((INSTANCE) == TIM5) || \
14963                                           ((INSTANCE) == TIM8))
14964 
14965 /************ TIM Instances : DMA requests generation (COMDE) *****************/
14966 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
14967                                           ((INSTANCE) == TIM2) || \
14968                                           ((INSTANCE) == TIM3) || \
14969                                           ((INSTANCE) == TIM4) || \
14970                                           ((INSTANCE) == TIM5) || \
14971                                           ((INSTANCE) == TIM8))
14972 
14973 /******************** TIM Instances : DMA burst feature ***********************/
14974 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
14975                                              ((INSTANCE) == TIM2) || \
14976                                              ((INSTANCE) == TIM3) || \
14977                                              ((INSTANCE) == TIM4) || \
14978                                              ((INSTANCE) == TIM5) || \
14979                                              ((INSTANCE) == TIM8))
14980 
14981 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
14982 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14983                                           ((INSTANCE) == TIM2) || \
14984                                           ((INSTANCE) == TIM3) || \
14985                                           ((INSTANCE) == TIM4) || \
14986                                           ((INSTANCE) == TIM5) || \
14987                                           ((INSTANCE) == TIM6) || \
14988                                           ((INSTANCE) == TIM7) || \
14989                                           ((INSTANCE) == TIM8) || \
14990                                           ((INSTANCE) == TIM9) || \
14991                                           ((INSTANCE) == TIM12))
14992 
14993 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
14994 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
14995                                          ((INSTANCE) == TIM2) || \
14996                                          ((INSTANCE) == TIM3) || \
14997                                          ((INSTANCE) == TIM4) || \
14998                                          ((INSTANCE) == TIM5) || \
14999                                          ((INSTANCE) == TIM8) || \
15000                                          ((INSTANCE) == TIM9) || \
15001                                          ((INSTANCE) == TIM12))
15002 
15003 /********************** TIM Instances : 32 bit Counter ************************/
15004 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
15005                                               ((INSTANCE) == TIM5))
15006 
15007 /***************** TIM Instances : external trigger input available ***********/
15008 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15009                                         ((INSTANCE) == TIM2) || \
15010                                         ((INSTANCE) == TIM3) || \
15011                                         ((INSTANCE) == TIM4) || \
15012                                         ((INSTANCE) == TIM5) || \
15013                                         ((INSTANCE) == TIM8))
15014 
15015 /****************** TIM Instances : remapping capability **********************/
15016 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
15017                                          ((INSTANCE) == TIM5)  || \
15018                                          ((INSTANCE) == TIM11))
15019 
15020 /******************* TIM Instances : output(s) available **********************/
15021 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
15022     ((((INSTANCE) == TIM1) &&                  \
15023      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15024       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15025       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15026       ((CHANNEL) == TIM_CHANNEL_4)))           \
15027     ||                                         \
15028     (((INSTANCE) == TIM2) &&                   \
15029      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15030       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15031       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15032       ((CHANNEL) == TIM_CHANNEL_4)))           \
15033     ||                                         \
15034     (((INSTANCE) == TIM3) &&                   \
15035      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15036       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15037       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15038       ((CHANNEL) == TIM_CHANNEL_4)))           \
15039     ||                                         \
15040     (((INSTANCE) == TIM4) &&                   \
15041      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15042       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15043       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15044       ((CHANNEL) == TIM_CHANNEL_4)))           \
15045     ||                                         \
15046     (((INSTANCE) == TIM5) &&                   \
15047      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15048       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15049       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15050       ((CHANNEL) == TIM_CHANNEL_4)))           \
15051     ||                                         \
15052     (((INSTANCE) == TIM8) &&                   \
15053      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15054       ((CHANNEL) == TIM_CHANNEL_2) ||          \
15055       ((CHANNEL) == TIM_CHANNEL_3) ||          \
15056       ((CHANNEL) == TIM_CHANNEL_4)))           \
15057     ||                                         \
15058     (((INSTANCE) == TIM9) &&                   \
15059      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15060       ((CHANNEL) == TIM_CHANNEL_2)))           \
15061     ||                                         \
15062     (((INSTANCE) == TIM10) &&                  \
15063      (((CHANNEL) == TIM_CHANNEL_1)))           \
15064     ||                                         \
15065     (((INSTANCE) == TIM11) &&                  \
15066      (((CHANNEL) == TIM_CHANNEL_1)))           \
15067     ||                                         \
15068     (((INSTANCE) == TIM12) &&                  \
15069      (((CHANNEL) == TIM_CHANNEL_1) ||          \
15070       ((CHANNEL) == TIM_CHANNEL_2)))           \
15071     ||                                         \
15072     (((INSTANCE) == TIM13) &&                  \
15073      (((CHANNEL) == TIM_CHANNEL_1)))           \
15074     ||                                         \
15075     (((INSTANCE) == TIM14) &&                  \
15076      (((CHANNEL) == TIM_CHANNEL_1))))
15077 
15078 /************ TIM Instances : complementary output(s) available ***************/
15079 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
15080    ((((INSTANCE) == TIM1) &&                    \
15081      (((CHANNEL) == TIM_CHANNEL_1) ||           \
15082       ((CHANNEL) == TIM_CHANNEL_2) ||           \
15083       ((CHANNEL) == TIM_CHANNEL_3)))            \
15084     ||                                          \
15085     (((INSTANCE) == TIM8) &&                    \
15086      (((CHANNEL) == TIM_CHANNEL_1) ||           \
15087       ((CHANNEL) == TIM_CHANNEL_2) ||           \
15088       ((CHANNEL) == TIM_CHANNEL_3))))
15089 
15090 /****************** TIM Instances : supporting counting mode selection ********/
15091 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15092                                                         ((INSTANCE) == TIM2) || \
15093                                                         ((INSTANCE) == TIM3) || \
15094                                                         ((INSTANCE) == TIM4) || \
15095                                                         ((INSTANCE) == TIM5) || \
15096                                                         ((INSTANCE) == TIM8))
15097 
15098 /****************** TIM Instances : supporting clock division *****************/
15099 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15100                                                    ((INSTANCE) == TIM2) || \
15101                                                    ((INSTANCE) == TIM3) || \
15102                                                    ((INSTANCE) == TIM4) || \
15103                                                    ((INSTANCE) == TIM5) || \
15104                                                    ((INSTANCE) == TIM8) || \
15105                                                    ((INSTANCE) == TIM9) || \
15106                                                    ((INSTANCE) == TIM10)|| \
15107                                                    ((INSTANCE) == TIM11)|| \
15108                                                    ((INSTANCE) == TIM12)|| \
15109                                                    ((INSTANCE) == TIM13)|| \
15110                                                    ((INSTANCE) == TIM14))
15111 
15112 /****************** TIM Instances : supporting commutation event generation ***/
15113 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15114                                                      ((INSTANCE) == TIM8))
15115 
15116 /****************** TIM Instances : supporting OCxREF clear *******************/
15117 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
15118                                                   ((INSTANCE) == TIM2) || \
15119                                                   ((INSTANCE) == TIM3) || \
15120                                                   ((INSTANCE) == TIM4) || \
15121                                                   ((INSTANCE) == TIM5) || \
15122                                                   ((INSTANCE) == TIM8))
15123 
15124 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15125 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15126                                                          ((INSTANCE) == TIM2) || \
15127                                                          ((INSTANCE) == TIM3) || \
15128                                                          ((INSTANCE) == TIM4) || \
15129                                                          ((INSTANCE) == TIM5) || \
15130                                                          ((INSTANCE) == TIM8) || \
15131                                                          ((INSTANCE) == TIM9) || \
15132                                                          ((INSTANCE) == TIM12))
15133 
15134 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15135 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15136                                                          ((INSTANCE) == TIM2) || \
15137                                                          ((INSTANCE) == TIM3) || \
15138                                                          ((INSTANCE) == TIM4) || \
15139                                                          ((INSTANCE) == TIM5) || \
15140                                                          ((INSTANCE) == TIM8))
15141 
15142 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
15143 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
15144                                                         ((INSTANCE) == TIM2) || \
15145                                                         ((INSTANCE) == TIM3) || \
15146                                                         ((INSTANCE) == TIM4) || \
15147                                                         ((INSTANCE) == TIM5) || \
15148                                                         ((INSTANCE) == TIM8) || \
15149                                                         ((INSTANCE) == TIM9) || \
15150                                                         ((INSTANCE) == TIM12))
15151 
15152 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
15153 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
15154                                                         ((INSTANCE) == TIM2) || \
15155                                                         ((INSTANCE) == TIM3) || \
15156                                                         ((INSTANCE) == TIM4) || \
15157                                                         ((INSTANCE) == TIM5) || \
15158                                                         ((INSTANCE) == TIM8) || \
15159                                                         ((INSTANCE) == TIM9) || \
15160                                                         ((INSTANCE) == TIM12))
15161 
15162 
15163 /****************** TIM Instances : supporting repetition counter *************/
15164 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15165                                                         ((INSTANCE) == TIM8))
15166 
15167 /****************** TIM Instances : supporting encoder interface **************/
15168 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15169                                                       ((INSTANCE) == TIM2) || \
15170                                                       ((INSTANCE) == TIM3) || \
15171                                                       ((INSTANCE) == TIM4) || \
15172                                                       ((INSTANCE) == TIM5) || \
15173                                                           ((INSTANCE) == TIM8))
15174 
15175 /****************** TIM Instances : supporting the break function *************/
15176 #define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15177                                           ((INSTANCE) == TIM8))
15178 
15179 /****************** TIM Instances : supporting Hall sensor interface **********/
15180 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
15181                                                           ((INSTANCE) == TIM8))
15182 
15183 /******************** USART Instances : Synchronous mode **********************/
15184 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15185                                      ((INSTANCE) == USART2) || \
15186                                      ((INSTANCE) == USART3) || \
15187                                      ((INSTANCE) == USART6))
15188 
15189 /******************** UART Instances : Asynchronous mode **********************/
15190 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15191                                     ((INSTANCE) == USART2) || \
15192                                     ((INSTANCE) == USART3) || \
15193                                     ((INSTANCE) == UART4)  || \
15194                                     ((INSTANCE) == UART5)  || \
15195                                     ((INSTANCE) == USART6))
15196 
15197 /****************** UART Instances : Hardware Flow control ********************/
15198 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15199                                            ((INSTANCE) == USART2) || \
15200                                            ((INSTANCE) == USART3) || \
15201                                            ((INSTANCE) == USART6))
15202 
15203 /********************* UART Instances : Smart card mode ***********************/
15204 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15205                                          ((INSTANCE) == USART2) || \
15206                                          ((INSTANCE) == USART3) || \
15207                                          ((INSTANCE) == USART6))
15208 
15209 /*********************** UART Instances : IRDA mode ***************************/
15210 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
15211                                     ((INSTANCE) == USART2) || \
15212                                     ((INSTANCE) == USART3) || \
15213                                     ((INSTANCE) == UART4)  || \
15214                                     ((INSTANCE) == UART5)  || \
15215                                     ((INSTANCE) == USART6))
15216 
15217 /* Legacy defines */
15218 #define IS_UART_HALFDUPLEX_INSTANCE    IS_UART_INSTANCE
15219 #define IS_UART_LIN_INSTANCE           IS_UART_INSTANCE
15220 
15221 /*********************** PCD Instances ****************************************/
15222 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15223                                        ((INSTANCE) == USB_OTG_HS))
15224 
15225 /*********************** HCD Instances ****************************************/
15226 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15227                                        ((INSTANCE) == USB_OTG_HS))
15228 
15229 /****************************** IWDG Instances ********************************/
15230 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
15231 
15232 /****************************** WWDG Instances ********************************/
15233 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
15234 
15235 /****************************** SDIO Instances ********************************/
15236 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
15237 
15238 /****************************** USB Exported Constants ************************/
15239 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
15240 #define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
15241 #define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
15242 #define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
15243 
15244 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
15245 #define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
15246 #define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
15247 #define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
15248 
15249 /**
15250   * @}
15251   */
15252 
15253 /**
15254   * @}
15255   */
15256 
15257 /**
15258   * @}
15259   */
15260 
15261 #ifdef __cplusplus
15262 }
15263 #endif /* __cplusplus */
15264 
15265 #endif /* __STM32F217xx_H */
15266 
15267 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
15268