1 /********************************************************************* 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 ********************************************************************** 5 * * 6 * (c) 1995 - 2021 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: support@segger.com * 9 * * 10 ********************************************************************** 11 * * 12 * SEGGER RTT * Real Time Transfer for embedded targets * 13 * * 14 ********************************************************************** 15 * * 16 * All rights reserved. * 17 * * 18 * SEGGER strongly recommends to not make any changes * 19 * to or modify the source code of this software in order to stay * 20 * compatible with the RTT protocol and J-Link. * 21 * * 22 * Redistribution and use in source and binary forms, with or * 23 * without modification, are permitted provided that the following * 24 * condition is met: * 25 * * 26 * o Redistributions of source code must retain the above copyright * 27 * notice, this condition and the following disclaimer. * 28 * * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 30 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 31 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 32 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 33 * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * 34 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 35 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 36 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 37 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 38 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 40 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 41 * DAMAGE. * 42 * * 43 ********************************************************************** 44 * * 45 * RTT version: 7.22 * 46 * * 47 ********************************************************************** 48 49 ---------------------------END-OF-HEADER------------------------------ 50 File : SEGGER_RTT_Conf.h 51 Purpose : Implementation of SEGGER real-time transfer (RTT) which 52 allows real-time communication on targets which support 53 debugger memory accesses while the CPU is running. 54 Revision: $Rev: 21386 $ 55 56 */ 57 58 #ifndef SEGGER_RTT_CONF_H 59 #define SEGGER_RTT_CONF_H 60 61 #ifdef __IAR_SYSTEMS_ICC__ 62 #include <intrinsics.h> 63 #endif 64 65 /********************************************************************* 66 * 67 * Defines, configurable 68 * 69 ********************************************************************** 70 */ 71 72 // 73 // Take in and set to correct values for Cortex-A systems with CPU cache 74 // 75 //#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system 76 //#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached 77 // 78 // Most common case: 79 // Up-channel 0: RTT 80 // Up-channel 1: SystemView 81 // 82 #ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS 83 #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) 84 #endif 85 // 86 // Most common case: 87 // Down-channel 0: RTT 88 // Down-channel 1: SystemView 89 // 90 #ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS 91 #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) 92 #endif 93 94 #ifndef BUFFER_SIZE_UP 95 #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k) 96 #endif 97 98 #ifndef BUFFER_SIZE_DOWN 99 #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) 100 #endif 101 102 #ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE 103 #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) 104 #endif 105 106 #ifndef SEGGER_RTT_MODE_DEFAULT 107 #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) 108 #endif 109 110 /********************************************************************* 111 * 112 * RTT memcpy configuration 113 * 114 * memcpy() is good for large amounts of data, 115 * but the overhead is big for small amounts, which are usually stored via RTT. 116 * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. 117 * 118 * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. 119 * This is may be required with memory access restrictions, 120 * such as on Cortex-A devices with MMU. 121 */ 122 #ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP 123 #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop 124 #endif 125 // 126 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets 127 // 128 //#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) 129 // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) 130 //#endif 131 132 // 133 // Target is not allowed to perform other RTT operations while string still has not been stored completely. 134 // Otherwise we would probably end up with a mixed string in the buffer. 135 // If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here. 136 // 137 // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4. 138 // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches. 139 // When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly. 140 // (Higher priority = lower priority number) 141 // Default value for embOS: 128u 142 // Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) 143 // In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC 144 // or define SEGGER_RTT_LOCK() to completely disable interrupts. 145 // 146 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 147 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) 148 #endif 149 150 /********************************************************************* 151 * 152 * RTT lock configuration for SEGGER Embedded Studio, 153 * Rowley CrossStudio and GCC 154 */ 155 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) 156 #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) 157 #define SEGGER_RTT_LOCK() { \ 158 unsigned int _SEGGER_RTT__LockState; \ 159 __asm volatile ("mrs %0, primask \n\t" \ 160 "movs r1, #1 \n\t" \ 161 "msr primask, r1 \n\t" \ 162 : "=r" (_SEGGER_RTT__LockState) \ 163 : \ 164 : "r1", "cc" \ 165 ); 166 167 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ 168 : \ 169 : "r" (_SEGGER_RTT__LockState) \ 170 : \ 171 ); \ 172 } 173 #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) 174 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 175 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 176 #endif 177 #define SEGGER_RTT_LOCK() { \ 178 unsigned int _SEGGER_RTT__LockState; \ 179 __asm volatile ("mrs %0, basepri \n\t" \ 180 "mov r1, %1 \n\t" \ 181 "msr basepri, r1 \n\t" \ 182 : "=r" (_SEGGER_RTT__LockState) \ 183 : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ 184 : "r1", "cc" \ 185 ); 186 187 #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ 188 : \ 189 : "r" (_SEGGER_RTT__LockState) \ 190 : \ 191 ); \ 192 } 193 194 #elif defined(__ARM_ARCH_7A__) 195 #define SEGGER_RTT_LOCK() { \ 196 unsigned int _SEGGER_RTT__LockState; \ 197 __asm volatile ("mrs r1, CPSR \n\t" \ 198 "mov %0, r1 \n\t" \ 199 "orr r1, r1, #0xC0 \n\t" \ 200 "msr CPSR_c, r1 \n\t" \ 201 : "=r" (_SEGGER_RTT__LockState) \ 202 : \ 203 : "r1", "cc" \ 204 ); 205 206 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 207 "mrs r1, CPSR \n\t" \ 208 "bic r1, r1, #0xC0 \n\t" \ 209 "and r0, r0, #0xC0 \n\t" \ 210 "orr r1, r1, r0 \n\t" \ 211 "msr CPSR_c, r1 \n\t" \ 212 : \ 213 : "r" (_SEGGER_RTT__LockState) \ 214 : "r0", "r1", "cc" \ 215 ); \ 216 } 217 #elif defined(__riscv) || defined(__riscv_xlen) 218 #define SEGGER_RTT_LOCK() { \ 219 unsigned int _SEGGER_RTT__LockState; \ 220 __asm volatile ("csrr %0, mstatus \n\t" \ 221 "csrci mstatus, 8 \n\t" \ 222 "andi %0, %0, 8 \n\t" \ 223 : "=r" (_SEGGER_RTT__LockState) \ 224 : \ 225 : \ 226 ); 227 228 #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ 229 "or %0, %0, a1 \n\t" \ 230 "csrs mstatus, %0 \n\t" \ 231 : \ 232 : "r" (_SEGGER_RTT__LockState) \ 233 : "a1" \ 234 ); \ 235 } 236 #else 237 #define SEGGER_RTT_LOCK() 238 #define SEGGER_RTT_UNLOCK() 239 #endif 240 #endif 241 242 /********************************************************************* 243 * 244 * RTT lock configuration for IAR EWARM 245 */ 246 #ifdef __ICCARM__ 247 #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ 248 (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) 249 #define SEGGER_RTT_LOCK() { \ 250 unsigned int _SEGGER_RTT__LockState; \ 251 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 252 __set_PRIMASK(1); 253 254 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 255 } 256 #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ 257 (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ 258 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ 259 (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) 260 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 261 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 262 #endif 263 #define SEGGER_RTT_LOCK() { \ 264 unsigned int _SEGGER_RTT__LockState; \ 265 _SEGGER_RTT__LockState = __get_BASEPRI(); \ 266 __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 267 268 #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \ 269 } 270 #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \ 271 (defined (__ARM7R__) && (__CORE__ == __ARM7R__)) 272 #define SEGGER_RTT_LOCK() { \ 273 unsigned int _SEGGER_RTT__LockState; \ 274 __asm volatile ("mrs r1, CPSR \n\t" \ 275 "mov %0, r1 \n\t" \ 276 "orr r1, r1, #0xC0 \n\t" \ 277 "msr CPSR_c, r1 \n\t" \ 278 : "=r" (_SEGGER_RTT__LockState) \ 279 : \ 280 : "r1", "cc" \ 281 ); 282 283 #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ 284 "mrs r1, CPSR \n\t" \ 285 "bic r1, r1, #0xC0 \n\t" \ 286 "and r0, r0, #0xC0 \n\t" \ 287 "orr r1, r1, r0 \n\t" \ 288 "msr CPSR_c, r1 \n\t" \ 289 : \ 290 : "r" (_SEGGER_RTT__LockState) \ 291 : "r0", "r1", "cc" \ 292 ); \ 293 } 294 #endif 295 #endif 296 297 /********************************************************************* 298 * 299 * RTT lock configuration for IAR RX 300 */ 301 #ifdef __ICCRX__ 302 #define SEGGER_RTT_LOCK() { \ 303 unsigned long _SEGGER_RTT__LockState; \ 304 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 305 __disable_interrupt(); 306 307 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 308 } 309 #endif 310 311 /********************************************************************* 312 * 313 * RTT lock configuration for IAR RL78 314 */ 315 #ifdef __ICCRL78__ 316 #define SEGGER_RTT_LOCK() { \ 317 __istate_t _SEGGER_RTT__LockState; \ 318 _SEGGER_RTT__LockState = __get_interrupt_state(); \ 319 __disable_interrupt(); 320 321 #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \ 322 } 323 #endif 324 325 /********************************************************************* 326 * 327 * RTT lock configuration for KEIL ARM 328 */ 329 #ifdef __CC_ARM 330 #if (defined __TARGET_ARCH_6S_M) 331 #define SEGGER_RTT_LOCK() { \ 332 unsigned int _SEGGER_RTT__LockState; \ 333 register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \ 334 _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \ 335 _SEGGER_RTT__PRIMASK = 1u; \ 336 __schedule_barrier(); 337 338 #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \ 339 __schedule_barrier(); \ 340 } 341 #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) 342 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 343 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 344 #endif 345 #define SEGGER_RTT_LOCK() { \ 346 unsigned int _SEGGER_RTT__LockState; \ 347 register unsigned char BASEPRI __asm( "basepri"); \ 348 _SEGGER_RTT__LockState = BASEPRI; \ 349 BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ 350 __schedule_barrier(); 351 352 #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \ 353 __schedule_barrier(); \ 354 } 355 #endif 356 #endif 357 358 /********************************************************************* 359 * 360 * RTT lock configuration for TI ARM 361 */ 362 #ifdef __TI_ARM__ 363 #if defined (__TI_ARM_V6M0__) 364 #define SEGGER_RTT_LOCK() { \ 365 unsigned int _SEGGER_RTT__LockState; \ 366 _SEGGER_RTT__LockState = __get_PRIMASK(); \ 367 __set_PRIMASK(1); 368 369 #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \ 370 } 371 #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) 372 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY 373 #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) 374 #endif 375 #define SEGGER_RTT_LOCK() { \ 376 unsigned int _SEGGER_RTT__LockState; \ 377 _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); 378 379 #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \ 380 } 381 #endif 382 #endif 383 384 /********************************************************************* 385 * 386 * RTT lock configuration for CCRX 387 */ 388 #ifdef __RX 389 #include <machine.h> 390 #define SEGGER_RTT_LOCK() { \ 391 unsigned long _SEGGER_RTT__LockState; \ 392 _SEGGER_RTT__LockState = get_psw() & 0x010000; \ 393 clrpsw_i(); 394 395 #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \ 396 } 397 #endif 398 399 /********************************************************************* 400 * 401 * RTT lock configuration for embOS Simulation on Windows 402 * (Can also be used for generic RTT locking with embOS) 403 */ 404 #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) 405 406 void OS_SIM_EnterCriticalSection(void); 407 void OS_SIM_LeaveCriticalSection(void); 408 409 #define SEGGER_RTT_LOCK() { \ 410 OS_SIM_EnterCriticalSection(); 411 412 #define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ 413 } 414 #endif 415 416 /********************************************************************* 417 * 418 * RTT lock configuration fallback 419 */ 420 #ifndef SEGGER_RTT_LOCK 421 #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) 422 #endif 423 424 #ifndef SEGGER_RTT_UNLOCK 425 #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) 426 #endif 427 428 #endif 429 /*************************** End of file ****************************/ 430
