1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_USDHC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_USDHC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_USDHC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_USDHC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- USDHC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** USDHC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ 74 __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ 75 __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ 76 __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ 77 __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ 78 __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ 79 __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ 80 __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ 81 __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ 82 __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ 83 __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ 84 __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ 85 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ 86 __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ 87 __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ 88 __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ 89 __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ 90 __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ 91 __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ 92 uint8_t RESERVED_0[4]; 93 __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ 94 __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */ 95 __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ 96 uint8_t RESERVED_1[4]; 97 __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ 98 __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ 99 __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ 100 uint8_t RESERVED_2[4]; 101 __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */ 102 __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */ 103 uint8_t RESERVED_3[72]; 104 __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ 105 __IO uint32_t MMC_BOOT; /**< eMMC Boot, offset: 0xC4 */ 106 __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ 107 __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ 108 uint8_t RESERVED_4[48]; 109 __I uint32_t CQVER; /**< Command Queuing Version, offset: 0x100 */ 110 __IO uint32_t CQCAP; /**< Command Queuing Capabilities, offset: 0x104 */ 111 __IO uint32_t CQCFG; /**< Command Queuing Configuration, offset: 0x108 */ 112 __IO uint32_t CQCTL; /**< Command Queuing Control, offset: 0x10C */ 113 __IO uint32_t CQIS; /**< Command Queuing Interrupt Status, offset: 0x110 */ 114 __IO uint32_t CQISTE; /**< Command Queuing Interrupt Status Enable, offset: 0x114 */ 115 __IO uint32_t CQISGE; /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */ 116 __IO uint32_t CQIC; /**< Command Queuing Interrupt Coalescing, offset: 0x11C */ 117 __IO uint32_t CQTDLBA; /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */ 118 __IO uint32_t CQTDLBAU; /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */ 119 __IO uint32_t CQTDBR; /**< Command Queuing Task Doorbell, offset: 0x128 */ 120 __IO uint32_t CQTCN; /**< Command Queuing Task Completion Notification, offset: 0x12C */ 121 __I uint32_t CQDQS; /**< Command Queuing Device Queue Status, offset: 0x130 */ 122 __I uint32_t CQDPT; /**< Command Queuing Device Pending Tasks, offset: 0x134 */ 123 __IO uint32_t CQTCLR; /**< Command Queuing Task Clear, offset: 0x138 */ 124 uint8_t RESERVED_5[4]; 125 __IO uint32_t CQSSC1; /**< Command Queuing Send Status Configuration 1, offset: 0x140 */ 126 __IO uint32_t CQSSC2; /**< Command Queuing Send Status Configuration 2, offset: 0x144 */ 127 __I uint32_t CQCRDCT; /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */ 128 uint8_t RESERVED_6[4]; 129 __IO uint32_t CQRMEM; /**< Command Queuing Response Mode Error Mask, offset: 0x150 */ 130 __I uint32_t CQTERRI; /**< Command Queuing Task Error Information, offset: 0x154 */ 131 __I uint32_t CQCRI; /**< Command Queuing Command Response Index, offset: 0x158 */ 132 __I uint32_t CQCRA; /**< Command Queuing Command Response Argument, offset: 0x15C */ 133 } USDHC_Type, *USDHC_MemMapPtr; 134 135 /** Number of instances of the USDHC module. */ 136 #define USDHC_INSTANCE_COUNT (1u) 137 138 /* USDHC - Peripheral instance base addresses */ 139 /** Peripheral USDHC base address */ 140 #define IP_USDHC_BASE (0x42300000u) 141 /** Peripheral USDHC base pointer */ 142 #define IP_USDHC ((USDHC_Type *)IP_USDHC_BASE) 143 /** Array initializer of USDHC peripheral base addresses */ 144 #define IP_USDHC_BASE_ADDRS { IP_USDHC_BASE } 145 /** Array initializer of USDHC peripheral base pointers */ 146 #define IP_USDHC_BASE_PTRS { IP_USDHC } 147 148 /* ---------------------------------------------------------------------------- 149 -- USDHC Register Masks 150 ---------------------------------------------------------------------------- */ 151 152 /*! 153 * @addtogroup USDHC_Register_Masks USDHC Register Masks 154 * @{ 155 */ 156 157 /*! @name DS_ADDR - DMA System Address */ 158 /*! @{ */ 159 160 #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) 161 #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) 162 #define USDHC_DS_ADDR_DS_ADDR_WIDTH (32U) 163 #define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) 164 /*! @} */ 165 166 /*! @name BLK_ATT - Block Attributes */ 167 /*! @{ */ 168 169 #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) 170 #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) 171 #define USDHC_BLK_ATT_BLKSIZE_WIDTH (13U) 172 #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) 173 174 #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) 175 #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) 176 #define USDHC_BLK_ATT_BLKCNT_WIDTH (16U) 177 #define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) 178 /*! @} */ 179 180 /*! @name CMD_ARG - Command Argument */ 181 /*! @{ */ 182 183 #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) 184 #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) 185 #define USDHC_CMD_ARG_CMDARG_WIDTH (32U) 186 #define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) 187 /*! @} */ 188 189 /*! @name CMD_XFR_TYP - Command Transfer Type */ 190 /*! @{ */ 191 192 #define USDHC_CMD_XFR_TYP_DMAEN_MASK (0x1U) 193 #define USDHC_CMD_XFR_TYP_DMAEN_SHIFT (0U) 194 #define USDHC_CMD_XFR_TYP_DMAEN_WIDTH (1U) 195 #define USDHC_CMD_XFR_TYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DMAEN_SHIFT)) & USDHC_CMD_XFR_TYP_DMAEN_MASK) 196 197 #define USDHC_CMD_XFR_TYP_BCEN_MASK (0x2U) 198 #define USDHC_CMD_XFR_TYP_BCEN_SHIFT (1U) 199 #define USDHC_CMD_XFR_TYP_BCEN_WIDTH (1U) 200 #define USDHC_CMD_XFR_TYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_BCEN_SHIFT)) & USDHC_CMD_XFR_TYP_BCEN_MASK) 201 202 #define USDHC_CMD_XFR_TYP_AC12EN_MASK (0x4U) 203 #define USDHC_CMD_XFR_TYP_AC12EN_SHIFT (2U) 204 #define USDHC_CMD_XFR_TYP_AC12EN_WIDTH (1U) 205 #define USDHC_CMD_XFR_TYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC12EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC12EN_MASK) 206 207 #define USDHC_CMD_XFR_TYP_DDR_EN_MASK (0x8U) 208 #define USDHC_CMD_XFR_TYP_DDR_EN_SHIFT (3U) 209 #define USDHC_CMD_XFR_TYP_DDR_EN_WIDTH (1U) 210 #define USDHC_CMD_XFR_TYP_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DDR_EN_SHIFT)) & USDHC_CMD_XFR_TYP_DDR_EN_MASK) 211 212 #define USDHC_CMD_XFR_TYP_DTDSEL_MASK (0x10U) 213 #define USDHC_CMD_XFR_TYP_DTDSEL_SHIFT (4U) 214 #define USDHC_CMD_XFR_TYP_DTDSEL_WIDTH (1U) 215 #define USDHC_CMD_XFR_TYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DTDSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DTDSEL_MASK) 216 217 #define USDHC_CMD_XFR_TYP_MSBSEL_MASK (0x20U) 218 #define USDHC_CMD_XFR_TYP_MSBSEL_SHIFT (5U) 219 #define USDHC_CMD_XFR_TYP_MSBSEL_WIDTH (1U) 220 #define USDHC_CMD_XFR_TYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_MSBSEL_SHIFT)) & USDHC_CMD_XFR_TYP_MSBSEL_MASK) 221 222 #define USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK (0x40U) 223 #define USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT (6U) 224 #define USDHC_CMD_XFR_TYP_NIBBLE_POS_WIDTH (1U) 225 #define USDHC_CMD_XFR_TYP_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_NIBBLE_POS_SHIFT)) & USDHC_CMD_XFR_TYP_NIBBLE_POS_MASK) 226 227 #define USDHC_CMD_XFR_TYP_AC23EN_MASK (0x80U) 228 #define USDHC_CMD_XFR_TYP_AC23EN_SHIFT (7U) 229 #define USDHC_CMD_XFR_TYP_AC23EN_WIDTH (1U) 230 #define USDHC_CMD_XFR_TYP_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_AC23EN_SHIFT)) & USDHC_CMD_XFR_TYP_AC23EN_MASK) 231 232 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) 233 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) 234 #define USDHC_CMD_XFR_TYP_RSPTYP_WIDTH (2U) 235 #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) 236 237 #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) 238 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) 239 #define USDHC_CMD_XFR_TYP_CCCEN_WIDTH (1U) 240 #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) 241 242 #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) 243 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) 244 #define USDHC_CMD_XFR_TYP_CICEN_WIDTH (1U) 245 #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) 246 247 #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) 248 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) 249 #define USDHC_CMD_XFR_TYP_DPSEL_WIDTH (1U) 250 #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) 251 252 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) 253 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) 254 #define USDHC_CMD_XFR_TYP_CMDTYP_WIDTH (2U) 255 #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) 256 257 #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) 258 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) 259 #define USDHC_CMD_XFR_TYP_CMDINX_WIDTH (6U) 260 #define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) 261 /*! @} */ 262 263 /*! @name CMD_RSP0 - Command Response0 */ 264 /*! @{ */ 265 266 #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) 267 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) 268 #define USDHC_CMD_RSP0_CMDRSP0_WIDTH (32U) 269 #define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) 270 /*! @} */ 271 272 /*! @name CMD_RSP1 - Command Response1 */ 273 /*! @{ */ 274 275 #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) 276 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) 277 #define USDHC_CMD_RSP1_CMDRSP1_WIDTH (32U) 278 #define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) 279 /*! @} */ 280 281 /*! @name CMD_RSP2 - Command Response2 */ 282 /*! @{ */ 283 284 #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) 285 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) 286 #define USDHC_CMD_RSP2_CMDRSP2_WIDTH (32U) 287 #define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) 288 /*! @} */ 289 290 /*! @name CMD_RSP3 - Command Response3 */ 291 /*! @{ */ 292 293 #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) 294 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) 295 #define USDHC_CMD_RSP3_CMDRSP3_WIDTH (32U) 296 #define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) 297 /*! @} */ 298 299 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ 300 /*! @{ */ 301 302 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) 303 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) 304 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_WIDTH (32U) 305 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) 306 /*! @} */ 307 308 /*! @name PRES_STATE - Present State */ 309 /*! @{ */ 310 311 #define USDHC_PRES_STATE_CIHB_MASK (0x1U) 312 #define USDHC_PRES_STATE_CIHB_SHIFT (0U) 313 #define USDHC_PRES_STATE_CIHB_WIDTH (1U) 314 #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) 315 316 #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) 317 #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) 318 #define USDHC_PRES_STATE_CDIHB_WIDTH (1U) 319 #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) 320 321 #define USDHC_PRES_STATE_DLA_MASK (0x4U) 322 #define USDHC_PRES_STATE_DLA_SHIFT (2U) 323 #define USDHC_PRES_STATE_DLA_WIDTH (1U) 324 #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) 325 326 #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) 327 #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) 328 #define USDHC_PRES_STATE_SDSTB_WIDTH (1U) 329 #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) 330 331 #define USDHC_PRES_STATE_WTA_MASK (0x100U) 332 #define USDHC_PRES_STATE_WTA_SHIFT (8U) 333 #define USDHC_PRES_STATE_WTA_WIDTH (1U) 334 #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) 335 336 #define USDHC_PRES_STATE_RTA_MASK (0x200U) 337 #define USDHC_PRES_STATE_RTA_SHIFT (9U) 338 #define USDHC_PRES_STATE_RTA_WIDTH (1U) 339 #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) 340 341 #define USDHC_PRES_STATE_BWEN_MASK (0x400U) 342 #define USDHC_PRES_STATE_BWEN_SHIFT (10U) 343 #define USDHC_PRES_STATE_BWEN_WIDTH (1U) 344 #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) 345 346 #define USDHC_PRES_STATE_BREN_MASK (0x800U) 347 #define USDHC_PRES_STATE_BREN_SHIFT (11U) 348 #define USDHC_PRES_STATE_BREN_WIDTH (1U) 349 #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) 350 351 #define USDHC_PRES_STATE_RTR_MASK (0x1000U) 352 #define USDHC_PRES_STATE_RTR_SHIFT (12U) 353 #define USDHC_PRES_STATE_RTR_WIDTH (1U) 354 #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) 355 356 #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) 357 #define USDHC_PRES_STATE_TSCD_SHIFT (15U) 358 #define USDHC_PRES_STATE_TSCD_WIDTH (1U) 359 #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) 360 361 #define USDHC_PRES_STATE_CINST_MASK (0x10000U) 362 #define USDHC_PRES_STATE_CINST_SHIFT (16U) 363 #define USDHC_PRES_STATE_CINST_WIDTH (1U) 364 #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) 365 366 #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) 367 #define USDHC_PRES_STATE_CLSL_SHIFT (23U) 368 #define USDHC_PRES_STATE_CLSL_WIDTH (1U) 369 #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) 370 371 #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) 372 #define USDHC_PRES_STATE_DLSL_SHIFT (24U) 373 #define USDHC_PRES_STATE_DLSL_WIDTH (8U) 374 #define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) 375 /*! @} */ 376 377 /*! @name PROT_CTRL - Protocol Control */ 378 /*! @{ */ 379 380 #define USDHC_PROT_CTRL_DTW_MASK (0x6U) 381 #define USDHC_PROT_CTRL_DTW_SHIFT (1U) 382 #define USDHC_PROT_CTRL_DTW_WIDTH (2U) 383 #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) 384 385 #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) 386 #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) 387 #define USDHC_PROT_CTRL_D3CD_WIDTH (1U) 388 #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) 389 390 #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) 391 #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) 392 #define USDHC_PROT_CTRL_EMODE_WIDTH (2U) 393 #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) 394 395 #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) 396 #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) 397 #define USDHC_PROT_CTRL_DMASEL_WIDTH (2U) 398 #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) 399 400 #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) 401 #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) 402 #define USDHC_PROT_CTRL_SABGREQ_WIDTH (1U) 403 #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) 404 405 #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) 406 #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) 407 #define USDHC_PROT_CTRL_CREQ_WIDTH (1U) 408 #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) 409 410 #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) 411 #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) 412 #define USDHC_PROT_CTRL_RWCTL_WIDTH (1U) 413 #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) 414 415 #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) 416 #define USDHC_PROT_CTRL_IABG_SHIFT (19U) 417 #define USDHC_PROT_CTRL_IABG_WIDTH (1U) 418 #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) 419 420 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) 421 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) 422 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_WIDTH (1U) 423 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) 424 425 #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) 426 #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) 427 #define USDHC_PROT_CTRL_WECINT_WIDTH (1U) 428 #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) 429 430 #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) 431 #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) 432 #define USDHC_PROT_CTRL_WECINS_WIDTH (1U) 433 #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) 434 435 #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) 436 #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) 437 #define USDHC_PROT_CTRL_WECRM_WIDTH (1U) 438 #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) 439 440 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) 441 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) 442 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_WIDTH (1U) 443 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) 444 /*! @} */ 445 446 /*! @name SYS_CTRL - System Control */ 447 /*! @{ */ 448 449 #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) 450 #define USDHC_SYS_CTRL_DVS_SHIFT (4U) 451 #define USDHC_SYS_CTRL_DVS_WIDTH (4U) 452 #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) 453 454 #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) 455 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) 456 #define USDHC_SYS_CTRL_SDCLKFS_WIDTH (8U) 457 #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) 458 459 #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) 460 #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) 461 #define USDHC_SYS_CTRL_DTOCV_WIDTH (4U) 462 #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) 463 464 #define USDHC_SYS_CTRL_RST_FIFO_MASK (0x400000U) 465 #define USDHC_SYS_CTRL_RST_FIFO_SHIFT (22U) 466 #define USDHC_SYS_CTRL_RST_FIFO_WIDTH (1U) 467 #define USDHC_SYS_CTRL_RST_FIFO(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RST_FIFO_SHIFT)) & USDHC_SYS_CTRL_RST_FIFO_MASK) 468 469 #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) 470 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) 471 #define USDHC_SYS_CTRL_IPP_RST_N_WIDTH (1U) 472 #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) 473 474 #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) 475 #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) 476 #define USDHC_SYS_CTRL_RSTA_WIDTH (1U) 477 #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) 478 479 #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) 480 #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) 481 #define USDHC_SYS_CTRL_RSTC_WIDTH (1U) 482 #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) 483 484 #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) 485 #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) 486 #define USDHC_SYS_CTRL_RSTD_WIDTH (1U) 487 #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) 488 489 #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) 490 #define USDHC_SYS_CTRL_INITA_SHIFT (27U) 491 #define USDHC_SYS_CTRL_INITA_WIDTH (1U) 492 #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) 493 494 #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) 495 #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) 496 #define USDHC_SYS_CTRL_RSTT_WIDTH (1U) 497 #define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) 498 /*! @} */ 499 500 /*! @name INT_STATUS - Interrupt Status */ 501 /*! @{ */ 502 503 #define USDHC_INT_STATUS_CC_MASK (0x1U) 504 #define USDHC_INT_STATUS_CC_SHIFT (0U) 505 #define USDHC_INT_STATUS_CC_WIDTH (1U) 506 #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) 507 508 #define USDHC_INT_STATUS_TC_MASK (0x2U) 509 #define USDHC_INT_STATUS_TC_SHIFT (1U) 510 #define USDHC_INT_STATUS_TC_WIDTH (1U) 511 #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) 512 513 #define USDHC_INT_STATUS_BGE_MASK (0x4U) 514 #define USDHC_INT_STATUS_BGE_SHIFT (2U) 515 #define USDHC_INT_STATUS_BGE_WIDTH (1U) 516 #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) 517 518 #define USDHC_INT_STATUS_DINT_MASK (0x8U) 519 #define USDHC_INT_STATUS_DINT_SHIFT (3U) 520 #define USDHC_INT_STATUS_DINT_WIDTH (1U) 521 #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) 522 523 #define USDHC_INT_STATUS_BWR_MASK (0x10U) 524 #define USDHC_INT_STATUS_BWR_SHIFT (4U) 525 #define USDHC_INT_STATUS_BWR_WIDTH (1U) 526 #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) 527 528 #define USDHC_INT_STATUS_BRR_MASK (0x20U) 529 #define USDHC_INT_STATUS_BRR_SHIFT (5U) 530 #define USDHC_INT_STATUS_BRR_WIDTH (1U) 531 #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) 532 533 #define USDHC_INT_STATUS_CINS_MASK (0x40U) 534 #define USDHC_INT_STATUS_CINS_SHIFT (6U) 535 #define USDHC_INT_STATUS_CINS_WIDTH (1U) 536 #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) 537 538 #define USDHC_INT_STATUS_CRM_MASK (0x80U) 539 #define USDHC_INT_STATUS_CRM_SHIFT (7U) 540 #define USDHC_INT_STATUS_CRM_WIDTH (1U) 541 #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) 542 543 #define USDHC_INT_STATUS_CINT_MASK (0x100U) 544 #define USDHC_INT_STATUS_CINT_SHIFT (8U) 545 #define USDHC_INT_STATUS_CINT_WIDTH (1U) 546 #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) 547 548 #define USDHC_INT_STATUS_RTE_MASK (0x1000U) 549 #define USDHC_INT_STATUS_RTE_SHIFT (12U) 550 #define USDHC_INT_STATUS_RTE_WIDTH (1U) 551 #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) 552 553 #define USDHC_INT_STATUS_TP_MASK (0x2000U) 554 #define USDHC_INT_STATUS_TP_SHIFT (13U) 555 #define USDHC_INT_STATUS_TP_WIDTH (1U) 556 #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) 557 558 #define USDHC_INT_STATUS_CQI_MASK (0x4000U) 559 #define USDHC_INT_STATUS_CQI_SHIFT (14U) 560 #define USDHC_INT_STATUS_CQI_WIDTH (1U) 561 #define USDHC_INT_STATUS_CQI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK) 562 563 #define USDHC_INT_STATUS_ERR_INT_STATUS_MASK (0x8000U) 564 #define USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT (15U) 565 #define USDHC_INT_STATUS_ERR_INT_STATUS_WIDTH (1U) 566 #define USDHC_INT_STATUS_ERR_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_ERR_INT_STATUS_SHIFT)) & USDHC_INT_STATUS_ERR_INT_STATUS_MASK) 567 568 #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) 569 #define USDHC_INT_STATUS_CTOE_SHIFT (16U) 570 #define USDHC_INT_STATUS_CTOE_WIDTH (1U) 571 #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) 572 573 #define USDHC_INT_STATUS_CCE_MASK (0x20000U) 574 #define USDHC_INT_STATUS_CCE_SHIFT (17U) 575 #define USDHC_INT_STATUS_CCE_WIDTH (1U) 576 #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) 577 578 #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) 579 #define USDHC_INT_STATUS_CEBE_SHIFT (18U) 580 #define USDHC_INT_STATUS_CEBE_WIDTH (1U) 581 #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) 582 583 #define USDHC_INT_STATUS_CIE_MASK (0x80000U) 584 #define USDHC_INT_STATUS_CIE_SHIFT (19U) 585 #define USDHC_INT_STATUS_CIE_WIDTH (1U) 586 #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) 587 588 #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) 589 #define USDHC_INT_STATUS_DTOE_SHIFT (20U) 590 #define USDHC_INT_STATUS_DTOE_WIDTH (1U) 591 #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) 592 593 #define USDHC_INT_STATUS_DCE_MASK (0x200000U) 594 #define USDHC_INT_STATUS_DCE_SHIFT (21U) 595 #define USDHC_INT_STATUS_DCE_WIDTH (1U) 596 #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) 597 598 #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) 599 #define USDHC_INT_STATUS_DEBE_SHIFT (22U) 600 #define USDHC_INT_STATUS_DEBE_WIDTH (1U) 601 #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) 602 603 #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) 604 #define USDHC_INT_STATUS_AC12E_SHIFT (24U) 605 #define USDHC_INT_STATUS_AC12E_WIDTH (1U) 606 #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) 607 608 #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) 609 #define USDHC_INT_STATUS_TNE_SHIFT (26U) 610 #define USDHC_INT_STATUS_TNE_WIDTH (1U) 611 #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) 612 613 #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) 614 #define USDHC_INT_STATUS_DMAE_SHIFT (28U) 615 #define USDHC_INT_STATUS_DMAE_WIDTH (1U) 616 #define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) 617 /*! @} */ 618 619 /*! @name INT_STATUS_EN - Interrupt Status Enable */ 620 /*! @{ */ 621 622 #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) 623 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) 624 #define USDHC_INT_STATUS_EN_CCSEN_WIDTH (1U) 625 #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) 626 627 #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) 628 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) 629 #define USDHC_INT_STATUS_EN_TCSEN_WIDTH (1U) 630 #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) 631 632 #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) 633 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) 634 #define USDHC_INT_STATUS_EN_BGESEN_WIDTH (1U) 635 #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) 636 637 #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) 638 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) 639 #define USDHC_INT_STATUS_EN_DINTSEN_WIDTH (1U) 640 #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) 641 642 #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) 643 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) 644 #define USDHC_INT_STATUS_EN_BWRSEN_WIDTH (1U) 645 #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) 646 647 #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) 648 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) 649 #define USDHC_INT_STATUS_EN_BRRSEN_WIDTH (1U) 650 #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) 651 652 #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) 653 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) 654 #define USDHC_INT_STATUS_EN_CINSSEN_WIDTH (1U) 655 #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) 656 657 #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) 658 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) 659 #define USDHC_INT_STATUS_EN_CRMSEN_WIDTH (1U) 660 #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) 661 662 #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) 663 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) 664 #define USDHC_INT_STATUS_EN_CINTSEN_WIDTH (1U) 665 #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) 666 667 #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) 668 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) 669 #define USDHC_INT_STATUS_EN_RTESEN_WIDTH (1U) 670 #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) 671 672 #define USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U) 673 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U) 674 #define USDHC_INT_STATUS_EN_TPSEN_WIDTH (1U) 675 #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) 676 677 #define USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U) 678 #define USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U) 679 #define USDHC_INT_STATUS_EN_CQISEN_WIDTH (1U) 680 #define USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK) 681 682 #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) 683 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) 684 #define USDHC_INT_STATUS_EN_CTOESEN_WIDTH (1U) 685 #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) 686 687 #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) 688 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) 689 #define USDHC_INT_STATUS_EN_CCESEN_WIDTH (1U) 690 #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) 691 692 #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) 693 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) 694 #define USDHC_INT_STATUS_EN_CEBESEN_WIDTH (1U) 695 #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) 696 697 #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) 698 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) 699 #define USDHC_INT_STATUS_EN_CIESEN_WIDTH (1U) 700 #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) 701 702 #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) 703 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) 704 #define USDHC_INT_STATUS_EN_DTOESEN_WIDTH (1U) 705 #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) 706 707 #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) 708 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) 709 #define USDHC_INT_STATUS_EN_DCESEN_WIDTH (1U) 710 #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) 711 712 #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) 713 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) 714 #define USDHC_INT_STATUS_EN_DEBESEN_WIDTH (1U) 715 #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) 716 717 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) 718 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) 719 #define USDHC_INT_STATUS_EN_AC12ESEN_WIDTH (1U) 720 #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) 721 722 #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) 723 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) 724 #define USDHC_INT_STATUS_EN_TNESEN_WIDTH (1U) 725 #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) 726 727 #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) 728 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) 729 #define USDHC_INT_STATUS_EN_DMAESEN_WIDTH (1U) 730 #define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) 731 /*! @} */ 732 733 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ 734 /*! @{ */ 735 736 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) 737 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) 738 #define USDHC_INT_SIGNAL_EN_CCIEN_WIDTH (1U) 739 #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) 740 741 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) 742 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) 743 #define USDHC_INT_SIGNAL_EN_TCIEN_WIDTH (1U) 744 #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) 745 746 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) 747 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) 748 #define USDHC_INT_SIGNAL_EN_BGEIEN_WIDTH (1U) 749 #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) 750 751 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) 752 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) 753 #define USDHC_INT_SIGNAL_EN_DINTIEN_WIDTH (1U) 754 #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) 755 756 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) 757 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) 758 #define USDHC_INT_SIGNAL_EN_BWRIEN_WIDTH (1U) 759 #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) 760 761 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) 762 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) 763 #define USDHC_INT_SIGNAL_EN_BRRIEN_WIDTH (1U) 764 #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) 765 766 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) 767 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) 768 #define USDHC_INT_SIGNAL_EN_CINSIEN_WIDTH (1U) 769 #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) 770 771 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) 772 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) 773 #define USDHC_INT_SIGNAL_EN_CRMIEN_WIDTH (1U) 774 #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) 775 776 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) 777 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) 778 #define USDHC_INT_SIGNAL_EN_CINTIEN_WIDTH (1U) 779 #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) 780 781 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) 782 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) 783 #define USDHC_INT_SIGNAL_EN_RTEIEN_WIDTH (1U) 784 #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) 785 786 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U) 787 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U) 788 #define USDHC_INT_SIGNAL_EN_TPIEN_WIDTH (1U) 789 #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) 790 791 #define USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U) 792 #define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U) 793 #define USDHC_INT_SIGNAL_EN_CQIIEN_WIDTH (1U) 794 #define USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK) 795 796 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) 797 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) 798 #define USDHC_INT_SIGNAL_EN_CTOEIEN_WIDTH (1U) 799 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) 800 801 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) 802 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) 803 #define USDHC_INT_SIGNAL_EN_CCEIEN_WIDTH (1U) 804 #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) 805 806 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) 807 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) 808 #define USDHC_INT_SIGNAL_EN_CEBEIEN_WIDTH (1U) 809 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) 810 811 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) 812 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) 813 #define USDHC_INT_SIGNAL_EN_CIEIEN_WIDTH (1U) 814 #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) 815 816 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) 817 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) 818 #define USDHC_INT_SIGNAL_EN_DTOEIEN_WIDTH (1U) 819 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) 820 821 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) 822 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) 823 #define USDHC_INT_SIGNAL_EN_DCEIEN_WIDTH (1U) 824 #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) 825 826 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) 827 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) 828 #define USDHC_INT_SIGNAL_EN_DEBEIEN_WIDTH (1U) 829 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) 830 831 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) 832 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) 833 #define USDHC_INT_SIGNAL_EN_AC12EIEN_WIDTH (1U) 834 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) 835 836 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) 837 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) 838 #define USDHC_INT_SIGNAL_EN_TNEIEN_WIDTH (1U) 839 #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) 840 841 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) 842 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) 843 #define USDHC_INT_SIGNAL_EN_DMAEIEN_WIDTH (1U) 844 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) 845 /*! @} */ 846 847 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ 848 /*! @{ */ 849 850 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) 851 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) 852 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_WIDTH (1U) 853 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) 854 855 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) 856 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) 857 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_WIDTH (1U) 858 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) 859 860 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x4U) 861 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (2U) 862 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_WIDTH (1U) 863 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) 864 865 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x8U) 866 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (3U) 867 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_WIDTH (1U) 868 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) 869 870 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) 871 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) 872 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_WIDTH (1U) 873 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) 874 875 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) 876 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) 877 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_WIDTH (1U) 878 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) 879 880 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) 881 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) 882 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_WIDTH (1U) 883 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) 884 885 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) 886 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) 887 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_WIDTH (1U) 888 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) 889 /*! @} */ 890 891 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ 892 /*! @{ */ 893 894 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) 895 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) 896 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_WIDTH (1U) 897 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) 898 899 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) 900 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) 901 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_WIDTH (1U) 902 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) 903 904 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) 905 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) 906 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_WIDTH (1U) 907 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) 908 909 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) 910 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) 911 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_WIDTH (1U) 912 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) 913 914 #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) 915 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) 916 #define USDHC_HOST_CTRL_CAP_MBL_WIDTH (3U) 917 #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) 918 919 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) 920 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) 921 #define USDHC_HOST_CTRL_CAP_ADMAS_WIDTH (1U) 922 #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) 923 924 #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) 925 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) 926 #define USDHC_HOST_CTRL_CAP_HSS_WIDTH (1U) 927 #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) 928 929 #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) 930 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) 931 #define USDHC_HOST_CTRL_CAP_DMAS_WIDTH (1U) 932 #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) 933 934 #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) 935 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) 936 #define USDHC_HOST_CTRL_CAP_SRS_WIDTH (1U) 937 #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) 938 939 #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) 940 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) 941 #define USDHC_HOST_CTRL_CAP_VS33_WIDTH (1U) 942 #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) 943 944 #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) 945 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) 946 #define USDHC_HOST_CTRL_CAP_VS30_WIDTH (1U) 947 #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) 948 949 #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) 950 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) 951 #define USDHC_HOST_CTRL_CAP_VS18_WIDTH (1U) 952 #define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) 953 /*! @} */ 954 955 /*! @name WTMK_LVL - Watermark Level */ 956 /*! @{ */ 957 958 #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) 959 #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) 960 #define USDHC_WTMK_LVL_RD_WML_WIDTH (8U) 961 #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) 962 963 #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) 964 #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) 965 #define USDHC_WTMK_LVL_WR_WML_WIDTH (8U) 966 #define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) 967 /*! @} */ 968 969 /*! @name MIX_CTRL - Mixer Control */ 970 /*! @{ */ 971 972 #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) 973 #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) 974 #define USDHC_MIX_CTRL_DMAEN_WIDTH (1U) 975 #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) 976 977 #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) 978 #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) 979 #define USDHC_MIX_CTRL_BCEN_WIDTH (1U) 980 #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) 981 982 #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) 983 #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) 984 #define USDHC_MIX_CTRL_AC12EN_WIDTH (1U) 985 #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) 986 987 #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) 988 #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) 989 #define USDHC_MIX_CTRL_DDR_EN_WIDTH (1U) 990 #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) 991 992 #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) 993 #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) 994 #define USDHC_MIX_CTRL_DTDSEL_WIDTH (1U) 995 #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) 996 997 #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) 998 #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) 999 #define USDHC_MIX_CTRL_MSBSEL_WIDTH (1U) 1000 #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) 1001 1002 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) 1003 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) 1004 #define USDHC_MIX_CTRL_NIBBLE_POS_WIDTH (1U) 1005 #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) 1006 1007 #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) 1008 #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) 1009 #define USDHC_MIX_CTRL_AC23EN_WIDTH (1U) 1010 #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) 1011 1012 #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) 1013 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) 1014 #define USDHC_MIX_CTRL_EXE_TUNE_WIDTH (1U) 1015 #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) 1016 1017 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) 1018 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) 1019 #define USDHC_MIX_CTRL_SMP_CLK_SEL_WIDTH (1U) 1020 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) 1021 1022 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) 1023 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) 1024 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_WIDTH (1U) 1025 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) 1026 1027 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) 1028 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) 1029 #define USDHC_MIX_CTRL_FBCLK_SEL_WIDTH (1U) 1030 #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) 1031 1032 #define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) 1033 #define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) 1034 #define USDHC_MIX_CTRL_HS400_MODE_WIDTH (1U) 1035 #define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) 1036 1037 #define USDHC_MIX_CTRL_EN_HS400_MODE_MASK (0x8000000U) 1038 #define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT (27U) 1039 #define USDHC_MIX_CTRL_EN_HS400_MODE_WIDTH (1U) 1040 #define USDHC_MIX_CTRL_EN_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK) 1041 /*! @} */ 1042 1043 /*! @name FORCE_EVENT - Force Event */ 1044 /*! @{ */ 1045 1046 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) 1047 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) 1048 #define USDHC_FORCE_EVENT_FEVTAC12NE_WIDTH (1U) 1049 #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) 1050 1051 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) 1052 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) 1053 #define USDHC_FORCE_EVENT_FEVTAC12TOE_WIDTH (1U) 1054 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) 1055 1056 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) 1057 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) 1058 #define USDHC_FORCE_EVENT_FEVTAC12CE_WIDTH (1U) 1059 #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) 1060 1061 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) 1062 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) 1063 #define USDHC_FORCE_EVENT_FEVTAC12EBE_WIDTH (1U) 1064 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) 1065 1066 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) 1067 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) 1068 #define USDHC_FORCE_EVENT_FEVTAC12IE_WIDTH (1U) 1069 #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) 1070 1071 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) 1072 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) 1073 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_WIDTH (1U) 1074 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) 1075 1076 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) 1077 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) 1078 #define USDHC_FORCE_EVENT_FEVTCTOE_WIDTH (1U) 1079 #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) 1080 1081 #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) 1082 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) 1083 #define USDHC_FORCE_EVENT_FEVTCCE_WIDTH (1U) 1084 #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) 1085 1086 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) 1087 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) 1088 #define USDHC_FORCE_EVENT_FEVTCEBE_WIDTH (1U) 1089 #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) 1090 1091 #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) 1092 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) 1093 #define USDHC_FORCE_EVENT_FEVTCIE_WIDTH (1U) 1094 #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) 1095 1096 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) 1097 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) 1098 #define USDHC_FORCE_EVENT_FEVTDTOE_WIDTH (1U) 1099 #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) 1100 1101 #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) 1102 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) 1103 #define USDHC_FORCE_EVENT_FEVTDCE_WIDTH (1U) 1104 #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) 1105 1106 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) 1107 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) 1108 #define USDHC_FORCE_EVENT_FEVTDEBE_WIDTH (1U) 1109 #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) 1110 1111 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) 1112 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) 1113 #define USDHC_FORCE_EVENT_FEVTAC12E_WIDTH (1U) 1114 #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) 1115 1116 #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) 1117 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) 1118 #define USDHC_FORCE_EVENT_FEVTTNE_WIDTH (1U) 1119 #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) 1120 1121 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) 1122 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) 1123 #define USDHC_FORCE_EVENT_FEVTDMAE_WIDTH (1U) 1124 #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) 1125 1126 #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) 1127 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) 1128 #define USDHC_FORCE_EVENT_FEVTCINT_WIDTH (1U) 1129 #define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) 1130 /*! @} */ 1131 1132 /*! @name ADMA_ERR_STATUS - ADMA Error Status */ 1133 /*! @{ */ 1134 1135 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) 1136 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) 1137 #define USDHC_ADMA_ERR_STATUS_ADMAES_WIDTH (2U) 1138 #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) 1139 1140 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) 1141 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) 1142 #define USDHC_ADMA_ERR_STATUS_ADMALME_WIDTH (1U) 1143 #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) 1144 1145 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) 1146 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) 1147 #define USDHC_ADMA_ERR_STATUS_ADMADCE_WIDTH (1U) 1148 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) 1149 /*! @} */ 1150 1151 /*! @name ADMA_SYS_ADDR - ADMA System Address */ 1152 /*! @{ */ 1153 1154 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) 1155 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) 1156 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_WIDTH (30U) 1157 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) 1158 /*! @} */ 1159 1160 /*! @name DLL_CTRL - DLL (Delay Line) Control */ 1161 /*! @{ */ 1162 1163 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) 1164 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) 1165 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_WIDTH (1U) 1166 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) 1167 1168 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) 1169 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) 1170 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_WIDTH (1U) 1171 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) 1172 1173 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) 1174 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) 1175 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_WIDTH (1U) 1176 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) 1177 1178 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) 1179 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) 1180 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_WIDTH (4U) 1181 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) 1182 1183 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) 1184 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) 1185 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_WIDTH (1U) 1186 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) 1187 1188 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) 1189 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) 1190 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_WIDTH (1U) 1191 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) 1192 1193 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) 1194 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) 1195 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_WIDTH (7U) 1196 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) 1197 1198 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) 1199 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) 1200 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_WIDTH (3U) 1201 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) 1202 1203 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) 1204 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) 1205 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_WIDTH (8U) 1206 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) 1207 1208 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) 1209 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) 1210 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_WIDTH (4U) 1211 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) 1212 /*! @} */ 1213 1214 /*! @name DLL_STATUS - DLL Status */ 1215 /*! @{ */ 1216 1217 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) 1218 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) 1219 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_WIDTH (1U) 1220 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) 1221 1222 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) 1223 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) 1224 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_WIDTH (1U) 1225 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) 1226 1227 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) 1228 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) 1229 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_WIDTH (7U) 1230 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) 1231 1232 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) 1233 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) 1234 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_WIDTH (7U) 1235 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) 1236 /*! @} */ 1237 1238 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ 1239 /*! @{ */ 1240 1241 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) 1242 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) 1243 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_WIDTH (4U) 1244 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) 1245 1246 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) 1247 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) 1248 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_WIDTH (4U) 1249 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) 1250 1251 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) 1252 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) 1253 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_WIDTH (7U) 1254 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) 1255 1256 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) 1257 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) 1258 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_WIDTH (1U) 1259 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) 1260 1261 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) 1262 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) 1263 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_WIDTH (4U) 1264 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) 1265 1266 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) 1267 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) 1268 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_WIDTH (4U) 1269 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) 1270 1271 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) 1272 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) 1273 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_WIDTH (7U) 1274 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) 1275 1276 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) 1277 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) 1278 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_WIDTH (1U) 1279 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) 1280 /*! @} */ 1281 1282 /*! @name STROBE_DLL_CTRL - Strobe DLL control */ 1283 /*! @{ */ 1284 1285 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) 1286 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) 1287 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_WIDTH (1U) 1288 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) 1289 1290 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) 1291 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) 1292 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_WIDTH (1U) 1293 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) 1294 1295 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) 1296 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) 1297 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_WIDTH (1U) 1298 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) 1299 1300 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) 1301 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) 1302 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_WIDTH (4U) 1303 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) 1304 1305 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U) 1306 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U) 1307 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_WIDTH (1U) 1308 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK) 1309 1310 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) 1311 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) 1312 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_WIDTH (1U) 1313 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) 1314 1315 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) 1316 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) 1317 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_WIDTH (7U) 1318 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) 1319 1320 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) 1321 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) 1322 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_WIDTH (8U) 1323 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) 1324 1325 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) 1326 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) 1327 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_WIDTH (4U) 1328 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK) 1329 /*! @} */ 1330 1331 /*! @name STROBE_DLL_STATUS - Strobe DLL status */ 1332 /*! @{ */ 1333 1334 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) 1335 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) 1336 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_WIDTH (1U) 1337 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) 1338 1339 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) 1340 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) 1341 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_WIDTH (1U) 1342 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) 1343 1344 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) 1345 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) 1346 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_WIDTH (7U) 1347 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) 1348 1349 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) 1350 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) 1351 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_WIDTH (7U) 1352 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK) 1353 /*! @} */ 1354 1355 /*! @name VEND_SPEC - Vendor Specific Register */ 1356 /*! @{ */ 1357 1358 #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) 1359 #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) 1360 #define USDHC_VEND_SPEC_VSELECT_WIDTH (1U) 1361 #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) 1362 1363 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) 1364 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) 1365 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_WIDTH (1U) 1366 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) 1367 1368 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) 1369 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) 1370 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_WIDTH (1U) 1371 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) 1372 1373 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) 1374 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) 1375 #define USDHC_VEND_SPEC_CRC_CHK_DIS_WIDTH (1U) 1376 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) 1377 1378 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) 1379 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) 1380 #define USDHC_VEND_SPEC_CMD_BYTE_EN_WIDTH (1U) 1381 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) 1382 /*! @} */ 1383 1384 /*! @name MMC_BOOT - eMMC Boot */ 1385 /*! @{ */ 1386 1387 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) 1388 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) 1389 #define USDHC_MMC_BOOT_DTOCV_ACK_WIDTH (4U) 1390 #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) 1391 1392 #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) 1393 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) 1394 #define USDHC_MMC_BOOT_BOOT_ACK_WIDTH (1U) 1395 #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) 1396 1397 #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) 1398 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) 1399 #define USDHC_MMC_BOOT_BOOT_MODE_WIDTH (1U) 1400 #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) 1401 1402 #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) 1403 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) 1404 #define USDHC_MMC_BOOT_BOOT_EN_WIDTH (1U) 1405 #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) 1406 1407 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) 1408 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) 1409 #define USDHC_MMC_BOOT_AUTO_SABG_EN_WIDTH (1U) 1410 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) 1411 1412 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) 1413 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) 1414 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_WIDTH (1U) 1415 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) 1416 1417 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) 1418 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) 1419 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_WIDTH (16U) 1420 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) 1421 /*! @} */ 1422 1423 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ 1424 /*! @{ */ 1425 1426 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) 1427 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) 1428 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_WIDTH (1U) 1429 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) 1430 1431 #define USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK (0x30U) 1432 #define USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT (4U) 1433 #define USDHC_VEND_SPEC2_TUNING_BIT_EN_WIDTH (2U) 1434 #define USDHC_VEND_SPEC2_TUNING_BIT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_BIT_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_BIT_EN_MASK) 1435 1436 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) 1437 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) 1438 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_WIDTH (1U) 1439 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) 1440 1441 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) 1442 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) 1443 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_WIDTH (1U) 1444 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) 1445 1446 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) 1447 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) 1448 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_WIDTH (1U) 1449 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) 1450 1451 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) 1452 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) 1453 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_WIDTH (1U) 1454 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) 1455 1456 #define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) 1457 #define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) 1458 #define USDHC_VEND_SPEC2_EN_32K_CLK_WIDTH (1U) 1459 #define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) 1460 1461 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK (0xFFFF0000U) 1462 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT (16U) 1463 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_WIDTH (16U) 1464 #define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK) 1465 /*! @} */ 1466 1467 /*! @name TUNING_CTRL - Tuning Control */ 1468 /*! @{ */ 1469 1470 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU) 1471 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) 1472 #define USDHC_TUNING_CTRL_TUNING_START_TAP_WIDTH (7U) 1473 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) 1474 1475 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U) 1476 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U) 1477 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_WIDTH (1U) 1478 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK) 1479 1480 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) 1481 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) 1482 #define USDHC_TUNING_CTRL_TUNING_COUNTER_WIDTH (8U) 1483 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) 1484 1485 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) 1486 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) 1487 #define USDHC_TUNING_CTRL_TUNING_STEP_WIDTH (3U) 1488 #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) 1489 1490 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) 1491 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) 1492 #define USDHC_TUNING_CTRL_TUNING_WINDOW_WIDTH (3U) 1493 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) 1494 1495 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) 1496 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) 1497 #define USDHC_TUNING_CTRL_STD_TUNING_EN_WIDTH (1U) 1498 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) 1499 /*! @} */ 1500 1501 /*! @name CQVER - Command Queuing Version */ 1502 /*! @{ */ 1503 1504 #define USDHC_CQVER_VERSION_SUFFIX_MASK (0xFU) 1505 #define USDHC_CQVER_VERSION_SUFFIX_SHIFT (0U) 1506 #define USDHC_CQVER_VERSION_SUFFIX_WIDTH (4U) 1507 #define USDHC_CQVER_VERSION_SUFFIX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK) 1508 1509 #define USDHC_CQVER_MINOR_VN_MASK (0xF0U) 1510 #define USDHC_CQVER_MINOR_VN_SHIFT (4U) 1511 #define USDHC_CQVER_MINOR_VN_WIDTH (4U) 1512 #define USDHC_CQVER_MINOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK) 1513 1514 #define USDHC_CQVER_MAJOR_VN_MASK (0xF00U) 1515 #define USDHC_CQVER_MAJOR_VN_SHIFT (8U) 1516 #define USDHC_CQVER_MAJOR_VN_WIDTH (4U) 1517 #define USDHC_CQVER_MAJOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK) 1518 /*! @} */ 1519 1520 /*! @name CQCAP - Command Queuing Capabilities */ 1521 /*! @{ */ 1522 1523 #define USDHC_CQCAP_ITCFVAL_MASK (0x3FFU) 1524 #define USDHC_CQCAP_ITCFVAL_SHIFT (0U) 1525 #define USDHC_CQCAP_ITCFVAL_WIDTH (10U) 1526 #define USDHC_CQCAP_ITCFVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK) 1527 1528 #define USDHC_CQCAP_ITCFMUL_MASK (0xF000U) 1529 #define USDHC_CQCAP_ITCFMUL_SHIFT (12U) 1530 #define USDHC_CQCAP_ITCFMUL_WIDTH (4U) 1531 #define USDHC_CQCAP_ITCFMUL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK) 1532 /*! @} */ 1533 1534 /*! @name CQCFG - Command Queuing Configuration */ 1535 /*! @{ */ 1536 1537 #define USDHC_CQCFG_CQUE_MASK (0x1U) 1538 #define USDHC_CQCFG_CQUE_SHIFT (0U) 1539 #define USDHC_CQCFG_CQUE_WIDTH (1U) 1540 #define USDHC_CQCFG_CQUE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK) 1541 1542 #define USDHC_CQCFG_TDS_MASK (0x100U) 1543 #define USDHC_CQCFG_TDS_SHIFT (8U) 1544 #define USDHC_CQCFG_TDS_WIDTH (1U) 1545 #define USDHC_CQCFG_TDS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK) 1546 1547 #define USDHC_CQCFG_DCMDE_MASK (0x1000U) 1548 #define USDHC_CQCFG_DCMDE_SHIFT (12U) 1549 #define USDHC_CQCFG_DCMDE_WIDTH (1U) 1550 #define USDHC_CQCFG_DCMDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK) 1551 /*! @} */ 1552 1553 /*! @name CQCTL - Command Queuing Control */ 1554 /*! @{ */ 1555 1556 #define USDHC_CQCTL_HALT_MASK (0x1U) 1557 #define USDHC_CQCTL_HALT_SHIFT (0U) 1558 #define USDHC_CQCTL_HALT_WIDTH (1U) 1559 #define USDHC_CQCTL_HALT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK) 1560 1561 #define USDHC_CQCTL_CLEAR_MASK (0x100U) 1562 #define USDHC_CQCTL_CLEAR_SHIFT (8U) 1563 #define USDHC_CQCTL_CLEAR_WIDTH (1U) 1564 #define USDHC_CQCTL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK) 1565 /*! @} */ 1566 1567 /*! @name CQIS - Command Queuing Interrupt Status */ 1568 /*! @{ */ 1569 1570 #define USDHC_CQIS_HAC_MASK (0x1U) 1571 #define USDHC_CQIS_HAC_SHIFT (0U) 1572 #define USDHC_CQIS_HAC_WIDTH (1U) 1573 #define USDHC_CQIS_HAC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK) 1574 1575 #define USDHC_CQIS_TCC_MASK (0x2U) 1576 #define USDHC_CQIS_TCC_SHIFT (1U) 1577 #define USDHC_CQIS_TCC_WIDTH (1U) 1578 #define USDHC_CQIS_TCC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK) 1579 1580 #define USDHC_CQIS_RED_MASK (0x4U) 1581 #define USDHC_CQIS_RED_SHIFT (2U) 1582 #define USDHC_CQIS_RED_WIDTH (1U) 1583 #define USDHC_CQIS_RED(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK) 1584 1585 #define USDHC_CQIS_TCL_MASK (0x8U) 1586 #define USDHC_CQIS_TCL_SHIFT (3U) 1587 #define USDHC_CQIS_TCL_WIDTH (1U) 1588 #define USDHC_CQIS_TCL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK) 1589 /*! @} */ 1590 1591 /*! @name CQISTE - Command Queuing Interrupt Status Enable */ 1592 /*! @{ */ 1593 1594 #define USDHC_CQISTE_HAC_STE_MASK (0x1U) 1595 #define USDHC_CQISTE_HAC_STE_SHIFT (0U) 1596 #define USDHC_CQISTE_HAC_STE_WIDTH (1U) 1597 #define USDHC_CQISTE_HAC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK) 1598 1599 #define USDHC_CQISTE_TCC_STE_MASK (0x2U) 1600 #define USDHC_CQISTE_TCC_STE_SHIFT (1U) 1601 #define USDHC_CQISTE_TCC_STE_WIDTH (1U) 1602 #define USDHC_CQISTE_TCC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK) 1603 1604 #define USDHC_CQISTE_RED_STE_MASK (0x4U) 1605 #define USDHC_CQISTE_RED_STE_SHIFT (2U) 1606 #define USDHC_CQISTE_RED_STE_WIDTH (1U) 1607 #define USDHC_CQISTE_RED_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK) 1608 1609 #define USDHC_CQISTE_TCL_STE_MASK (0x8U) 1610 #define USDHC_CQISTE_TCL_STE_SHIFT (3U) 1611 #define USDHC_CQISTE_TCL_STE_WIDTH (1U) 1612 #define USDHC_CQISTE_TCL_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK) 1613 /*! @} */ 1614 1615 /*! @name CQISGE - Command Queuing Interrupt Signal Enable */ 1616 /*! @{ */ 1617 1618 #define USDHC_CQISGE_HAC_SGE_MASK (0x1U) 1619 #define USDHC_CQISGE_HAC_SGE_SHIFT (0U) 1620 #define USDHC_CQISGE_HAC_SGE_WIDTH (1U) 1621 #define USDHC_CQISGE_HAC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK) 1622 1623 #define USDHC_CQISGE_TCC_SGE_MASK (0x2U) 1624 #define USDHC_CQISGE_TCC_SGE_SHIFT (1U) 1625 #define USDHC_CQISGE_TCC_SGE_WIDTH (1U) 1626 #define USDHC_CQISGE_TCC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK) 1627 1628 #define USDHC_CQISGE_RED_SGE_MASK (0x4U) 1629 #define USDHC_CQISGE_RED_SGE_SHIFT (2U) 1630 #define USDHC_CQISGE_RED_SGE_WIDTH (1U) 1631 #define USDHC_CQISGE_RED_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK) 1632 1633 #define USDHC_CQISGE_TCL_SGE_MASK (0x8U) 1634 #define USDHC_CQISGE_TCL_SGE_SHIFT (3U) 1635 #define USDHC_CQISGE_TCL_SGE_WIDTH (1U) 1636 #define USDHC_CQISGE_TCL_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK) 1637 /*! @} */ 1638 1639 /*! @name CQIC - Command Queuing Interrupt Coalescing */ 1640 /*! @{ */ 1641 1642 #define USDHC_CQIC_ICTOVAL_MASK (0x7FU) 1643 #define USDHC_CQIC_ICTOVAL_SHIFT (0U) 1644 #define USDHC_CQIC_ICTOVAL_WIDTH (7U) 1645 #define USDHC_CQIC_ICTOVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK) 1646 1647 #define USDHC_CQIC_ICTOVALWEN_MASK (0x80U) 1648 #define USDHC_CQIC_ICTOVALWEN_SHIFT (7U) 1649 #define USDHC_CQIC_ICTOVALWEN_WIDTH (1U) 1650 #define USDHC_CQIC_ICTOVALWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK) 1651 1652 #define USDHC_CQIC_ICCTH_MASK (0x1F00U) 1653 #define USDHC_CQIC_ICCTH_SHIFT (8U) 1654 #define USDHC_CQIC_ICCTH_WIDTH (5U) 1655 #define USDHC_CQIC_ICCTH(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK) 1656 1657 #define USDHC_CQIC_ICCTHWEN_MASK (0x8000U) 1658 #define USDHC_CQIC_ICCTHWEN_SHIFT (15U) 1659 #define USDHC_CQIC_ICCTHWEN_WIDTH (1U) 1660 #define USDHC_CQIC_ICCTHWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK) 1661 1662 #define USDHC_CQIC_ICCTR_MASK (0x10000U) 1663 #define USDHC_CQIC_ICCTR_SHIFT (16U) 1664 #define USDHC_CQIC_ICCTR_WIDTH (1U) 1665 #define USDHC_CQIC_ICCTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK) 1666 1667 #define USDHC_CQIC_ICSB_MASK (0x100000U) 1668 #define USDHC_CQIC_ICSB_SHIFT (20U) 1669 #define USDHC_CQIC_ICSB_WIDTH (1U) 1670 #define USDHC_CQIC_ICSB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK) 1671 1672 #define USDHC_CQIC_ICENDIS_MASK (0x80000000U) 1673 #define USDHC_CQIC_ICENDIS_SHIFT (31U) 1674 #define USDHC_CQIC_ICENDIS_WIDTH (1U) 1675 #define USDHC_CQIC_ICENDIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK) 1676 /*! @} */ 1677 1678 /*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */ 1679 /*! @{ */ 1680 1681 #define USDHC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFU) 1682 #define USDHC_CQTDLBA_TDLBA_SHIFT (0U) 1683 #define USDHC_CQTDLBA_TDLBA_WIDTH (32U) 1684 #define USDHC_CQTDLBA_TDLBA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK) 1685 /*! @} */ 1686 1687 /*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */ 1688 /*! @{ */ 1689 1690 #define USDHC_CQTDLBAU_TDLBAU_MASK (0xFFFFFFFFU) 1691 #define USDHC_CQTDLBAU_TDLBAU_SHIFT (0U) 1692 #define USDHC_CQTDLBAU_TDLBAU_WIDTH (32U) 1693 #define USDHC_CQTDLBAU_TDLBAU(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK) 1694 /*! @} */ 1695 1696 /*! @name CQTDBR - Command Queuing Task Doorbell */ 1697 /*! @{ */ 1698 1699 #define USDHC_CQTDBR_TDBR_MASK (0xFFFFFFFFU) 1700 #define USDHC_CQTDBR_TDBR_SHIFT (0U) 1701 #define USDHC_CQTDBR_TDBR_WIDTH (32U) 1702 #define USDHC_CQTDBR_TDBR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK) 1703 /*! @} */ 1704 1705 /*! @name CQTCN - Command Queuing Task Completion Notification */ 1706 /*! @{ */ 1707 1708 #define USDHC_CQTCN_TCN_MASK (0xFFFFFFFFU) 1709 #define USDHC_CQTCN_TCN_SHIFT (0U) 1710 #define USDHC_CQTCN_TCN_WIDTH (32U) 1711 #define USDHC_CQTCN_TCN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK) 1712 /*! @} */ 1713 1714 /*! @name CQDQS - Command Queuing Device Queue Status */ 1715 /*! @{ */ 1716 1717 #define USDHC_CQDQS_DQS_MASK (0xFFFFFFFFU) 1718 #define USDHC_CQDQS_DQS_SHIFT (0U) 1719 #define USDHC_CQDQS_DQS_WIDTH (32U) 1720 #define USDHC_CQDQS_DQS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK) 1721 /*! @} */ 1722 1723 /*! @name CQDPT - Command Queuing Device Pending Tasks */ 1724 /*! @{ */ 1725 1726 #define USDHC_CQDPT_DPT_MASK (0xFFFFFFFFU) 1727 #define USDHC_CQDPT_DPT_SHIFT (0U) 1728 #define USDHC_CQDPT_DPT_WIDTH (32U) 1729 #define USDHC_CQDPT_DPT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK) 1730 /*! @} */ 1731 1732 /*! @name CQTCLR - Command Queuing Task Clear */ 1733 /*! @{ */ 1734 1735 #define USDHC_CQTCLR_TCLR_MASK (0xFFFFFFFFU) 1736 #define USDHC_CQTCLR_TCLR_SHIFT (0U) 1737 #define USDHC_CQTCLR_TCLR_WIDTH (32U) 1738 #define USDHC_CQTCLR_TCLR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK) 1739 /*! @} */ 1740 1741 /*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */ 1742 /*! @{ */ 1743 1744 #define USDHC_CQSSC1_CIT_MASK (0xFFFFU) 1745 #define USDHC_CQSSC1_CIT_SHIFT (0U) 1746 #define USDHC_CQSSC1_CIT_WIDTH (16U) 1747 #define USDHC_CQSSC1_CIT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK) 1748 1749 #define USDHC_CQSSC1_CBC_MASK (0xF0000U) 1750 #define USDHC_CQSSC1_CBC_SHIFT (16U) 1751 #define USDHC_CQSSC1_CBC_WIDTH (4U) 1752 #define USDHC_CQSSC1_CBC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK) 1753 /*! @} */ 1754 1755 /*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */ 1756 /*! @{ */ 1757 1758 #define USDHC_CQSSC2_SSC2_MASK (0xFFFFU) 1759 #define USDHC_CQSSC2_SSC2_SHIFT (0U) 1760 #define USDHC_CQSSC2_SSC2_WIDTH (16U) 1761 #define USDHC_CQSSC2_SSC2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK) 1762 /*! @} */ 1763 1764 /*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */ 1765 /*! @{ */ 1766 1767 #define USDHC_CQCRDCT_CRDCT_MASK (0xFFFFFFFFU) 1768 #define USDHC_CQCRDCT_CRDCT_SHIFT (0U) 1769 #define USDHC_CQCRDCT_CRDCT_WIDTH (32U) 1770 #define USDHC_CQCRDCT_CRDCT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK) 1771 /*! @} */ 1772 1773 /*! @name CQRMEM - Command Queuing Response Mode Error Mask */ 1774 /*! @{ */ 1775 1776 #define USDHC_CQRMEM_RMEM_MASK (0xFFFFFFFFU) 1777 #define USDHC_CQRMEM_RMEM_SHIFT (0U) 1778 #define USDHC_CQRMEM_RMEM_WIDTH (32U) 1779 #define USDHC_CQRMEM_RMEM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK) 1780 /*! @} */ 1781 1782 /*! @name CQTERRI - Command Queuing Task Error Information */ 1783 /*! @{ */ 1784 1785 #define USDHC_CQTERRI_RMECI_MASK (0x3FU) 1786 #define USDHC_CQTERRI_RMECI_SHIFT (0U) 1787 #define USDHC_CQTERRI_RMECI_WIDTH (6U) 1788 #define USDHC_CQTERRI_RMECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK) 1789 1790 #define USDHC_CQTERRI_RMETID_MASK (0x1F00U) 1791 #define USDHC_CQTERRI_RMETID_SHIFT (8U) 1792 #define USDHC_CQTERRI_RMETID_WIDTH (5U) 1793 #define USDHC_CQTERRI_RMETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK) 1794 1795 #define USDHC_CQTERRI_RMEFV_MASK (0x8000U) 1796 #define USDHC_CQTERRI_RMEFV_SHIFT (15U) 1797 #define USDHC_CQTERRI_RMEFV_WIDTH (1U) 1798 #define USDHC_CQTERRI_RMEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK) 1799 1800 #define USDHC_CQTERRI_DTECI_MASK (0x3F0000U) 1801 #define USDHC_CQTERRI_DTECI_SHIFT (16U) 1802 #define USDHC_CQTERRI_DTECI_WIDTH (6U) 1803 #define USDHC_CQTERRI_DTECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK) 1804 1805 #define USDHC_CQTERRI_DTETID_MASK (0x1F000000U) 1806 #define USDHC_CQTERRI_DTETID_SHIFT (24U) 1807 #define USDHC_CQTERRI_DTETID_WIDTH (5U) 1808 #define USDHC_CQTERRI_DTETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK) 1809 1810 #define USDHC_CQTERRI_DTEFV_MASK (0x80000000U) 1811 #define USDHC_CQTERRI_DTEFV_SHIFT (31U) 1812 #define USDHC_CQTERRI_DTEFV_WIDTH (1U) 1813 #define USDHC_CQTERRI_DTEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK) 1814 /*! @} */ 1815 1816 /*! @name CQCRI - Command Queuing Command Response Index */ 1817 /*! @{ */ 1818 1819 #define USDHC_CQCRI_LCMDRI_MASK (0x3FU) 1820 #define USDHC_CQCRI_LCMDRI_SHIFT (0U) 1821 #define USDHC_CQCRI_LCMDRI_WIDTH (6U) 1822 #define USDHC_CQCRI_LCMDRI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK) 1823 /*! @} */ 1824 1825 /*! @name CQCRA - Command Queuing Command Response Argument */ 1826 /*! @{ */ 1827 1828 #define USDHC_CQCRA_LCMDRA_MASK (0xFFFFFFFFU) 1829 #define USDHC_CQCRA_LCMDRA_SHIFT (0U) 1830 #define USDHC_CQCRA_LCMDRA_WIDTH (32U) 1831 #define USDHC_CQCRA_LCMDRA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK) 1832 /*! @} */ 1833 1834 /*! 1835 * @} 1836 */ /* end of group USDHC_Register_Masks */ 1837 1838 /*! 1839 * @} 1840 */ /* end of group USDHC_Peripheral_Access_Layer */ 1841 1842 #endif /* #if !defined(S32Z2_USDHC_H_) */ 1843
