1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SEC_S250.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SEC_S250 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SEC_S250_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SEC_S250_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SEC_S250 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SEC_S250_Peripheral_Access_Layer SEC_S250 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SEC_S250 - Size of Registers Arrays */ 72 #define SEC_S250_HSE_GPR_2TO11_COUNT 10u 73 74 /** SEC_S250 - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[8]; 77 __I uint32_t MISCDAT0; /**< Miscellaneous Data 0, offset: 0x8 */ 78 uint8_t RESERVED_1[16]; 79 __IO uint32_t HSE_DAT0; /**< HSE_H Data 0, offset: 0x1C */ 80 uint8_t RESERVED_2[4]; 81 __IO uint32_t HSE_DAT[SEC_S250_HSE_GPR_2TO11_COUNT]; /**< HSE_H Data n, array offset: 0x24, array step: 0x4 */ 82 __IO uint32_t HSE_QSPI0_DAT0; /**< QuadSPI_0 Data 0, offset: 0x4C */ 83 __IO uint32_t HSE_QSPI0_DAT1; /**< QuadSPI_0 Data 1, offset: 0x50 */ 84 __IO uint32_t HSE_QSPI1_DAT0; /**< QuadSPI_1 Data 0, offset: 0x54 */ 85 __IO uint32_t HSE_QSPI1_DAT1; /**< QuadSPI_1 Data 1, offset: 0x58 */ 86 } SEC_S250_Type, *SEC_S250_MemMapPtr; 87 88 /** Number of instances of the SEC_S250 module. */ 89 #define SEC_S250_INSTANCE_COUNT (1u) 90 91 /* SEC_S250 - Peripheral instance base addresses */ 92 /** Peripheral SEC base address */ 93 #define IP_SEC_BASE (0x42280000u) 94 /** Peripheral SEC base pointer */ 95 #define IP_SEC ((SEC_S250_Type *)IP_SEC_BASE) 96 /** Array initializer of SEC_S250 peripheral base addresses */ 97 #define IP_SEC_S250_BASE_ADDRS { IP_SEC_BASE } 98 /** Array initializer of SEC_S250 peripheral base pointers */ 99 #define IP_SEC_S250_BASE_PTRS { IP_SEC } 100 101 /* ---------------------------------------------------------------------------- 102 -- SEC_S250 Register Masks 103 ---------------------------------------------------------------------------- */ 104 105 /*! 106 * @addtogroup SEC_S250_Register_Masks SEC_S250 Register Masks 107 * @{ 108 */ 109 110 /*! @name MISCDAT0 - Miscellaneous Data 0 */ 111 /*! @{ */ 112 113 #define SEC_S250_MISCDAT0_EDB_MASK (0x1U) 114 #define SEC_S250_MISCDAT0_EDB_SHIFT (0U) 115 #define SEC_S250_MISCDAT0_EDB_WIDTH (1U) 116 #define SEC_S250_MISCDAT0_EDB(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_MISCDAT0_EDB_SHIFT)) & SEC_S250_MISCDAT0_EDB_MASK) 117 /*! @} */ 118 119 /*! @name HSE_DAT0 - HSE_H Data 0 */ 120 /*! @{ */ 121 122 #define SEC_S250_HSE_DAT0_DATA0_MASK (0x3FU) 123 #define SEC_S250_HSE_DAT0_DATA0_SHIFT (0U) 124 #define SEC_S250_HSE_DAT0_DATA0_WIDTH (6U) 125 #define SEC_S250_HSE_DAT0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_DAT0_DATA0_SHIFT)) & SEC_S250_HSE_DAT0_DATA0_MASK) 126 127 #define SEC_S250_HSE_DAT0_EDB_NEW_MASK (0x40U) 128 #define SEC_S250_HSE_DAT0_EDB_NEW_SHIFT (6U) 129 #define SEC_S250_HSE_DAT0_EDB_NEW_WIDTH (1U) 130 #define SEC_S250_HSE_DAT0_EDB_NEW(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_DAT0_EDB_NEW_SHIFT)) & SEC_S250_HSE_DAT0_EDB_NEW_MASK) 131 132 #define SEC_S250_HSE_DAT0_DATA1_MASK (0xFFFFFF80U) 133 #define SEC_S250_HSE_DAT0_DATA1_SHIFT (7U) 134 #define SEC_S250_HSE_DAT0_DATA1_WIDTH (25U) 135 #define SEC_S250_HSE_DAT0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_DAT0_DATA1_SHIFT)) & SEC_S250_HSE_DAT0_DATA1_MASK) 136 /*! @} */ 137 138 /*! @name HSE_DAT - HSE_H Data n */ 139 /*! @{ */ 140 141 #define SEC_S250_HSE_DAT_DATA_MASK (0xFFFFFFFFU) 142 #define SEC_S250_HSE_DAT_DATA_SHIFT (0U) 143 #define SEC_S250_HSE_DAT_DATA_WIDTH (32U) 144 #define SEC_S250_HSE_DAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_DAT_DATA_SHIFT)) & SEC_S250_HSE_DAT_DATA_MASK) 145 /*! @} */ 146 147 /*! @name HSE_QSPI0_DAT0 - QuadSPI_0 Data 0 */ 148 /*! @{ */ 149 150 #define SEC_S250_HSE_QSPI0_DAT0_DATA0_MASK (0x3FU) 151 #define SEC_S250_HSE_QSPI0_DAT0_DATA0_SHIFT (0U) 152 #define SEC_S250_HSE_QSPI0_DAT0_DATA0_WIDTH (6U) 153 #define SEC_S250_HSE_QSPI0_DAT0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI0_DAT0_DATA0_SHIFT)) & SEC_S250_HSE_QSPI0_DAT0_DATA0_MASK) 154 155 #define SEC_S250_HSE_QSPI0_DAT0_DATA1_MASK (0x100U) 156 #define SEC_S250_HSE_QSPI0_DAT0_DATA1_SHIFT (8U) 157 #define SEC_S250_HSE_QSPI0_DAT0_DATA1_WIDTH (1U) 158 #define SEC_S250_HSE_QSPI0_DAT0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI0_DAT0_DATA1_SHIFT)) & SEC_S250_HSE_QSPI0_DAT0_DATA1_MASK) 159 /*! @} */ 160 161 /*! @name HSE_QSPI0_DAT1 - QuadSPI_0 Data 1 */ 162 /*! @{ */ 163 164 #define SEC_S250_HSE_QSPI0_DAT1_DATA0_MASK (0x7FFU) 165 #define SEC_S250_HSE_QSPI0_DAT1_DATA0_SHIFT (0U) 166 #define SEC_S250_HSE_QSPI0_DAT1_DATA0_WIDTH (11U) 167 #define SEC_S250_HSE_QSPI0_DAT1_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI0_DAT1_DATA0_SHIFT)) & SEC_S250_HSE_QSPI0_DAT1_DATA0_MASK) 168 169 #define SEC_S250_HSE_QSPI0_DAT1_DATA1_MASK (0x10000U) 170 #define SEC_S250_HSE_QSPI0_DAT1_DATA1_SHIFT (16U) 171 #define SEC_S250_HSE_QSPI0_DAT1_DATA1_WIDTH (1U) 172 #define SEC_S250_HSE_QSPI0_DAT1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI0_DAT1_DATA1_SHIFT)) & SEC_S250_HSE_QSPI0_DAT1_DATA1_MASK) 173 /*! @} */ 174 175 /*! @name HSE_QSPI1_DAT0 - QuadSPI_1 Data 0 */ 176 /*! @{ */ 177 178 #define SEC_S250_HSE_QSPI1_DAT0_DATA0_MASK (0x3FU) 179 #define SEC_S250_HSE_QSPI1_DAT0_DATA0_SHIFT (0U) 180 #define SEC_S250_HSE_QSPI1_DAT0_DATA0_WIDTH (6U) 181 #define SEC_S250_HSE_QSPI1_DAT0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI1_DAT0_DATA0_SHIFT)) & SEC_S250_HSE_QSPI1_DAT0_DATA0_MASK) 182 183 #define SEC_S250_HSE_QSPI1_DAT0_DATA1_MASK (0x100U) 184 #define SEC_S250_HSE_QSPI1_DAT0_DATA1_SHIFT (8U) 185 #define SEC_S250_HSE_QSPI1_DAT0_DATA1_WIDTH (1U) 186 #define SEC_S250_HSE_QSPI1_DAT0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI1_DAT0_DATA1_SHIFT)) & SEC_S250_HSE_QSPI1_DAT0_DATA1_MASK) 187 /*! @} */ 188 189 /*! @name HSE_QSPI1_DAT1 - QuadSPI_1 Data 1 */ 190 /*! @{ */ 191 192 #define SEC_S250_HSE_QSPI1_DAT1_DATA0_MASK (0x7FFU) 193 #define SEC_S250_HSE_QSPI1_DAT1_DATA0_SHIFT (0U) 194 #define SEC_S250_HSE_QSPI1_DAT1_DATA0_WIDTH (11U) 195 #define SEC_S250_HSE_QSPI1_DAT1_DATA0(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI1_DAT1_DATA0_SHIFT)) & SEC_S250_HSE_QSPI1_DAT1_DATA0_MASK) 196 197 #define SEC_S250_HSE_QSPI1_DAT1_DATA1_MASK (0x10000U) 198 #define SEC_S250_HSE_QSPI1_DAT1_DATA1_SHIFT (16U) 199 #define SEC_S250_HSE_QSPI1_DAT1_DATA1_WIDTH (1U) 200 #define SEC_S250_HSE_QSPI1_DAT1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << SEC_S250_HSE_QSPI1_DAT1_DATA1_SHIFT)) & SEC_S250_HSE_QSPI1_DAT1_DATA1_MASK) 201 /*! @} */ 202 203 /*! 204 * @} 205 */ /* end of group SEC_S250_Register_Masks */ 206 207 /*! 208 * @} 209 */ /* end of group SEC_S250_Peripheral_Access_Layer */ 210 211 #endif /* #if !defined(S32Z2_SEC_S250_H_) */ 212
