1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_RTU_L_VFCCU.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_RTU_L_VFCCU
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_RTU_L_VFCCU_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_RTU_L_VFCCU_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- RTU_L_VFCCU Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup RTU_L_VFCCU_Peripheral_Access_Layer RTU_L_VFCCU Peripheral Access Layer
68  * @{
69  */
70 
71 /** RTU_L_VFCCU - Size of Registers Arrays */
72 #define RTU_L_VFCCU_SW_RKN_COUNT                  6u
73 
74 /** RTU_L_VFCCU - Register Layout Typedef */
75 typedef struct {
76   __IO uint32_t GDFHID_C0;                         /**< Global DID-FHID Map, offset: 0x0 */
77   __IO uint32_t GDFHID_C1;                         /**< Global DID-FHID Map, offset: 0x4 */
78   uint8_t RESERVED_0[24];
79   __IO uint32_t GFLTPO_C0;                         /**< Global Fault Polarity, offset: 0x20 */
80   __IO uint32_t GFLTPO_C1;                         /**< Global Fault Polarity, offset: 0x24 */
81   uint8_t RESERVED_1[56];
82   __IO uint32_t GFLTRC_C0;                         /**< Global Fault Recovery, offset: 0x60 */
83   __IO uint32_t GFLTRC_C1;                         /**< Global Fault Recovery, offset: 0x64 */
84   uint8_t RESERVED_2[56];
85   __IO uint32_t GFLTOVDC0;                         /**< Global Fault Overflow Detection, offset: 0xA0 */
86   __IO uint32_t GFLTOVDC1;                         /**< Global Fault Overflow Detection, offset: 0xA4 */
87   uint8_t RESERVED_3[104];
88   __IO uint32_t GSWFLODC;                          /**< Global Software Fault Overflow Detection Disable, offset: 0x110 */
89   uint8_t RESERVED_4[28];
90   __IO uint32_t GCTRL;                             /**< Global Space Control, offset: 0x130 */
91   __IO uint32_t GINTOVFS;                          /**< Global DID FSM Status, offset: 0x134 */
92   uint8_t RESERVED_5[428];
93   __IO uint32_t GDBGCFG;                           /**< Global Debug, offset: 0x2E4 */
94   __I  uint32_t GDBGSTAT;                          /**< Global Debug Status, offset: 0x2E8 */
95   uint8_t RESERVED_6[15636];
96   struct RTU_L_VFCCU_SW_RKN {                      /* offset: 0x4000, array step: 0x20 */
97     __I  uint32_t SWRPTDID;                          /**< Software Fault Reported DID, array offset: 0x4000, array step: 0x20 */
98     __IO uint32_t SWRKSET_0;                         /**< Software Reaction Set, array offset: 0x4004, array step: 0x20 */
99     uint8_t RESERVED_0[4];
100     __IO uint32_t SWRKCLR_0;                         /**< Software Reaction Clear, array offset: 0x400C, array step: 0x20 */
101     uint8_t RESERVED_1[16];
102   } SW_RKN[RTU_L_VFCCU_SW_RKN_COUNT];
103   uint8_t RESERVED_7[16192];
104   __IO uint32_t FHCFG0;                            /**< Fault Handler, offset: 0x8000 */
105   __I  uint32_t FHSRVDS0;                          /**< Fault Handler Status, offset: 0x8004 */
106   uint8_t RESERVED_8[8];
107   __IO uint32_t FHFLTENC00;                        /**< Fault Enable, offset: 0x8010 */
108   __IO uint32_t FHFLTENC01;                        /**< Fault Enable, offset: 0x8014 */
109   uint8_t RESERVED_9[56];
110   __IO uint32_t FHFLTS00;                          /**< Fault Status, offset: 0x8050 */
111   __IO uint32_t FHFLTS01;                          /**< Fault Status, offset: 0x8054 */
112   uint8_t RESERVED_10[56];
113   __IO uint32_t FHFLTRKC00;                        /**< Fault Reaction Set Configuration, offset: 0x8090 */
114   __IO uint32_t FHFLTRKC01;                        /**< Fault Reaction Set Configuration, offset: 0x8094 */
115   __IO uint32_t FHFLTRKC02;                        /**< Fault Reaction Set Configuration, offset: 0x8098 */
116   __IO uint32_t FHFLTRKC03;                        /**< Fault Reaction Set Configuration, offset: 0x809C */
117   __IO uint32_t FHFLTRKC04;                        /**< Fault Reaction Set Configuration, offset: 0x80A0 */
118   __IO uint32_t FHFLTRKC05;                        /**< Fault Reaction Set Configuration, offset: 0x80A4 */
119   __IO uint32_t FHFLTRKC06;                        /**< Fault Reaction Set Configuration, offset: 0x80A8 */
120   uint8_t RESERVED_11[228];
121   __IO uint32_t FHIMRKC0_00;                       /**< Immediate Reaction Configuration, offset: 0x8190 */
122   uint8_t RESERVED_12[12];
123   __IO uint32_t FHIMRKC0_10;                       /**< Immediate Reaction Configuration, offset: 0x81A0 */
124   uint8_t RESERVED_13[12];
125   __IO uint32_t FHIMRKC0_20;                       /**< Immediate Reaction Configuration, offset: 0x81B0 */
126   uint8_t RESERVED_14[12];
127   __IO uint32_t FHIMRKC0_30;                       /**< Immediate Reaction Configuration, offset: 0x81C0 */
128   uint8_t RESERVED_15[12];
129   __IO uint32_t FHIMRKC0_40;                       /**< Immediate Reaction Configuration, offset: 0x81D0 */
130   uint8_t RESERVED_16[12];
131   __IO uint32_t FHIMRKC0_50;                       /**< Immediate Reaction Configuration, offset: 0x81E0 */
132 } RTU_L_VFCCU_Type, *RTU_L_VFCCU_MemMapPtr;
133 
134 /** Number of instances of the RTU_L_VFCCU module. */
135 #define RTU_L_VFCCU_INSTANCE_COUNT               (2u)
136 
137 /* RTU_L_VFCCU - Peripheral instance base addresses */
138 /** Peripheral RTU0__L_VFCCU base address */
139 #define IP_RTU0__L_VFCCU_BASE                    (0x76130000u)
140 /** Peripheral RTU0__L_VFCCU base pointer */
141 #define IP_RTU0__L_VFCCU                         ((RTU_L_VFCCU_Type *)IP_RTU0__L_VFCCU_BASE)
142 /** Peripheral RTU1__L_VFCCU base address */
143 #define IP_RTU1__L_VFCCU_BASE                    (0x76930000u)
144 /** Peripheral RTU1__L_VFCCU base pointer */
145 #define IP_RTU1__L_VFCCU                         ((RTU_L_VFCCU_Type *)IP_RTU1__L_VFCCU_BASE)
146 /** Array initializer of RTU_L_VFCCU peripheral base addresses */
147 #define IP_RTU_L_VFCCU_BASE_ADDRS                { IP_RTU0__L_VFCCU_BASE, IP_RTU1__L_VFCCU_BASE }
148 /** Array initializer of RTU_L_VFCCU peripheral base pointers */
149 #define IP_RTU_L_VFCCU_BASE_PTRS                 { IP_RTU0__L_VFCCU, IP_RTU1__L_VFCCU }
150 
151 /* ----------------------------------------------------------------------------
152    -- RTU_L_VFCCU Register Masks
153    ---------------------------------------------------------------------------- */
154 
155 /*!
156  * @addtogroup RTU_L_VFCCU_Register_Masks RTU_L_VFCCU Register Masks
157  * @{
158  */
159 
160 /*! @name GDFHID_C0 - Global DID-FHID Map */
161 /*! @{ */
162 
163 #define RTU_L_VFCCU_GDFHID_C0_FHDID0_MASK        (0x7U)
164 #define RTU_L_VFCCU_GDFHID_C0_FHDID0_SHIFT       (0U)
165 #define RTU_L_VFCCU_GDFHID_C0_FHDID0_WIDTH       (3U)
166 #define RTU_L_VFCCU_GDFHID_C0_FHDID0(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID0_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID0_MASK)
167 
168 #define RTU_L_VFCCU_GDFHID_C0_FHDID1_MASK        (0x70U)
169 #define RTU_L_VFCCU_GDFHID_C0_FHDID1_SHIFT       (4U)
170 #define RTU_L_VFCCU_GDFHID_C0_FHDID1_WIDTH       (3U)
171 #define RTU_L_VFCCU_GDFHID_C0_FHDID1(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID1_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID1_MASK)
172 
173 #define RTU_L_VFCCU_GDFHID_C0_FHDID2_MASK        (0x700U)
174 #define RTU_L_VFCCU_GDFHID_C0_FHDID2_SHIFT       (8U)
175 #define RTU_L_VFCCU_GDFHID_C0_FHDID2_WIDTH       (3U)
176 #define RTU_L_VFCCU_GDFHID_C0_FHDID2(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID2_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID2_MASK)
177 
178 #define RTU_L_VFCCU_GDFHID_C0_FHDID3_MASK        (0x7000U)
179 #define RTU_L_VFCCU_GDFHID_C0_FHDID3_SHIFT       (12U)
180 #define RTU_L_VFCCU_GDFHID_C0_FHDID3_WIDTH       (3U)
181 #define RTU_L_VFCCU_GDFHID_C0_FHDID3(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID3_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID3_MASK)
182 
183 #define RTU_L_VFCCU_GDFHID_C0_FHDID4_MASK        (0x70000U)
184 #define RTU_L_VFCCU_GDFHID_C0_FHDID4_SHIFT       (16U)
185 #define RTU_L_VFCCU_GDFHID_C0_FHDID4_WIDTH       (3U)
186 #define RTU_L_VFCCU_GDFHID_C0_FHDID4(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID4_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID4_MASK)
187 
188 #define RTU_L_VFCCU_GDFHID_C0_FHDID5_MASK        (0x700000U)
189 #define RTU_L_VFCCU_GDFHID_C0_FHDID5_SHIFT       (20U)
190 #define RTU_L_VFCCU_GDFHID_C0_FHDID5_WIDTH       (3U)
191 #define RTU_L_VFCCU_GDFHID_C0_FHDID5(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID5_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID5_MASK)
192 
193 #define RTU_L_VFCCU_GDFHID_C0_FHDID6_MASK        (0x7000000U)
194 #define RTU_L_VFCCU_GDFHID_C0_FHDID6_SHIFT       (24U)
195 #define RTU_L_VFCCU_GDFHID_C0_FHDID6_WIDTH       (3U)
196 #define RTU_L_VFCCU_GDFHID_C0_FHDID6(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID6_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID6_MASK)
197 
198 #define RTU_L_VFCCU_GDFHID_C0_FHDID7_MASK        (0x70000000U)
199 #define RTU_L_VFCCU_GDFHID_C0_FHDID7_SHIFT       (28U)
200 #define RTU_L_VFCCU_GDFHID_C0_FHDID7_WIDTH       (3U)
201 #define RTU_L_VFCCU_GDFHID_C0_FHDID7(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C0_FHDID7_SHIFT)) & RTU_L_VFCCU_GDFHID_C0_FHDID7_MASK)
202 /*! @} */
203 
204 /*! @name GDFHID_C1 - Global DID-FHID Map */
205 /*! @{ */
206 
207 #define RTU_L_VFCCU_GDFHID_C1_FHDID8_MASK        (0x7U)
208 #define RTU_L_VFCCU_GDFHID_C1_FHDID8_SHIFT       (0U)
209 #define RTU_L_VFCCU_GDFHID_C1_FHDID8_WIDTH       (3U)
210 #define RTU_L_VFCCU_GDFHID_C1_FHDID8(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID8_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID8_MASK)
211 
212 #define RTU_L_VFCCU_GDFHID_C1_FHDID9_MASK        (0x70U)
213 #define RTU_L_VFCCU_GDFHID_C1_FHDID9_SHIFT       (4U)
214 #define RTU_L_VFCCU_GDFHID_C1_FHDID9_WIDTH       (3U)
215 #define RTU_L_VFCCU_GDFHID_C1_FHDID9(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID9_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID9_MASK)
216 
217 #define RTU_L_VFCCU_GDFHID_C1_FHDID10_MASK       (0x700U)
218 #define RTU_L_VFCCU_GDFHID_C1_FHDID10_SHIFT      (8U)
219 #define RTU_L_VFCCU_GDFHID_C1_FHDID10_WIDTH      (3U)
220 #define RTU_L_VFCCU_GDFHID_C1_FHDID10(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID10_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID10_MASK)
221 
222 #define RTU_L_VFCCU_GDFHID_C1_FHDID11_MASK       (0x7000U)
223 #define RTU_L_VFCCU_GDFHID_C1_FHDID11_SHIFT      (12U)
224 #define RTU_L_VFCCU_GDFHID_C1_FHDID11_WIDTH      (3U)
225 #define RTU_L_VFCCU_GDFHID_C1_FHDID11(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID11_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID11_MASK)
226 
227 #define RTU_L_VFCCU_GDFHID_C1_FHDID12_MASK       (0x70000U)
228 #define RTU_L_VFCCU_GDFHID_C1_FHDID12_SHIFT      (16U)
229 #define RTU_L_VFCCU_GDFHID_C1_FHDID12_WIDTH      (3U)
230 #define RTU_L_VFCCU_GDFHID_C1_FHDID12(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID12_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID12_MASK)
231 
232 #define RTU_L_VFCCU_GDFHID_C1_FHDID13_MASK       (0x700000U)
233 #define RTU_L_VFCCU_GDFHID_C1_FHDID13_SHIFT      (20U)
234 #define RTU_L_VFCCU_GDFHID_C1_FHDID13_WIDTH      (3U)
235 #define RTU_L_VFCCU_GDFHID_C1_FHDID13(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID13_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID13_MASK)
236 
237 #define RTU_L_VFCCU_GDFHID_C1_FHDID14_MASK       (0x7000000U)
238 #define RTU_L_VFCCU_GDFHID_C1_FHDID14_SHIFT      (24U)
239 #define RTU_L_VFCCU_GDFHID_C1_FHDID14_WIDTH      (3U)
240 #define RTU_L_VFCCU_GDFHID_C1_FHDID14(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID14_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID14_MASK)
241 
242 #define RTU_L_VFCCU_GDFHID_C1_FHDID15_MASK       (0x70000000U)
243 #define RTU_L_VFCCU_GDFHID_C1_FHDID15_SHIFT      (28U)
244 #define RTU_L_VFCCU_GDFHID_C1_FHDID15_WIDTH      (3U)
245 #define RTU_L_VFCCU_GDFHID_C1_FHDID15(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDFHID_C1_FHDID15_SHIFT)) & RTU_L_VFCCU_GDFHID_C1_FHDID15_MASK)
246 /*! @} */
247 
248 /*! @name GFLTPO_C0 - Global Fault Polarity */
249 /*! @{ */
250 
251 #define RTU_L_VFCCU_GFLTPO_C0_PS0_MASK           (0x1U)
252 #define RTU_L_VFCCU_GFLTPO_C0_PS0_SHIFT          (0U)
253 #define RTU_L_VFCCU_GFLTPO_C0_PS0_WIDTH          (1U)
254 #define RTU_L_VFCCU_GFLTPO_C0_PS0(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS0_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS0_MASK)
255 
256 #define RTU_L_VFCCU_GFLTPO_C0_PS1_MASK           (0x2U)
257 #define RTU_L_VFCCU_GFLTPO_C0_PS1_SHIFT          (1U)
258 #define RTU_L_VFCCU_GFLTPO_C0_PS1_WIDTH          (1U)
259 #define RTU_L_VFCCU_GFLTPO_C0_PS1(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS1_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS1_MASK)
260 
261 #define RTU_L_VFCCU_GFLTPO_C0_PS2_MASK           (0x4U)
262 #define RTU_L_VFCCU_GFLTPO_C0_PS2_SHIFT          (2U)
263 #define RTU_L_VFCCU_GFLTPO_C0_PS2_WIDTH          (1U)
264 #define RTU_L_VFCCU_GFLTPO_C0_PS2(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS2_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS2_MASK)
265 
266 #define RTU_L_VFCCU_GFLTPO_C0_PS3_MASK           (0x8U)
267 #define RTU_L_VFCCU_GFLTPO_C0_PS3_SHIFT          (3U)
268 #define RTU_L_VFCCU_GFLTPO_C0_PS3_WIDTH          (1U)
269 #define RTU_L_VFCCU_GFLTPO_C0_PS3(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS3_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS3_MASK)
270 
271 #define RTU_L_VFCCU_GFLTPO_C0_PS4_MASK           (0x10U)
272 #define RTU_L_VFCCU_GFLTPO_C0_PS4_SHIFT          (4U)
273 #define RTU_L_VFCCU_GFLTPO_C0_PS4_WIDTH          (1U)
274 #define RTU_L_VFCCU_GFLTPO_C0_PS4(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS4_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS4_MASK)
275 
276 #define RTU_L_VFCCU_GFLTPO_C0_PS5_MASK           (0x20U)
277 #define RTU_L_VFCCU_GFLTPO_C0_PS5_SHIFT          (5U)
278 #define RTU_L_VFCCU_GFLTPO_C0_PS5_WIDTH          (1U)
279 #define RTU_L_VFCCU_GFLTPO_C0_PS5(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS5_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS5_MASK)
280 
281 #define RTU_L_VFCCU_GFLTPO_C0_PS6_MASK           (0x40U)
282 #define RTU_L_VFCCU_GFLTPO_C0_PS6_SHIFT          (6U)
283 #define RTU_L_VFCCU_GFLTPO_C0_PS6_WIDTH          (1U)
284 #define RTU_L_VFCCU_GFLTPO_C0_PS6(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS6_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS6_MASK)
285 
286 #define RTU_L_VFCCU_GFLTPO_C0_PS7_MASK           (0x80U)
287 #define RTU_L_VFCCU_GFLTPO_C0_PS7_SHIFT          (7U)
288 #define RTU_L_VFCCU_GFLTPO_C0_PS7_WIDTH          (1U)
289 #define RTU_L_VFCCU_GFLTPO_C0_PS7(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS7_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS7_MASK)
290 
291 #define RTU_L_VFCCU_GFLTPO_C0_PS8_MASK           (0x100U)
292 #define RTU_L_VFCCU_GFLTPO_C0_PS8_SHIFT          (8U)
293 #define RTU_L_VFCCU_GFLTPO_C0_PS8_WIDTH          (1U)
294 #define RTU_L_VFCCU_GFLTPO_C0_PS8(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS8_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS8_MASK)
295 
296 #define RTU_L_VFCCU_GFLTPO_C0_PS9_MASK           (0x200U)
297 #define RTU_L_VFCCU_GFLTPO_C0_PS9_SHIFT          (9U)
298 #define RTU_L_VFCCU_GFLTPO_C0_PS9_WIDTH          (1U)
299 #define RTU_L_VFCCU_GFLTPO_C0_PS9(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS9_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS9_MASK)
300 
301 #define RTU_L_VFCCU_GFLTPO_C0_PS10_MASK          (0x400U)
302 #define RTU_L_VFCCU_GFLTPO_C0_PS10_SHIFT         (10U)
303 #define RTU_L_VFCCU_GFLTPO_C0_PS10_WIDTH         (1U)
304 #define RTU_L_VFCCU_GFLTPO_C0_PS10(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS10_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS10_MASK)
305 
306 #define RTU_L_VFCCU_GFLTPO_C0_PS11_MASK          (0x800U)
307 #define RTU_L_VFCCU_GFLTPO_C0_PS11_SHIFT         (11U)
308 #define RTU_L_VFCCU_GFLTPO_C0_PS11_WIDTH         (1U)
309 #define RTU_L_VFCCU_GFLTPO_C0_PS11(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS11_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS11_MASK)
310 
311 #define RTU_L_VFCCU_GFLTPO_C0_PS12_MASK          (0x1000U)
312 #define RTU_L_VFCCU_GFLTPO_C0_PS12_SHIFT         (12U)
313 #define RTU_L_VFCCU_GFLTPO_C0_PS12_WIDTH         (1U)
314 #define RTU_L_VFCCU_GFLTPO_C0_PS12(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS12_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS12_MASK)
315 
316 #define RTU_L_VFCCU_GFLTPO_C0_PS13_MASK          (0x2000U)
317 #define RTU_L_VFCCU_GFLTPO_C0_PS13_SHIFT         (13U)
318 #define RTU_L_VFCCU_GFLTPO_C0_PS13_WIDTH         (1U)
319 #define RTU_L_VFCCU_GFLTPO_C0_PS13(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS13_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS13_MASK)
320 
321 #define RTU_L_VFCCU_GFLTPO_C0_PS14_MASK          (0x4000U)
322 #define RTU_L_VFCCU_GFLTPO_C0_PS14_SHIFT         (14U)
323 #define RTU_L_VFCCU_GFLTPO_C0_PS14_WIDTH         (1U)
324 #define RTU_L_VFCCU_GFLTPO_C0_PS14(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS14_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS14_MASK)
325 
326 #define RTU_L_VFCCU_GFLTPO_C0_PS15_MASK          (0x8000U)
327 #define RTU_L_VFCCU_GFLTPO_C0_PS15_SHIFT         (15U)
328 #define RTU_L_VFCCU_GFLTPO_C0_PS15_WIDTH         (1U)
329 #define RTU_L_VFCCU_GFLTPO_C0_PS15(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS15_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS15_MASK)
330 
331 #define RTU_L_VFCCU_GFLTPO_C0_PS16_MASK          (0x10000U)
332 #define RTU_L_VFCCU_GFLTPO_C0_PS16_SHIFT         (16U)
333 #define RTU_L_VFCCU_GFLTPO_C0_PS16_WIDTH         (1U)
334 #define RTU_L_VFCCU_GFLTPO_C0_PS16(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS16_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS16_MASK)
335 
336 #define RTU_L_VFCCU_GFLTPO_C0_PS17_MASK          (0x20000U)
337 #define RTU_L_VFCCU_GFLTPO_C0_PS17_SHIFT         (17U)
338 #define RTU_L_VFCCU_GFLTPO_C0_PS17_WIDTH         (1U)
339 #define RTU_L_VFCCU_GFLTPO_C0_PS17(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS17_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS17_MASK)
340 
341 #define RTU_L_VFCCU_GFLTPO_C0_PS18_MASK          (0x40000U)
342 #define RTU_L_VFCCU_GFLTPO_C0_PS18_SHIFT         (18U)
343 #define RTU_L_VFCCU_GFLTPO_C0_PS18_WIDTH         (1U)
344 #define RTU_L_VFCCU_GFLTPO_C0_PS18(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS18_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS18_MASK)
345 
346 #define RTU_L_VFCCU_GFLTPO_C0_PS19_MASK          (0x80000U)
347 #define RTU_L_VFCCU_GFLTPO_C0_PS19_SHIFT         (19U)
348 #define RTU_L_VFCCU_GFLTPO_C0_PS19_WIDTH         (1U)
349 #define RTU_L_VFCCU_GFLTPO_C0_PS19(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS19_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS19_MASK)
350 
351 #define RTU_L_VFCCU_GFLTPO_C0_PS20_MASK          (0x100000U)
352 #define RTU_L_VFCCU_GFLTPO_C0_PS20_SHIFT         (20U)
353 #define RTU_L_VFCCU_GFLTPO_C0_PS20_WIDTH         (1U)
354 #define RTU_L_VFCCU_GFLTPO_C0_PS20(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS20_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS20_MASK)
355 
356 #define RTU_L_VFCCU_GFLTPO_C0_PS21_MASK          (0x200000U)
357 #define RTU_L_VFCCU_GFLTPO_C0_PS21_SHIFT         (21U)
358 #define RTU_L_VFCCU_GFLTPO_C0_PS21_WIDTH         (1U)
359 #define RTU_L_VFCCU_GFLTPO_C0_PS21(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS21_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS21_MASK)
360 
361 #define RTU_L_VFCCU_GFLTPO_C0_PS22_MASK          (0x400000U)
362 #define RTU_L_VFCCU_GFLTPO_C0_PS22_SHIFT         (22U)
363 #define RTU_L_VFCCU_GFLTPO_C0_PS22_WIDTH         (1U)
364 #define RTU_L_VFCCU_GFLTPO_C0_PS22(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS22_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS22_MASK)
365 
366 #define RTU_L_VFCCU_GFLTPO_C0_PS23_MASK          (0x800000U)
367 #define RTU_L_VFCCU_GFLTPO_C0_PS23_SHIFT         (23U)
368 #define RTU_L_VFCCU_GFLTPO_C0_PS23_WIDTH         (1U)
369 #define RTU_L_VFCCU_GFLTPO_C0_PS23(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS23_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS23_MASK)
370 
371 #define RTU_L_VFCCU_GFLTPO_C0_PS24_MASK          (0x1000000U)
372 #define RTU_L_VFCCU_GFLTPO_C0_PS24_SHIFT         (24U)
373 #define RTU_L_VFCCU_GFLTPO_C0_PS24_WIDTH         (1U)
374 #define RTU_L_VFCCU_GFLTPO_C0_PS24(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS24_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS24_MASK)
375 
376 #define RTU_L_VFCCU_GFLTPO_C0_PS25_MASK          (0x2000000U)
377 #define RTU_L_VFCCU_GFLTPO_C0_PS25_SHIFT         (25U)
378 #define RTU_L_VFCCU_GFLTPO_C0_PS25_WIDTH         (1U)
379 #define RTU_L_VFCCU_GFLTPO_C0_PS25(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS25_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS25_MASK)
380 
381 #define RTU_L_VFCCU_GFLTPO_C0_PS26_MASK          (0x4000000U)
382 #define RTU_L_VFCCU_GFLTPO_C0_PS26_SHIFT         (26U)
383 #define RTU_L_VFCCU_GFLTPO_C0_PS26_WIDTH         (1U)
384 #define RTU_L_VFCCU_GFLTPO_C0_PS26(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS26_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS26_MASK)
385 
386 #define RTU_L_VFCCU_GFLTPO_C0_PS27_MASK          (0x8000000U)
387 #define RTU_L_VFCCU_GFLTPO_C0_PS27_SHIFT         (27U)
388 #define RTU_L_VFCCU_GFLTPO_C0_PS27_WIDTH         (1U)
389 #define RTU_L_VFCCU_GFLTPO_C0_PS27(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS27_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS27_MASK)
390 
391 #define RTU_L_VFCCU_GFLTPO_C0_PS28_MASK          (0x10000000U)
392 #define RTU_L_VFCCU_GFLTPO_C0_PS28_SHIFT         (28U)
393 #define RTU_L_VFCCU_GFLTPO_C0_PS28_WIDTH         (1U)
394 #define RTU_L_VFCCU_GFLTPO_C0_PS28(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS28_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS28_MASK)
395 
396 #define RTU_L_VFCCU_GFLTPO_C0_PS29_MASK          (0x20000000U)
397 #define RTU_L_VFCCU_GFLTPO_C0_PS29_SHIFT         (29U)
398 #define RTU_L_VFCCU_GFLTPO_C0_PS29_WIDTH         (1U)
399 #define RTU_L_VFCCU_GFLTPO_C0_PS29(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS29_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS29_MASK)
400 
401 #define RTU_L_VFCCU_GFLTPO_C0_PS30_MASK          (0x40000000U)
402 #define RTU_L_VFCCU_GFLTPO_C0_PS30_SHIFT         (30U)
403 #define RTU_L_VFCCU_GFLTPO_C0_PS30_WIDTH         (1U)
404 #define RTU_L_VFCCU_GFLTPO_C0_PS30(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS30_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS30_MASK)
405 
406 #define RTU_L_VFCCU_GFLTPO_C0_PS31_MASK          (0x80000000U)
407 #define RTU_L_VFCCU_GFLTPO_C0_PS31_SHIFT         (31U)
408 #define RTU_L_VFCCU_GFLTPO_C0_PS31_WIDTH         (1U)
409 #define RTU_L_VFCCU_GFLTPO_C0_PS31(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C0_PS31_SHIFT)) & RTU_L_VFCCU_GFLTPO_C0_PS31_MASK)
410 /*! @} */
411 
412 /*! @name GFLTPO_C1 - Global Fault Polarity */
413 /*! @{ */
414 
415 #define RTU_L_VFCCU_GFLTPO_C1_PS32_MASK          (0x1U)
416 #define RTU_L_VFCCU_GFLTPO_C1_PS32_SHIFT         (0U)
417 #define RTU_L_VFCCU_GFLTPO_C1_PS32_WIDTH         (1U)
418 #define RTU_L_VFCCU_GFLTPO_C1_PS32(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS32_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS32_MASK)
419 
420 #define RTU_L_VFCCU_GFLTPO_C1_PS33_MASK          (0x2U)
421 #define RTU_L_VFCCU_GFLTPO_C1_PS33_SHIFT         (1U)
422 #define RTU_L_VFCCU_GFLTPO_C1_PS33_WIDTH         (1U)
423 #define RTU_L_VFCCU_GFLTPO_C1_PS33(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS33_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS33_MASK)
424 
425 #define RTU_L_VFCCU_GFLTPO_C1_PS34_MASK          (0x4U)
426 #define RTU_L_VFCCU_GFLTPO_C1_PS34_SHIFT         (2U)
427 #define RTU_L_VFCCU_GFLTPO_C1_PS34_WIDTH         (1U)
428 #define RTU_L_VFCCU_GFLTPO_C1_PS34(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS34_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS34_MASK)
429 
430 #define RTU_L_VFCCU_GFLTPO_C1_PS35_MASK          (0x8U)
431 #define RTU_L_VFCCU_GFLTPO_C1_PS35_SHIFT         (3U)
432 #define RTU_L_VFCCU_GFLTPO_C1_PS35_WIDTH         (1U)
433 #define RTU_L_VFCCU_GFLTPO_C1_PS35(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS35_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS35_MASK)
434 
435 #define RTU_L_VFCCU_GFLTPO_C1_PS36_MASK          (0x10U)
436 #define RTU_L_VFCCU_GFLTPO_C1_PS36_SHIFT         (4U)
437 #define RTU_L_VFCCU_GFLTPO_C1_PS36_WIDTH         (1U)
438 #define RTU_L_VFCCU_GFLTPO_C1_PS36(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS36_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS36_MASK)
439 
440 #define RTU_L_VFCCU_GFLTPO_C1_PS37_MASK          (0x20U)
441 #define RTU_L_VFCCU_GFLTPO_C1_PS37_SHIFT         (5U)
442 #define RTU_L_VFCCU_GFLTPO_C1_PS37_WIDTH         (1U)
443 #define RTU_L_VFCCU_GFLTPO_C1_PS37(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS37_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS37_MASK)
444 
445 #define RTU_L_VFCCU_GFLTPO_C1_PS38_MASK          (0x40U)
446 #define RTU_L_VFCCU_GFLTPO_C1_PS38_SHIFT         (6U)
447 #define RTU_L_VFCCU_GFLTPO_C1_PS38_WIDTH         (1U)
448 #define RTU_L_VFCCU_GFLTPO_C1_PS38(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS38_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS38_MASK)
449 
450 #define RTU_L_VFCCU_GFLTPO_C1_PS39_MASK          (0x80U)
451 #define RTU_L_VFCCU_GFLTPO_C1_PS39_SHIFT         (7U)
452 #define RTU_L_VFCCU_GFLTPO_C1_PS39_WIDTH         (1U)
453 #define RTU_L_VFCCU_GFLTPO_C1_PS39(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS39_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS39_MASK)
454 
455 #define RTU_L_VFCCU_GFLTPO_C1_PS40_MASK          (0x100U)
456 #define RTU_L_VFCCU_GFLTPO_C1_PS40_SHIFT         (8U)
457 #define RTU_L_VFCCU_GFLTPO_C1_PS40_WIDTH         (1U)
458 #define RTU_L_VFCCU_GFLTPO_C1_PS40(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS40_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS40_MASK)
459 
460 #define RTU_L_VFCCU_GFLTPO_C1_PS41_MASK          (0x200U)
461 #define RTU_L_VFCCU_GFLTPO_C1_PS41_SHIFT         (9U)
462 #define RTU_L_VFCCU_GFLTPO_C1_PS41_WIDTH         (1U)
463 #define RTU_L_VFCCU_GFLTPO_C1_PS41(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS41_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS41_MASK)
464 
465 #define RTU_L_VFCCU_GFLTPO_C1_PS42_MASK          (0x400U)
466 #define RTU_L_VFCCU_GFLTPO_C1_PS42_SHIFT         (10U)
467 #define RTU_L_VFCCU_GFLTPO_C1_PS42_WIDTH         (1U)
468 #define RTU_L_VFCCU_GFLTPO_C1_PS42(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS42_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS42_MASK)
469 
470 #define RTU_L_VFCCU_GFLTPO_C1_PS43_MASK          (0x800U)
471 #define RTU_L_VFCCU_GFLTPO_C1_PS43_SHIFT         (11U)
472 #define RTU_L_VFCCU_GFLTPO_C1_PS43_WIDTH         (1U)
473 #define RTU_L_VFCCU_GFLTPO_C1_PS43(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS43_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS43_MASK)
474 
475 #define RTU_L_VFCCU_GFLTPO_C1_PS44_MASK          (0x1000U)
476 #define RTU_L_VFCCU_GFLTPO_C1_PS44_SHIFT         (12U)
477 #define RTU_L_VFCCU_GFLTPO_C1_PS44_WIDTH         (1U)
478 #define RTU_L_VFCCU_GFLTPO_C1_PS44(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS44_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS44_MASK)
479 
480 #define RTU_L_VFCCU_GFLTPO_C1_PS45_MASK          (0x2000U)
481 #define RTU_L_VFCCU_GFLTPO_C1_PS45_SHIFT         (13U)
482 #define RTU_L_VFCCU_GFLTPO_C1_PS45_WIDTH         (1U)
483 #define RTU_L_VFCCU_GFLTPO_C1_PS45(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS45_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS45_MASK)
484 
485 #define RTU_L_VFCCU_GFLTPO_C1_PS46_MASK          (0x4000U)
486 #define RTU_L_VFCCU_GFLTPO_C1_PS46_SHIFT         (14U)
487 #define RTU_L_VFCCU_GFLTPO_C1_PS46_WIDTH         (1U)
488 #define RTU_L_VFCCU_GFLTPO_C1_PS46(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS46_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS46_MASK)
489 
490 #define RTU_L_VFCCU_GFLTPO_C1_PS47_MASK          (0x8000U)
491 #define RTU_L_VFCCU_GFLTPO_C1_PS47_SHIFT         (15U)
492 #define RTU_L_VFCCU_GFLTPO_C1_PS47_WIDTH         (1U)
493 #define RTU_L_VFCCU_GFLTPO_C1_PS47(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS47_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS47_MASK)
494 
495 #define RTU_L_VFCCU_GFLTPO_C1_PS48_MASK          (0x10000U)
496 #define RTU_L_VFCCU_GFLTPO_C1_PS48_SHIFT         (16U)
497 #define RTU_L_VFCCU_GFLTPO_C1_PS48_WIDTH         (1U)
498 #define RTU_L_VFCCU_GFLTPO_C1_PS48(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS48_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS48_MASK)
499 
500 #define RTU_L_VFCCU_GFLTPO_C1_PS49_MASK          (0x20000U)
501 #define RTU_L_VFCCU_GFLTPO_C1_PS49_SHIFT         (17U)
502 #define RTU_L_VFCCU_GFLTPO_C1_PS49_WIDTH         (1U)
503 #define RTU_L_VFCCU_GFLTPO_C1_PS49(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTPO_C1_PS49_SHIFT)) & RTU_L_VFCCU_GFLTPO_C1_PS49_MASK)
504 /*! @} */
505 
506 /*! @name GFLTRC_C0 - Global Fault Recovery */
507 /*! @{ */
508 
509 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW0_MASK        (0x1U)
510 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW0_SHIFT       (0U)
511 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW0_WIDTH       (1U)
512 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW0(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW0_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW0_MASK)
513 
514 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW1_MASK        (0x2U)
515 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW1_SHIFT       (1U)
516 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW1_WIDTH       (1U)
517 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW1(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW1_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW1_MASK)
518 
519 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW2_MASK        (0x4U)
520 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW2_SHIFT       (2U)
521 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW2_WIDTH       (1U)
522 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW2(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW2_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW2_MASK)
523 
524 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW3_MASK        (0x8U)
525 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW3_SHIFT       (3U)
526 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW3_WIDTH       (1U)
527 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW3(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW3_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW3_MASK)
528 
529 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW4_MASK        (0x10U)
530 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW4_SHIFT       (4U)
531 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW4_WIDTH       (1U)
532 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW4(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW4_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW4_MASK)
533 
534 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW5_MASK        (0x20U)
535 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW5_SHIFT       (5U)
536 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW5_WIDTH       (1U)
537 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW5(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW5_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW5_MASK)
538 
539 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW6_MASK        (0x40U)
540 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW6_SHIFT       (6U)
541 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW6_WIDTH       (1U)
542 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW6(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW6_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW6_MASK)
543 
544 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW7_MASK        (0x80U)
545 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW7_SHIFT       (7U)
546 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW7_WIDTH       (1U)
547 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW7(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW7_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW7_MASK)
548 
549 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW8_MASK        (0x100U)
550 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW8_SHIFT       (8U)
551 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW8_WIDTH       (1U)
552 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW8(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW8_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW8_MASK)
553 
554 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW9_MASK        (0x200U)
555 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW9_SHIFT       (9U)
556 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW9_WIDTH       (1U)
557 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW9(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW9_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW9_MASK)
558 
559 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW10_MASK       (0x400U)
560 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW10_SHIFT      (10U)
561 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW10_WIDTH      (1U)
562 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW10(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW10_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW10_MASK)
563 
564 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW11_MASK       (0x800U)
565 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW11_SHIFT      (11U)
566 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW11_WIDTH      (1U)
567 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW11(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW11_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW11_MASK)
568 
569 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW12_MASK       (0x1000U)
570 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW12_SHIFT      (12U)
571 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW12_WIDTH      (1U)
572 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW12(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW12_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW12_MASK)
573 
574 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW13_MASK       (0x2000U)
575 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW13_SHIFT      (13U)
576 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW13_WIDTH      (1U)
577 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW13(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW13_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW13_MASK)
578 
579 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW14_MASK       (0x4000U)
580 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW14_SHIFT      (14U)
581 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW14_WIDTH      (1U)
582 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW14(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW14_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW14_MASK)
583 
584 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW15_MASK       (0x8000U)
585 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW15_SHIFT      (15U)
586 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW15_WIDTH      (1U)
587 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW15(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW15_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW15_MASK)
588 
589 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW16_MASK       (0x10000U)
590 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW16_SHIFT      (16U)
591 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW16_WIDTH      (1U)
592 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW16(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW16_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW16_MASK)
593 
594 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW17_MASK       (0x20000U)
595 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW17_SHIFT      (17U)
596 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW17_WIDTH      (1U)
597 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW17(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW17_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW17_MASK)
598 
599 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW18_MASK       (0x40000U)
600 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW18_SHIFT      (18U)
601 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW18_WIDTH      (1U)
602 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW18(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW18_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW18_MASK)
603 
604 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW19_MASK       (0x80000U)
605 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW19_SHIFT      (19U)
606 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW19_WIDTH      (1U)
607 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW19(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW19_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW19_MASK)
608 
609 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW20_MASK       (0x100000U)
610 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW20_SHIFT      (20U)
611 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW20_WIDTH      (1U)
612 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW20(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW20_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW20_MASK)
613 
614 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW21_MASK       (0x200000U)
615 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW21_SHIFT      (21U)
616 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW21_WIDTH      (1U)
617 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW21(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW21_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW21_MASK)
618 
619 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW22_MASK       (0x400000U)
620 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW22_SHIFT      (22U)
621 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW22_WIDTH      (1U)
622 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW22(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW22_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW22_MASK)
623 
624 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW23_MASK       (0x800000U)
625 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW23_SHIFT      (23U)
626 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW23_WIDTH      (1U)
627 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW23(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW23_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW23_MASK)
628 
629 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW24_MASK       (0x1000000U)
630 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW24_SHIFT      (24U)
631 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW24_WIDTH      (1U)
632 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW24(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW24_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW24_MASK)
633 
634 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW25_MASK       (0x2000000U)
635 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW25_SHIFT      (25U)
636 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW25_WIDTH      (1U)
637 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW25(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW25_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW25_MASK)
638 
639 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW26_MASK       (0x4000000U)
640 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW26_SHIFT      (26U)
641 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW26_WIDTH      (1U)
642 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW26(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW26_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW26_MASK)
643 
644 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW27_MASK       (0x8000000U)
645 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW27_SHIFT      (27U)
646 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW27_WIDTH      (1U)
647 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW27(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW27_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW27_MASK)
648 
649 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW28_MASK       (0x10000000U)
650 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW28_SHIFT      (28U)
651 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW28_WIDTH      (1U)
652 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW28(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW28_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW28_MASK)
653 
654 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW29_MASK       (0x20000000U)
655 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW29_SHIFT      (29U)
656 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW29_WIDTH      (1U)
657 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW29(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW29_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW29_MASK)
658 
659 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW30_MASK       (0x40000000U)
660 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW30_SHIFT      (30U)
661 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW30_WIDTH      (1U)
662 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW30(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW30_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW30_MASK)
663 
664 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW31_MASK       (0x80000000U)
665 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW31_SHIFT      (31U)
666 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW31_WIDTH      (1U)
667 #define RTU_L_VFCCU_GFLTRC_C0_RHWSW31(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C0_RHWSW31_SHIFT)) & RTU_L_VFCCU_GFLTRC_C0_RHWSW31_MASK)
668 /*! @} */
669 
670 /*! @name GFLTRC_C1 - Global Fault Recovery */
671 /*! @{ */
672 
673 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW32_MASK       (0x1U)
674 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW32_SHIFT      (0U)
675 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW32_WIDTH      (1U)
676 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW32(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW32_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW32_MASK)
677 
678 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW33_MASK       (0x2U)
679 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW33_SHIFT      (1U)
680 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW33_WIDTH      (1U)
681 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW33(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW33_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW33_MASK)
682 
683 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW34_MASK       (0x4U)
684 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW34_SHIFT      (2U)
685 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW34_WIDTH      (1U)
686 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW34(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW34_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW34_MASK)
687 
688 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW35_MASK       (0x8U)
689 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW35_SHIFT      (3U)
690 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW35_WIDTH      (1U)
691 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW35(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW35_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW35_MASK)
692 
693 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW36_MASK       (0x10U)
694 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW36_SHIFT      (4U)
695 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW36_WIDTH      (1U)
696 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW36(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW36_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW36_MASK)
697 
698 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW37_MASK       (0x20U)
699 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW37_SHIFT      (5U)
700 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW37_WIDTH      (1U)
701 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW37(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW37_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW37_MASK)
702 
703 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW38_MASK       (0x40U)
704 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW38_SHIFT      (6U)
705 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW38_WIDTH      (1U)
706 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW38(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW38_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW38_MASK)
707 
708 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW39_MASK       (0x80U)
709 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW39_SHIFT      (7U)
710 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW39_WIDTH      (1U)
711 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW39(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW39_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW39_MASK)
712 
713 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW40_MASK       (0x100U)
714 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW40_SHIFT      (8U)
715 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW40_WIDTH      (1U)
716 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW40(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW40_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW40_MASK)
717 
718 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW41_MASK       (0x200U)
719 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW41_SHIFT      (9U)
720 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW41_WIDTH      (1U)
721 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW41(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW41_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW41_MASK)
722 
723 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW42_MASK       (0x400U)
724 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW42_SHIFT      (10U)
725 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW42_WIDTH      (1U)
726 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW42(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW42_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW42_MASK)
727 
728 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW43_MASK       (0x800U)
729 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW43_SHIFT      (11U)
730 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW43_WIDTH      (1U)
731 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW43(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW43_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW43_MASK)
732 
733 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW44_MASK       (0x1000U)
734 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW44_SHIFT      (12U)
735 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW44_WIDTH      (1U)
736 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW44(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW44_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW44_MASK)
737 
738 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW45_MASK       (0x2000U)
739 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW45_SHIFT      (13U)
740 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW45_WIDTH      (1U)
741 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW45(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW45_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW45_MASK)
742 
743 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW46_MASK       (0x4000U)
744 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW46_SHIFT      (14U)
745 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW46_WIDTH      (1U)
746 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW46(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW46_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW46_MASK)
747 
748 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW47_MASK       (0x8000U)
749 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW47_SHIFT      (15U)
750 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW47_WIDTH      (1U)
751 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW47(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW47_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW47_MASK)
752 
753 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW48_MASK       (0x10000U)
754 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW48_SHIFT      (16U)
755 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW48_WIDTH      (1U)
756 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW48(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW48_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW48_MASK)
757 
758 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW49_MASK       (0x20000U)
759 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW49_SHIFT      (17U)
760 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW49_WIDTH      (1U)
761 #define RTU_L_VFCCU_GFLTRC_C1_RHWSW49(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTRC_C1_RHWSW49_SHIFT)) & RTU_L_VFCCU_GFLTRC_C1_RHWSW49_MASK)
762 /*! @} */
763 
764 /*! @name GFLTOVDC0 - Global Fault Overflow Detection */
765 /*! @{ */
766 
767 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS0_MASK      (0x1U)
768 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS0_SHIFT     (0U)
769 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS0_WIDTH     (1U)
770 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS0_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS0_MASK)
771 
772 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS1_MASK      (0x2U)
773 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS1_SHIFT     (1U)
774 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS1_WIDTH     (1U)
775 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS1_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS1_MASK)
776 
777 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS2_MASK      (0x4U)
778 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS2_SHIFT     (2U)
779 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS2_WIDTH     (1U)
780 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS2_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS2_MASK)
781 
782 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS3_MASK      (0x8U)
783 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS3_SHIFT     (3U)
784 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS3_WIDTH     (1U)
785 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS3_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS3_MASK)
786 
787 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS4_MASK      (0x10U)
788 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS4_SHIFT     (4U)
789 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS4_WIDTH     (1U)
790 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS4_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS4_MASK)
791 
792 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS5_MASK      (0x20U)
793 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS5_SHIFT     (5U)
794 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS5_WIDTH     (1U)
795 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS5_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS5_MASK)
796 
797 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS6_MASK      (0x40U)
798 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS6_SHIFT     (6U)
799 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS6_WIDTH     (1U)
800 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS6(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS6_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS6_MASK)
801 
802 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS7_MASK      (0x80U)
803 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS7_SHIFT     (7U)
804 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS7_WIDTH     (1U)
805 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS7(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS7_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS7_MASK)
806 
807 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS8_MASK      (0x100U)
808 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS8_SHIFT     (8U)
809 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS8_WIDTH     (1U)
810 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS8(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS8_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS8_MASK)
811 
812 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS9_MASK      (0x200U)
813 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS9_SHIFT     (9U)
814 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS9_WIDTH     (1U)
815 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS9(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS9_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS9_MASK)
816 
817 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS10_MASK     (0x400U)
818 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS10_SHIFT    (10U)
819 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS10_WIDTH    (1U)
820 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS10(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS10_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS10_MASK)
821 
822 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS11_MASK     (0x800U)
823 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS11_SHIFT    (11U)
824 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS11_WIDTH    (1U)
825 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS11(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS11_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS11_MASK)
826 
827 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS12_MASK     (0x1000U)
828 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS12_SHIFT    (12U)
829 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS12_WIDTH    (1U)
830 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS12(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS12_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS12_MASK)
831 
832 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS13_MASK     (0x2000U)
833 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS13_SHIFT    (13U)
834 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS13_WIDTH    (1U)
835 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS13(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS13_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS13_MASK)
836 
837 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS14_MASK     (0x4000U)
838 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS14_SHIFT    (14U)
839 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS14_WIDTH    (1U)
840 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS14(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS14_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS14_MASK)
841 
842 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS15_MASK     (0x8000U)
843 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS15_SHIFT    (15U)
844 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS15_WIDTH    (1U)
845 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS15(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS15_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS15_MASK)
846 
847 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS16_MASK     (0x10000U)
848 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS16_SHIFT    (16U)
849 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS16_WIDTH    (1U)
850 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS16(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS16_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS16_MASK)
851 
852 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS17_MASK     (0x20000U)
853 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS17_SHIFT    (17U)
854 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS17_WIDTH    (1U)
855 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS17(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS17_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS17_MASK)
856 
857 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS18_MASK     (0x40000U)
858 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS18_SHIFT    (18U)
859 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS18_WIDTH    (1U)
860 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS18(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS18_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS18_MASK)
861 
862 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS19_MASK     (0x80000U)
863 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS19_SHIFT    (19U)
864 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS19_WIDTH    (1U)
865 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS19(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS19_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS19_MASK)
866 
867 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS20_MASK     (0x100000U)
868 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS20_SHIFT    (20U)
869 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS20_WIDTH    (1U)
870 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS20(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS20_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS20_MASK)
871 
872 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS21_MASK     (0x200000U)
873 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS21_SHIFT    (21U)
874 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS21_WIDTH    (1U)
875 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS21(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS21_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS21_MASK)
876 
877 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS22_MASK     (0x400000U)
878 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS22_SHIFT    (22U)
879 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS22_WIDTH    (1U)
880 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS22(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS22_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS22_MASK)
881 
882 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS23_MASK     (0x800000U)
883 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS23_SHIFT    (23U)
884 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS23_WIDTH    (1U)
885 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS23(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS23_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS23_MASK)
886 
887 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS24_MASK     (0x1000000U)
888 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS24_SHIFT    (24U)
889 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS24_WIDTH    (1U)
890 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS24(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS24_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS24_MASK)
891 
892 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS25_MASK     (0x2000000U)
893 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS25_SHIFT    (25U)
894 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS25_WIDTH    (1U)
895 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS25(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS25_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS25_MASK)
896 
897 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS26_MASK     (0x4000000U)
898 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS26_SHIFT    (26U)
899 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS26_WIDTH    (1U)
900 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS26(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS26_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS26_MASK)
901 
902 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS27_MASK     (0x8000000U)
903 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS27_SHIFT    (27U)
904 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS27_WIDTH    (1U)
905 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS27(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS27_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS27_MASK)
906 
907 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS28_MASK     (0x10000000U)
908 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS28_SHIFT    (28U)
909 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS28_WIDTH    (1U)
910 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS28(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS28_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS28_MASK)
911 
912 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS29_MASK     (0x20000000U)
913 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS29_SHIFT    (29U)
914 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS29_WIDTH    (1U)
915 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS29(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS29_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS29_MASK)
916 
917 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS30_MASK     (0x40000000U)
918 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS30_SHIFT    (30U)
919 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS30_WIDTH    (1U)
920 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS30(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS30_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS30_MASK)
921 
922 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS31_MASK     (0x80000000U)
923 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS31_SHIFT    (31U)
924 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS31_WIDTH    (1U)
925 #define RTU_L_VFCCU_GFLTOVDC0_OVF_DIS31(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC0_OVF_DIS31_SHIFT)) & RTU_L_VFCCU_GFLTOVDC0_OVF_DIS31_MASK)
926 /*! @} */
927 
928 /*! @name GFLTOVDC1 - Global Fault Overflow Detection */
929 /*! @{ */
930 
931 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS32_MASK     (0x1U)
932 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS32_SHIFT    (0U)
933 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS32_WIDTH    (1U)
934 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS32(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS32_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS32_MASK)
935 
936 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS33_MASK     (0x2U)
937 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS33_SHIFT    (1U)
938 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS33_WIDTH    (1U)
939 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS33(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS33_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS33_MASK)
940 
941 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS34_MASK     (0x4U)
942 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS34_SHIFT    (2U)
943 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS34_WIDTH    (1U)
944 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS34(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS34_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS34_MASK)
945 
946 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS35_MASK     (0x8U)
947 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS35_SHIFT    (3U)
948 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS35_WIDTH    (1U)
949 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS35(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS35_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS35_MASK)
950 
951 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS36_MASK     (0x10U)
952 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS36_SHIFT    (4U)
953 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS36_WIDTH    (1U)
954 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS36(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS36_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS36_MASK)
955 
956 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS37_MASK     (0x20U)
957 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS37_SHIFT    (5U)
958 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS37_WIDTH    (1U)
959 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS37(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS37_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS37_MASK)
960 
961 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS38_MASK     (0x40U)
962 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS38_SHIFT    (6U)
963 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS38_WIDTH    (1U)
964 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS38(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS38_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS38_MASK)
965 
966 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS39_MASK     (0x80U)
967 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS39_SHIFT    (7U)
968 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS39_WIDTH    (1U)
969 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS39(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS39_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS39_MASK)
970 
971 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS40_MASK     (0x100U)
972 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS40_SHIFT    (8U)
973 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS40_WIDTH    (1U)
974 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS40(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS40_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS40_MASK)
975 
976 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS41_MASK     (0x200U)
977 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS41_SHIFT    (9U)
978 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS41_WIDTH    (1U)
979 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS41(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS41_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS41_MASK)
980 
981 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS42_MASK     (0x400U)
982 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS42_SHIFT    (10U)
983 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS42_WIDTH    (1U)
984 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS42(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS42_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS42_MASK)
985 
986 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS43_MASK     (0x800U)
987 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS43_SHIFT    (11U)
988 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS43_WIDTH    (1U)
989 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS43(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS43_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS43_MASK)
990 
991 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS44_MASK     (0x1000U)
992 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS44_SHIFT    (12U)
993 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS44_WIDTH    (1U)
994 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS44(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS44_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS44_MASK)
995 
996 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS45_MASK     (0x2000U)
997 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS45_SHIFT    (13U)
998 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS45_WIDTH    (1U)
999 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS45(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS45_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS45_MASK)
1000 
1001 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS46_MASK     (0x4000U)
1002 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS46_SHIFT    (14U)
1003 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS46_WIDTH    (1U)
1004 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS46(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS46_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS46_MASK)
1005 
1006 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS47_MASK     (0x8000U)
1007 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS47_SHIFT    (15U)
1008 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS47_WIDTH    (1U)
1009 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS47(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS47_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS47_MASK)
1010 
1011 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS48_MASK     (0x10000U)
1012 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS48_SHIFT    (16U)
1013 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS48_WIDTH    (1U)
1014 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS48(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS48_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS48_MASK)
1015 
1016 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS49_MASK     (0x20000U)
1017 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS49_SHIFT    (17U)
1018 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS49_WIDTH    (1U)
1019 #define RTU_L_VFCCU_GFLTOVDC1_OVF_DIS49(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GFLTOVDC1_OVF_DIS49_SHIFT)) & RTU_L_VFCCU_GFLTOVDC1_OVF_DIS49_MASK)
1020 /*! @} */
1021 
1022 /*! @name GSWFLODC - Global Software Fault Overflow Detection Disable */
1023 /*! @{ */
1024 
1025 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS0_MASK     (0x1U)
1026 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS0_SHIFT    (0U)
1027 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS0_WIDTH    (1U)
1028 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS0(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GSWFLODC_SWOVF_DIS0_SHIFT)) & RTU_L_VFCCU_GSWFLODC_SWOVF_DIS0_MASK)
1029 
1030 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS1_MASK     (0x2U)
1031 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS1_SHIFT    (1U)
1032 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS1_WIDTH    (1U)
1033 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS1(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GSWFLODC_SWOVF_DIS1_SHIFT)) & RTU_L_VFCCU_GSWFLODC_SWOVF_DIS1_MASK)
1034 
1035 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS2_MASK     (0x4U)
1036 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS2_SHIFT    (2U)
1037 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS2_WIDTH    (1U)
1038 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS2(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GSWFLODC_SWOVF_DIS2_SHIFT)) & RTU_L_VFCCU_GSWFLODC_SWOVF_DIS2_MASK)
1039 
1040 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS3_MASK     (0x8U)
1041 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS3_SHIFT    (3U)
1042 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS3_WIDTH    (1U)
1043 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS3(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GSWFLODC_SWOVF_DIS3_SHIFT)) & RTU_L_VFCCU_GSWFLODC_SWOVF_DIS3_MASK)
1044 
1045 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS4_MASK     (0x10U)
1046 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS4_SHIFT    (4U)
1047 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS4_WIDTH    (1U)
1048 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS4(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GSWFLODC_SWOVF_DIS4_SHIFT)) & RTU_L_VFCCU_GSWFLODC_SWOVF_DIS4_MASK)
1049 
1050 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS5_MASK     (0x20U)
1051 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS5_SHIFT    (5U)
1052 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS5_WIDTH    (1U)
1053 #define RTU_L_VFCCU_GSWFLODC_SWOVF_DIS5(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GSWFLODC_SWOVF_DIS5_SHIFT)) & RTU_L_VFCCU_GSWFLODC_SWOVF_DIS5_MASK)
1054 /*! @} */
1055 
1056 /*! @name GCTRL - Global Space Control */
1057 /*! @{ */
1058 
1059 #define RTU_L_VFCCU_GCTRL_OVF_EN_MASK            (0x1U)
1060 #define RTU_L_VFCCU_GCTRL_OVF_EN_SHIFT           (0U)
1061 #define RTU_L_VFCCU_GCTRL_OVF_EN_WIDTH           (1U)
1062 #define RTU_L_VFCCU_GCTRL_OVF_EN(x)              (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GCTRL_OVF_EN_SHIFT)) & RTU_L_VFCCU_GCTRL_OVF_EN_MASK)
1063 /*! @} */
1064 
1065 /*! @name GINTOVFS - Global DID FSM Status */
1066 /*! @{ */
1067 
1068 #define RTU_L_VFCCU_GINTOVFS_FLTSERV_MASK        (0x80U)
1069 #define RTU_L_VFCCU_GINTOVFS_FLTSERV_SHIFT       (7U)
1070 #define RTU_L_VFCCU_GINTOVFS_FLTSERV_WIDTH       (1U)
1071 #define RTU_L_VFCCU_GINTOVFS_FLTSERV(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GINTOVFS_FLTSERV_SHIFT)) & RTU_L_VFCCU_GINTOVFS_FLTSERV_MASK)
1072 
1073 #define RTU_L_VFCCU_GINTOVFS_OVF_DET_MASK        (0x100U)
1074 #define RTU_L_VFCCU_GINTOVFS_OVF_DET_SHIFT       (8U)
1075 #define RTU_L_VFCCU_GINTOVFS_OVF_DET_WIDTH       (1U)
1076 #define RTU_L_VFCCU_GINTOVFS_OVF_DET(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GINTOVFS_OVF_DET_SHIFT)) & RTU_L_VFCCU_GINTOVFS_OVF_DET_MASK)
1077 
1078 #define RTU_L_VFCCU_GINTOVFS_SERV_DID_MASK       (0xF0000U)
1079 #define RTU_L_VFCCU_GINTOVFS_SERV_DID_SHIFT      (16U)
1080 #define RTU_L_VFCCU_GINTOVFS_SERV_DID_WIDTH      (4U)
1081 #define RTU_L_VFCCU_GINTOVFS_SERV_DID(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GINTOVFS_SERV_DID_SHIFT)) & RTU_L_VFCCU_GINTOVFS_SERV_DID_MASK)
1082 
1083 #define RTU_L_VFCCU_GINTOVFS_OVF_DID_MASK        (0xF000000U)
1084 #define RTU_L_VFCCU_GINTOVFS_OVF_DID_SHIFT       (24U)
1085 #define RTU_L_VFCCU_GINTOVFS_OVF_DID_WIDTH       (4U)
1086 #define RTU_L_VFCCU_GINTOVFS_OVF_DID(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GINTOVFS_OVF_DID_SHIFT)) & RTU_L_VFCCU_GINTOVFS_OVF_DID_MASK)
1087 /*! @} */
1088 
1089 /*! @name GDBGCFG - Global Debug */
1090 /*! @{ */
1091 
1092 #define RTU_L_VFCCU_GDBGCFG_FRZ_MASK             (0x10000U)
1093 #define RTU_L_VFCCU_GDBGCFG_FRZ_SHIFT            (16U)
1094 #define RTU_L_VFCCU_GDBGCFG_FRZ_WIDTH            (1U)
1095 #define RTU_L_VFCCU_GDBGCFG_FRZ(x)               (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDBGCFG_FRZ_SHIFT)) & RTU_L_VFCCU_GDBGCFG_FRZ_MASK)
1096 /*! @} */
1097 
1098 /*! @name GDBGSTAT - Global Debug Status */
1099 /*! @{ */
1100 
1101 #define RTU_L_VFCCU_GDBGSTAT_FLTIND_MASK         (0xFFU)
1102 #define RTU_L_VFCCU_GDBGSTAT_FLTIND_SHIFT        (0U)
1103 #define RTU_L_VFCCU_GDBGSTAT_FLTIND_WIDTH        (8U)
1104 #define RTU_L_VFCCU_GDBGSTAT_FLTIND(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_GDBGSTAT_FLTIND_SHIFT)) & RTU_L_VFCCU_GDBGSTAT_FLTIND_MASK)
1105 /*! @} */
1106 
1107 /*! @name SWRPTDID - Software Fault Reported DID */
1108 /*! @{ */
1109 
1110 #define RTU_L_VFCCU_SWRPTDID_DID_MASK            (0xFU)
1111 #define RTU_L_VFCCU_SWRPTDID_DID_SHIFT           (0U)
1112 #define RTU_L_VFCCU_SWRPTDID_DID_WIDTH           (4U)
1113 #define RTU_L_VFCCU_SWRPTDID_DID(x)              (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRPTDID_DID_SHIFT)) & RTU_L_VFCCU_SWRPTDID_DID_MASK)
1114 /*! @} */
1115 
1116 /*! @name SWRKSET_0 - Software Reaction Set */
1117 /*! @{ */
1118 
1119 #define RTU_L_VFCCU_SWRKSET_0_RKNEN0_MASK        (0x1U)
1120 #define RTU_L_VFCCU_SWRKSET_0_RKNEN0_SHIFT       (0U)
1121 #define RTU_L_VFCCU_SWRKSET_0_RKNEN0_WIDTH       (1U)
1122 #define RTU_L_VFCCU_SWRKSET_0_RKNEN0(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKSET_0_RKNEN0_SHIFT)) & RTU_L_VFCCU_SWRKSET_0_RKNEN0_MASK)
1123 
1124 #define RTU_L_VFCCU_SWRKSET_0_RKNEN1_MASK        (0x2U)
1125 #define RTU_L_VFCCU_SWRKSET_0_RKNEN1_SHIFT       (1U)
1126 #define RTU_L_VFCCU_SWRKSET_0_RKNEN1_WIDTH       (1U)
1127 #define RTU_L_VFCCU_SWRKSET_0_RKNEN1(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKSET_0_RKNEN1_SHIFT)) & RTU_L_VFCCU_SWRKSET_0_RKNEN1_MASK)
1128 
1129 #define RTU_L_VFCCU_SWRKSET_0_RKNEN2_MASK        (0x4U)
1130 #define RTU_L_VFCCU_SWRKSET_0_RKNEN2_SHIFT       (2U)
1131 #define RTU_L_VFCCU_SWRKSET_0_RKNEN2_WIDTH       (1U)
1132 #define RTU_L_VFCCU_SWRKSET_0_RKNEN2(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKSET_0_RKNEN2_SHIFT)) & RTU_L_VFCCU_SWRKSET_0_RKNEN2_MASK)
1133 
1134 #define RTU_L_VFCCU_SWRKSET_0_RKNEN3_MASK        (0x8U)
1135 #define RTU_L_VFCCU_SWRKSET_0_RKNEN3_SHIFT       (3U)
1136 #define RTU_L_VFCCU_SWRKSET_0_RKNEN3_WIDTH       (1U)
1137 #define RTU_L_VFCCU_SWRKSET_0_RKNEN3(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKSET_0_RKNEN3_SHIFT)) & RTU_L_VFCCU_SWRKSET_0_RKNEN3_MASK)
1138 
1139 #define RTU_L_VFCCU_SWRKSET_0_RKNEN4_MASK        (0x10U)
1140 #define RTU_L_VFCCU_SWRKSET_0_RKNEN4_SHIFT       (4U)
1141 #define RTU_L_VFCCU_SWRKSET_0_RKNEN4_WIDTH       (1U)
1142 #define RTU_L_VFCCU_SWRKSET_0_RKNEN4(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKSET_0_RKNEN4_SHIFT)) & RTU_L_VFCCU_SWRKSET_0_RKNEN4_MASK)
1143 
1144 #define RTU_L_VFCCU_SWRKSET_0_RKNEN5_MASK        (0x20U)
1145 #define RTU_L_VFCCU_SWRKSET_0_RKNEN5_SHIFT       (5U)
1146 #define RTU_L_VFCCU_SWRKSET_0_RKNEN5_WIDTH       (1U)
1147 #define RTU_L_VFCCU_SWRKSET_0_RKNEN5(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKSET_0_RKNEN5_SHIFT)) & RTU_L_VFCCU_SWRKSET_0_RKNEN5_MASK)
1148 /*! @} */
1149 
1150 /*! @name SWRKCLR_0 - Software Reaction Clear */
1151 /*! @{ */
1152 
1153 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR0_MASK       (0x1U)
1154 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR0_SHIFT      (0U)
1155 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR0_WIDTH      (1U)
1156 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR0(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKCLR_0_RKNCLR0_SHIFT)) & RTU_L_VFCCU_SWRKCLR_0_RKNCLR0_MASK)
1157 
1158 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR1_MASK       (0x2U)
1159 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR1_SHIFT      (1U)
1160 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR1_WIDTH      (1U)
1161 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR1(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKCLR_0_RKNCLR1_SHIFT)) & RTU_L_VFCCU_SWRKCLR_0_RKNCLR1_MASK)
1162 
1163 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR2_MASK       (0x4U)
1164 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR2_SHIFT      (2U)
1165 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR2_WIDTH      (1U)
1166 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR2(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKCLR_0_RKNCLR2_SHIFT)) & RTU_L_VFCCU_SWRKCLR_0_RKNCLR2_MASK)
1167 
1168 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR3_MASK       (0x8U)
1169 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR3_SHIFT      (3U)
1170 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR3_WIDTH      (1U)
1171 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR3(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKCLR_0_RKNCLR3_SHIFT)) & RTU_L_VFCCU_SWRKCLR_0_RKNCLR3_MASK)
1172 
1173 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR4_MASK       (0x10U)
1174 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR4_SHIFT      (4U)
1175 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR4_WIDTH      (1U)
1176 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR4(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKCLR_0_RKNCLR4_SHIFT)) & RTU_L_VFCCU_SWRKCLR_0_RKNCLR4_MASK)
1177 
1178 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR5_MASK       (0x20U)
1179 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR5_SHIFT      (5U)
1180 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR5_WIDTH      (1U)
1181 #define RTU_L_VFCCU_SWRKCLR_0_RKNCLR5(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_SWRKCLR_0_RKNCLR5_SHIFT)) & RTU_L_VFCCU_SWRKCLR_0_RKNCLR5_MASK)
1182 /*! @} */
1183 
1184 /*! @name FHCFG0 - Fault Handler */
1185 /*! @{ */
1186 
1187 #define RTU_L_VFCCU_FHCFG0_FHIDEN_MASK           (0x1U)
1188 #define RTU_L_VFCCU_FHCFG0_FHIDEN_SHIFT          (0U)
1189 #define RTU_L_VFCCU_FHCFG0_FHIDEN_WIDTH          (1U)
1190 #define RTU_L_VFCCU_FHCFG0_FHIDEN(x)             (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHCFG0_FHIDEN_SHIFT)) & RTU_L_VFCCU_FHCFG0_FHIDEN_MASK)
1191 /*! @} */
1192 
1193 /*! @name FHSRVDS0 - Fault Handler Status */
1194 /*! @{ */
1195 
1196 #define RTU_L_VFCCU_FHSRVDS0_SERV_DID_MASK       (0xFU)
1197 #define RTU_L_VFCCU_FHSRVDS0_SERV_DID_SHIFT      (0U)
1198 #define RTU_L_VFCCU_FHSRVDS0_SERV_DID_WIDTH      (4U)
1199 #define RTU_L_VFCCU_FHSRVDS0_SERV_DID(x)         (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHSRVDS0_SERV_DID_SHIFT)) & RTU_L_VFCCU_FHSRVDS0_SERV_DID_MASK)
1200 
1201 #define RTU_L_VFCCU_FHSRVDS0_AGGFLTS_MASK        (0x10U)
1202 #define RTU_L_VFCCU_FHSRVDS0_AGGFLTS_SHIFT       (4U)
1203 #define RTU_L_VFCCU_FHSRVDS0_AGGFLTS_WIDTH       (1U)
1204 #define RTU_L_VFCCU_FHSRVDS0_AGGFLTS(x)          (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHSRVDS0_AGGFLTS_SHIFT)) & RTU_L_VFCCU_FHSRVDS0_AGGFLTS_MASK)
1205 /*! @} */
1206 
1207 /*! @name FHFLTENC00 - Fault Enable */
1208 /*! @{ */
1209 
1210 #define RTU_L_VFCCU_FHFLTENC00_EN0_MASK          (0x1U)
1211 #define RTU_L_VFCCU_FHFLTENC00_EN0_SHIFT         (0U)
1212 #define RTU_L_VFCCU_FHFLTENC00_EN0_WIDTH         (1U)
1213 #define RTU_L_VFCCU_FHFLTENC00_EN0(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN0_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN0_MASK)
1214 
1215 #define RTU_L_VFCCU_FHFLTENC00_EN1_MASK          (0x2U)
1216 #define RTU_L_VFCCU_FHFLTENC00_EN1_SHIFT         (1U)
1217 #define RTU_L_VFCCU_FHFLTENC00_EN1_WIDTH         (1U)
1218 #define RTU_L_VFCCU_FHFLTENC00_EN1(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN1_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN1_MASK)
1219 
1220 #define RTU_L_VFCCU_FHFLTENC00_EN2_MASK          (0x4U)
1221 #define RTU_L_VFCCU_FHFLTENC00_EN2_SHIFT         (2U)
1222 #define RTU_L_VFCCU_FHFLTENC00_EN2_WIDTH         (1U)
1223 #define RTU_L_VFCCU_FHFLTENC00_EN2(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN2_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN2_MASK)
1224 
1225 #define RTU_L_VFCCU_FHFLTENC00_EN3_MASK          (0x8U)
1226 #define RTU_L_VFCCU_FHFLTENC00_EN3_SHIFT         (3U)
1227 #define RTU_L_VFCCU_FHFLTENC00_EN3_WIDTH         (1U)
1228 #define RTU_L_VFCCU_FHFLTENC00_EN3(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN3_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN3_MASK)
1229 
1230 #define RTU_L_VFCCU_FHFLTENC00_EN4_MASK          (0x10U)
1231 #define RTU_L_VFCCU_FHFLTENC00_EN4_SHIFT         (4U)
1232 #define RTU_L_VFCCU_FHFLTENC00_EN4_WIDTH         (1U)
1233 #define RTU_L_VFCCU_FHFLTENC00_EN4(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN4_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN4_MASK)
1234 
1235 #define RTU_L_VFCCU_FHFLTENC00_EN5_MASK          (0x20U)
1236 #define RTU_L_VFCCU_FHFLTENC00_EN5_SHIFT         (5U)
1237 #define RTU_L_VFCCU_FHFLTENC00_EN5_WIDTH         (1U)
1238 #define RTU_L_VFCCU_FHFLTENC00_EN5(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN5_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN5_MASK)
1239 
1240 #define RTU_L_VFCCU_FHFLTENC00_EN6_MASK          (0x40U)
1241 #define RTU_L_VFCCU_FHFLTENC00_EN6_SHIFT         (6U)
1242 #define RTU_L_VFCCU_FHFLTENC00_EN6_WIDTH         (1U)
1243 #define RTU_L_VFCCU_FHFLTENC00_EN6(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN6_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN6_MASK)
1244 
1245 #define RTU_L_VFCCU_FHFLTENC00_EN7_MASK          (0x80U)
1246 #define RTU_L_VFCCU_FHFLTENC00_EN7_SHIFT         (7U)
1247 #define RTU_L_VFCCU_FHFLTENC00_EN7_WIDTH         (1U)
1248 #define RTU_L_VFCCU_FHFLTENC00_EN7(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN7_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN7_MASK)
1249 
1250 #define RTU_L_VFCCU_FHFLTENC00_EN8_MASK          (0x100U)
1251 #define RTU_L_VFCCU_FHFLTENC00_EN8_SHIFT         (8U)
1252 #define RTU_L_VFCCU_FHFLTENC00_EN8_WIDTH         (1U)
1253 #define RTU_L_VFCCU_FHFLTENC00_EN8(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN8_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN8_MASK)
1254 
1255 #define RTU_L_VFCCU_FHFLTENC00_EN9_MASK          (0x200U)
1256 #define RTU_L_VFCCU_FHFLTENC00_EN9_SHIFT         (9U)
1257 #define RTU_L_VFCCU_FHFLTENC00_EN9_WIDTH         (1U)
1258 #define RTU_L_VFCCU_FHFLTENC00_EN9(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN9_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN9_MASK)
1259 
1260 #define RTU_L_VFCCU_FHFLTENC00_EN10_MASK         (0x400U)
1261 #define RTU_L_VFCCU_FHFLTENC00_EN10_SHIFT        (10U)
1262 #define RTU_L_VFCCU_FHFLTENC00_EN10_WIDTH        (1U)
1263 #define RTU_L_VFCCU_FHFLTENC00_EN10(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN10_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN10_MASK)
1264 
1265 #define RTU_L_VFCCU_FHFLTENC00_EN11_MASK         (0x800U)
1266 #define RTU_L_VFCCU_FHFLTENC00_EN11_SHIFT        (11U)
1267 #define RTU_L_VFCCU_FHFLTENC00_EN11_WIDTH        (1U)
1268 #define RTU_L_VFCCU_FHFLTENC00_EN11(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN11_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN11_MASK)
1269 
1270 #define RTU_L_VFCCU_FHFLTENC00_EN12_MASK         (0x1000U)
1271 #define RTU_L_VFCCU_FHFLTENC00_EN12_SHIFT        (12U)
1272 #define RTU_L_VFCCU_FHFLTENC00_EN12_WIDTH        (1U)
1273 #define RTU_L_VFCCU_FHFLTENC00_EN12(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN12_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN12_MASK)
1274 
1275 #define RTU_L_VFCCU_FHFLTENC00_EN13_MASK         (0x2000U)
1276 #define RTU_L_VFCCU_FHFLTENC00_EN13_SHIFT        (13U)
1277 #define RTU_L_VFCCU_FHFLTENC00_EN13_WIDTH        (1U)
1278 #define RTU_L_VFCCU_FHFLTENC00_EN13(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN13_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN13_MASK)
1279 
1280 #define RTU_L_VFCCU_FHFLTENC00_EN14_MASK         (0x4000U)
1281 #define RTU_L_VFCCU_FHFLTENC00_EN14_SHIFT        (14U)
1282 #define RTU_L_VFCCU_FHFLTENC00_EN14_WIDTH        (1U)
1283 #define RTU_L_VFCCU_FHFLTENC00_EN14(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN14_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN14_MASK)
1284 
1285 #define RTU_L_VFCCU_FHFLTENC00_EN15_MASK         (0x8000U)
1286 #define RTU_L_VFCCU_FHFLTENC00_EN15_SHIFT        (15U)
1287 #define RTU_L_VFCCU_FHFLTENC00_EN15_WIDTH        (1U)
1288 #define RTU_L_VFCCU_FHFLTENC00_EN15(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN15_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN15_MASK)
1289 
1290 #define RTU_L_VFCCU_FHFLTENC00_EN16_MASK         (0x10000U)
1291 #define RTU_L_VFCCU_FHFLTENC00_EN16_SHIFT        (16U)
1292 #define RTU_L_VFCCU_FHFLTENC00_EN16_WIDTH        (1U)
1293 #define RTU_L_VFCCU_FHFLTENC00_EN16(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN16_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN16_MASK)
1294 
1295 #define RTU_L_VFCCU_FHFLTENC00_EN17_MASK         (0x20000U)
1296 #define RTU_L_VFCCU_FHFLTENC00_EN17_SHIFT        (17U)
1297 #define RTU_L_VFCCU_FHFLTENC00_EN17_WIDTH        (1U)
1298 #define RTU_L_VFCCU_FHFLTENC00_EN17(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN17_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN17_MASK)
1299 
1300 #define RTU_L_VFCCU_FHFLTENC00_EN18_MASK         (0x40000U)
1301 #define RTU_L_VFCCU_FHFLTENC00_EN18_SHIFT        (18U)
1302 #define RTU_L_VFCCU_FHFLTENC00_EN18_WIDTH        (1U)
1303 #define RTU_L_VFCCU_FHFLTENC00_EN18(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN18_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN18_MASK)
1304 
1305 #define RTU_L_VFCCU_FHFLTENC00_EN19_MASK         (0x80000U)
1306 #define RTU_L_VFCCU_FHFLTENC00_EN19_SHIFT        (19U)
1307 #define RTU_L_VFCCU_FHFLTENC00_EN19_WIDTH        (1U)
1308 #define RTU_L_VFCCU_FHFLTENC00_EN19(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN19_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN19_MASK)
1309 
1310 #define RTU_L_VFCCU_FHFLTENC00_EN20_MASK         (0x100000U)
1311 #define RTU_L_VFCCU_FHFLTENC00_EN20_SHIFT        (20U)
1312 #define RTU_L_VFCCU_FHFLTENC00_EN20_WIDTH        (1U)
1313 #define RTU_L_VFCCU_FHFLTENC00_EN20(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN20_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN20_MASK)
1314 
1315 #define RTU_L_VFCCU_FHFLTENC00_EN21_MASK         (0x200000U)
1316 #define RTU_L_VFCCU_FHFLTENC00_EN21_SHIFT        (21U)
1317 #define RTU_L_VFCCU_FHFLTENC00_EN21_WIDTH        (1U)
1318 #define RTU_L_VFCCU_FHFLTENC00_EN21(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN21_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN21_MASK)
1319 
1320 #define RTU_L_VFCCU_FHFLTENC00_EN22_MASK         (0x400000U)
1321 #define RTU_L_VFCCU_FHFLTENC00_EN22_SHIFT        (22U)
1322 #define RTU_L_VFCCU_FHFLTENC00_EN22_WIDTH        (1U)
1323 #define RTU_L_VFCCU_FHFLTENC00_EN22(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN22_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN22_MASK)
1324 
1325 #define RTU_L_VFCCU_FHFLTENC00_EN23_MASK         (0x800000U)
1326 #define RTU_L_VFCCU_FHFLTENC00_EN23_SHIFT        (23U)
1327 #define RTU_L_VFCCU_FHFLTENC00_EN23_WIDTH        (1U)
1328 #define RTU_L_VFCCU_FHFLTENC00_EN23(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN23_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN23_MASK)
1329 
1330 #define RTU_L_VFCCU_FHFLTENC00_EN24_MASK         (0x1000000U)
1331 #define RTU_L_VFCCU_FHFLTENC00_EN24_SHIFT        (24U)
1332 #define RTU_L_VFCCU_FHFLTENC00_EN24_WIDTH        (1U)
1333 #define RTU_L_VFCCU_FHFLTENC00_EN24(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN24_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN24_MASK)
1334 
1335 #define RTU_L_VFCCU_FHFLTENC00_EN25_MASK         (0x2000000U)
1336 #define RTU_L_VFCCU_FHFLTENC00_EN25_SHIFT        (25U)
1337 #define RTU_L_VFCCU_FHFLTENC00_EN25_WIDTH        (1U)
1338 #define RTU_L_VFCCU_FHFLTENC00_EN25(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN25_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN25_MASK)
1339 
1340 #define RTU_L_VFCCU_FHFLTENC00_EN26_MASK         (0x4000000U)
1341 #define RTU_L_VFCCU_FHFLTENC00_EN26_SHIFT        (26U)
1342 #define RTU_L_VFCCU_FHFLTENC00_EN26_WIDTH        (1U)
1343 #define RTU_L_VFCCU_FHFLTENC00_EN26(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN26_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN26_MASK)
1344 
1345 #define RTU_L_VFCCU_FHFLTENC00_EN27_MASK         (0x8000000U)
1346 #define RTU_L_VFCCU_FHFLTENC00_EN27_SHIFT        (27U)
1347 #define RTU_L_VFCCU_FHFLTENC00_EN27_WIDTH        (1U)
1348 #define RTU_L_VFCCU_FHFLTENC00_EN27(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN27_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN27_MASK)
1349 
1350 #define RTU_L_VFCCU_FHFLTENC00_EN28_MASK         (0x10000000U)
1351 #define RTU_L_VFCCU_FHFLTENC00_EN28_SHIFT        (28U)
1352 #define RTU_L_VFCCU_FHFLTENC00_EN28_WIDTH        (1U)
1353 #define RTU_L_VFCCU_FHFLTENC00_EN28(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN28_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN28_MASK)
1354 
1355 #define RTU_L_VFCCU_FHFLTENC00_EN29_MASK         (0x20000000U)
1356 #define RTU_L_VFCCU_FHFLTENC00_EN29_SHIFT        (29U)
1357 #define RTU_L_VFCCU_FHFLTENC00_EN29_WIDTH        (1U)
1358 #define RTU_L_VFCCU_FHFLTENC00_EN29(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN29_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN29_MASK)
1359 
1360 #define RTU_L_VFCCU_FHFLTENC00_EN30_MASK         (0x40000000U)
1361 #define RTU_L_VFCCU_FHFLTENC00_EN30_SHIFT        (30U)
1362 #define RTU_L_VFCCU_FHFLTENC00_EN30_WIDTH        (1U)
1363 #define RTU_L_VFCCU_FHFLTENC00_EN30(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN30_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN30_MASK)
1364 
1365 #define RTU_L_VFCCU_FHFLTENC00_EN31_MASK         (0x80000000U)
1366 #define RTU_L_VFCCU_FHFLTENC00_EN31_SHIFT        (31U)
1367 #define RTU_L_VFCCU_FHFLTENC00_EN31_WIDTH        (1U)
1368 #define RTU_L_VFCCU_FHFLTENC00_EN31(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC00_EN31_SHIFT)) & RTU_L_VFCCU_FHFLTENC00_EN31_MASK)
1369 /*! @} */
1370 
1371 /*! @name FHFLTENC01 - Fault Enable */
1372 /*! @{ */
1373 
1374 #define RTU_L_VFCCU_FHFLTENC01_EN32_MASK         (0x1U)
1375 #define RTU_L_VFCCU_FHFLTENC01_EN32_SHIFT        (0U)
1376 #define RTU_L_VFCCU_FHFLTENC01_EN32_WIDTH        (1U)
1377 #define RTU_L_VFCCU_FHFLTENC01_EN32(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN32_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN32_MASK)
1378 
1379 #define RTU_L_VFCCU_FHFLTENC01_EN33_MASK         (0x2U)
1380 #define RTU_L_VFCCU_FHFLTENC01_EN33_SHIFT        (1U)
1381 #define RTU_L_VFCCU_FHFLTENC01_EN33_WIDTH        (1U)
1382 #define RTU_L_VFCCU_FHFLTENC01_EN33(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN33_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN33_MASK)
1383 
1384 #define RTU_L_VFCCU_FHFLTENC01_EN34_MASK         (0x4U)
1385 #define RTU_L_VFCCU_FHFLTENC01_EN34_SHIFT        (2U)
1386 #define RTU_L_VFCCU_FHFLTENC01_EN34_WIDTH        (1U)
1387 #define RTU_L_VFCCU_FHFLTENC01_EN34(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN34_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN34_MASK)
1388 
1389 #define RTU_L_VFCCU_FHFLTENC01_EN35_MASK         (0x8U)
1390 #define RTU_L_VFCCU_FHFLTENC01_EN35_SHIFT        (3U)
1391 #define RTU_L_VFCCU_FHFLTENC01_EN35_WIDTH        (1U)
1392 #define RTU_L_VFCCU_FHFLTENC01_EN35(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN35_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN35_MASK)
1393 
1394 #define RTU_L_VFCCU_FHFLTENC01_EN36_MASK         (0x10U)
1395 #define RTU_L_VFCCU_FHFLTENC01_EN36_SHIFT        (4U)
1396 #define RTU_L_VFCCU_FHFLTENC01_EN36_WIDTH        (1U)
1397 #define RTU_L_VFCCU_FHFLTENC01_EN36(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN36_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN36_MASK)
1398 
1399 #define RTU_L_VFCCU_FHFLTENC01_EN37_MASK         (0x20U)
1400 #define RTU_L_VFCCU_FHFLTENC01_EN37_SHIFT        (5U)
1401 #define RTU_L_VFCCU_FHFLTENC01_EN37_WIDTH        (1U)
1402 #define RTU_L_VFCCU_FHFLTENC01_EN37(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN37_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN37_MASK)
1403 
1404 #define RTU_L_VFCCU_FHFLTENC01_EN38_MASK         (0x40U)
1405 #define RTU_L_VFCCU_FHFLTENC01_EN38_SHIFT        (6U)
1406 #define RTU_L_VFCCU_FHFLTENC01_EN38_WIDTH        (1U)
1407 #define RTU_L_VFCCU_FHFLTENC01_EN38(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN38_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN38_MASK)
1408 
1409 #define RTU_L_VFCCU_FHFLTENC01_EN39_MASK         (0x80U)
1410 #define RTU_L_VFCCU_FHFLTENC01_EN39_SHIFT        (7U)
1411 #define RTU_L_VFCCU_FHFLTENC01_EN39_WIDTH        (1U)
1412 #define RTU_L_VFCCU_FHFLTENC01_EN39(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN39_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN39_MASK)
1413 
1414 #define RTU_L_VFCCU_FHFLTENC01_EN40_MASK         (0x100U)
1415 #define RTU_L_VFCCU_FHFLTENC01_EN40_SHIFT        (8U)
1416 #define RTU_L_VFCCU_FHFLTENC01_EN40_WIDTH        (1U)
1417 #define RTU_L_VFCCU_FHFLTENC01_EN40(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN40_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN40_MASK)
1418 
1419 #define RTU_L_VFCCU_FHFLTENC01_EN41_MASK         (0x200U)
1420 #define RTU_L_VFCCU_FHFLTENC01_EN41_SHIFT        (9U)
1421 #define RTU_L_VFCCU_FHFLTENC01_EN41_WIDTH        (1U)
1422 #define RTU_L_VFCCU_FHFLTENC01_EN41(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN41_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN41_MASK)
1423 
1424 #define RTU_L_VFCCU_FHFLTENC01_EN42_MASK         (0x400U)
1425 #define RTU_L_VFCCU_FHFLTENC01_EN42_SHIFT        (10U)
1426 #define RTU_L_VFCCU_FHFLTENC01_EN42_WIDTH        (1U)
1427 #define RTU_L_VFCCU_FHFLTENC01_EN42(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN42_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN42_MASK)
1428 
1429 #define RTU_L_VFCCU_FHFLTENC01_EN43_MASK         (0x800U)
1430 #define RTU_L_VFCCU_FHFLTENC01_EN43_SHIFT        (11U)
1431 #define RTU_L_VFCCU_FHFLTENC01_EN43_WIDTH        (1U)
1432 #define RTU_L_VFCCU_FHFLTENC01_EN43(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN43_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN43_MASK)
1433 
1434 #define RTU_L_VFCCU_FHFLTENC01_EN44_MASK         (0x1000U)
1435 #define RTU_L_VFCCU_FHFLTENC01_EN44_SHIFT        (12U)
1436 #define RTU_L_VFCCU_FHFLTENC01_EN44_WIDTH        (1U)
1437 #define RTU_L_VFCCU_FHFLTENC01_EN44(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN44_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN44_MASK)
1438 
1439 #define RTU_L_VFCCU_FHFLTENC01_EN45_MASK         (0x2000U)
1440 #define RTU_L_VFCCU_FHFLTENC01_EN45_SHIFT        (13U)
1441 #define RTU_L_VFCCU_FHFLTENC01_EN45_WIDTH        (1U)
1442 #define RTU_L_VFCCU_FHFLTENC01_EN45(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN45_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN45_MASK)
1443 
1444 #define RTU_L_VFCCU_FHFLTENC01_EN46_MASK         (0x4000U)
1445 #define RTU_L_VFCCU_FHFLTENC01_EN46_SHIFT        (14U)
1446 #define RTU_L_VFCCU_FHFLTENC01_EN46_WIDTH        (1U)
1447 #define RTU_L_VFCCU_FHFLTENC01_EN46(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN46_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN46_MASK)
1448 
1449 #define RTU_L_VFCCU_FHFLTENC01_EN47_MASK         (0x8000U)
1450 #define RTU_L_VFCCU_FHFLTENC01_EN47_SHIFT        (15U)
1451 #define RTU_L_VFCCU_FHFLTENC01_EN47_WIDTH        (1U)
1452 #define RTU_L_VFCCU_FHFLTENC01_EN47(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN47_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN47_MASK)
1453 
1454 #define RTU_L_VFCCU_FHFLTENC01_EN48_MASK         (0x10000U)
1455 #define RTU_L_VFCCU_FHFLTENC01_EN48_SHIFT        (16U)
1456 #define RTU_L_VFCCU_FHFLTENC01_EN48_WIDTH        (1U)
1457 #define RTU_L_VFCCU_FHFLTENC01_EN48(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN48_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN48_MASK)
1458 
1459 #define RTU_L_VFCCU_FHFLTENC01_EN49_MASK         (0x20000U)
1460 #define RTU_L_VFCCU_FHFLTENC01_EN49_SHIFT        (17U)
1461 #define RTU_L_VFCCU_FHFLTENC01_EN49_WIDTH        (1U)
1462 #define RTU_L_VFCCU_FHFLTENC01_EN49(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTENC01_EN49_SHIFT)) & RTU_L_VFCCU_FHFLTENC01_EN49_MASK)
1463 /*! @} */
1464 
1465 /*! @name FHFLTS00 - Fault Status */
1466 /*! @{ */
1467 
1468 #define RTU_L_VFCCU_FHFLTS00_STAT0_MASK          (0x1U)
1469 #define RTU_L_VFCCU_FHFLTS00_STAT0_SHIFT         (0U)
1470 #define RTU_L_VFCCU_FHFLTS00_STAT0_WIDTH         (1U)
1471 #define RTU_L_VFCCU_FHFLTS00_STAT0(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT0_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT0_MASK)
1472 
1473 #define RTU_L_VFCCU_FHFLTS00_STAT1_MASK          (0x2U)
1474 #define RTU_L_VFCCU_FHFLTS00_STAT1_SHIFT         (1U)
1475 #define RTU_L_VFCCU_FHFLTS00_STAT1_WIDTH         (1U)
1476 #define RTU_L_VFCCU_FHFLTS00_STAT1(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT1_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT1_MASK)
1477 
1478 #define RTU_L_VFCCU_FHFLTS00_STAT2_MASK          (0x4U)
1479 #define RTU_L_VFCCU_FHFLTS00_STAT2_SHIFT         (2U)
1480 #define RTU_L_VFCCU_FHFLTS00_STAT2_WIDTH         (1U)
1481 #define RTU_L_VFCCU_FHFLTS00_STAT2(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT2_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT2_MASK)
1482 
1483 #define RTU_L_VFCCU_FHFLTS00_STAT3_MASK          (0x8U)
1484 #define RTU_L_VFCCU_FHFLTS00_STAT3_SHIFT         (3U)
1485 #define RTU_L_VFCCU_FHFLTS00_STAT3_WIDTH         (1U)
1486 #define RTU_L_VFCCU_FHFLTS00_STAT3(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT3_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT3_MASK)
1487 
1488 #define RTU_L_VFCCU_FHFLTS00_STAT4_MASK          (0x10U)
1489 #define RTU_L_VFCCU_FHFLTS00_STAT4_SHIFT         (4U)
1490 #define RTU_L_VFCCU_FHFLTS00_STAT4_WIDTH         (1U)
1491 #define RTU_L_VFCCU_FHFLTS00_STAT4(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT4_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT4_MASK)
1492 
1493 #define RTU_L_VFCCU_FHFLTS00_STAT5_MASK          (0x20U)
1494 #define RTU_L_VFCCU_FHFLTS00_STAT5_SHIFT         (5U)
1495 #define RTU_L_VFCCU_FHFLTS00_STAT5_WIDTH         (1U)
1496 #define RTU_L_VFCCU_FHFLTS00_STAT5(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT5_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT5_MASK)
1497 
1498 #define RTU_L_VFCCU_FHFLTS00_STAT6_MASK          (0x40U)
1499 #define RTU_L_VFCCU_FHFLTS00_STAT6_SHIFT         (6U)
1500 #define RTU_L_VFCCU_FHFLTS00_STAT6_WIDTH         (1U)
1501 #define RTU_L_VFCCU_FHFLTS00_STAT6(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT6_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT6_MASK)
1502 
1503 #define RTU_L_VFCCU_FHFLTS00_STAT7_MASK          (0x80U)
1504 #define RTU_L_VFCCU_FHFLTS00_STAT7_SHIFT         (7U)
1505 #define RTU_L_VFCCU_FHFLTS00_STAT7_WIDTH         (1U)
1506 #define RTU_L_VFCCU_FHFLTS00_STAT7(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT7_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT7_MASK)
1507 
1508 #define RTU_L_VFCCU_FHFLTS00_STAT8_MASK          (0x100U)
1509 #define RTU_L_VFCCU_FHFLTS00_STAT8_SHIFT         (8U)
1510 #define RTU_L_VFCCU_FHFLTS00_STAT8_WIDTH         (1U)
1511 #define RTU_L_VFCCU_FHFLTS00_STAT8(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT8_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT8_MASK)
1512 
1513 #define RTU_L_VFCCU_FHFLTS00_STAT9_MASK          (0x200U)
1514 #define RTU_L_VFCCU_FHFLTS00_STAT9_SHIFT         (9U)
1515 #define RTU_L_VFCCU_FHFLTS00_STAT9_WIDTH         (1U)
1516 #define RTU_L_VFCCU_FHFLTS00_STAT9(x)            (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT9_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT9_MASK)
1517 
1518 #define RTU_L_VFCCU_FHFLTS00_STAT10_MASK         (0x400U)
1519 #define RTU_L_VFCCU_FHFLTS00_STAT10_SHIFT        (10U)
1520 #define RTU_L_VFCCU_FHFLTS00_STAT10_WIDTH        (1U)
1521 #define RTU_L_VFCCU_FHFLTS00_STAT10(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT10_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT10_MASK)
1522 
1523 #define RTU_L_VFCCU_FHFLTS00_STAT11_MASK         (0x800U)
1524 #define RTU_L_VFCCU_FHFLTS00_STAT11_SHIFT        (11U)
1525 #define RTU_L_VFCCU_FHFLTS00_STAT11_WIDTH        (1U)
1526 #define RTU_L_VFCCU_FHFLTS00_STAT11(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT11_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT11_MASK)
1527 
1528 #define RTU_L_VFCCU_FHFLTS00_STAT12_MASK         (0x1000U)
1529 #define RTU_L_VFCCU_FHFLTS00_STAT12_SHIFT        (12U)
1530 #define RTU_L_VFCCU_FHFLTS00_STAT12_WIDTH        (1U)
1531 #define RTU_L_VFCCU_FHFLTS00_STAT12(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT12_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT12_MASK)
1532 
1533 #define RTU_L_VFCCU_FHFLTS00_STAT13_MASK         (0x2000U)
1534 #define RTU_L_VFCCU_FHFLTS00_STAT13_SHIFT        (13U)
1535 #define RTU_L_VFCCU_FHFLTS00_STAT13_WIDTH        (1U)
1536 #define RTU_L_VFCCU_FHFLTS00_STAT13(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT13_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT13_MASK)
1537 
1538 #define RTU_L_VFCCU_FHFLTS00_STAT14_MASK         (0x4000U)
1539 #define RTU_L_VFCCU_FHFLTS00_STAT14_SHIFT        (14U)
1540 #define RTU_L_VFCCU_FHFLTS00_STAT14_WIDTH        (1U)
1541 #define RTU_L_VFCCU_FHFLTS00_STAT14(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT14_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT14_MASK)
1542 
1543 #define RTU_L_VFCCU_FHFLTS00_STAT15_MASK         (0x8000U)
1544 #define RTU_L_VFCCU_FHFLTS00_STAT15_SHIFT        (15U)
1545 #define RTU_L_VFCCU_FHFLTS00_STAT15_WIDTH        (1U)
1546 #define RTU_L_VFCCU_FHFLTS00_STAT15(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT15_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT15_MASK)
1547 
1548 #define RTU_L_VFCCU_FHFLTS00_STAT16_MASK         (0x10000U)
1549 #define RTU_L_VFCCU_FHFLTS00_STAT16_SHIFT        (16U)
1550 #define RTU_L_VFCCU_FHFLTS00_STAT16_WIDTH        (1U)
1551 #define RTU_L_VFCCU_FHFLTS00_STAT16(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT16_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT16_MASK)
1552 
1553 #define RTU_L_VFCCU_FHFLTS00_STAT17_MASK         (0x20000U)
1554 #define RTU_L_VFCCU_FHFLTS00_STAT17_SHIFT        (17U)
1555 #define RTU_L_VFCCU_FHFLTS00_STAT17_WIDTH        (1U)
1556 #define RTU_L_VFCCU_FHFLTS00_STAT17(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT17_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT17_MASK)
1557 
1558 #define RTU_L_VFCCU_FHFLTS00_STAT18_MASK         (0x40000U)
1559 #define RTU_L_VFCCU_FHFLTS00_STAT18_SHIFT        (18U)
1560 #define RTU_L_VFCCU_FHFLTS00_STAT18_WIDTH        (1U)
1561 #define RTU_L_VFCCU_FHFLTS00_STAT18(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT18_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT18_MASK)
1562 
1563 #define RTU_L_VFCCU_FHFLTS00_STAT19_MASK         (0x80000U)
1564 #define RTU_L_VFCCU_FHFLTS00_STAT19_SHIFT        (19U)
1565 #define RTU_L_VFCCU_FHFLTS00_STAT19_WIDTH        (1U)
1566 #define RTU_L_VFCCU_FHFLTS00_STAT19(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT19_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT19_MASK)
1567 
1568 #define RTU_L_VFCCU_FHFLTS00_STAT20_MASK         (0x100000U)
1569 #define RTU_L_VFCCU_FHFLTS00_STAT20_SHIFT        (20U)
1570 #define RTU_L_VFCCU_FHFLTS00_STAT20_WIDTH        (1U)
1571 #define RTU_L_VFCCU_FHFLTS00_STAT20(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT20_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT20_MASK)
1572 
1573 #define RTU_L_VFCCU_FHFLTS00_STAT21_MASK         (0x200000U)
1574 #define RTU_L_VFCCU_FHFLTS00_STAT21_SHIFT        (21U)
1575 #define RTU_L_VFCCU_FHFLTS00_STAT21_WIDTH        (1U)
1576 #define RTU_L_VFCCU_FHFLTS00_STAT21(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT21_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT21_MASK)
1577 
1578 #define RTU_L_VFCCU_FHFLTS00_STAT22_MASK         (0x400000U)
1579 #define RTU_L_VFCCU_FHFLTS00_STAT22_SHIFT        (22U)
1580 #define RTU_L_VFCCU_FHFLTS00_STAT22_WIDTH        (1U)
1581 #define RTU_L_VFCCU_FHFLTS00_STAT22(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT22_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT22_MASK)
1582 
1583 #define RTU_L_VFCCU_FHFLTS00_STAT23_MASK         (0x800000U)
1584 #define RTU_L_VFCCU_FHFLTS00_STAT23_SHIFT        (23U)
1585 #define RTU_L_VFCCU_FHFLTS00_STAT23_WIDTH        (1U)
1586 #define RTU_L_VFCCU_FHFLTS00_STAT23(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT23_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT23_MASK)
1587 
1588 #define RTU_L_VFCCU_FHFLTS00_STAT24_MASK         (0x1000000U)
1589 #define RTU_L_VFCCU_FHFLTS00_STAT24_SHIFT        (24U)
1590 #define RTU_L_VFCCU_FHFLTS00_STAT24_WIDTH        (1U)
1591 #define RTU_L_VFCCU_FHFLTS00_STAT24(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT24_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT24_MASK)
1592 
1593 #define RTU_L_VFCCU_FHFLTS00_STAT25_MASK         (0x2000000U)
1594 #define RTU_L_VFCCU_FHFLTS00_STAT25_SHIFT        (25U)
1595 #define RTU_L_VFCCU_FHFLTS00_STAT25_WIDTH        (1U)
1596 #define RTU_L_VFCCU_FHFLTS00_STAT25(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT25_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT25_MASK)
1597 
1598 #define RTU_L_VFCCU_FHFLTS00_STAT26_MASK         (0x4000000U)
1599 #define RTU_L_VFCCU_FHFLTS00_STAT26_SHIFT        (26U)
1600 #define RTU_L_VFCCU_FHFLTS00_STAT26_WIDTH        (1U)
1601 #define RTU_L_VFCCU_FHFLTS00_STAT26(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT26_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT26_MASK)
1602 
1603 #define RTU_L_VFCCU_FHFLTS00_STAT27_MASK         (0x8000000U)
1604 #define RTU_L_VFCCU_FHFLTS00_STAT27_SHIFT        (27U)
1605 #define RTU_L_VFCCU_FHFLTS00_STAT27_WIDTH        (1U)
1606 #define RTU_L_VFCCU_FHFLTS00_STAT27(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT27_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT27_MASK)
1607 
1608 #define RTU_L_VFCCU_FHFLTS00_STAT28_MASK         (0x10000000U)
1609 #define RTU_L_VFCCU_FHFLTS00_STAT28_SHIFT        (28U)
1610 #define RTU_L_VFCCU_FHFLTS00_STAT28_WIDTH        (1U)
1611 #define RTU_L_VFCCU_FHFLTS00_STAT28(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT28_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT28_MASK)
1612 
1613 #define RTU_L_VFCCU_FHFLTS00_STAT29_MASK         (0x20000000U)
1614 #define RTU_L_VFCCU_FHFLTS00_STAT29_SHIFT        (29U)
1615 #define RTU_L_VFCCU_FHFLTS00_STAT29_WIDTH        (1U)
1616 #define RTU_L_VFCCU_FHFLTS00_STAT29(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT29_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT29_MASK)
1617 
1618 #define RTU_L_VFCCU_FHFLTS00_STAT30_MASK         (0x40000000U)
1619 #define RTU_L_VFCCU_FHFLTS00_STAT30_SHIFT        (30U)
1620 #define RTU_L_VFCCU_FHFLTS00_STAT30_WIDTH        (1U)
1621 #define RTU_L_VFCCU_FHFLTS00_STAT30(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT30_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT30_MASK)
1622 
1623 #define RTU_L_VFCCU_FHFLTS00_STAT31_MASK         (0x80000000U)
1624 #define RTU_L_VFCCU_FHFLTS00_STAT31_SHIFT        (31U)
1625 #define RTU_L_VFCCU_FHFLTS00_STAT31_WIDTH        (1U)
1626 #define RTU_L_VFCCU_FHFLTS00_STAT31(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS00_STAT31_SHIFT)) & RTU_L_VFCCU_FHFLTS00_STAT31_MASK)
1627 /*! @} */
1628 
1629 /*! @name FHFLTS01 - Fault Status */
1630 /*! @{ */
1631 
1632 #define RTU_L_VFCCU_FHFLTS01_STAT32_MASK         (0x1U)
1633 #define RTU_L_VFCCU_FHFLTS01_STAT32_SHIFT        (0U)
1634 #define RTU_L_VFCCU_FHFLTS01_STAT32_WIDTH        (1U)
1635 #define RTU_L_VFCCU_FHFLTS01_STAT32(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT32_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT32_MASK)
1636 
1637 #define RTU_L_VFCCU_FHFLTS01_STAT33_MASK         (0x2U)
1638 #define RTU_L_VFCCU_FHFLTS01_STAT33_SHIFT        (1U)
1639 #define RTU_L_VFCCU_FHFLTS01_STAT33_WIDTH        (1U)
1640 #define RTU_L_VFCCU_FHFLTS01_STAT33(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT33_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT33_MASK)
1641 
1642 #define RTU_L_VFCCU_FHFLTS01_STAT34_MASK         (0x4U)
1643 #define RTU_L_VFCCU_FHFLTS01_STAT34_SHIFT        (2U)
1644 #define RTU_L_VFCCU_FHFLTS01_STAT34_WIDTH        (1U)
1645 #define RTU_L_VFCCU_FHFLTS01_STAT34(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT34_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT34_MASK)
1646 
1647 #define RTU_L_VFCCU_FHFLTS01_STAT35_MASK         (0x8U)
1648 #define RTU_L_VFCCU_FHFLTS01_STAT35_SHIFT        (3U)
1649 #define RTU_L_VFCCU_FHFLTS01_STAT35_WIDTH        (1U)
1650 #define RTU_L_VFCCU_FHFLTS01_STAT35(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT35_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT35_MASK)
1651 
1652 #define RTU_L_VFCCU_FHFLTS01_STAT36_MASK         (0x10U)
1653 #define RTU_L_VFCCU_FHFLTS01_STAT36_SHIFT        (4U)
1654 #define RTU_L_VFCCU_FHFLTS01_STAT36_WIDTH        (1U)
1655 #define RTU_L_VFCCU_FHFLTS01_STAT36(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT36_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT36_MASK)
1656 
1657 #define RTU_L_VFCCU_FHFLTS01_STAT37_MASK         (0x20U)
1658 #define RTU_L_VFCCU_FHFLTS01_STAT37_SHIFT        (5U)
1659 #define RTU_L_VFCCU_FHFLTS01_STAT37_WIDTH        (1U)
1660 #define RTU_L_VFCCU_FHFLTS01_STAT37(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT37_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT37_MASK)
1661 
1662 #define RTU_L_VFCCU_FHFLTS01_STAT38_MASK         (0x40U)
1663 #define RTU_L_VFCCU_FHFLTS01_STAT38_SHIFT        (6U)
1664 #define RTU_L_VFCCU_FHFLTS01_STAT38_WIDTH        (1U)
1665 #define RTU_L_VFCCU_FHFLTS01_STAT38(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT38_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT38_MASK)
1666 
1667 #define RTU_L_VFCCU_FHFLTS01_STAT39_MASK         (0x80U)
1668 #define RTU_L_VFCCU_FHFLTS01_STAT39_SHIFT        (7U)
1669 #define RTU_L_VFCCU_FHFLTS01_STAT39_WIDTH        (1U)
1670 #define RTU_L_VFCCU_FHFLTS01_STAT39(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT39_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT39_MASK)
1671 
1672 #define RTU_L_VFCCU_FHFLTS01_STAT40_MASK         (0x100U)
1673 #define RTU_L_VFCCU_FHFLTS01_STAT40_SHIFT        (8U)
1674 #define RTU_L_VFCCU_FHFLTS01_STAT40_WIDTH        (1U)
1675 #define RTU_L_VFCCU_FHFLTS01_STAT40(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT40_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT40_MASK)
1676 
1677 #define RTU_L_VFCCU_FHFLTS01_STAT41_MASK         (0x200U)
1678 #define RTU_L_VFCCU_FHFLTS01_STAT41_SHIFT        (9U)
1679 #define RTU_L_VFCCU_FHFLTS01_STAT41_WIDTH        (1U)
1680 #define RTU_L_VFCCU_FHFLTS01_STAT41(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT41_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT41_MASK)
1681 
1682 #define RTU_L_VFCCU_FHFLTS01_STAT42_MASK         (0x400U)
1683 #define RTU_L_VFCCU_FHFLTS01_STAT42_SHIFT        (10U)
1684 #define RTU_L_VFCCU_FHFLTS01_STAT42_WIDTH        (1U)
1685 #define RTU_L_VFCCU_FHFLTS01_STAT42(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT42_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT42_MASK)
1686 
1687 #define RTU_L_VFCCU_FHFLTS01_STAT43_MASK         (0x800U)
1688 #define RTU_L_VFCCU_FHFLTS01_STAT43_SHIFT        (11U)
1689 #define RTU_L_VFCCU_FHFLTS01_STAT43_WIDTH        (1U)
1690 #define RTU_L_VFCCU_FHFLTS01_STAT43(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT43_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT43_MASK)
1691 
1692 #define RTU_L_VFCCU_FHFLTS01_STAT44_MASK         (0x1000U)
1693 #define RTU_L_VFCCU_FHFLTS01_STAT44_SHIFT        (12U)
1694 #define RTU_L_VFCCU_FHFLTS01_STAT44_WIDTH        (1U)
1695 #define RTU_L_VFCCU_FHFLTS01_STAT44(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT44_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT44_MASK)
1696 
1697 #define RTU_L_VFCCU_FHFLTS01_STAT45_MASK         (0x2000U)
1698 #define RTU_L_VFCCU_FHFLTS01_STAT45_SHIFT        (13U)
1699 #define RTU_L_VFCCU_FHFLTS01_STAT45_WIDTH        (1U)
1700 #define RTU_L_VFCCU_FHFLTS01_STAT45(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT45_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT45_MASK)
1701 
1702 #define RTU_L_VFCCU_FHFLTS01_STAT46_MASK         (0x4000U)
1703 #define RTU_L_VFCCU_FHFLTS01_STAT46_SHIFT        (14U)
1704 #define RTU_L_VFCCU_FHFLTS01_STAT46_WIDTH        (1U)
1705 #define RTU_L_VFCCU_FHFLTS01_STAT46(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT46_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT46_MASK)
1706 
1707 #define RTU_L_VFCCU_FHFLTS01_STAT47_MASK         (0x8000U)
1708 #define RTU_L_VFCCU_FHFLTS01_STAT47_SHIFT        (15U)
1709 #define RTU_L_VFCCU_FHFLTS01_STAT47_WIDTH        (1U)
1710 #define RTU_L_VFCCU_FHFLTS01_STAT47(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT47_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT47_MASK)
1711 
1712 #define RTU_L_VFCCU_FHFLTS01_STAT48_MASK         (0x10000U)
1713 #define RTU_L_VFCCU_FHFLTS01_STAT48_SHIFT        (16U)
1714 #define RTU_L_VFCCU_FHFLTS01_STAT48_WIDTH        (1U)
1715 #define RTU_L_VFCCU_FHFLTS01_STAT48(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT48_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT48_MASK)
1716 
1717 #define RTU_L_VFCCU_FHFLTS01_STAT49_MASK         (0x20000U)
1718 #define RTU_L_VFCCU_FHFLTS01_STAT49_SHIFT        (17U)
1719 #define RTU_L_VFCCU_FHFLTS01_STAT49_WIDTH        (1U)
1720 #define RTU_L_VFCCU_FHFLTS01_STAT49(x)           (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTS01_STAT49_SHIFT)) & RTU_L_VFCCU_FHFLTS01_STAT49_MASK)
1721 /*! @} */
1722 
1723 /*! @name FHFLTRKC00 - Fault Reaction Set Configuration */
1724 /*! @{ */
1725 
1726 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL0_MASK      (0x7U)
1727 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL0_SHIFT     (0U)
1728 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL0_WIDTH     (3U)
1729 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL0_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL0_MASK)
1730 
1731 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL1_MASK      (0x70U)
1732 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL1_SHIFT     (4U)
1733 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL1_WIDTH     (3U)
1734 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL1_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL1_MASK)
1735 
1736 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL2_MASK      (0x700U)
1737 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL2_SHIFT     (8U)
1738 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL2_WIDTH     (3U)
1739 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL2_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL2_MASK)
1740 
1741 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL3_MASK      (0x7000U)
1742 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL3_SHIFT     (12U)
1743 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL3_WIDTH     (3U)
1744 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL3_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL3_MASK)
1745 
1746 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL4_MASK      (0x70000U)
1747 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL4_SHIFT     (16U)
1748 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL4_WIDTH     (3U)
1749 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL4_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL4_MASK)
1750 
1751 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL5_MASK      (0x700000U)
1752 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL5_SHIFT     (20U)
1753 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL5_WIDTH     (3U)
1754 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL5_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL5_MASK)
1755 
1756 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL6_MASK      (0x7000000U)
1757 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL6_SHIFT     (24U)
1758 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL6_WIDTH     (3U)
1759 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL6(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL6_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL6_MASK)
1760 
1761 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL7_MASK      (0x70000000U)
1762 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL7_SHIFT     (28U)
1763 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL7_WIDTH     (3U)
1764 #define RTU_L_VFCCU_FHFLTRKC00_RKNSEL7(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC00_RKNSEL7_SHIFT)) & RTU_L_VFCCU_FHFLTRKC00_RKNSEL7_MASK)
1765 /*! @} */
1766 
1767 /*! @name FHFLTRKC01 - Fault Reaction Set Configuration */
1768 /*! @{ */
1769 
1770 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL8_MASK      (0x7U)
1771 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL8_SHIFT     (0U)
1772 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL8_WIDTH     (3U)
1773 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL8(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL8_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL8_MASK)
1774 
1775 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL9_MASK      (0x70U)
1776 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL9_SHIFT     (4U)
1777 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL9_WIDTH     (3U)
1778 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL9(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL9_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL9_MASK)
1779 
1780 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL10_MASK     (0x700U)
1781 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL10_SHIFT    (8U)
1782 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL10_WIDTH    (3U)
1783 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL10(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL10_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL10_MASK)
1784 
1785 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL11_MASK     (0x7000U)
1786 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL11_SHIFT    (12U)
1787 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL11_WIDTH    (3U)
1788 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL11(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL11_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL11_MASK)
1789 
1790 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL12_MASK     (0x70000U)
1791 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL12_SHIFT    (16U)
1792 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL12_WIDTH    (3U)
1793 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL12(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL12_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL12_MASK)
1794 
1795 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL13_MASK     (0x700000U)
1796 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL13_SHIFT    (20U)
1797 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL13_WIDTH    (3U)
1798 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL13(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL13_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL13_MASK)
1799 
1800 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL14_MASK     (0x7000000U)
1801 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL14_SHIFT    (24U)
1802 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL14_WIDTH    (3U)
1803 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL14(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL14_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL14_MASK)
1804 
1805 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL15_MASK     (0x70000000U)
1806 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL15_SHIFT    (28U)
1807 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL15_WIDTH    (3U)
1808 #define RTU_L_VFCCU_FHFLTRKC01_RKNSEL15(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC01_RKNSEL15_SHIFT)) & RTU_L_VFCCU_FHFLTRKC01_RKNSEL15_MASK)
1809 /*! @} */
1810 
1811 /*! @name FHFLTRKC02 - Fault Reaction Set Configuration */
1812 /*! @{ */
1813 
1814 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL16_MASK     (0x7U)
1815 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL16_SHIFT    (0U)
1816 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL16_WIDTH    (3U)
1817 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL16(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL16_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL16_MASK)
1818 
1819 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL17_MASK     (0x70U)
1820 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL17_SHIFT    (4U)
1821 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL17_WIDTH    (3U)
1822 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL17(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL17_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL17_MASK)
1823 
1824 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL18_MASK     (0x700U)
1825 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL18_SHIFT    (8U)
1826 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL18_WIDTH    (3U)
1827 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL18(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL18_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL18_MASK)
1828 
1829 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL19_MASK     (0x7000U)
1830 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL19_SHIFT    (12U)
1831 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL19_WIDTH    (3U)
1832 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL19(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL19_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL19_MASK)
1833 
1834 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL20_MASK     (0x70000U)
1835 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL20_SHIFT    (16U)
1836 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL20_WIDTH    (3U)
1837 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL20(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL20_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL20_MASK)
1838 
1839 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL21_MASK     (0x700000U)
1840 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL21_SHIFT    (20U)
1841 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL21_WIDTH    (3U)
1842 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL21(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL21_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL21_MASK)
1843 
1844 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL22_MASK     (0x7000000U)
1845 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL22_SHIFT    (24U)
1846 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL22_WIDTH    (3U)
1847 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL22(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL22_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL22_MASK)
1848 
1849 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL23_MASK     (0x70000000U)
1850 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL23_SHIFT    (28U)
1851 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL23_WIDTH    (3U)
1852 #define RTU_L_VFCCU_FHFLTRKC02_RKNSEL23(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC02_RKNSEL23_SHIFT)) & RTU_L_VFCCU_FHFLTRKC02_RKNSEL23_MASK)
1853 /*! @} */
1854 
1855 /*! @name FHFLTRKC03 - Fault Reaction Set Configuration */
1856 /*! @{ */
1857 
1858 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL24_MASK     (0x7U)
1859 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL24_SHIFT    (0U)
1860 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL24_WIDTH    (3U)
1861 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL24(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL24_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL24_MASK)
1862 
1863 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL25_MASK     (0x70U)
1864 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL25_SHIFT    (4U)
1865 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL25_WIDTH    (3U)
1866 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL25(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL25_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL25_MASK)
1867 
1868 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL26_MASK     (0x700U)
1869 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL26_SHIFT    (8U)
1870 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL26_WIDTH    (3U)
1871 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL26(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL26_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL26_MASK)
1872 
1873 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL27_MASK     (0x7000U)
1874 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL27_SHIFT    (12U)
1875 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL27_WIDTH    (3U)
1876 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL27(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL27_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL27_MASK)
1877 
1878 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL28_MASK     (0x70000U)
1879 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL28_SHIFT    (16U)
1880 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL28_WIDTH    (3U)
1881 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL28(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL28_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL28_MASK)
1882 
1883 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL29_MASK     (0x700000U)
1884 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL29_SHIFT    (20U)
1885 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL29_WIDTH    (3U)
1886 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL29(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL29_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL29_MASK)
1887 
1888 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL30_MASK     (0x7000000U)
1889 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL30_SHIFT    (24U)
1890 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL30_WIDTH    (3U)
1891 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL30(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL30_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL30_MASK)
1892 
1893 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL31_MASK     (0x70000000U)
1894 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL31_SHIFT    (28U)
1895 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL31_WIDTH    (3U)
1896 #define RTU_L_VFCCU_FHFLTRKC03_RKNSEL31(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC03_RKNSEL31_SHIFT)) & RTU_L_VFCCU_FHFLTRKC03_RKNSEL31_MASK)
1897 /*! @} */
1898 
1899 /*! @name FHFLTRKC04 - Fault Reaction Set Configuration */
1900 /*! @{ */
1901 
1902 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL32_MASK     (0x7U)
1903 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL32_SHIFT    (0U)
1904 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL32_WIDTH    (3U)
1905 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL32(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL32_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL32_MASK)
1906 
1907 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL33_MASK     (0x70U)
1908 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL33_SHIFT    (4U)
1909 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL33_WIDTH    (3U)
1910 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL33(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL33_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL33_MASK)
1911 
1912 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL34_MASK     (0x700U)
1913 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL34_SHIFT    (8U)
1914 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL34_WIDTH    (3U)
1915 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL34(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL34_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL34_MASK)
1916 
1917 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL35_MASK     (0x7000U)
1918 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL35_SHIFT    (12U)
1919 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL35_WIDTH    (3U)
1920 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL35(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL35_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL35_MASK)
1921 
1922 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL36_MASK     (0x70000U)
1923 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL36_SHIFT    (16U)
1924 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL36_WIDTH    (3U)
1925 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL36(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL36_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL36_MASK)
1926 
1927 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL37_MASK     (0x700000U)
1928 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL37_SHIFT    (20U)
1929 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL37_WIDTH    (3U)
1930 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL37(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL37_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL37_MASK)
1931 
1932 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL38_MASK     (0x7000000U)
1933 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL38_SHIFT    (24U)
1934 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL38_WIDTH    (3U)
1935 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL38(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL38_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL38_MASK)
1936 
1937 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL39_MASK     (0x70000000U)
1938 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL39_SHIFT    (28U)
1939 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL39_WIDTH    (3U)
1940 #define RTU_L_VFCCU_FHFLTRKC04_RKNSEL39(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC04_RKNSEL39_SHIFT)) & RTU_L_VFCCU_FHFLTRKC04_RKNSEL39_MASK)
1941 /*! @} */
1942 
1943 /*! @name FHFLTRKC05 - Fault Reaction Set Configuration */
1944 /*! @{ */
1945 
1946 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL40_MASK     (0x7U)
1947 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL40_SHIFT    (0U)
1948 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL40_WIDTH    (3U)
1949 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL40(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL40_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL40_MASK)
1950 
1951 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL41_MASK     (0x70U)
1952 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL41_SHIFT    (4U)
1953 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL41_WIDTH    (3U)
1954 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL41(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL41_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL41_MASK)
1955 
1956 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL42_MASK     (0x700U)
1957 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL42_SHIFT    (8U)
1958 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL42_WIDTH    (3U)
1959 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL42(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL42_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL42_MASK)
1960 
1961 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL43_MASK     (0x7000U)
1962 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL43_SHIFT    (12U)
1963 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL43_WIDTH    (3U)
1964 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL43(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL43_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL43_MASK)
1965 
1966 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL44_MASK     (0x70000U)
1967 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL44_SHIFT    (16U)
1968 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL44_WIDTH    (3U)
1969 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL44(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL44_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL44_MASK)
1970 
1971 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL45_MASK     (0x700000U)
1972 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL45_SHIFT    (20U)
1973 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL45_WIDTH    (3U)
1974 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL45(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL45_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL45_MASK)
1975 
1976 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL46_MASK     (0x7000000U)
1977 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL46_SHIFT    (24U)
1978 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL46_WIDTH    (3U)
1979 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL46(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL46_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL46_MASK)
1980 
1981 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL47_MASK     (0x70000000U)
1982 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL47_SHIFT    (28U)
1983 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL47_WIDTH    (3U)
1984 #define RTU_L_VFCCU_FHFLTRKC05_RKNSEL47(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC05_RKNSEL47_SHIFT)) & RTU_L_VFCCU_FHFLTRKC05_RKNSEL47_MASK)
1985 /*! @} */
1986 
1987 /*! @name FHFLTRKC06 - Fault Reaction Set Configuration */
1988 /*! @{ */
1989 
1990 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL48_MASK     (0x7U)
1991 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL48_SHIFT    (0U)
1992 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL48_WIDTH    (3U)
1993 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL48(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC06_RKNSEL48_SHIFT)) & RTU_L_VFCCU_FHFLTRKC06_RKNSEL48_MASK)
1994 
1995 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL49_MASK     (0x70U)
1996 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL49_SHIFT    (4U)
1997 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL49_WIDTH    (3U)
1998 #define RTU_L_VFCCU_FHFLTRKC06_RKNSEL49(x)       (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHFLTRKC06_RKNSEL49_SHIFT)) & RTU_L_VFCCU_FHFLTRKC06_RKNSEL49_MASK)
1999 /*! @} */
2000 
2001 /*! @name FHIMRKC0_00 - Immediate Reaction Configuration */
2002 /*! @{ */
2003 
2004 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN0_MASK      (0x1U)
2005 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN0_SHIFT     (0U)
2006 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN0_WIDTH     (1U)
2007 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_00_RKNEN0_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_00_RKNEN0_MASK)
2008 
2009 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN1_MASK      (0x2U)
2010 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN1_SHIFT     (1U)
2011 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN1_WIDTH     (1U)
2012 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_00_RKNEN1_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_00_RKNEN1_MASK)
2013 
2014 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN2_MASK      (0x4U)
2015 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN2_SHIFT     (2U)
2016 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN2_WIDTH     (1U)
2017 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_00_RKNEN2_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_00_RKNEN2_MASK)
2018 
2019 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN3_MASK      (0x8U)
2020 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN3_SHIFT     (3U)
2021 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN3_WIDTH     (1U)
2022 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_00_RKNEN3_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_00_RKNEN3_MASK)
2023 
2024 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN4_MASK      (0x10U)
2025 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN4_SHIFT     (4U)
2026 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN4_WIDTH     (1U)
2027 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_00_RKNEN4_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_00_RKNEN4_MASK)
2028 
2029 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN5_MASK      (0x20U)
2030 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN5_SHIFT     (5U)
2031 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN5_WIDTH     (1U)
2032 #define RTU_L_VFCCU_FHIMRKC0_00_RKNEN5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_00_RKNEN5_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_00_RKNEN5_MASK)
2033 /*! @} */
2034 
2035 /*! @name FHIMRKC0_10 - Immediate Reaction Configuration */
2036 /*! @{ */
2037 
2038 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN0_MASK      (0x1U)
2039 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN0_SHIFT     (0U)
2040 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN0_WIDTH     (1U)
2041 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_10_RKNEN0_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_10_RKNEN0_MASK)
2042 
2043 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN1_MASK      (0x2U)
2044 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN1_SHIFT     (1U)
2045 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN1_WIDTH     (1U)
2046 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_10_RKNEN1_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_10_RKNEN1_MASK)
2047 
2048 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN2_MASK      (0x4U)
2049 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN2_SHIFT     (2U)
2050 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN2_WIDTH     (1U)
2051 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_10_RKNEN2_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_10_RKNEN2_MASK)
2052 
2053 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN3_MASK      (0x8U)
2054 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN3_SHIFT     (3U)
2055 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN3_WIDTH     (1U)
2056 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_10_RKNEN3_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_10_RKNEN3_MASK)
2057 
2058 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN4_MASK      (0x10U)
2059 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN4_SHIFT     (4U)
2060 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN4_WIDTH     (1U)
2061 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_10_RKNEN4_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_10_RKNEN4_MASK)
2062 
2063 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN5_MASK      (0x20U)
2064 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN5_SHIFT     (5U)
2065 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN5_WIDTH     (1U)
2066 #define RTU_L_VFCCU_FHIMRKC0_10_RKNEN5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_10_RKNEN5_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_10_RKNEN5_MASK)
2067 /*! @} */
2068 
2069 /*! @name FHIMRKC0_20 - Immediate Reaction Configuration */
2070 /*! @{ */
2071 
2072 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN0_MASK      (0x1U)
2073 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN0_SHIFT     (0U)
2074 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN0_WIDTH     (1U)
2075 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_20_RKNEN0_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_20_RKNEN0_MASK)
2076 
2077 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN1_MASK      (0x2U)
2078 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN1_SHIFT     (1U)
2079 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN1_WIDTH     (1U)
2080 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_20_RKNEN1_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_20_RKNEN1_MASK)
2081 
2082 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN2_MASK      (0x4U)
2083 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN2_SHIFT     (2U)
2084 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN2_WIDTH     (1U)
2085 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_20_RKNEN2_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_20_RKNEN2_MASK)
2086 
2087 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN3_MASK      (0x8U)
2088 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN3_SHIFT     (3U)
2089 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN3_WIDTH     (1U)
2090 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_20_RKNEN3_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_20_RKNEN3_MASK)
2091 
2092 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN4_MASK      (0x10U)
2093 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN4_SHIFT     (4U)
2094 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN4_WIDTH     (1U)
2095 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_20_RKNEN4_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_20_RKNEN4_MASK)
2096 
2097 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN5_MASK      (0x20U)
2098 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN5_SHIFT     (5U)
2099 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN5_WIDTH     (1U)
2100 #define RTU_L_VFCCU_FHIMRKC0_20_RKNEN5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_20_RKNEN5_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_20_RKNEN5_MASK)
2101 /*! @} */
2102 
2103 /*! @name FHIMRKC0_30 - Immediate Reaction Configuration */
2104 /*! @{ */
2105 
2106 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN0_MASK      (0x1U)
2107 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN0_SHIFT     (0U)
2108 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN0_WIDTH     (1U)
2109 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_30_RKNEN0_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_30_RKNEN0_MASK)
2110 
2111 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN1_MASK      (0x2U)
2112 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN1_SHIFT     (1U)
2113 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN1_WIDTH     (1U)
2114 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_30_RKNEN1_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_30_RKNEN1_MASK)
2115 
2116 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN2_MASK      (0x4U)
2117 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN2_SHIFT     (2U)
2118 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN2_WIDTH     (1U)
2119 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_30_RKNEN2_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_30_RKNEN2_MASK)
2120 
2121 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN3_MASK      (0x8U)
2122 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN3_SHIFT     (3U)
2123 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN3_WIDTH     (1U)
2124 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_30_RKNEN3_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_30_RKNEN3_MASK)
2125 
2126 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN4_MASK      (0x10U)
2127 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN4_SHIFT     (4U)
2128 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN4_WIDTH     (1U)
2129 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_30_RKNEN4_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_30_RKNEN4_MASK)
2130 
2131 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN5_MASK      (0x20U)
2132 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN5_SHIFT     (5U)
2133 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN5_WIDTH     (1U)
2134 #define RTU_L_VFCCU_FHIMRKC0_30_RKNEN5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_30_RKNEN5_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_30_RKNEN5_MASK)
2135 /*! @} */
2136 
2137 /*! @name FHIMRKC0_40 - Immediate Reaction Configuration */
2138 /*! @{ */
2139 
2140 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN0_MASK      (0x1U)
2141 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN0_SHIFT     (0U)
2142 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN0_WIDTH     (1U)
2143 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_40_RKNEN0_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_40_RKNEN0_MASK)
2144 
2145 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN1_MASK      (0x2U)
2146 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN1_SHIFT     (1U)
2147 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN1_WIDTH     (1U)
2148 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_40_RKNEN1_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_40_RKNEN1_MASK)
2149 
2150 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN2_MASK      (0x4U)
2151 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN2_SHIFT     (2U)
2152 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN2_WIDTH     (1U)
2153 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_40_RKNEN2_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_40_RKNEN2_MASK)
2154 
2155 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN3_MASK      (0x8U)
2156 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN3_SHIFT     (3U)
2157 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN3_WIDTH     (1U)
2158 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_40_RKNEN3_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_40_RKNEN3_MASK)
2159 
2160 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN4_MASK      (0x10U)
2161 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN4_SHIFT     (4U)
2162 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN4_WIDTH     (1U)
2163 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_40_RKNEN4_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_40_RKNEN4_MASK)
2164 
2165 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN5_MASK      (0x20U)
2166 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN5_SHIFT     (5U)
2167 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN5_WIDTH     (1U)
2168 #define RTU_L_VFCCU_FHIMRKC0_40_RKNEN5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_40_RKNEN5_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_40_RKNEN5_MASK)
2169 /*! @} */
2170 
2171 /*! @name FHIMRKC0_50 - Immediate Reaction Configuration */
2172 /*! @{ */
2173 
2174 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN0_MASK      (0x1U)
2175 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN0_SHIFT     (0U)
2176 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN0_WIDTH     (1U)
2177 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_50_RKNEN0_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_50_RKNEN0_MASK)
2178 
2179 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN1_MASK      (0x2U)
2180 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN1_SHIFT     (1U)
2181 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN1_WIDTH     (1U)
2182 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_50_RKNEN1_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_50_RKNEN1_MASK)
2183 
2184 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN2_MASK      (0x4U)
2185 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN2_SHIFT     (2U)
2186 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN2_WIDTH     (1U)
2187 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_50_RKNEN2_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_50_RKNEN2_MASK)
2188 
2189 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN3_MASK      (0x8U)
2190 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN3_SHIFT     (3U)
2191 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN3_WIDTH     (1U)
2192 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_50_RKNEN3_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_50_RKNEN3_MASK)
2193 
2194 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN4_MASK      (0x10U)
2195 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN4_SHIFT     (4U)
2196 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN4_WIDTH     (1U)
2197 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN4(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_50_RKNEN4_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_50_RKNEN4_MASK)
2198 
2199 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN5_MASK      (0x20U)
2200 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN5_SHIFT     (5U)
2201 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN5_WIDTH     (1U)
2202 #define RTU_L_VFCCU_FHIMRKC0_50_RKNEN5(x)        (((uint32_t)(((uint32_t)(x)) << RTU_L_VFCCU_FHIMRKC0_50_RKNEN5_SHIFT)) & RTU_L_VFCCU_FHIMRKC0_50_RKNEN5_MASK)
2203 /*! @} */
2204 
2205 /*!
2206  * @}
2207  */ /* end of group RTU_L_VFCCU_Register_Masks */
2208 
2209 /*!
2210  * @}
2211  */ /* end of group RTU_L_VFCCU_Peripheral_Access_Layer */
2212 
2213 #endif  /* #if !defined(S32Z2_RTU_L_VFCCU_H_) */
2214