1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_QUEUE_MANAGER3.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_QUEUE_MANAGER3 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_QUEUE_MANAGER3_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_QUEUE_MANAGER3_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- QUEUE_MANAGER3 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup QUEUE_MANAGER3_Peripheral_Access_Layer QUEUE_MANAGER3 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** QUEUE_MANAGER3 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t Q3_EN_DEPTH; /**< QX EN DEPTH, offset: 0x0 */ 74 __IO uint32_t Q3_FIRST_ADDR; /**< Q3 FIRST ADDR, offset: 0x4 */ 75 __IO uint32_t Q3_BASE_PTR; /**< Q3 BASE PTR, offset: 0x8 */ 76 __IO uint32_t Q3_CHNK_SIZE; /**< Q3 CHNK SIZE, offset: 0xC */ 77 __IO uint32_t Q3_DSC_EN_INC0; /**< Q3 DSC EN INC0, offset: 0x10 */ 78 __I uint32_t Q3_STATUS; /**< Q3 STATUS, offset: 0x14 */ 79 __I uint32_t Q3_RPTR_INT; /**< Q3 RPTR INT, offset: 0x18 */ 80 __I uint32_t Q3_DSC_CFG; /**< Q3 DSC CFG, offset: 0x1C */ 81 __I uint32_t Q3_DSC_SRCP; /**< Q3 DSC SRCP, offset: 0x20 */ 82 __I uint32_t Q3_DSC_DSTP; /**< Q3 DSC DSTP, offset: 0x24 */ 83 __I uint32_t Q3_DSC_DMASZ; /**< Q3 DSC DMASZ, offset: 0x28 */ 84 __I uint32_t Q3_DSC_SRC; /**< Q3 DSC SRC, offset: 0x2C */ 85 __I uint32_t Q3_DSC_LINE; /**< Q3 DSC LINE, offset: 0x30 */ 86 __I uint32_t Q3_DSC_DST; /**< Q3 DSC DST, offset: 0x34 */ 87 __I uint32_t Q3_DSC_HGHT; /**< Q3 DSC HGHT, offset: 0x38 */ 88 uint8_t RESERVED_0[4]; 89 __IO uint32_t Q3_DSC_EN_INC1; /**< Q3 DSC EN INC1, offset: 0x40 */ 90 __I uint32_t Q3_EN_CNT; /**< Q3 EN CNT, offset: 0x44 */ 91 } QUEUE_MANAGER3_Type, *QUEUE_MANAGER3_MemMapPtr; 92 93 /** Number of instances of the QUEUE_MANAGER3 module. */ 94 #define QUEUE_MANAGER3_INSTANCE_COUNT (1u) 95 96 /* QUEUE_MANAGER3 - Peripheral instance base addresses */ 97 /** Peripheral CEVA_SPF2__QUEUE_MANAGER3 base address */ 98 #define IP_CEVA_SPF2__QUEUE_MANAGER3_BASE (0x24401380u) 99 /** Peripheral CEVA_SPF2__QUEUE_MANAGER3 base pointer */ 100 #define IP_CEVA_SPF2__QUEUE_MANAGER3 ((QUEUE_MANAGER3_Type *)IP_CEVA_SPF2__QUEUE_MANAGER3_BASE) 101 /** Array initializer of QUEUE_MANAGER3 peripheral base addresses */ 102 #define IP_QUEUE_MANAGER3_BASE_ADDRS { IP_CEVA_SPF2__QUEUE_MANAGER3_BASE } 103 /** Array initializer of QUEUE_MANAGER3 peripheral base pointers */ 104 #define IP_QUEUE_MANAGER3_BASE_PTRS { IP_CEVA_SPF2__QUEUE_MANAGER3 } 105 106 /* ---------------------------------------------------------------------------- 107 -- QUEUE_MANAGER3 Register Masks 108 ---------------------------------------------------------------------------- */ 109 110 /*! 111 * @addtogroup QUEUE_MANAGER3_Register_Masks QUEUE_MANAGER3 Register Masks 112 * @{ 113 */ 114 115 /*! @name Q3_EN_DEPTH - QX EN DEPTH */ 116 /*! @{ */ 117 118 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_DEPTH_MASK (0x1FFFU) 119 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_DEPTH_SHIFT (0U) 120 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_DEPTH_WIDTH (13U) 121 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_DEPTH_QX_DEPTH_SHIFT)) & QUEUE_MANAGER3_Q3_EN_DEPTH_QX_DEPTH_MASK) 122 123 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_MASK (0xF0000U) 124 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SHIFT (16U) 125 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_WIDTH (4U) 126 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SHIFT)) & QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_MASK) 127 128 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SEL_MASK (0x100000U) 129 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SEL_SHIFT (20U) 130 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SEL_WIDTH (1U) 131 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SEL(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SEL_SHIFT)) & QUEUE_MANAGER3_Q3_EN_DEPTH_QX_PRI_ABS_SEL_MASK) 132 133 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_AUTO_MASK (0x200000U) 134 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_AUTO_SHIFT (21U) 135 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_AUTO_WIDTH (1U) 136 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_AUTO(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_DEPTH_QX_AUTO_SHIFT)) & QUEUE_MANAGER3_Q3_EN_DEPTH_QX_AUTO_MASK) 137 138 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CEX_PAUSE_MASK (0x400000U) 139 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CEX_PAUSE_SHIFT (22U) 140 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CEX_PAUSE_WIDTH (1U) 141 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CEX_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CEX_PAUSE_SHIFT)) & QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CEX_PAUSE_MASK) 142 143 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CONT_FRAME_MASK (0x40000000U) 144 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CONT_FRAME_SHIFT (30U) 145 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CONT_FRAME_WIDTH (1U) 146 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CONT_FRAME(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CONT_FRAME_SHIFT)) & QUEUE_MANAGER3_Q3_EN_DEPTH_QX_CONT_FRAME_MASK) 147 148 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_EN_MASK (0x80000000U) 149 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_EN_SHIFT (31U) 150 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_EN_WIDTH (1U) 151 #define QUEUE_MANAGER3_Q3_EN_DEPTH_QX_EN(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_DEPTH_QX_EN_SHIFT)) & QUEUE_MANAGER3_Q3_EN_DEPTH_QX_EN_MASK) 152 /*! @} */ 153 154 /*! @name Q3_FIRST_ADDR - Q3 FIRST ADDR */ 155 /*! @{ */ 156 157 #define QUEUE_MANAGER3_Q3_FIRST_ADDR_QX_FIRST_ADDR_MASK (0xFFFFFFFFU) 158 #define QUEUE_MANAGER3_Q3_FIRST_ADDR_QX_FIRST_ADDR_SHIFT (0U) 159 #define QUEUE_MANAGER3_Q3_FIRST_ADDR_QX_FIRST_ADDR_WIDTH (32U) 160 #define QUEUE_MANAGER3_Q3_FIRST_ADDR_QX_FIRST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_FIRST_ADDR_QX_FIRST_ADDR_SHIFT)) & QUEUE_MANAGER3_Q3_FIRST_ADDR_QX_FIRST_ADDR_MASK) 161 /*! @} */ 162 163 /*! @name Q3_BASE_PTR - Q3 BASE PTR */ 164 /*! @{ */ 165 166 #define QUEUE_MANAGER3_Q3_BASE_PTR_QX_BASE_PTR_MASK (0xFFFFFFFFU) 167 #define QUEUE_MANAGER3_Q3_BASE_PTR_QX_BASE_PTR_SHIFT (0U) 168 #define QUEUE_MANAGER3_Q3_BASE_PTR_QX_BASE_PTR_WIDTH (32U) 169 #define QUEUE_MANAGER3_Q3_BASE_PTR_QX_BASE_PTR(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_BASE_PTR_QX_BASE_PTR_SHIFT)) & QUEUE_MANAGER3_Q3_BASE_PTR_QX_BASE_PTR_MASK) 170 /*! @} */ 171 172 /*! @name Q3_CHNK_SIZE - Q3 CHNK SIZE */ 173 /*! @{ */ 174 175 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_SIZE_MASK (0x3FFFU) 176 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_SIZE_SHIFT (0U) 177 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_SIZE_WIDTH (14U) 178 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_SIZE_SHIFT)) & QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_SIZE_MASK) 179 180 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_LINES_MASK (0xFFFF0000U) 181 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_LINES_SHIFT (16U) 182 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_LINES_WIDTH (16U) 183 #define QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_LINES(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_LINES_SHIFT)) & QUEUE_MANAGER3_Q3_CHNK_SIZE_QX_CHNK_LINES_MASK) 184 /*! @} */ 185 186 /*! @name Q3_DSC_EN_INC0 - Q3 DSC EN INC0 */ 187 /*! @{ */ 188 189 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_INC_VAL0_MASK (0x7FFU) 190 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_INC_VAL0_SHIFT (0U) 191 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_INC_VAL0_WIDTH (11U) 192 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_INC_VAL0(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_INC_VAL0_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_INC_VAL0_MASK) 193 194 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_EN0_MASK (0x10000U) 195 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_EN0_SHIFT (16U) 196 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_EN0_WIDTH (1U) 197 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_EN0(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_EN0_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_EN0_MASK) 198 199 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_CNT_CFG_0_MASK (0x20000U) 200 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_CNT_CFG_0_SHIFT (17U) 201 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_CNT_CFG_0_WIDTH (1U) 202 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_CNT_CFG_0(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_CNT_CFG_0_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_DSC_CNT_CFG_0_MASK) 203 204 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_CNT_DIS0_MASK (0x80000000U) 205 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_CNT_DIS0_SHIFT (31U) 206 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_CNT_DIS0_WIDTH (1U) 207 #define QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_CNT_DIS0(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_CNT_DIS0_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC0_QX_EN_CNT_DIS0_MASK) 208 /*! @} */ 209 210 /*! @name Q3_STATUS - Q3 STATUS */ 211 /*! @{ */ 212 213 #define QUEUE_MANAGER3_Q3_STATUS_QX_WD_WAIT_MASK (0x40000000U) 214 #define QUEUE_MANAGER3_Q3_STATUS_QX_WD_WAIT_SHIFT (30U) 215 #define QUEUE_MANAGER3_Q3_STATUS_QX_WD_WAIT_WIDTH (1U) 216 #define QUEUE_MANAGER3_Q3_STATUS_QX_WD_WAIT(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_STATUS_QX_WD_WAIT_SHIFT)) & QUEUE_MANAGER3_Q3_STATUS_QX_WD_WAIT_MASK) 217 218 #define QUEUE_MANAGER3_Q3_STATUS_QX_STATUS_MASK (0x80000000U) 219 #define QUEUE_MANAGER3_Q3_STATUS_QX_STATUS_SHIFT (31U) 220 #define QUEUE_MANAGER3_Q3_STATUS_QX_STATUS_WIDTH (1U) 221 #define QUEUE_MANAGER3_Q3_STATUS_QX_STATUS(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_STATUS_QX_STATUS_SHIFT)) & QUEUE_MANAGER3_Q3_STATUS_QX_STATUS_MASK) 222 /*! @} */ 223 224 /*! @name Q3_RPTR_INT - Q3 RPTR INT */ 225 /*! @{ */ 226 227 #define QUEUE_MANAGER3_Q3_RPTR_INT_QX_RPTR_INT_MASK (0x3FFFFU) 228 #define QUEUE_MANAGER3_Q3_RPTR_INT_QX_RPTR_INT_SHIFT (0U) 229 #define QUEUE_MANAGER3_Q3_RPTR_INT_QX_RPTR_INT_WIDTH (18U) 230 #define QUEUE_MANAGER3_Q3_RPTR_INT_QX_RPTR_INT(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_RPTR_INT_QX_RPTR_INT_SHIFT)) & QUEUE_MANAGER3_Q3_RPTR_INT_QX_RPTR_INT_MASK) 231 /*! @} */ 232 233 /*! @name Q3_DSC_CFG - Q3 DSC CFG */ 234 /*! @{ */ 235 236 #define QUEUE_MANAGER3_Q3_DSC_CFG_QX_DSC_CFG_MASK (0xFFFFFFFFU) 237 #define QUEUE_MANAGER3_Q3_DSC_CFG_QX_DSC_CFG_SHIFT (0U) 238 #define QUEUE_MANAGER3_Q3_DSC_CFG_QX_DSC_CFG_WIDTH (32U) 239 #define QUEUE_MANAGER3_Q3_DSC_CFG_QX_DSC_CFG(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_CFG_QX_DSC_CFG_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_CFG_QX_DSC_CFG_MASK) 240 /*! @} */ 241 242 /*! @name Q3_DSC_SRCP - Q3 DSC SRCP */ 243 /*! @{ */ 244 245 #define QUEUE_MANAGER3_Q3_DSC_SRCP_QX_DSC_SRCP_MASK (0xFFFFFFFFU) 246 #define QUEUE_MANAGER3_Q3_DSC_SRCP_QX_DSC_SRCP_SHIFT (0U) 247 #define QUEUE_MANAGER3_Q3_DSC_SRCP_QX_DSC_SRCP_WIDTH (32U) 248 #define QUEUE_MANAGER3_Q3_DSC_SRCP_QX_DSC_SRCP(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_SRCP_QX_DSC_SRCP_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_SRCP_QX_DSC_SRCP_MASK) 249 /*! @} */ 250 251 /*! @name Q3_DSC_DSTP - Q3 DSC DSTP */ 252 /*! @{ */ 253 254 #define QUEUE_MANAGER3_Q3_DSC_DSTP_QX_DSC_DSTP_MASK (0xFFFFFFFFU) 255 #define QUEUE_MANAGER3_Q3_DSC_DSTP_QX_DSC_DSTP_SHIFT (0U) 256 #define QUEUE_MANAGER3_Q3_DSC_DSTP_QX_DSC_DSTP_WIDTH (32U) 257 #define QUEUE_MANAGER3_Q3_DSC_DSTP_QX_DSC_DSTP(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_DSTP_QX_DSC_DSTP_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_DSTP_QX_DSC_DSTP_MASK) 258 /*! @} */ 259 260 /*! @name Q3_DSC_DMASZ - Q3 DSC DMASZ */ 261 /*! @{ */ 262 263 #define QUEUE_MANAGER3_Q3_DSC_DMASZ_QX_DSC_DMASZ_MASK (0xFFFFFFFFU) 264 #define QUEUE_MANAGER3_Q3_DSC_DMASZ_QX_DSC_DMASZ_SHIFT (0U) 265 #define QUEUE_MANAGER3_Q3_DSC_DMASZ_QX_DSC_DMASZ_WIDTH (32U) 266 #define QUEUE_MANAGER3_Q3_DSC_DMASZ_QX_DSC_DMASZ(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_DMASZ_QX_DSC_DMASZ_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_DMASZ_QX_DSC_DMASZ_MASK) 267 /*! @} */ 268 269 /*! @name Q3_DSC_SRC - Q3 DSC SRC */ 270 /*! @{ */ 271 272 #define QUEUE_MANAGER3_Q3_DSC_SRC_QX_DSC_SRC_MASK (0xFFFFFFFFU) 273 #define QUEUE_MANAGER3_Q3_DSC_SRC_QX_DSC_SRC_SHIFT (0U) 274 #define QUEUE_MANAGER3_Q3_DSC_SRC_QX_DSC_SRC_WIDTH (32U) 275 #define QUEUE_MANAGER3_Q3_DSC_SRC_QX_DSC_SRC(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_SRC_QX_DSC_SRC_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_SRC_QX_DSC_SRC_MASK) 276 /*! @} */ 277 278 /*! @name Q3_DSC_LINE - Q3 DSC LINE */ 279 /*! @{ */ 280 281 #define QUEUE_MANAGER3_Q3_DSC_LINE_QX_DSC_LINE_MASK (0xFFFFFFFFU) 282 #define QUEUE_MANAGER3_Q3_DSC_LINE_QX_DSC_LINE_SHIFT (0U) 283 #define QUEUE_MANAGER3_Q3_DSC_LINE_QX_DSC_LINE_WIDTH (32U) 284 #define QUEUE_MANAGER3_Q3_DSC_LINE_QX_DSC_LINE(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_LINE_QX_DSC_LINE_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_LINE_QX_DSC_LINE_MASK) 285 /*! @} */ 286 287 /*! @name Q3_DSC_DST - Q3 DSC DST */ 288 /*! @{ */ 289 290 #define QUEUE_MANAGER3_Q3_DSC_DST_QX_DSC_DST_MASK (0xFFFFFFFFU) 291 #define QUEUE_MANAGER3_Q3_DSC_DST_QX_DSC_DST_SHIFT (0U) 292 #define QUEUE_MANAGER3_Q3_DSC_DST_QX_DSC_DST_WIDTH (32U) 293 #define QUEUE_MANAGER3_Q3_DSC_DST_QX_DSC_DST(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_DST_QX_DSC_DST_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_DST_QX_DSC_DST_MASK) 294 /*! @} */ 295 296 /*! @name Q3_DSC_HGHT - Q3 DSC HGHT */ 297 /*! @{ */ 298 299 #define QUEUE_MANAGER3_Q3_DSC_HGHT_QX_DSC_HGHT_MASK (0xFFFFFFFFU) 300 #define QUEUE_MANAGER3_Q3_DSC_HGHT_QX_DSC_HGHT_SHIFT (0U) 301 #define QUEUE_MANAGER3_Q3_DSC_HGHT_QX_DSC_HGHT_WIDTH (32U) 302 #define QUEUE_MANAGER3_Q3_DSC_HGHT_QX_DSC_HGHT(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_HGHT_QX_DSC_HGHT_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_HGHT_QX_DSC_HGHT_MASK) 303 /*! @} */ 304 305 /*! @name Q3_DSC_EN_INC1 - Q3 DSC EN INC1 */ 306 /*! @{ */ 307 308 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_INC_VAL1_MASK (0x7FFU) 309 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_INC_VAL1_SHIFT (0U) 310 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_INC_VAL1_WIDTH (11U) 311 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_INC_VAL1(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_INC_VAL1_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_INC_VAL1_MASK) 312 313 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_EN1_MASK (0x10000U) 314 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_EN1_SHIFT (16U) 315 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_EN1_WIDTH (1U) 316 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_EN1(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_EN1_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_EN1_MASK) 317 318 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_CNT_CFG_1_MASK (0x20000U) 319 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_CNT_CFG_1_SHIFT (17U) 320 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_CNT_CFG_1_WIDTH (1U) 321 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_CNT_CFG_1(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_CNT_CFG_1_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_DSC_CNT_CFG_1_MASK) 322 323 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_CNT_DIS1_MASK (0x80000000U) 324 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_CNT_DIS1_SHIFT (31U) 325 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_CNT_DIS1_WIDTH (1U) 326 #define QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_CNT_DIS1(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_CNT_DIS1_SHIFT)) & QUEUE_MANAGER3_Q3_DSC_EN_INC1_QX_EN_CNT_DIS1_MASK) 327 /*! @} */ 328 329 /*! @name Q3_EN_CNT - Q3 EN CNT */ 330 /*! @{ */ 331 332 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT0_MASK (0x3FFFU) 333 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT0_SHIFT (0U) 334 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT0_WIDTH (14U) 335 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT0(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT0_SHIFT)) & QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT0_MASK) 336 337 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT1_MASK (0x3FFF0000U) 338 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT1_SHIFT (16U) 339 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT1_WIDTH (14U) 340 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT1(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT1_SHIFT)) & QUEUE_MANAGER3_Q3_EN_CNT_QX_EN_CNT1_MASK) 341 342 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_WD_WAIT_MASK (0x40000000U) 343 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_WD_WAIT_SHIFT (30U) 344 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_WD_WAIT_WIDTH (1U) 345 #define QUEUE_MANAGER3_Q3_EN_CNT_QX_WD_WAIT(x) (((uint32_t)(((uint32_t)(x)) << QUEUE_MANAGER3_Q3_EN_CNT_QX_WD_WAIT_SHIFT)) & QUEUE_MANAGER3_Q3_EN_CNT_QX_WD_WAIT_MASK) 346 /*! @} */ 347 348 /*! 349 * @} 350 */ /* end of group QUEUE_MANAGER3_Register_Masks */ 351 352 /*! 353 * @} 354 */ /* end of group QUEUE_MANAGER3_Peripheral_Access_Layer */ 355 356 #endif /* #if !defined(S32Z2_QUEUE_MANAGER3_H_) */ 357
