1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_QuadSPI_ARDB.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_QuadSPI_ARDB 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_QuadSPI_ARDB_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_QuadSPI_ARDB_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- QuadSPI_ARDB Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup QuadSPI_ARDB_Peripheral_Access_Layer QuadSPI_ARDB Peripheral Access Layer 68 * @{ 69 */ 70 71 /** QuadSPI_ARDB - Size of Registers Arrays */ 72 #define QuadSPI_ARDB_ARDB_COUNT 128u 73 74 /** QuadSPI_ARDB - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t ARDB[QuadSPI_ARDB_ARDB_COUNT]; /**< AHB RX Data Buffer Register, array offset: 0x0, array step: 0x4 */ 77 } QuadSPI_ARDB_Type, *QuadSPI_ARDB_MemMapPtr; 78 79 /** Number of instances of the QuadSPI_ARDB module. */ 80 #define QuadSPI_ARDB_INSTANCE_COUNT (2u) 81 82 /* QuadSPI_ARDB - Peripheral instance base addresses */ 83 /** Peripheral QUADSPI_0_ARDB base address */ 84 #define IP_QUADSPI_0_ARDB_BASE (0x70000000u) 85 /** Peripheral QUADSPI_0_ARDB base pointer */ 86 #define IP_QUADSPI_0_ARDB ((QuadSPI_ARDB_Type *)IP_QUADSPI_0_ARDB_BASE) 87 /** Peripheral QUADSPI_1_ARDB base address */ 88 #define IP_QUADSPI_1_ARDB_BASE (0x71000000u) 89 /** Peripheral QUADSPI_1_ARDB base pointer */ 90 #define IP_QUADSPI_1_ARDB ((QuadSPI_ARDB_Type *)IP_QUADSPI_1_ARDB_BASE) 91 /** Array initializer of QuadSPI_ARDB peripheral base addresses */ 92 #define IP_QuadSPI_ARDB_BASE_ADDRS { IP_QUADSPI_0_ARDB_BASE, IP_QUADSPI_1_ARDB_BASE } 93 /** Array initializer of QuadSPI_ARDB peripheral base pointers */ 94 #define IP_QuadSPI_ARDB_BASE_PTRS { IP_QUADSPI_0_ARDB, IP_QUADSPI_1_ARDB } 95 96 /* ---------------------------------------------------------------------------- 97 -- QuadSPI_ARDB Register Masks 98 ---------------------------------------------------------------------------- */ 99 100 /*! 101 * @addtogroup QuadSPI_ARDB_Register_Masks QuadSPI_ARDB Register Masks 102 * @{ 103 */ 104 105 /*! @name ARDB - AHB RX Data Buffer Register */ 106 /*! @{ */ 107 108 #define QuadSPI_ARDB_ARDB_ARXD_MASK (0xFFFFFFFFU) 109 #define QuadSPI_ARDB_ARDB_ARXD_SHIFT (0U) 110 #define QuadSPI_ARDB_ARDB_ARXD_WIDTH (32U) 111 #define QuadSPI_ARDB_ARDB_ARXD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_ARDB_ARDB_ARXD_SHIFT)) & QuadSPI_ARDB_ARDB_ARXD_MASK) 112 /*! @} */ 113 114 /*! 115 * @} 116 */ /* end of group QuadSPI_ARDB_Register_Masks */ 117 118 /*! 119 * @} 120 */ /* end of group QuadSPI_ARDB_Peripheral_Access_Layer */ 121 122 #endif /* #if !defined(S32Z2_QuadSPI_ARDB_H_) */ 123
