1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_PSI5.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_PSI5 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_PSI5_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_PSI5_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PSI5 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PSI5_Peripheral_Access_Layer PSI5 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PSI5 - Size of Registers Arrays */ 72 #define PSI5_CHANNEL_CH_PMR_COUNT 32u 73 #define PSI5_CHANNEL_CH_SFR_COUNT 6u 74 #define PSI5_CHANNEL_CH_SFCR_COUNT 6u 75 #define PSI5_CHANNEL_COUNT 4u 76 77 /** PSI5 - Register Layout Typedef */ 78 typedef struct { 79 uint8_t RESERVED_0[2]; 80 __IO uint16_t GCR; /**< Global Control Register, offset: 0x2 */ 81 uint8_t RESERVED_1[4]; 82 struct PSI5_CHANNEL { /* offset: 0x8, array step: 0x1C0 */ 83 __IO uint32_t CH_PCCR; /**< PSI5 Channel Control Register, array offset: 0x8, array step: 0x1C0 */ 84 __IO uint32_t CH_DCR; /**< DMA Control Register, array offset: 0xC, array step: 0x1C0 */ 85 __IO uint32_t CH_DSR; /**< DMA Status Register, array offset: 0x10, array step: 0x1C0 */ 86 __IO uint32_t CH_GICR; /**< General Interrupt Control Register, array offset: 0x14, array step: 0x1C0 */ 87 __IO uint32_t CH_NDICR; /**< New Data Interrupt Control Register, array offset: 0x18, array step: 0x1C0 */ 88 __IO uint32_t CH_OWICR; /**< Overwrite Interrupt Control Register, array offset: 0x1C, array step: 0x1C0 */ 89 __IO uint32_t CH_EICR; /**< Error Interrupt Control Register, array offset: 0x20, array step: 0x1C0 */ 90 __IO uint32_t CH_GISR; /**< General Interrupt Status Register, array offset: 0x24, array step: 0x1C0 */ 91 __I uint32_t CH_DPMR; /**< DMA PSI5 Message Register, array offset: 0x28, array step: 0x1C0 */ 92 __I uint32_t CH_DSFR; /**< DMA SMC Frame Register, array offset: 0x2C, array step: 0x1C0 */ 93 __I uint32_t CH_DDSR; /**< DMA Diagnostic Status Register, array offset: 0x30, array step: 0x1C0 */ 94 __I uint32_t CH_PMRRL; /**< PSI5 Message Receive Register Low, array offset: 0x34, array step: 0x1C0 */ 95 __I uint32_t CH_PMRRH; /**< PSI5 Message Receive Register High, array offset: 0x38, array step: 0x1C0 */ 96 struct PSI5_CHANNEL_CH_PMR { /* offset: 0x3C, array step: index*0x1C0, index2*0x8 */ 97 __IO uint32_t CH_PMRL; /**< PSI5 Message Register Low i, array offset: 0x3C, array step: index*0x1C0, index2*0x8 */ 98 __IO uint32_t CH_PMRH; /**< PSI5 Message Register High i, array offset: 0x40, array step: index*0x1C0, index2*0x8 */ 99 } CH_PMR[PSI5_CHANNEL_CH_PMR_COUNT]; 100 __IO uint32_t CH_SFR[PSI5_CHANNEL_CH_SFR_COUNT]; /**< SMC Frame Register n, array offset: 0x13C, array step: index*0x1C0, index2*0x4 */ 101 __IO uint32_t CH_NDSR; /**< New Data Status Register, array offset: 0x154, array step: 0x1C0 */ 102 __IO uint32_t CH_OWSR; /**< Overwrite Status Register, array offset: 0x158, array step: 0x1C0 */ 103 __IO uint32_t CH_EISR; /**< Error Indication Status Register, array offset: 0x15C, array step: 0x1C0 */ 104 __O uint32_t CH_SNDSR; /**< Set New Data Status Register, array offset: 0x160, array step: 0x1C0 */ 105 __O uint32_t CH_SOWSR; /**< Set Overwrite Status Register, array offset: 0x164, array step: 0x1C0 */ 106 __O uint32_t CH_SEISR; /**< Set Error Status Register, array offset: 0x168, array step: 0x1C0 */ 107 __O uint32_t CH_SSESR; /**< Set SMC Error Status Register, array offset: 0x16C, array step: 0x1C0 */ 108 __I uint32_t CH_STSRR; /**< Sync Time Stamp Read Register, array offset: 0x170, array step: 0x1C0 */ 109 __I uint32_t CH_DTSRR; /**< Data Time Stamp Read Register, array offset: 0x174, array step: 0x1C0 */ 110 __IO uint32_t CH_SFCR[PSI5_CHANNEL_CH_SFCR_COUNT]; /**< Slot n Frame Configuration Register, array offset: 0x178, array step: index*0x1C0, index2*0x4 */ 111 __IO uint16_t CH_S2SBR; /**< Slot 2 Start Boundary Register, array offset: 0x190, array step: 0x1C0 */ 112 __IO uint16_t CH_S1SBR; /**< Slot 1 Start Boundary Register, array offset: 0x192, array step: 0x1C0 */ 113 __IO uint16_t CH_S4SBR; /**< Slot 4 Start Boundary Register, array offset: 0x194, array step: 0x1C0 */ 114 __IO uint16_t CH_S3SBR; /**< Slot 3 Start Boundary Register, array offset: 0x196, array step: 0x1C0 */ 115 __IO uint16_t CH_S6SBR; /**< Slot 6 Start Boundary Register, array offset: 0x198, array step: 0x1C0 */ 116 __IO uint16_t CH_S5SBR; /**< Slot 5 Start Boundary Register, array offset: 0x19A, array step: 0x1C0 */ 117 __IO uint32_t CH_SNEBR; /**< Slot n End Boundary Register, array offset: 0x19C, array step: 0x1C0 */ 118 __IO uint16_t CH_MDDIS_OFF; /**< Manchestor Decoder Disable Offset, array offset: 0x1A0, array step: 0x1C0 */ 119 __IO uint16_t CH_DOBCR; /**< Data Output Block Configuration Register, array offset: 0x1A2, array step: 0x1C0 */ 120 __IO uint16_t CH_PW1D; /**< Pulse Width for Data Bit Value 1, array offset: 0x1A4, array step: 0x1C0 */ 121 __IO uint16_t CH_PW0D; /**< Pulse Width for Data Bit Value 0, array offset: 0x1A6, array step: 0x1C0 */ 122 __IO uint16_t CH_CIPR; /**< Counter Initialize Pulse Register, array offset: 0x1A8, array step: 0x1C0 */ 123 __IO uint16_t CH_CTPR; /**< Counter Target Pulse Register, array offset: 0x1AA, array step: 0x1C0 */ 124 __IO uint32_t CH_DPRL; /**< Data Preparation Register Low, array offset: 0x1AC, array step: 0x1C0 */ 125 uint32_t CH_DPRH; /**< Data Preparation Register High, array offset: 0x1B0, array step: 0x1C0 */ 126 __IO uint32_t CH_DBRL; /**< Data Buffer Register Low, array offset: 0x1B4, array step: 0x1C0 */ 127 __IO uint32_t CH_DBRH; /**< Data Buffer Register High, array offset: 0x1B8, array step: 0x1C0 */ 128 __IO uint32_t CH_DSRL; /**< Data Shift Register Low, array offset: 0x1BC, array step: 0x1C0 */ 129 __IO uint32_t CH_DSRH; /**< Data Shift Register High, array offset: 0x1C0, array step: 0x1C0 */ 130 uint8_t RESERVED_0[4]; 131 } CHANNEL[PSI5_CHANNEL_COUNT]; 132 } PSI5_Type, *PSI5_MemMapPtr; 133 134 /** Number of instances of the PSI5 module. */ 135 #define PSI5_INSTANCE_COUNT (2u) 136 137 /* PSI5 - Peripheral instance base addresses */ 138 /** Peripheral PSI5_0 base address */ 139 #define IP_PSI5_0_BASE (0x401E0000u) 140 /** Peripheral PSI5_0 base pointer */ 141 #define IP_PSI5_0 ((PSI5_Type *)IP_PSI5_0_BASE) 142 /** Peripheral PSI5_1 base address */ 143 #define IP_PSI5_1_BASE (0x421E0000u) 144 /** Peripheral PSI5_1 base pointer */ 145 #define IP_PSI5_1 ((PSI5_Type *)IP_PSI5_1_BASE) 146 /** Array initializer of PSI5 peripheral base addresses */ 147 #define IP_PSI5_BASE_ADDRS { IP_PSI5_0_BASE, IP_PSI5_1_BASE } 148 /** Array initializer of PSI5 peripheral base pointers */ 149 #define IP_PSI5_BASE_PTRS { IP_PSI5_0, IP_PSI5_1 } 150 151 /* ---------------------------------------------------------------------------- 152 -- PSI5 Register Masks 153 ---------------------------------------------------------------------------- */ 154 155 /*! 156 * @addtogroup PSI5_Register_Masks PSI5 Register Masks 157 * @{ 158 */ 159 160 /*! @name GCR - Global Control Register */ 161 /*! @{ */ 162 163 #define PSI5_GCR_GLOBAL_DISABLE_REQ_MASK (0x1U) 164 #define PSI5_GCR_GLOBAL_DISABLE_REQ_SHIFT (0U) 165 #define PSI5_GCR_GLOBAL_DISABLE_REQ_WIDTH (1U) 166 #define PSI5_GCR_GLOBAL_DISABLE_REQ(x) (((uint16_t)(((uint16_t)(x)) << PSI5_GCR_GLOBAL_DISABLE_REQ_SHIFT)) & PSI5_GCR_GLOBAL_DISABLE_REQ_MASK) 167 168 #define PSI5_GCR_CTC_GED_MASK (0x2U) 169 #define PSI5_GCR_CTC_GED_SHIFT (1U) 170 #define PSI5_GCR_CTC_GED_WIDTH (1U) 171 #define PSI5_GCR_CTC_GED(x) (((uint16_t)(((uint16_t)(x)) << PSI5_GCR_CTC_GED_SHIFT)) & PSI5_GCR_CTC_GED_MASK) 172 /*! @} */ 173 174 /*! @name CH_PCCR - PSI5 Channel Control Register */ 175 /*! @{ */ 176 177 #define PSI5_CH_PCCR_PSI5_CH_EN_MASK (0x1U) 178 #define PSI5_CH_PCCR_PSI5_CH_EN_SHIFT (0U) 179 #define PSI5_CH_PCCR_PSI5_CH_EN_WIDTH (1U) 180 #define PSI5_CH_PCCR_PSI5_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_PSI5_CH_EN_SHIFT)) & PSI5_CH_PCCR_PSI5_CH_EN_MASK) 181 182 #define PSI5_CH_PCCR_PSI5_CH_CONFIG_MASK (0x2U) 183 #define PSI5_CH_PCCR_PSI5_CH_CONFIG_SHIFT (1U) 184 #define PSI5_CH_PCCR_PSI5_CH_CONFIG_WIDTH (1U) 185 #define PSI5_CH_PCCR_PSI5_CH_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_PSI5_CH_CONFIG_SHIFT)) & PSI5_CH_PCCR_PSI5_CH_CONFIG_MASK) 186 187 #define PSI5_CH_PCCR_MODE_MASK (0x4U) 188 #define PSI5_CH_PCCR_MODE_SHIFT (2U) 189 #define PSI5_CH_PCCR_MODE_WIDTH (1U) 190 #define PSI5_CH_PCCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_MODE_SHIFT)) & PSI5_CH_PCCR_MODE_MASK) 191 192 #define PSI5_CH_PCCR_BIT_RATE_MASK (0x8U) 193 #define PSI5_CH_PCCR_BIT_RATE_SHIFT (3U) 194 #define PSI5_CH_PCCR_BIT_RATE_WIDTH (1U) 195 #define PSI5_CH_PCCR_BIT_RATE(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_BIT_RATE_SHIFT)) & PSI5_CH_PCCR_BIT_RATE_MASK) 196 197 #define PSI5_CH_PCCR_FAST_CLR_PSI5_MASK (0x10U) 198 #define PSI5_CH_PCCR_FAST_CLR_PSI5_SHIFT (4U) 199 #define PSI5_CH_PCCR_FAST_CLR_PSI5_WIDTH (1U) 200 #define PSI5_CH_PCCR_FAST_CLR_PSI5(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_FAST_CLR_PSI5_SHIFT)) & PSI5_CH_PCCR_FAST_CLR_PSI5_MASK) 201 202 #define PSI5_CH_PCCR_FAST_CLR_SMC_MASK (0x20U) 203 #define PSI5_CH_PCCR_FAST_CLR_SMC_SHIFT (5U) 204 #define PSI5_CH_PCCR_FAST_CLR_SMC_WIDTH (1U) 205 #define PSI5_CH_PCCR_FAST_CLR_SMC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_FAST_CLR_SMC_SHIFT)) & PSI5_CH_PCCR_FAST_CLR_SMC_MASK) 206 207 #define PSI5_CH_PCCR_SP_TS_CLK_SEL_MASK (0x100U) 208 #define PSI5_CH_PCCR_SP_TS_CLK_SEL_SHIFT (8U) 209 #define PSI5_CH_PCCR_SP_TS_CLK_SEL_WIDTH (1U) 210 #define PSI5_CH_PCCR_SP_TS_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_SP_TS_CLK_SEL_SHIFT)) & PSI5_CH_PCCR_SP_TS_CLK_SEL_MASK) 211 212 #define PSI5_CH_PCCR_DEBUG_FREEZE_CTRL_MASK (0x200U) 213 #define PSI5_CH_PCCR_DEBUG_FREEZE_CTRL_SHIFT (9U) 214 #define PSI5_CH_PCCR_DEBUG_FREEZE_CTRL_WIDTH (1U) 215 #define PSI5_CH_PCCR_DEBUG_FREEZE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_DEBUG_FREEZE_CTRL_SHIFT)) & PSI5_CH_PCCR_DEBUG_FREEZE_CTRL_MASK) 216 217 #define PSI5_CH_PCCR_DEBUG_EN_MASK (0x400U) 218 #define PSI5_CH_PCCR_DEBUG_EN_SHIFT (10U) 219 #define PSI5_CH_PCCR_DEBUG_EN_WIDTH (1U) 220 #define PSI5_CH_PCCR_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_DEBUG_EN_SHIFT)) & PSI5_CH_PCCR_DEBUG_EN_MASK) 221 222 #define PSI5_CH_PCCR_GTM_RESET_ASYNC_EN_MASK (0x4000U) 223 #define PSI5_CH_PCCR_GTM_RESET_ASYNC_EN_SHIFT (14U) 224 #define PSI5_CH_PCCR_GTM_RESET_ASYNC_EN_WIDTH (1U) 225 #define PSI5_CH_PCCR_GTM_RESET_ASYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_GTM_RESET_ASYNC_EN_SHIFT)) & PSI5_CH_PCCR_GTM_RESET_ASYNC_EN_MASK) 226 227 #define PSI5_CH_PCCR_ERROR_SELECT0_MASK (0x10000U) 228 #define PSI5_CH_PCCR_ERROR_SELECT0_SHIFT (16U) 229 #define PSI5_CH_PCCR_ERROR_SELECT0_WIDTH (1U) 230 #define PSI5_CH_PCCR_ERROR_SELECT0(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_ERROR_SELECT0_SHIFT)) & PSI5_CH_PCCR_ERROR_SELECT0_MASK) 231 232 #define PSI5_CH_PCCR_ERROR_SELECT1_MASK (0x20000U) 233 #define PSI5_CH_PCCR_ERROR_SELECT1_SHIFT (17U) 234 #define PSI5_CH_PCCR_ERROR_SELECT1_WIDTH (1U) 235 #define PSI5_CH_PCCR_ERROR_SELECT1(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_ERROR_SELECT1_SHIFT)) & PSI5_CH_PCCR_ERROR_SELECT1_MASK) 236 237 #define PSI5_CH_PCCR_ERROR_SELECT2_MASK (0x40000U) 238 #define PSI5_CH_PCCR_ERROR_SELECT2_SHIFT (18U) 239 #define PSI5_CH_PCCR_ERROR_SELECT2_WIDTH (1U) 240 #define PSI5_CH_PCCR_ERROR_SELECT2(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_ERROR_SELECT2_SHIFT)) & PSI5_CH_PCCR_ERROR_SELECT2_MASK) 241 242 #define PSI5_CH_PCCR_ERROR_SELECT3_MASK (0x80000U) 243 #define PSI5_CH_PCCR_ERROR_SELECT3_SHIFT (19U) 244 #define PSI5_CH_PCCR_ERROR_SELECT3_WIDTH (1U) 245 #define PSI5_CH_PCCR_ERROR_SELECT3(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_ERROR_SELECT3_SHIFT)) & PSI5_CH_PCCR_ERROR_SELECT3_MASK) 246 247 #define PSI5_CH_PCCR_ERROR_SELECT4_MASK (0x100000U) 248 #define PSI5_CH_PCCR_ERROR_SELECT4_SHIFT (20U) 249 #define PSI5_CH_PCCR_ERROR_SELECT4_WIDTH (1U) 250 #define PSI5_CH_PCCR_ERROR_SELECT4(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_ERROR_SELECT4_SHIFT)) & PSI5_CH_PCCR_ERROR_SELECT4_MASK) 251 252 #define PSI5_CH_PCCR_MEM_DEPTH_MASK (0x1F000000U) 253 #define PSI5_CH_PCCR_MEM_DEPTH_SHIFT (24U) 254 #define PSI5_CH_PCCR_MEM_DEPTH_WIDTH (5U) 255 #define PSI5_CH_PCCR_MEM_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_MEM_DEPTH_SHIFT)) & PSI5_CH_PCCR_MEM_DEPTH_MASK) 256 257 #define PSI5_CH_PCCR_CTC_ED_MASK (0x40000000U) 258 #define PSI5_CH_PCCR_CTC_ED_SHIFT (30U) 259 #define PSI5_CH_PCCR_CTC_ED_WIDTH (1U) 260 #define PSI5_CH_PCCR_CTC_ED(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_CTC_ED_SHIFT)) & PSI5_CH_PCCR_CTC_ED_MASK) 261 262 #define PSI5_CH_PCCR_CTC_GED_SEL_MASK (0x80000000U) 263 #define PSI5_CH_PCCR_CTC_GED_SEL_SHIFT (31U) 264 #define PSI5_CH_PCCR_CTC_GED_SEL_WIDTH (1U) 265 #define PSI5_CH_PCCR_CTC_GED_SEL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PCCR_CTC_GED_SEL_SHIFT)) & PSI5_CH_PCCR_CTC_GED_SEL_MASK) 266 /*! @} */ 267 268 /*! @name CH_DCR - DMA Control Register */ 269 /*! @{ */ 270 271 #define PSI5_CH_DCR_DMA_PM_DS_CONFIG_MASK (0x3U) 272 #define PSI5_CH_DCR_DMA_PM_DS_CONFIG_SHIFT (0U) 273 #define PSI5_CH_DCR_DMA_PM_DS_CONFIG_WIDTH (2U) 274 #define PSI5_CH_DCR_DMA_PM_DS_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_DMA_PM_DS_CONFIG_SHIFT)) & PSI5_CH_DCR_DMA_PM_DS_CONFIG_MASK) 275 276 #define PSI5_CH_DCR_DMA_EN_SF_MASK (0x4U) 277 #define PSI5_CH_DCR_DMA_EN_SF_SHIFT (2U) 278 #define PSI5_CH_DCR_DMA_EN_SF_WIDTH (1U) 279 #define PSI5_CH_DCR_DMA_EN_SF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_DMA_EN_SF_SHIFT)) & PSI5_CH_DCR_DMA_EN_SF_MASK) 280 281 #define PSI5_CH_DCR_IE_DMA_PM_DS_UF_MASK (0x100U) 282 #define PSI5_CH_DCR_IE_DMA_PM_DS_UF_SHIFT (8U) 283 #define PSI5_CH_DCR_IE_DMA_PM_DS_UF_WIDTH (1U) 284 #define PSI5_CH_DCR_IE_DMA_PM_DS_UF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_IE_DMA_PM_DS_UF_SHIFT)) & PSI5_CH_DCR_IE_DMA_PM_DS_UF_MASK) 285 286 #define PSI5_CH_DCR_IE_DMA_SFUF_MASK (0x400U) 287 #define PSI5_CH_DCR_IE_DMA_SFUF_SHIFT (10U) 288 #define PSI5_CH_DCR_IE_DMA_SFUF_WIDTH (1U) 289 #define PSI5_CH_DCR_IE_DMA_SFUF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_IE_DMA_SFUF_SHIFT)) & PSI5_CH_DCR_IE_DMA_SFUF_MASK) 290 291 #define PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK (0x800U) 292 #define PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_SHIFT (11U) 293 #define PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_WIDTH (1U) 294 #define PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_SHIFT)) & PSI5_CH_DCR_IE_DMA_PM_DS_FIFO_FULL_MASK) 295 296 #define PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK (0x20000U) 297 #define PSI5_CH_DCR_IE_DMA_TF_PM_DS_SHIFT (17U) 298 #define PSI5_CH_DCR_IE_DMA_TF_PM_DS_WIDTH (1U) 299 #define PSI5_CH_DCR_IE_DMA_TF_PM_DS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_IE_DMA_TF_PM_DS_SHIFT)) & PSI5_CH_DCR_IE_DMA_TF_PM_DS_MASK) 300 301 #define PSI5_CH_DCR_IE_DMA_TF_SF_MASK (0x40000U) 302 #define PSI5_CH_DCR_IE_DMA_TF_SF_SHIFT (18U) 303 #define PSI5_CH_DCR_IE_DMA_TF_SF_WIDTH (1U) 304 #define PSI5_CH_DCR_IE_DMA_TF_SF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_IE_DMA_TF_SF_SHIFT)) & PSI5_CH_DCR_IE_DMA_TF_SF_MASK) 305 306 #define PSI5_CH_DCR_DMA_PM_DS_WM_MASK (0x1F000000U) 307 #define PSI5_CH_DCR_DMA_PM_DS_WM_SHIFT (24U) 308 #define PSI5_CH_DCR_DMA_PM_DS_WM_WIDTH (5U) 309 #define PSI5_CH_DCR_DMA_PM_DS_WM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DCR_DMA_PM_DS_WM_SHIFT)) & PSI5_CH_DCR_DMA_PM_DS_WM_MASK) 310 /*! @} */ 311 312 /*! @name CH_DSR - DMA Status Register */ 313 /*! @{ */ 314 315 #define PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK (0x100U) 316 #define PSI5_CH_DSR_IS_DMA_PM_DS_UF_SHIFT (8U) 317 #define PSI5_CH_DSR_IS_DMA_PM_DS_UF_WIDTH (1U) 318 #define PSI5_CH_DSR_IS_DMA_PM_DS_UF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSR_IS_DMA_PM_DS_UF_SHIFT)) & PSI5_CH_DSR_IS_DMA_PM_DS_UF_MASK) 319 320 #define PSI5_CH_DSR_IS_DMA_SFUF_MASK (0x400U) 321 #define PSI5_CH_DSR_IS_DMA_SFUF_SHIFT (10U) 322 #define PSI5_CH_DSR_IS_DMA_SFUF_WIDTH (1U) 323 #define PSI5_CH_DSR_IS_DMA_SFUF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSR_IS_DMA_SFUF_SHIFT)) & PSI5_CH_DSR_IS_DMA_SFUF_MASK) 324 325 #define PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK (0x800U) 326 #define PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_SHIFT (11U) 327 #define PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_WIDTH (1U) 328 #define PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_SHIFT)) & PSI5_CH_DSR_IS_DMA_PM_DS_FIFO_FULL_MASK) 329 330 #define PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK (0x20000U) 331 #define PSI5_CH_DSR_IS_DMA_TF_PM_DS_SHIFT (17U) 332 #define PSI5_CH_DSR_IS_DMA_TF_PM_DS_WIDTH (1U) 333 #define PSI5_CH_DSR_IS_DMA_TF_PM_DS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSR_IS_DMA_TF_PM_DS_SHIFT)) & PSI5_CH_DSR_IS_DMA_TF_PM_DS_MASK) 334 335 #define PSI5_CH_DSR_IS_DMA_TF_SF_MASK (0x40000U) 336 #define PSI5_CH_DSR_IS_DMA_TF_SF_SHIFT (18U) 337 #define PSI5_CH_DSR_IS_DMA_TF_SF_WIDTH (1U) 338 #define PSI5_CH_DSR_IS_DMA_TF_SF(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSR_IS_DMA_TF_SF_SHIFT)) & PSI5_CH_DSR_IS_DMA_TF_SF_MASK) 339 /*! @} */ 340 341 /*! @name CH_GICR - General Interrupt Control Register */ 342 /*! @{ */ 343 344 #define PSI5_CH_GICR_IE_PRR_MASK (0x10000U) 345 #define PSI5_CH_GICR_IE_PRR_SHIFT (16U) 346 #define PSI5_CH_GICR_IE_PRR_WIDTH (1U) 347 #define PSI5_CH_GICR_IE_PRR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_PRR_SHIFT)) & PSI5_CH_GICR_IE_PRR_MASK) 348 349 #define PSI5_CH_GICR_IE_BRR_MASK (0x20000U) 350 #define PSI5_CH_GICR_IE_BRR_SHIFT (17U) 351 #define PSI5_CH_GICR_IE_BRR_WIDTH (1U) 352 #define PSI5_CH_GICR_IE_BRR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_BRR_SHIFT)) & PSI5_CH_GICR_IE_BRR_MASK) 353 354 #define PSI5_CH_GICR_IE_DSRR_MASK (0x40000U) 355 #define PSI5_CH_GICR_IE_DSRR_SHIFT (18U) 356 #define PSI5_CH_GICR_IE_DSRR_WIDTH (1U) 357 #define PSI5_CH_GICR_IE_DSRR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_DSRR_SHIFT)) & PSI5_CH_GICR_IE_DSRR_MASK) 358 359 #define PSI5_CH_GICR_IE_PROW_MASK (0x80000U) 360 #define PSI5_CH_GICR_IE_PROW_SHIFT (19U) 361 #define PSI5_CH_GICR_IE_PROW_WIDTH (1U) 362 #define PSI5_CH_GICR_IE_PROW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_PROW_SHIFT)) & PSI5_CH_GICR_IE_PROW_MASK) 363 364 #define PSI5_CH_GICR_IE_BROW_MASK (0x100000U) 365 #define PSI5_CH_GICR_IE_BROW_SHIFT (20U) 366 #define PSI5_CH_GICR_IE_BROW_WIDTH (1U) 367 #define PSI5_CH_GICR_IE_BROW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_BROW_SHIFT)) & PSI5_CH_GICR_IE_BROW_MASK) 368 369 #define PSI5_CH_GICR_IE_DSROW_MASK (0x200000U) 370 #define PSI5_CH_GICR_IE_DSROW_SHIFT (21U) 371 #define PSI5_CH_GICR_IE_DSROW_WIDTH (1U) 372 #define PSI5_CH_GICR_IE_DSROW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_DSROW_SHIFT)) & PSI5_CH_GICR_IE_DSROW_MASK) 373 374 #define PSI5_CH_GICR_IE_DTS_MASK (0x400000U) 375 #define PSI5_CH_GICR_IE_DTS_SHIFT (22U) 376 #define PSI5_CH_GICR_IE_DTS_WIDTH (1U) 377 #define PSI5_CH_GICR_IE_DTS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_DTS_SHIFT)) & PSI5_CH_GICR_IE_DTS_MASK) 378 379 #define PSI5_CH_GICR_IE_STS_MASK (0x800000U) 380 #define PSI5_CH_GICR_IE_STS_SHIFT (23U) 381 #define PSI5_CH_GICR_IE_STS_WIDTH (1U) 382 #define PSI5_CH_GICR_IE_STS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GICR_IE_STS_SHIFT)) & PSI5_CH_GICR_IE_STS_MASK) 383 /*! @} */ 384 385 /*! @name CH_NDICR - New Data Interrupt Control Register */ 386 /*! @{ */ 387 388 #define PSI5_CH_NDICR_IE_ND_MASK (0xFFFFFFFFU) 389 #define PSI5_CH_NDICR_IE_ND_SHIFT (0U) 390 #define PSI5_CH_NDICR_IE_ND_WIDTH (32U) 391 #define PSI5_CH_NDICR_IE_ND(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_NDICR_IE_ND_SHIFT)) & PSI5_CH_NDICR_IE_ND_MASK) 392 /*! @} */ 393 394 /*! @name CH_OWICR - Overwrite Interrupt Control Register */ 395 /*! @{ */ 396 397 #define PSI5_CH_OWICR_IE_OW_MASK (0xFFFFFFFFU) 398 #define PSI5_CH_OWICR_IE_OW_SHIFT (0U) 399 #define PSI5_CH_OWICR_IE_OW_WIDTH (32U) 400 #define PSI5_CH_OWICR_IE_OW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_OWICR_IE_OW_SHIFT)) & PSI5_CH_OWICR_IE_OW_MASK) 401 /*! @} */ 402 403 /*! @name CH_EICR - Error Interrupt Control Register */ 404 /*! @{ */ 405 406 #define PSI5_CH_EICR_IE_ERROR_MASK (0xFFFFFFFFU) 407 #define PSI5_CH_EICR_IE_ERROR_SHIFT (0U) 408 #define PSI5_CH_EICR_IE_ERROR_WIDTH (32U) 409 #define PSI5_CH_EICR_IE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_EICR_IE_ERROR_SHIFT)) & PSI5_CH_EICR_IE_ERROR_MASK) 410 /*! @} */ 411 412 /*! @name CH_GISR - General Interrupt Status Register */ 413 /*! @{ */ 414 415 #define PSI5_CH_GISR_IS_NVSM_MASK (0x3FU) 416 #define PSI5_CH_GISR_IS_NVSM_SHIFT (0U) 417 #define PSI5_CH_GISR_IS_NVSM_WIDTH (6U) 418 #define PSI5_CH_GISR_IS_NVSM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_NVSM_SHIFT)) & PSI5_CH_GISR_IS_NVSM_MASK) 419 420 #define PSI5_CH_GISR_IS_OWSM_MASK (0x3F00U) 421 #define PSI5_CH_GISR_IS_OWSM_SHIFT (8U) 422 #define PSI5_CH_GISR_IS_OWSM_WIDTH (6U) 423 #define PSI5_CH_GISR_IS_OWSM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_OWSM_SHIFT)) & PSI5_CH_GISR_IS_OWSM_MASK) 424 425 #define PSI5_CH_GISR_DPR_RDY_MASK (0x10000U) 426 #define PSI5_CH_GISR_DPR_RDY_SHIFT (16U) 427 #define PSI5_CH_GISR_DPR_RDY_WIDTH (1U) 428 #define PSI5_CH_GISR_DPR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_DPR_RDY_SHIFT)) & PSI5_CH_GISR_DPR_RDY_MASK) 429 430 #define PSI5_CH_GISR_DBR_RDY_MASK (0x20000U) 431 #define PSI5_CH_GISR_DBR_RDY_SHIFT (17U) 432 #define PSI5_CH_GISR_DBR_RDY_WIDTH (1U) 433 #define PSI5_CH_GISR_DBR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_DBR_RDY_SHIFT)) & PSI5_CH_GISR_DBR_RDY_MASK) 434 435 #define PSI5_CH_GISR_DSR_RDY_MASK (0x40000U) 436 #define PSI5_CH_GISR_DSR_RDY_SHIFT (18U) 437 #define PSI5_CH_GISR_DSR_RDY_WIDTH (1U) 438 #define PSI5_CH_GISR_DSR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_DSR_RDY_SHIFT)) & PSI5_CH_GISR_DSR_RDY_MASK) 439 440 #define PSI5_CH_GISR_IS_PROW_MASK (0x80000U) 441 #define PSI5_CH_GISR_IS_PROW_SHIFT (19U) 442 #define PSI5_CH_GISR_IS_PROW_WIDTH (1U) 443 #define PSI5_CH_GISR_IS_PROW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_PROW_SHIFT)) & PSI5_CH_GISR_IS_PROW_MASK) 444 445 #define PSI5_CH_GISR_IS_BROW_MASK (0x100000U) 446 #define PSI5_CH_GISR_IS_BROW_SHIFT (20U) 447 #define PSI5_CH_GISR_IS_BROW_WIDTH (1U) 448 #define PSI5_CH_GISR_IS_BROW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_BROW_SHIFT)) & PSI5_CH_GISR_IS_BROW_MASK) 449 450 #define PSI5_CH_GISR_IS_DSROW_MASK (0x200000U) 451 #define PSI5_CH_GISR_IS_DSROW_SHIFT (21U) 452 #define PSI5_CH_GISR_IS_DSROW_WIDTH (1U) 453 #define PSI5_CH_GISR_IS_DSROW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_DSROW_SHIFT)) & PSI5_CH_GISR_IS_DSROW_MASK) 454 455 #define PSI5_CH_GISR_IS_DTS_MASK (0x400000U) 456 #define PSI5_CH_GISR_IS_DTS_SHIFT (22U) 457 #define PSI5_CH_GISR_IS_DTS_WIDTH (1U) 458 #define PSI5_CH_GISR_IS_DTS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_DTS_SHIFT)) & PSI5_CH_GISR_IS_DTS_MASK) 459 460 #define PSI5_CH_GISR_IS_STS_MASK (0x800000U) 461 #define PSI5_CH_GISR_IS_STS_SHIFT (23U) 462 #define PSI5_CH_GISR_IS_STS_WIDTH (1U) 463 #define PSI5_CH_GISR_IS_STS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_STS_SHIFT)) & PSI5_CH_GISR_IS_STS_MASK) 464 465 #define PSI5_CH_GISR_IS_CESM_MASK (0x3F000000U) 466 #define PSI5_CH_GISR_IS_CESM_SHIFT (24U) 467 #define PSI5_CH_GISR_IS_CESM_WIDTH (6U) 468 #define PSI5_CH_GISR_IS_CESM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_CESM_SHIFT)) & PSI5_CH_GISR_IS_CESM_MASK) 469 470 #define PSI5_CH_GISR_IS_DB_FR_MASK (0x80000000U) 471 #define PSI5_CH_GISR_IS_DB_FR_SHIFT (31U) 472 #define PSI5_CH_GISR_IS_DB_FR_WIDTH (1U) 473 #define PSI5_CH_GISR_IS_DB_FR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_GISR_IS_DB_FR_SHIFT)) & PSI5_CH_GISR_IS_DB_FR_MASK) 474 /*! @} */ 475 476 /*! @name CH_DPMR - DMA PSI5 Message Register */ 477 /*! @{ */ 478 479 #define PSI5_CH_DPMR_PSI5_RXDATA_MASK (0xFFFFFFFFU) 480 #define PSI5_CH_DPMR_PSI5_RXDATA_SHIFT (0U) 481 #define PSI5_CH_DPMR_PSI5_RXDATA_WIDTH (32U) 482 #define PSI5_CH_DPMR_PSI5_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DPMR_PSI5_RXDATA_SHIFT)) & PSI5_CH_DPMR_PSI5_RXDATA_MASK) 483 /*! @} */ 484 485 /*! @name CH_DSFR - DMA SMC Frame Register */ 486 /*! @{ */ 487 488 #define PSI5_CH_DSFR_SMC_RXDATA_MASK (0xFFFFFFFFU) 489 #define PSI5_CH_DSFR_SMC_RXDATA_SHIFT (0U) 490 #define PSI5_CH_DSFR_SMC_RXDATA_WIDTH (32U) 491 #define PSI5_CH_DSFR_SMC_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSFR_SMC_RXDATA_SHIFT)) & PSI5_CH_DSFR_SMC_RXDATA_MASK) 492 /*! @} */ 493 494 /*! @name CH_DDSR - DMA Diagnostic Status Register */ 495 /*! @{ */ 496 497 #define PSI5_CH_DDSR_DDS_MASK (0xFFFFFFFFU) 498 #define PSI5_CH_DDSR_DDS_SHIFT (0U) 499 #define PSI5_CH_DDSR_DDS_WIDTH (32U) 500 #define PSI5_CH_DDSR_DDS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DDSR_DDS_SHIFT)) & PSI5_CH_DDSR_DDS_MASK) 501 /*! @} */ 502 503 /*! @name CH_PMRRL - PSI5 Message Receive Register Low */ 504 /*! @{ */ 505 506 #define PSI5_CH_PMRRL_C_MASK (0x1U) 507 #define PSI5_CH_PMRRL_C_SHIFT (0U) 508 #define PSI5_CH_PMRRL_C_WIDTH (1U) 509 #define PSI5_CH_PMRRL_C(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRL_C_SHIFT)) & PSI5_CH_PMRRL_C_MASK) 510 511 #define PSI5_CH_PMRRL_CRC_MASK (0xEU) 512 #define PSI5_CH_PMRRL_CRC_SHIFT (1U) 513 #define PSI5_CH_PMRRL_CRC_WIDTH (3U) 514 #define PSI5_CH_PMRRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRL_CRC_SHIFT)) & PSI5_CH_PMRRL_CRC_MASK) 515 516 #define PSI5_CH_PMRRL_DATA_REGION_MASK (0xFFFFFFF0U) 517 #define PSI5_CH_PMRRL_DATA_REGION_SHIFT (4U) 518 #define PSI5_CH_PMRRL_DATA_REGION_WIDTH (28U) 519 #define PSI5_CH_PMRRL_DATA_REGION(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRL_DATA_REGION_SHIFT)) & PSI5_CH_PMRRL_DATA_REGION_MASK) 520 /*! @} */ 521 522 /*! @name CH_PMRRH - PSI5 Message Receive Register High */ 523 /*! @{ */ 524 525 #define PSI5_CH_PMRRH_TimeStampValue_MASK (0xFFFFFFU) 526 #define PSI5_CH_PMRRH_TimeStampValue_SHIFT (0U) 527 #define PSI5_CH_PMRRH_TimeStampValue_WIDTH (24U) 528 #define PSI5_CH_PMRRH_TimeStampValue(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRH_TimeStampValue_SHIFT)) & PSI5_CH_PMRRH_TimeStampValue_MASK) 529 530 #define PSI5_CH_PMRRH_SlotCounter_MASK (0x7000000U) 531 #define PSI5_CH_PMRRH_SlotCounter_SHIFT (24U) 532 #define PSI5_CH_PMRRH_SlotCounter_WIDTH (3U) 533 #define PSI5_CH_PMRRH_SlotCounter(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRH_SlotCounter_SHIFT)) & PSI5_CH_PMRRH_SlotCounter_MASK) 534 535 #define PSI5_CH_PMRRH_T_MASK (0x8000000U) 536 #define PSI5_CH_PMRRH_T_SHIFT (27U) 537 #define PSI5_CH_PMRRH_T_WIDTH (1U) 538 #define PSI5_CH_PMRRH_T(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRH_T_SHIFT)) & PSI5_CH_PMRRH_T_MASK) 539 540 #define PSI5_CH_PMRRH_E_MASK (0x10000000U) 541 #define PSI5_CH_PMRRH_E_SHIFT (28U) 542 #define PSI5_CH_PMRRH_E_WIDTH (1U) 543 #define PSI5_CH_PMRRH_E(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRH_E_SHIFT)) & PSI5_CH_PMRRH_E_MASK) 544 545 #define PSI5_CH_PMRRH_EM_MASK (0x20000000U) 546 #define PSI5_CH_PMRRH_EM_SHIFT (29U) 547 #define PSI5_CH_PMRRH_EM_WIDTH (1U) 548 #define PSI5_CH_PMRRH_EM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRH_EM_SHIFT)) & PSI5_CH_PMRRH_EM_MASK) 549 550 #define PSI5_CH_PMRRH_F_MASK (0x40000000U) 551 #define PSI5_CH_PMRRH_F_SHIFT (30U) 552 #define PSI5_CH_PMRRH_F_WIDTH (1U) 553 #define PSI5_CH_PMRRH_F(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRRH_F_SHIFT)) & PSI5_CH_PMRRH_F_MASK) 554 /*! @} */ 555 556 /*! @name CH_PMRL - PSI5 Message Register Low i */ 557 /*! @{ */ 558 559 #define PSI5_CH_PMRL_C_MASK (0x1U) 560 #define PSI5_CH_PMRL_C_SHIFT (0U) 561 #define PSI5_CH_PMRL_C_WIDTH (1U) 562 #define PSI5_CH_PMRL_C(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRL_C_SHIFT)) & PSI5_CH_PMRL_C_MASK) 563 564 #define PSI5_CH_PMRL_CRCP_MASK (0xEU) 565 #define PSI5_CH_PMRL_CRCP_SHIFT (1U) 566 #define PSI5_CH_PMRL_CRCP_WIDTH (3U) 567 #define PSI5_CH_PMRL_CRCP(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRL_CRCP_SHIFT)) & PSI5_CH_PMRL_CRCP_MASK) 568 569 #define PSI5_CH_PMRL_DATA_REGION_MASK (0xFFFFFFF0U) 570 #define PSI5_CH_PMRL_DATA_REGION_SHIFT (4U) 571 #define PSI5_CH_PMRL_DATA_REGION_WIDTH (28U) 572 #define PSI5_CH_PMRL_DATA_REGION(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRL_DATA_REGION_SHIFT)) & PSI5_CH_PMRL_DATA_REGION_MASK) 573 /*! @} */ 574 575 /*! @name CH_PMRH - PSI5 Message Register High i */ 576 /*! @{ */ 577 578 #define PSI5_CH_PMRH_TimeStampValue_MASK (0xFFFFFFU) 579 #define PSI5_CH_PMRH_TimeStampValue_SHIFT (0U) 580 #define PSI5_CH_PMRH_TimeStampValue_WIDTH (24U) 581 #define PSI5_CH_PMRH_TimeStampValue(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRH_TimeStampValue_SHIFT)) & PSI5_CH_PMRH_TimeStampValue_MASK) 582 583 #define PSI5_CH_PMRH_Slot_Counter_MASK (0x7000000U) 584 #define PSI5_CH_PMRH_Slot_Counter_SHIFT (24U) 585 #define PSI5_CH_PMRH_Slot_Counter_WIDTH (3U) 586 #define PSI5_CH_PMRH_Slot_Counter(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRH_Slot_Counter_SHIFT)) & PSI5_CH_PMRH_Slot_Counter_MASK) 587 588 #define PSI5_CH_PMRH_T_MASK (0x8000000U) 589 #define PSI5_CH_PMRH_T_SHIFT (27U) 590 #define PSI5_CH_PMRH_T_WIDTH (1U) 591 #define PSI5_CH_PMRH_T(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRH_T_SHIFT)) & PSI5_CH_PMRH_T_MASK) 592 593 #define PSI5_CH_PMRH_E_MASK (0x10000000U) 594 #define PSI5_CH_PMRH_E_SHIFT (28U) 595 #define PSI5_CH_PMRH_E_WIDTH (1U) 596 #define PSI5_CH_PMRH_E(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRH_E_SHIFT)) & PSI5_CH_PMRH_E_MASK) 597 598 #define PSI5_CH_PMRH_EM_MASK (0x20000000U) 599 #define PSI5_CH_PMRH_EM_SHIFT (29U) 600 #define PSI5_CH_PMRH_EM_WIDTH (1U) 601 #define PSI5_CH_PMRH_EM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRH_EM_SHIFT)) & PSI5_CH_PMRH_EM_MASK) 602 603 #define PSI5_CH_PMRH_F_MASK (0x40000000U) 604 #define PSI5_CH_PMRH_F_SHIFT (30U) 605 #define PSI5_CH_PMRH_F_WIDTH (1U) 606 #define PSI5_CH_PMRH_F(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRH_F_SHIFT)) & PSI5_CH_PMRH_F_MASK) 607 608 #define PSI5_CH_PMRH_O_MASK (0x80000000U) 609 #define PSI5_CH_PMRH_O_SHIFT (31U) 610 #define PSI5_CH_PMRH_O_WIDTH (1U) 611 #define PSI5_CH_PMRH_O(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_PMRH_O_SHIFT)) & PSI5_CH_PMRH_O_MASK) 612 /*! @} */ 613 614 /*! @name CH_SFR - SMC Frame Register n */ 615 /*! @{ */ 616 617 #define PSI5_CH_SFR_DATA_MASK (0xFFFU) 618 #define PSI5_CH_SFR_DATA_SHIFT (0U) 619 #define PSI5_CH_SFR_DATA_WIDTH (12U) 620 #define PSI5_CH_SFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_DATA_SHIFT)) & PSI5_CH_SFR_DATA_MASK) 621 622 #define PSI5_CH_SFR_IDDATA_MASK (0xF000U) 623 #define PSI5_CH_SFR_IDDATA_SHIFT (12U) 624 #define PSI5_CH_SFR_IDDATA_WIDTH (4U) 625 #define PSI5_CH_SFR_IDDATA(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_IDDATA_SHIFT)) & PSI5_CH_SFR_IDDATA_MASK) 626 627 #define PSI5_CH_SFR_ID_MASK (0xF0000U) 628 #define PSI5_CH_SFR_ID_SHIFT (16U) 629 #define PSI5_CH_SFR_ID_WIDTH (4U) 630 #define PSI5_CH_SFR_ID(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_ID_SHIFT)) & PSI5_CH_SFR_ID_MASK) 631 632 #define PSI5_CH_SFR_C_MASK (0x100000U) 633 #define PSI5_CH_SFR_C_SHIFT (20U) 634 #define PSI5_CH_SFR_C_WIDTH (1U) 635 #define PSI5_CH_SFR_C(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_C_SHIFT)) & PSI5_CH_SFR_C_MASK) 636 637 #define PSI5_CH_SFR_CRC_MASK (0x7E00000U) 638 #define PSI5_CH_SFR_CRC_SHIFT (21U) 639 #define PSI5_CH_SFR_CRC_WIDTH (6U) 640 #define PSI5_CH_SFR_CRC(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_CRC_SHIFT)) & PSI5_CH_SFR_CRC_MASK) 641 642 #define PSI5_CH_SFR_OW_MASK (0x8000000U) 643 #define PSI5_CH_SFR_OW_SHIFT (27U) 644 #define PSI5_CH_SFR_OW_WIDTH (1U) 645 #define PSI5_CH_SFR_OW(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_OW_SHIFT)) & PSI5_CH_SFR_OW_MASK) 646 647 #define PSI5_CH_SFR_CER_MASK (0x10000000U) 648 #define PSI5_CH_SFR_CER_SHIFT (28U) 649 #define PSI5_CH_SFR_CER_WIDTH (1U) 650 #define PSI5_CH_SFR_CER(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_CER_SHIFT)) & PSI5_CH_SFR_CER_MASK) 651 652 #define PSI5_CH_SFR_SLOT_NO_MASK (0xE0000000U) 653 #define PSI5_CH_SFR_SLOT_NO_SHIFT (29U) 654 #define PSI5_CH_SFR_SLOT_NO_WIDTH (3U) 655 #define PSI5_CH_SFR_SLOT_NO(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFR_SLOT_NO_SHIFT)) & PSI5_CH_SFR_SLOT_NO_MASK) 656 /*! @} */ 657 658 /*! @name CH_NDSR - New Data Status Register */ 659 /*! @{ */ 660 661 #define PSI5_CH_NDSR_NDS_MASK (0xFFFFFFFFU) 662 #define PSI5_CH_NDSR_NDS_SHIFT (0U) 663 #define PSI5_CH_NDSR_NDS_WIDTH (32U) 664 #define PSI5_CH_NDSR_NDS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_NDSR_NDS_SHIFT)) & PSI5_CH_NDSR_NDS_MASK) 665 /*! @} */ 666 667 /*! @name CH_OWSR - Overwrite Status Register */ 668 /*! @{ */ 669 670 #define PSI5_CH_OWSR_OWS_MASK (0xFFFFFFFFU) 671 #define PSI5_CH_OWSR_OWS_SHIFT (0U) 672 #define PSI5_CH_OWSR_OWS_WIDTH (32U) 673 #define PSI5_CH_OWSR_OWS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_OWSR_OWS_SHIFT)) & PSI5_CH_OWSR_OWS_MASK) 674 /*! @} */ 675 676 /*! @name CH_EISR - Error Indication Status Register */ 677 /*! @{ */ 678 679 #define PSI5_CH_EISR_ERROR_MASK (0xFFFFFFFFU) 680 #define PSI5_CH_EISR_ERROR_SHIFT (0U) 681 #define PSI5_CH_EISR_ERROR_WIDTH (32U) 682 #define PSI5_CH_EISR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_EISR_ERROR_SHIFT)) & PSI5_CH_EISR_ERROR_MASK) 683 /*! @} */ 684 685 /*! @name CH_SNDSR - Set New Data Status Register */ 686 /*! @{ */ 687 688 #define PSI5_CH_SNDSR_SNDS_MASK (0xFFFFFFFFU) 689 #define PSI5_CH_SNDSR_SNDS_SHIFT (0U) 690 #define PSI5_CH_SNDSR_SNDS_WIDTH (32U) 691 #define PSI5_CH_SNDSR_SNDS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SNDSR_SNDS_SHIFT)) & PSI5_CH_SNDSR_SNDS_MASK) 692 /*! @} */ 693 694 /*! @name CH_SOWSR - Set Overwrite Status Register */ 695 /*! @{ */ 696 697 #define PSI5_CH_SOWSR_SOWS_MASK (0xFFFFFFFFU) 698 #define PSI5_CH_SOWSR_SOWS_SHIFT (0U) 699 #define PSI5_CH_SOWSR_SOWS_WIDTH (32U) 700 #define PSI5_CH_SOWSR_SOWS(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SOWSR_SOWS_SHIFT)) & PSI5_CH_SOWSR_SOWS_MASK) 701 /*! @} */ 702 703 /*! @name CH_SEISR - Set Error Status Register */ 704 /*! @{ */ 705 706 #define PSI5_CH_SEISR_SERROR_MASK (0xFFFFFFFFU) 707 #define PSI5_CH_SEISR_SERROR_SHIFT (0U) 708 #define PSI5_CH_SEISR_SERROR_WIDTH (32U) 709 #define PSI5_CH_SEISR_SERROR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SEISR_SERROR_SHIFT)) & PSI5_CH_SEISR_SERROR_MASK) 710 /*! @} */ 711 712 /*! @name CH_SSESR - Set SMC Error Status Register */ 713 /*! @{ */ 714 715 #define PSI5_CH_SSESR_SNVSM_MASK (0x3FU) 716 #define PSI5_CH_SSESR_SNVSM_SHIFT (0U) 717 #define PSI5_CH_SSESR_SNVSM_WIDTH (6U) 718 #define PSI5_CH_SSESR_SNVSM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SSESR_SNVSM_SHIFT)) & PSI5_CH_SSESR_SNVSM_MASK) 719 720 #define PSI5_CH_SSESR_SOWSM_MASK (0x3F00U) 721 #define PSI5_CH_SSESR_SOWSM_SHIFT (8U) 722 #define PSI5_CH_SSESR_SOWSM_WIDTH (6U) 723 #define PSI5_CH_SSESR_SOWSM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SSESR_SOWSM_SHIFT)) & PSI5_CH_SSESR_SOWSM_MASK) 724 725 #define PSI5_CH_SSESR_SCESM_MASK (0x3F000000U) 726 #define PSI5_CH_SSESR_SCESM_SHIFT (24U) 727 #define PSI5_CH_SSESR_SCESM_WIDTH (6U) 728 #define PSI5_CH_SSESR_SCESM(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SSESR_SCESM_SHIFT)) & PSI5_CH_SSESR_SCESM_MASK) 729 /*! @} */ 730 731 /*! @name CH_STSRR - Sync Time Stamp Read Register */ 732 /*! @{ */ 733 734 #define PSI5_CH_STSRR_STSV_MASK (0xFFFFFFU) 735 #define PSI5_CH_STSRR_STSV_SHIFT (0U) 736 #define PSI5_CH_STSRR_STSV_WIDTH (24U) 737 #define PSI5_CH_STSRR_STSV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_STSRR_STSV_SHIFT)) & PSI5_CH_STSRR_STSV_MASK) 738 /*! @} */ 739 740 /*! @name CH_DTSRR - Data Time Stamp Read Register */ 741 /*! @{ */ 742 743 #define PSI5_CH_DTSRR_DTSV_MASK (0xFFFFFFU) 744 #define PSI5_CH_DTSRR_DTSV_SHIFT (0U) 745 #define PSI5_CH_DTSRR_DTSV_WIDTH (24U) 746 #define PSI5_CH_DTSRR_DTSV(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DTSRR_DTSV_SHIFT)) & PSI5_CH_DTSRR_DTSV_MASK) 747 748 #define PSI5_CH_DTSRR_SLOT_COUNTER_MASK (0x7000000U) 749 #define PSI5_CH_DTSRR_SLOT_COUNTER_SHIFT (24U) 750 #define PSI5_CH_DTSRR_SLOT_COUNTER_WIDTH (3U) 751 #define PSI5_CH_DTSRR_SLOT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DTSRR_SLOT_COUNTER_SHIFT)) & PSI5_CH_DTSRR_SLOT_COUNTER_MASK) 752 /*! @} */ 753 754 /*! @name CH_SFCR - Slot n Frame Configuration Register */ 755 /*! @{ */ 756 757 #define PSI5_CH_SFCR_CRCP_MASK (0x1U) 758 #define PSI5_CH_SFCR_CRCP_SHIFT (0U) 759 #define PSI5_CH_SFCR_CRCP_WIDTH (1U) 760 #define PSI5_CH_SFCR_CRCP(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFCR_CRCP_SHIFT)) & PSI5_CH_SFCR_CRCP_MASK) 761 762 #define PSI5_CH_SFCR_DRL_MASK (0x3EU) 763 #define PSI5_CH_SFCR_DRL_SHIFT (1U) 764 #define PSI5_CH_SFCR_DRL_WIDTH (5U) 765 #define PSI5_CH_SFCR_DRL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFCR_DRL_SHIFT)) & PSI5_CH_SFCR_DRL_MASK) 766 767 #define PSI5_CH_SFCR_SMCL_MASK (0x8000U) 768 #define PSI5_CH_SFCR_SMCL_SHIFT (15U) 769 #define PSI5_CH_SFCR_SMCL_WIDTH (1U) 770 #define PSI5_CH_SFCR_SMCL(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFCR_SMCL_SHIFT)) & PSI5_CH_SFCR_SMCL_MASK) 771 772 #define PSI5_CH_SFCR_TS_CAPT_MASK (0x20000U) 773 #define PSI5_CH_SFCR_TS_CAPT_SHIFT (17U) 774 #define PSI5_CH_SFCR_TS_CAPT_WIDTH (1U) 775 #define PSI5_CH_SFCR_TS_CAPT(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFCR_TS_CAPT_SHIFT)) & PSI5_CH_SFCR_TS_CAPT_MASK) 776 777 #define PSI5_CH_SFCR_SLOT_EN_MASK (0x40000U) 778 #define PSI5_CH_SFCR_SLOT_EN_SHIFT (18U) 779 #define PSI5_CH_SFCR_SLOT_EN_WIDTH (1U) 780 #define PSI5_CH_SFCR_SLOT_EN(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SFCR_SLOT_EN_SHIFT)) & PSI5_CH_SFCR_SLOT_EN_MASK) 781 /*! @} */ 782 783 /*! @name CH_S2SBR - Slot 2 Start Boundary Register */ 784 /*! @{ */ 785 786 #define PSI5_CH_S2SBR_S2SBT_MASK (0x7FFFU) 787 #define PSI5_CH_S2SBR_S2SBT_SHIFT (0U) 788 #define PSI5_CH_S2SBR_S2SBT_WIDTH (15U) 789 #define PSI5_CH_S2SBR_S2SBT(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_S2SBR_S2SBT_SHIFT)) & PSI5_CH_S2SBR_S2SBT_MASK) 790 /*! @} */ 791 792 /*! @name CH_S1SBR - Slot 1 Start Boundary Register */ 793 /*! @{ */ 794 795 #define PSI5_CH_S1SBR_S1SBT_MASK (0x7FFFU) 796 #define PSI5_CH_S1SBR_S1SBT_SHIFT (0U) 797 #define PSI5_CH_S1SBR_S1SBT_WIDTH (15U) 798 #define PSI5_CH_S1SBR_S1SBT(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_S1SBR_S1SBT_SHIFT)) & PSI5_CH_S1SBR_S1SBT_MASK) 799 /*! @} */ 800 801 /*! @name CH_S4SBR - Slot 4 Start Boundary Register */ 802 /*! @{ */ 803 804 #define PSI5_CH_S4SBR_S4SBT_MASK (0x7FFFU) 805 #define PSI5_CH_S4SBR_S4SBT_SHIFT (0U) 806 #define PSI5_CH_S4SBR_S4SBT_WIDTH (15U) 807 #define PSI5_CH_S4SBR_S4SBT(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_S4SBR_S4SBT_SHIFT)) & PSI5_CH_S4SBR_S4SBT_MASK) 808 /*! @} */ 809 810 /*! @name CH_S3SBR - Slot 3 Start Boundary Register */ 811 /*! @{ */ 812 813 #define PSI5_CH_S3SBR_S3SBT_MASK (0x7FFFU) 814 #define PSI5_CH_S3SBR_S3SBT_SHIFT (0U) 815 #define PSI5_CH_S3SBR_S3SBT_WIDTH (15U) 816 #define PSI5_CH_S3SBR_S3SBT(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_S3SBR_S3SBT_SHIFT)) & PSI5_CH_S3SBR_S3SBT_MASK) 817 /*! @} */ 818 819 /*! @name CH_S6SBR - Slot 6 Start Boundary Register */ 820 /*! @{ */ 821 822 #define PSI5_CH_S6SBR_S6SBT_MASK (0x7FFFU) 823 #define PSI5_CH_S6SBR_S6SBT_SHIFT (0U) 824 #define PSI5_CH_S6SBR_S6SBT_WIDTH (15U) 825 #define PSI5_CH_S6SBR_S6SBT(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_S6SBR_S6SBT_SHIFT)) & PSI5_CH_S6SBR_S6SBT_MASK) 826 /*! @} */ 827 828 /*! @name CH_S5SBR - Slot 5 Start Boundary Register */ 829 /*! @{ */ 830 831 #define PSI5_CH_S5SBR_S5SBT_MASK (0x7FFFU) 832 #define PSI5_CH_S5SBR_S5SBT_SHIFT (0U) 833 #define PSI5_CH_S5SBR_S5SBT_WIDTH (15U) 834 #define PSI5_CH_S5SBR_S5SBT(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_S5SBR_S5SBT_SHIFT)) & PSI5_CH_S5SBR_S5SBT_MASK) 835 /*! @} */ 836 837 /*! @name CH_SNEBR - Slot n End Boundary Register */ 838 /*! @{ */ 839 840 #define PSI5_CH_SNEBR_SnEBT_MASK (0x7FFFU) 841 #define PSI5_CH_SNEBR_SnEBT_SHIFT (0U) 842 #define PSI5_CH_SNEBR_SnEBT_WIDTH (15U) 843 #define PSI5_CH_SNEBR_SnEBT(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SNEBR_SnEBT_SHIFT)) & PSI5_CH_SNEBR_SnEBT_MASK) 844 845 #define PSI5_CH_SNEBR_SLOT_NO_MASK (0x70000U) 846 #define PSI5_CH_SNEBR_SLOT_NO_SHIFT (16U) 847 #define PSI5_CH_SNEBR_SLOT_NO_WIDTH (3U) 848 #define PSI5_CH_SNEBR_SLOT_NO(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_SNEBR_SLOT_NO_SHIFT)) & PSI5_CH_SNEBR_SLOT_NO_MASK) 849 /*! @} */ 850 851 /*! @name CH_MDDIS_OFF - Manchestor Decoder Disable Offset */ 852 /*! @{ */ 853 854 #define PSI5_CH_MDDIS_OFF_MDDIS_OFF_MASK (0x7FU) 855 #define PSI5_CH_MDDIS_OFF_MDDIS_OFF_SHIFT (0U) 856 #define PSI5_CH_MDDIS_OFF_MDDIS_OFF_WIDTH (7U) 857 #define PSI5_CH_MDDIS_OFF_MDDIS_OFF(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_MDDIS_OFF_MDDIS_OFF_SHIFT)) & PSI5_CH_MDDIS_OFF_MDDIS_OFF_MASK) 858 /*! @} */ 859 860 /*! @name CH_DOBCR - Data Output Block Configuration Register */ 861 /*! @{ */ 862 863 #define PSI5_CH_DOBCR_SW_READY_MASK (0x1U) 864 #define PSI5_CH_DOBCR_SW_READY_SHIFT (0U) 865 #define PSI5_CH_DOBCR_SW_READY_WIDTH (1U) 866 #define PSI5_CH_DOBCR_SW_READY(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_SW_READY_SHIFT)) & PSI5_CH_DOBCR_SW_READY_MASK) 867 868 #define PSI5_CH_DOBCR_OP_SEL_MASK (0x2U) 869 #define PSI5_CH_DOBCR_OP_SEL_SHIFT (1U) 870 #define PSI5_CH_DOBCR_OP_SEL_WIDTH (1U) 871 #define PSI5_CH_DOBCR_OP_SEL(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_OP_SEL_SHIFT)) & PSI5_CH_DOBCR_OP_SEL_MASK) 872 873 #define PSI5_CH_DOBCR_SP_PULSE_SEL_MASK (0x4U) 874 #define PSI5_CH_DOBCR_SP_PULSE_SEL_SHIFT (2U) 875 #define PSI5_CH_DOBCR_SP_PULSE_SEL_WIDTH (1U) 876 #define PSI5_CH_DOBCR_SP_PULSE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_SP_PULSE_SEL_SHIFT)) & PSI5_CH_DOBCR_SP_PULSE_SEL_MASK) 877 878 #define PSI5_CH_DOBCR_GTM_TRIG_SEL_MASK (0x8U) 879 #define PSI5_CH_DOBCR_GTM_TRIG_SEL_SHIFT (3U) 880 #define PSI5_CH_DOBCR_GTM_TRIG_SEL_WIDTH (1U) 881 #define PSI5_CH_DOBCR_GTM_TRIG_SEL(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_GTM_TRIG_SEL_SHIFT)) & PSI5_CH_DOBCR_GTM_TRIG_SEL_MASK) 882 883 #define PSI5_CH_DOBCR_DEFAULT_SYNC_MASK (0x10U) 884 #define PSI5_CH_DOBCR_DEFAULT_SYNC_SHIFT (4U) 885 #define PSI5_CH_DOBCR_DEFAULT_SYNC_WIDTH (1U) 886 #define PSI5_CH_DOBCR_DEFAULT_SYNC(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_DEFAULT_SYNC_SHIFT)) & PSI5_CH_DOBCR_DEFAULT_SYNC_MASK) 887 888 #define PSI5_CH_DOBCR_CMD_TYPE_MASK (0xE0U) 889 #define PSI5_CH_DOBCR_CMD_TYPE_SHIFT (5U) 890 #define PSI5_CH_DOBCR_CMD_TYPE_WIDTH (3U) 891 #define PSI5_CH_DOBCR_CMD_TYPE(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_CMD_TYPE_SHIFT)) & PSI5_CH_DOBCR_CMD_TYPE_MASK) 892 893 #define PSI5_CH_DOBCR_DSR_RST_MASK (0x100U) 894 #define PSI5_CH_DOBCR_DSR_RST_SHIFT (8U) 895 #define PSI5_CH_DOBCR_DSR_RST_WIDTH (1U) 896 #define PSI5_CH_DOBCR_DSR_RST(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_DSR_RST_SHIFT)) & PSI5_CH_DOBCR_DSR_RST_MASK) 897 898 #define PSI5_CH_DOBCR_DBR_RST_MASK (0x200U) 899 #define PSI5_CH_DOBCR_DBR_RST_SHIFT (9U) 900 #define PSI5_CH_DOBCR_DBR_RST_WIDTH (1U) 901 #define PSI5_CH_DOBCR_DBR_RST(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_DBR_RST_SHIFT)) & PSI5_CH_DOBCR_DBR_RST_MASK) 902 903 #define PSI5_CH_DOBCR_DATA_LENGTH_MASK (0xFC00U) 904 #define PSI5_CH_DOBCR_DATA_LENGTH_SHIFT (10U) 905 #define PSI5_CH_DOBCR_DATA_LENGTH_WIDTH (6U) 906 #define PSI5_CH_DOBCR_DATA_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_DOBCR_DATA_LENGTH_SHIFT)) & PSI5_CH_DOBCR_DATA_LENGTH_MASK) 907 /*! @} */ 908 909 /*! @name CH_PW1D - Pulse Width for Data Bit Value 1 */ 910 /*! @{ */ 911 912 #define PSI5_CH_PW1D_Pulse_Width1_MASK (0x7FU) 913 #define PSI5_CH_PW1D_Pulse_Width1_SHIFT (0U) 914 #define PSI5_CH_PW1D_Pulse_Width1_WIDTH (7U) 915 #define PSI5_CH_PW1D_Pulse_Width1(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_PW1D_Pulse_Width1_SHIFT)) & PSI5_CH_PW1D_Pulse_Width1_MASK) 916 /*! @} */ 917 918 /*! @name CH_PW0D - Pulse Width for Data Bit Value 0 */ 919 /*! @{ */ 920 921 #define PSI5_CH_PW0D_Pulse_Width0_MASK (0x7FU) 922 #define PSI5_CH_PW0D_Pulse_Width0_SHIFT (0U) 923 #define PSI5_CH_PW0D_Pulse_Width0_WIDTH (7U) 924 #define PSI5_CH_PW0D_Pulse_Width0(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_PW0D_Pulse_Width0_SHIFT)) & PSI5_CH_PW0D_Pulse_Width0_MASK) 925 /*! @} */ 926 927 /*! @name CH_CIPR - Counter Initialize Pulse Register */ 928 /*! @{ */ 929 930 #define PSI5_CH_CIPR_CIPR_MASK (0xFFFFU) 931 #define PSI5_CH_CIPR_CIPR_SHIFT (0U) 932 #define PSI5_CH_CIPR_CIPR_WIDTH (16U) 933 #define PSI5_CH_CIPR_CIPR(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_CIPR_CIPR_SHIFT)) & PSI5_CH_CIPR_CIPR_MASK) 934 /*! @} */ 935 936 /*! @name CH_CTPR - Counter Target Pulse Register */ 937 /*! @{ */ 938 939 #define PSI5_CH_CTPR_CTPR_MASK (0xFFFFU) 940 #define PSI5_CH_CTPR_CTPR_SHIFT (0U) 941 #define PSI5_CH_CTPR_CTPR_WIDTH (16U) 942 #define PSI5_CH_CTPR_CTPR(x) (((uint16_t)(((uint16_t)(x)) << PSI5_CH_CTPR_CTPR_SHIFT)) & PSI5_CH_CTPR_CTPR_MASK) 943 /*! @} */ 944 945 /*! @name CH_DPRL - Data Preparation Register Low */ 946 /*! @{ */ 947 948 #define PSI5_CH_DPRL_DPR_MASK (0xFFFFFFU) 949 #define PSI5_CH_DPRL_DPR_SHIFT (0U) 950 #define PSI5_CH_DPRL_DPR_WIDTH (24U) 951 #define PSI5_CH_DPRL_DPR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DPRL_DPR_SHIFT)) & PSI5_CH_DPRL_DPR_MASK) 952 /*! @} */ 953 954 /*! @name CH_DBRL - Data Buffer Register Low */ 955 /*! @{ */ 956 957 #define PSI5_CH_DBRL_DBR_MASK (0xFFFFFFFFU) 958 #define PSI5_CH_DBRL_DBR_SHIFT (0U) 959 #define PSI5_CH_DBRL_DBR_WIDTH (32U) 960 #define PSI5_CH_DBRL_DBR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DBRL_DBR_SHIFT)) & PSI5_CH_DBRL_DBR_MASK) 961 /*! @} */ 962 963 /*! @name CH_DBRH - Data Buffer Register High */ 964 /*! @{ */ 965 966 #define PSI5_CH_DBRH_DBR_MASK (0xFFFFFFFFU) 967 #define PSI5_CH_DBRH_DBR_SHIFT (0U) 968 #define PSI5_CH_DBRH_DBR_WIDTH (32U) 969 #define PSI5_CH_DBRH_DBR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DBRH_DBR_SHIFT)) & PSI5_CH_DBRH_DBR_MASK) 970 /*! @} */ 971 972 /*! @name CH_DSRL - Data Shift Register Low */ 973 /*! @{ */ 974 975 #define PSI5_CH_DSRL_DSR_MASK (0xFFFFFFFFU) 976 #define PSI5_CH_DSRL_DSR_SHIFT (0U) 977 #define PSI5_CH_DSRL_DSR_WIDTH (32U) 978 #define PSI5_CH_DSRL_DSR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSRL_DSR_SHIFT)) & PSI5_CH_DSRL_DSR_MASK) 979 /*! @} */ 980 981 /*! @name CH_DSRH - Data Shift Register High */ 982 /*! @{ */ 983 984 #define PSI5_CH_DSRH_DSR_MASK (0xFFFFFFFFU) 985 #define PSI5_CH_DSRH_DSR_SHIFT (0U) 986 #define PSI5_CH_DSRH_DSR_WIDTH (32U) 987 #define PSI5_CH_DSRH_DSR(x) (((uint32_t)(((uint32_t)(x)) << PSI5_CH_DSRH_DSR_SHIFT)) & PSI5_CH_DSRH_DSR_MASK) 988 /*! @} */ 989 990 /*! 991 * @} 992 */ /* end of group PSI5_Register_Masks */ 993 994 /*! 995 * @} 996 */ /* end of group PSI5_Peripheral_Access_Layer */ 997 998 #endif /* #if !defined(S32Z2_PSI5_H_) */ 999
