1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MPU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_MPU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MPU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MPU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_MPU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_MPU_Peripheral_Access_Layer S32_MPU Peripheral Access Layer 68 */ 69 /** S32_MPU - Size of Registers Arrays */ 70 #define S32_MPU_A_COUNT 3u 71 #define S32_MPU_MAIR_COUNT 2u 72 73 /** S32_MPU - Register Layout Typedef */ 74 typedef struct { 75 uint8_t RESERVED_0[3472]; 76 __I uint32_t TYPE; /**< MPU Type Register, offset: 0xD90 */ 77 __IO uint32_t CTRL; /**< MPU Control Register, offset: 0xD94 */ 78 __IO uint32_t RNR; /**< MPU Region Number Register, offset: 0xD98 */ 79 __IO uint32_t RBAR; /**< MPU Region Base Address Register, offset: 0xD9C */ 80 __IO uint32_t RLAR; /**< MPU Region Limit Address Register, offset: 0xDA0 */ 81 struct { 82 __IO uint32_t RBAR; /**< MPU RBAR Aliases, array offset: 0xDA4, array step: 0x8 */ 83 __IO uint32_t RLAR; /**< MPU RLAR Aliases, array offset: 0xDA8, array step: 0x8 */ 84 } A[S32_MPU_A_COUNT]; 85 uint8_t RESERVED_1[4]; 86 __IO uint32_t MAIR[S32_MPU_MAIR_COUNT]; /**< MPU Memory Attribute Indirection Register, array offset: 0xDC0, array step: 0x4*/ 87 } S32_MPU_Type, *S32_MPU_MemMapPtr; 88 89 /** Number of instances of the S32_MPU module. */ 90 #define S32_MPU_INSTANCE_COUNT (1u) 91 92 /* S32_MPU - Peripheral instance base addresses */ 93 /** Peripheral S32_MPU base address */ 94 #define IP_S32_MPU_BASE (0xE000E000u) 95 /** Peripheral S32_MPU_NS base address */ 96 #define IP_S32_MPU_NS_BASE (0xE002E000u) 97 /** Peripheral S32_MPU base pointer */ 98 #define S32_MPU ((S32_MPU_Type *)IP_S32_MPU_BASE) 99 /** Peripheral S32_MPU_NS base pointer */ 100 #define S32_MPU_NS ((S32_MPU_Type *)IP_S32_MPU_NS_BASE) 101 /** Array initializer of S32_MPU peripheral base addresses */ 102 #define IP_S32_MPU_BASE_ADDRS { IP_S32_MPU_BASE } 103 /** Array initializer of S32_MPU peripheral base pointers */ 104 #define IP_S32_MPU_BASE_PTRS { IP_S32_MPU } 105 106 /* ---------------------------------------------------------------------------- 107 -- S32_MPU Register Masks 108 ---------------------------------------------------------------------------- */ 109 110 /*! 111 * @addtogroup S32_MPU_Register_Masks S32_MPU Register Masks 112 * @{ 113 */ 114 115 /* TYPE Bit Fields */ 116 #define S32_MPU_TYPE_SEPARATE_MASK 0x1u 117 #define S32_MPU_TYPE_SEPARATE_SHIFT 0u 118 #define S32_MPU_TYPE_SEPARATE_WIDTH 1u 119 #define S32_MPU_TYPE_SEPARATE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_TYPE_SEPARATE_SHIFT))&S32_MPU_TYPE_SEPARATE_MASK) 120 #define S32_MPU_TYPE_DREGION_MASK 0xFF00u 121 #define S32_MPU_TYPE_DREGION_SHIFT 8u 122 #define S32_MPU_TYPE_DREGION_WIDTH 8u 123 #define S32_MPU_TYPE_DREGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_TYPE_DREGION_SHIFT))&S32_MPU_TYPE_DREGION_MASK) 124 #define S32_MPU_TYPE_IREGION_MASK 0xFF0000u 125 #define S32_MPU_TYPE_IREGION_SHIFT 16u 126 #define S32_MPU_TYPE_IREGION_WIDTH 8u 127 #define S32_MPU_TYPE_IREGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_TYPE_IREGION_SHIFT))&S32_MPU_TYPE_IREGION_MASK) 128 /* CTRL Bit Fields */ 129 #define S32_MPU_CTRL_ENABLE_MASK 0x1u 130 #define S32_MPU_CTRL_ENABLE_SHIFT 0u 131 #define S32_MPU_CTRL_ENABLE_WIDTH 1u 132 #define S32_MPU_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_CTRL_ENABLE_SHIFT))&S32_MPU_CTRL_ENABLE_MASK) 133 #define S32_MPU_CTRL_HFNMIENA_MASK 0x2u 134 #define S32_MPU_CTRL_HFNMIENA_SHIFT 1u 135 #define S32_MPU_CTRL_HFNMIENA_WIDTH 1u 136 #define S32_MPU_CTRL_HFNMIENA(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_CTRL_HFNMIENA_SHIFT))&S32_MPU_CTRL_HFNMIENA_MASK) 137 #define S32_MPU_CTRL_PRIVDEFENA_MASK 0x4u 138 #define S32_MPU_CTRL_PRIVDEFENA_SHIFT 2u 139 #define S32_MPU_CTRL_PRIVDEFENA_WIDTH 1u 140 #define S32_MPU_CTRL_PRIVDEFENA(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_CTRL_PRIVDEFENA_SHIFT))&S32_MPU_CTRL_PRIVDEFENA_MASK) 141 /* RNR Bit Fields */ 142 #define S32_MPU_RNR_REGION_MASK 0xFFu 143 #define S32_MPU_RNR_REGION_SHIFT 0u 144 #define S32_MPU_RNR_REGION_WIDTH 8u 145 #define S32_MPU_RNR_REGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RNR_REGION_SHIFT))&S32_MPU_RNR_REGION_MASK) 146 /* RBAR Bit Fields */ 147 #define S32_MPU_RBAR_REGION_MASK 0xFu 148 #define S32_MPU_RBAR_REGION_SHIFT 0u 149 #define S32_MPU_RBAR_REGION_WIDTH 4u 150 #define S32_MPU_RBAR_REGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_REGION_SHIFT))&S32_MPU_RBAR_REGION_MASK) 151 #define S32_MPU_RBAR_VALID_MASK 0x10u 152 #define S32_MPU_RBAR_VALID_SHIFT 4u 153 #define S32_MPU_RBAR_VALID_WIDTH 1u 154 #define S32_MPU_RBAR_VALID(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_VALID_SHIFT))&S32_MPU_RBAR_VALID_MASK) 155 #define S32_MPU_RBAR_ADDR_MASK 0xFFFFFFE0u 156 #define S32_MPU_RBAR_ADDR_SHIFT 5u 157 #define S32_MPU_RBAR_ADDR_WIDTH 27u 158 #define S32_MPU_RBAR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_ADDR_SHIFT))&S32_MPU_RBAR_ADDR_MASK) 159 /* RLAR Bit Fields */ 160 #define S32_MPU_RLAR_ENABLE_MASK 0x1u 161 #define S32_MPU_RLAR_ENABLE_SHIFT 0u 162 #define S32_MPU_RLAR_ENABLE_WIDTH 1u 163 #define S32_MPU_RLAR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RLAR_ENABLE_SHIFT))&S32_MPU_RLAR_ENABLE_MASK) 164 #define S32_MPU_RLAR_ATTRINDX_MASK 0xEu 165 #define S32_MPU_RLAR_ATTRINDX_SHIFT 1u 166 #define S32_MPU_RLAR_ATTRINDX_WIDTH 3u 167 #define S32_MPU_RLAR_ATTRINDX(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RLAR_ATTRINDX_SHIFT))&S32_MPU_RLAR_ATTRINDX_MASK) 168 #define S32_MPU_RLAR_LIMIT_MASK 0xFFFFFFE0u 169 #define S32_MPU_RLAR_LIMIT_SHIFT 5u 170 #define S32_MPU_RLAR_LIMIT_WIDTH 27u 171 #define S32_MPU_RLAR_LIMIT(x) (((uint32_t)(x))&S32_MPU_RLAR_LIMIT_MASK) 172 /* A_RBAR Bit Fields */ 173 #define S32_MPU_A_RBAR_REGION_MASK 0xFu 174 #define S32_MPU_A_RBAR_REGION_SHIFT 0u 175 #define S32_MPU_A_RBAR_REGION_WIDTH 4u 176 #define S32_MPU_A_RBAR_REGION(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RBAR_REGION_SHIFT))&S32_MPU_A_RBAR_REGION_MASK) 177 #define S32_MPU_A_RBAR_VALID_MASK 0x10u 178 #define S32_MPU_A_RBAR_VALID_SHIFT 4u 179 #define S32_MPU_A_RBAR_VALID_WIDTH 1u 180 #define S32_MPU_A_RBAR_VALID(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RBAR_VALID_SHIFT))&S32_MPU_A_RBAR_VALID_MASK) 181 #define S32_MPU_A_RBAR_ADDR_MASK 0xFFFFFFE0u 182 #define S32_MPU_A_RBAR_ADDR_SHIFT 5u 183 #define S32_MPU_A_RBAR_ADDR_WIDTH 27u 184 #define S32_MPU_A_RBAR_ADDR(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RBAR_ADDR_SHIFT))&S32_MPU_A_RBAR_ADDR_MASK) 185 /* A_RLAR Bit Fields */ 186 #define S32_MPU_A_RLAR_ENABLE_MASK 0x1u 187 #define S32_MPU_A_RLAR_ENABLE_SHIFT 0u 188 #define S32_MPU_A_RLAR_ENABLE_WIDTH 1u 189 #define S32_MPU_A_RLAR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RLAR_ENABLE_SHIFT))&S32_MPU_A_RLAR_ENABLE_MASK) 190 #define S32_MPU_A_RLAR_ATTRINDX_MASK 0xEu 191 #define S32_MPU_A_RLAR_ATTRINDX_SHIFT 1u 192 #define S32_MPU_A_RLAR_ATTRINDX_WIDTH 3u 193 #define S32_MPU_A_RLAR_ATTRINDX(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RLAR_ATTRINDX_SHIFT))&S32_MPU_A_RLAR_ATTRINDX_MASK) 194 #define S32_MPU_A_RLAR_LIMIT_MASK 0xFFFFFFE0u 195 #define S32_MPU_A_RLAR_LIMIT_SHIFT 5u 196 #define S32_MPU_A_RLAR_LIMIT_WIDTH 27u 197 #define S32_MPU_A_RLAR_LIMIT(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_A_RLAR_LIMIT_SHIFT))&S32_MPU_A_RLAR_LIMIT_MASK) 198 199 #define S32_MPU_RBAR_AP_MASK 0x6u 200 #define S32_MPU_RBAR_AP_SHIFT 1u 201 #define S32_MPU_RBAR_AP_WIDTH 2u 202 #define S32_MPU_RBAR_AP(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_AP_SHIFT))&S32_MPU_RBAR_AP_MASK) 203 #define S32_MPU_RBAR_XN_MASK 0x1u 204 #define S32_MPU_RBAR_XN_SHIFT 0u 205 #define S32_MPU_RBAR_XN_WIDTH 1u 206 #define S32_MPU_RBAR_XN(x) (((uint32_t)(((uint32_t)(x))<<S32_MPU_RBAR_XN_SHIFT))&S32_MPU_RBAR_XN_MASK) 207 /* MAIR Bit Fields */ 208 #define S32_MPU_MAIR_ATTRx_SHIFT(x) ((uint32_t)(8u * ((uint32_t)(x)))) 209 #define S32_MPU_MAIR_ATTRx_MASK(x) ((uint32_t)(0xFFu << ((uint32_t)S32_MPU_MAIR_ATTRx_SHIFT(x)))) 210 #define S32_MPU_MAIR_ATTRx_WIDTH 8u 211 #define S32_MPU_MAIR_ATTRx(x,y) (((uint32_t)(((uint32_t)(y))<<S32_MPU_MAIR_ATTRx_SHIFT(x)))&S32_MPU_MAIR_ATTRx_MASK(x)) 212 213 /*! 214 * @} 215 */ /* end of group S32_MPU_Register_Masks */ 216 217 /*! 218 * @} 219 */ /* end of group S32_MPU_Peripheral_Access_Layer */ 220 221 #endif /* #if !defined(S32Z2_MPU_H_) */ 222
