1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MEW.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_MEW 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MEW_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MEW_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MEW Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MEW_Peripheral_Access_Layer MEW Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MEW - Size of Registers Arrays */ 72 #define MEW_ECC_EERDSR_COUNT 4u 73 74 /** MEW - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t ECC_GLBL_CTRL; /**< AXI ECC Global Control, offset: 0x0 */ 77 __IO uint32_t ECC_MX_EPA; /**< AXI ECC Maximum ECC Protected Address, offset: 0x4 */ 78 __IO uint32_t ECC_MN_EPA; /**< AXI ECC Minimum ECC Protected Address, offset: 0x8 */ 79 __IO uint32_t ECC_LK_PTN; /**< AXI ECC Lock Pattern, offset: 0xC */ 80 __IO uint32_t ECC_ULK_PTN; /**< AXI ECC Unlock Pattern, offset: 0x10 */ 81 uint8_t RESERVED_0[4]; 82 __I uint32_t ECC_EERAR; /**< ECC Error Report Address, offset: 0x18 */ 83 __I uint32_t ECC_EERDSR[MEW_ECC_EERDSR_COUNT]; /**< AXI ECC Error Report Data And Syndrome, array offset: 0x1C, array step: 0x4 */ 84 __IO uint32_t ECC_ERR_IE; /**< AXI ECC Error Interrupt Enable, offset: 0x2C */ 85 __IO uint32_t ECC_ERR_IN_STCLR; /**< AXI ECC Error Interupt Status And Clear, offset: 0x30 */ 86 __IO uint32_t EDC_ERR_IE; /**< AXI EDC Error Interrupt Enable, offset: 0x34 */ 87 __IO uint32_t EDC_ERR_IN_STCLR; /**< AXI EDC Error Interrupt Status And Clear, offset: 0x38 */ 88 uint8_t RESERVED_1[4]; 89 __IO uint32_t ECC_SHD_STAT_CTRL; /**< Shadow Control, RW Path Status And Status Clear, offset: 0x40 */ 90 __I uint32_t ECC_CBL_UNCBL_BIT_EC; /**< Correctable And Uncorrectable Bit Error Counter, offset: 0x44 */ 91 __I uint32_t ECC_CBL_UCBL_BEAT_EC; /**< Correctable And Uncorrectable Beat Error Counter, offset: 0x48 */ 92 uint8_t RESERVED_2[52]; 93 __IO uint32_t ECC_DBG_CTRL; /**< Debug And Debug Control, offset: 0x80 */ 94 } MEW_Type, *MEW_MemMapPtr; 95 96 /** Number of instances of the MEW module. */ 97 #define MEW_INSTANCE_COUNT (2u) 98 99 /* MEW - Peripheral instance base addresses */ 100 /** Peripheral MEW_0_AXI base address */ 101 #define IP_MEW_0_AXI_BASE (0x42380000u) 102 /** Peripheral MEW_0_AXI base pointer */ 103 #define IP_MEW_0_AXI ((MEW_Type *)IP_MEW_0_AXI_BASE) 104 /** Peripheral MEW_1_AXI base address */ 105 #define IP_MEW_1_AXI_BASE (0x42390000u) 106 /** Peripheral MEW_1_AXI base pointer */ 107 #define IP_MEW_1_AXI ((MEW_Type *)IP_MEW_1_AXI_BASE) 108 /** Array initializer of MEW peripheral base addresses */ 109 #define IP_MEW_BASE_ADDRS { IP_MEW_0_AXI_BASE, IP_MEW_1_AXI_BASE } 110 /** Array initializer of MEW peripheral base pointers */ 111 #define IP_MEW_BASE_PTRS { IP_MEW_0_AXI, IP_MEW_1_AXI } 112 113 /* ---------------------------------------------------------------------------- 114 -- MEW Register Masks 115 ---------------------------------------------------------------------------- */ 116 117 /*! 118 * @addtogroup MEW_Register_Masks MEW Register Masks 119 * @{ 120 */ 121 122 /*! @name ECC_GLBL_CTRL - AXI ECC Global Control */ 123 /*! @{ */ 124 125 #define MEW_ECC_GLBL_CTRL_RD_EN_MASK (0x1U) 126 #define MEW_ECC_GLBL_CTRL_RD_EN_SHIFT (0U) 127 #define MEW_ECC_GLBL_CTRL_RD_EN_WIDTH (1U) 128 #define MEW_ECC_GLBL_CTRL_RD_EN(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_GLBL_CTRL_RD_EN_SHIFT)) & MEW_ECC_GLBL_CTRL_RD_EN_MASK) 129 130 #define MEW_ECC_GLBL_CTRL_RD_EDCEN_MASK (0x8U) 131 #define MEW_ECC_GLBL_CTRL_RD_EDCEN_SHIFT (3U) 132 #define MEW_ECC_GLBL_CTRL_RD_EDCEN_WIDTH (1U) 133 #define MEW_ECC_GLBL_CTRL_RD_EDCEN(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_GLBL_CTRL_RD_EDCEN_SHIFT)) & MEW_ECC_GLBL_CTRL_RD_EDCEN_MASK) 134 135 #define MEW_ECC_GLBL_CTRL_WR_EN_MASK (0x10000U) 136 #define MEW_ECC_GLBL_CTRL_WR_EN_SHIFT (16U) 137 #define MEW_ECC_GLBL_CTRL_WR_EN_WIDTH (1U) 138 #define MEW_ECC_GLBL_CTRL_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_GLBL_CTRL_WR_EN_SHIFT)) & MEW_ECC_GLBL_CTRL_WR_EN_MASK) 139 140 #define MEW_ECC_GLBL_CTRL_WR_EDCEN_MASK (0x80000U) 141 #define MEW_ECC_GLBL_CTRL_WR_EDCEN_SHIFT (19U) 142 #define MEW_ECC_GLBL_CTRL_WR_EDCEN_WIDTH (1U) 143 #define MEW_ECC_GLBL_CTRL_WR_EDCEN(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_GLBL_CTRL_WR_EDCEN_SHIFT)) & MEW_ECC_GLBL_CTRL_WR_EDCEN_MASK) 144 /*! @} */ 145 146 /*! @name ECC_MX_EPA - AXI ECC Maximum ECC Protected Address */ 147 /*! @{ */ 148 149 #define MEW_ECC_MX_EPA_MX_EPA_MASK (0xFFFFFFFFU) 150 #define MEW_ECC_MX_EPA_MX_EPA_SHIFT (0U) 151 #define MEW_ECC_MX_EPA_MX_EPA_WIDTH (32U) 152 #define MEW_ECC_MX_EPA_MX_EPA(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_MX_EPA_MX_EPA_SHIFT)) & MEW_ECC_MX_EPA_MX_EPA_MASK) 153 /*! @} */ 154 155 /*! @name ECC_MN_EPA - AXI ECC Minimum ECC Protected Address */ 156 /*! @{ */ 157 158 #define MEW_ECC_MN_EPA_MN_EPA_MASK (0xFFFFFFFFU) 159 #define MEW_ECC_MN_EPA_MN_EPA_SHIFT (0U) 160 #define MEW_ECC_MN_EPA_MN_EPA_WIDTH (32U) 161 #define MEW_ECC_MN_EPA_MN_EPA(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_MN_EPA_MN_EPA_SHIFT)) & MEW_ECC_MN_EPA_MN_EPA_MASK) 162 /*! @} */ 163 164 /*! @name ECC_LK_PTN - AXI ECC Lock Pattern */ 165 /*! @{ */ 166 167 #define MEW_ECC_LK_PTN_LK_PTN_MASK (0xFFFFFFFFU) 168 #define MEW_ECC_LK_PTN_LK_PTN_SHIFT (0U) 169 #define MEW_ECC_LK_PTN_LK_PTN_WIDTH (32U) 170 #define MEW_ECC_LK_PTN_LK_PTN(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_LK_PTN_LK_PTN_SHIFT)) & MEW_ECC_LK_PTN_LK_PTN_MASK) 171 /*! @} */ 172 173 /*! @name ECC_ULK_PTN - AXI ECC Unlock Pattern */ 174 /*! @{ */ 175 176 #define MEW_ECC_ULK_PTN_ULK_PTN_MASK (0xFFFFFFFFU) 177 #define MEW_ECC_ULK_PTN_ULK_PTN_SHIFT (0U) 178 #define MEW_ECC_ULK_PTN_ULK_PTN_WIDTH (32U) 179 #define MEW_ECC_ULK_PTN_ULK_PTN(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ULK_PTN_ULK_PTN_SHIFT)) & MEW_ECC_ULK_PTN_ULK_PTN_MASK) 180 /*! @} */ 181 182 /*! @name ECC_EERAR - ECC Error Report Address */ 183 /*! @{ */ 184 185 #define MEW_ECC_EERAR_EERA_MASK (0xFFFFFFFFU) 186 #define MEW_ECC_EERAR_EERA_SHIFT (0U) 187 #define MEW_ECC_EERAR_EERA_WIDTH (32U) 188 #define MEW_ECC_EERAR_EERA(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_EERAR_EERA_SHIFT)) & MEW_ECC_EERAR_EERA_MASK) 189 /*! @} */ 190 191 /*! @name ECC_EERDSR - AXI ECC Error Report Data And Syndrome */ 192 /*! @{ */ 193 194 #define MEW_ECC_EERDSR_EERD_MASK (0xFFU) 195 #define MEW_ECC_EERDSR_EERD_SHIFT (0U) 196 #define MEW_ECC_EERDSR_EERD_WIDTH (8U) 197 #define MEW_ECC_EERDSR_EERD(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_EERDSR_EERD_SHIFT)) & MEW_ECC_EERDSR_EERD_MASK) 198 199 #define MEW_ECC_EERDSR_EECC_MASK (0xFF00U) 200 #define MEW_ECC_EERDSR_EECC_SHIFT (8U) 201 #define MEW_ECC_EERDSR_EECC_WIDTH (8U) 202 #define MEW_ECC_EERDSR_EECC(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_EERDSR_EECC_SHIFT)) & MEW_ECC_EERDSR_EECC_MASK) 203 204 #define MEW_ECC_EERDSR_EERS_MASK (0xFF0000U) 205 #define MEW_ECC_EERDSR_EERS_SHIFT (16U) 206 #define MEW_ECC_EERDSR_EERS_WIDTH (8U) 207 #define MEW_ECC_EERDSR_EERS(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_EERDSR_EERS_SHIFT)) & MEW_ECC_EERDSR_EERS_MASK) 208 /*! @} */ 209 210 /*! @name ECC_ERR_IE - AXI ECC Error Interrupt Enable */ 211 /*! @{ */ 212 213 #define MEW_ECC_ERR_IE_NCE_IE1_MASK (0x1U) 214 #define MEW_ECC_ERR_IE_NCE_IE1_SHIFT (0U) 215 #define MEW_ECC_ERR_IE_NCE_IE1_WIDTH (1U) 216 #define MEW_ECC_ERR_IE_NCE_IE1(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_NCE_IE1_SHIFT)) & MEW_ECC_ERR_IE_NCE_IE1_MASK) 217 218 #define MEW_ECC_ERR_IE_NCE_IE2_MASK (0x2U) 219 #define MEW_ECC_ERR_IE_NCE_IE2_SHIFT (1U) 220 #define MEW_ECC_ERR_IE_NCE_IE2_WIDTH (1U) 221 #define MEW_ECC_ERR_IE_NCE_IE2(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_NCE_IE2_SHIFT)) & MEW_ECC_ERR_IE_NCE_IE2_MASK) 222 223 #define MEW_ECC_ERR_IE_NCE_IE3_MASK (0x4U) 224 #define MEW_ECC_ERR_IE_NCE_IE3_SHIFT (2U) 225 #define MEW_ECC_ERR_IE_NCE_IE3_WIDTH (1U) 226 #define MEW_ECC_ERR_IE_NCE_IE3(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_NCE_IE3_SHIFT)) & MEW_ECC_ERR_IE_NCE_IE3_MASK) 227 228 #define MEW_ECC_ERR_IE_NCE_IE4_MASK (0x8U) 229 #define MEW_ECC_ERR_IE_NCE_IE4_SHIFT (3U) 230 #define MEW_ECC_ERR_IE_NCE_IE4_WIDTH (1U) 231 #define MEW_ECC_ERR_IE_NCE_IE4(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_NCE_IE4_SHIFT)) & MEW_ECC_ERR_IE_NCE_IE4_MASK) 232 233 #define MEW_ECC_ERR_IE_CE_IE1_MASK (0x10000U) 234 #define MEW_ECC_ERR_IE_CE_IE1_SHIFT (16U) 235 #define MEW_ECC_ERR_IE_CE_IE1_WIDTH (1U) 236 #define MEW_ECC_ERR_IE_CE_IE1(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_CE_IE1_SHIFT)) & MEW_ECC_ERR_IE_CE_IE1_MASK) 237 238 #define MEW_ECC_ERR_IE_CE_IE2_MASK (0x20000U) 239 #define MEW_ECC_ERR_IE_CE_IE2_SHIFT (17U) 240 #define MEW_ECC_ERR_IE_CE_IE2_WIDTH (1U) 241 #define MEW_ECC_ERR_IE_CE_IE2(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_CE_IE2_SHIFT)) & MEW_ECC_ERR_IE_CE_IE2_MASK) 242 243 #define MEW_ECC_ERR_IE_CE_IE3_MASK (0x40000U) 244 #define MEW_ECC_ERR_IE_CE_IE3_SHIFT (18U) 245 #define MEW_ECC_ERR_IE_CE_IE3_WIDTH (1U) 246 #define MEW_ECC_ERR_IE_CE_IE3(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_CE_IE3_SHIFT)) & MEW_ECC_ERR_IE_CE_IE3_MASK) 247 248 #define MEW_ECC_ERR_IE_CE_IE4_MASK (0x80000U) 249 #define MEW_ECC_ERR_IE_CE_IE4_SHIFT (19U) 250 #define MEW_ECC_ERR_IE_CE_IE4_WIDTH (1U) 251 #define MEW_ECC_ERR_IE_CE_IE4(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IE_CE_IE4_SHIFT)) & MEW_ECC_ERR_IE_CE_IE4_MASK) 252 /*! @} */ 253 254 /*! @name ECC_ERR_IN_STCLR - AXI ECC Error Interupt Status And Clear */ 255 /*! @{ */ 256 257 #define MEW_ECC_ERR_IN_STCLR_NCE_IF1_MASK (0x1U) 258 #define MEW_ECC_ERR_IN_STCLR_NCE_IF1_SHIFT (0U) 259 #define MEW_ECC_ERR_IN_STCLR_NCE_IF1_WIDTH (1U) 260 #define MEW_ECC_ERR_IN_STCLR_NCE_IF1(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_NCE_IF1_SHIFT)) & MEW_ECC_ERR_IN_STCLR_NCE_IF1_MASK) 261 262 #define MEW_ECC_ERR_IN_STCLR_NCE_IF2_MASK (0x2U) 263 #define MEW_ECC_ERR_IN_STCLR_NCE_IF2_SHIFT (1U) 264 #define MEW_ECC_ERR_IN_STCLR_NCE_IF2_WIDTH (1U) 265 #define MEW_ECC_ERR_IN_STCLR_NCE_IF2(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_NCE_IF2_SHIFT)) & MEW_ECC_ERR_IN_STCLR_NCE_IF2_MASK) 266 267 #define MEW_ECC_ERR_IN_STCLR_NCE_IF3_MASK (0x4U) 268 #define MEW_ECC_ERR_IN_STCLR_NCE_IF3_SHIFT (2U) 269 #define MEW_ECC_ERR_IN_STCLR_NCE_IF3_WIDTH (1U) 270 #define MEW_ECC_ERR_IN_STCLR_NCE_IF3(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_NCE_IF3_SHIFT)) & MEW_ECC_ERR_IN_STCLR_NCE_IF3_MASK) 271 272 #define MEW_ECC_ERR_IN_STCLR_NCE_IF4_MASK (0x8U) 273 #define MEW_ECC_ERR_IN_STCLR_NCE_IF4_SHIFT (3U) 274 #define MEW_ECC_ERR_IN_STCLR_NCE_IF4_WIDTH (1U) 275 #define MEW_ECC_ERR_IN_STCLR_NCE_IF4(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_NCE_IF4_SHIFT)) & MEW_ECC_ERR_IN_STCLR_NCE_IF4_MASK) 276 277 #define MEW_ECC_ERR_IN_STCLR_CE_IF1_MASK (0x10000U) 278 #define MEW_ECC_ERR_IN_STCLR_CE_IF1_SHIFT (16U) 279 #define MEW_ECC_ERR_IN_STCLR_CE_IF1_WIDTH (1U) 280 #define MEW_ECC_ERR_IN_STCLR_CE_IF1(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_CE_IF1_SHIFT)) & MEW_ECC_ERR_IN_STCLR_CE_IF1_MASK) 281 282 #define MEW_ECC_ERR_IN_STCLR_CE_IF2_MASK (0x20000U) 283 #define MEW_ECC_ERR_IN_STCLR_CE_IF2_SHIFT (17U) 284 #define MEW_ECC_ERR_IN_STCLR_CE_IF2_WIDTH (1U) 285 #define MEW_ECC_ERR_IN_STCLR_CE_IF2(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_CE_IF2_SHIFT)) & MEW_ECC_ERR_IN_STCLR_CE_IF2_MASK) 286 287 #define MEW_ECC_ERR_IN_STCLR_CE_IF3_MASK (0x40000U) 288 #define MEW_ECC_ERR_IN_STCLR_CE_IF3_SHIFT (18U) 289 #define MEW_ECC_ERR_IN_STCLR_CE_IF3_WIDTH (1U) 290 #define MEW_ECC_ERR_IN_STCLR_CE_IF3(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_CE_IF3_SHIFT)) & MEW_ECC_ERR_IN_STCLR_CE_IF3_MASK) 291 292 #define MEW_ECC_ERR_IN_STCLR_CE_IF4_MASK (0x80000U) 293 #define MEW_ECC_ERR_IN_STCLR_CE_IF4_SHIFT (19U) 294 #define MEW_ECC_ERR_IN_STCLR_CE_IF4_WIDTH (1U) 295 #define MEW_ECC_ERR_IN_STCLR_CE_IF4(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_ERR_IN_STCLR_CE_IF4_SHIFT)) & MEW_ECC_ERR_IN_STCLR_CE_IF4_MASK) 296 /*! @} */ 297 298 /*! @name EDC_ERR_IE - AXI EDC Error Interrupt Enable */ 299 /*! @{ */ 300 301 #define MEW_EDC_ERR_IE_EDC_EIE1_MASK (0x1U) 302 #define MEW_EDC_ERR_IE_EDC_EIE1_SHIFT (0U) 303 #define MEW_EDC_ERR_IE_EDC_EIE1_WIDTH (1U) 304 #define MEW_EDC_ERR_IE_EDC_EIE1(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_EIE1_SHIFT)) & MEW_EDC_ERR_IE_EDC_EIE1_MASK) 305 306 #define MEW_EDC_ERR_IE_EDC_EIE2_MASK (0x2U) 307 #define MEW_EDC_ERR_IE_EDC_EIE2_SHIFT (1U) 308 #define MEW_EDC_ERR_IE_EDC_EIE2_WIDTH (1U) 309 #define MEW_EDC_ERR_IE_EDC_EIE2(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_EIE2_SHIFT)) & MEW_EDC_ERR_IE_EDC_EIE2_MASK) 310 311 #define MEW_EDC_ERR_IE_EDC_EIE3_MASK (0x4U) 312 #define MEW_EDC_ERR_IE_EDC_EIE3_SHIFT (2U) 313 #define MEW_EDC_ERR_IE_EDC_EIE3_WIDTH (1U) 314 #define MEW_EDC_ERR_IE_EDC_EIE3(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_EIE3_SHIFT)) & MEW_EDC_ERR_IE_EDC_EIE3_MASK) 315 316 #define MEW_EDC_ERR_IE_EDC_EIE4_MASK (0x8U) 317 #define MEW_EDC_ERR_IE_EDC_EIE4_SHIFT (3U) 318 #define MEW_EDC_ERR_IE_EDC_EIE4_WIDTH (1U) 319 #define MEW_EDC_ERR_IE_EDC_EIE4(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_EIE4_SHIFT)) & MEW_EDC_ERR_IE_EDC_EIE4_MASK) 320 321 #define MEW_EDC_ERR_IE_EDC_DIE1_MASK (0x10000U) 322 #define MEW_EDC_ERR_IE_EDC_DIE1_SHIFT (16U) 323 #define MEW_EDC_ERR_IE_EDC_DIE1_WIDTH (1U) 324 #define MEW_EDC_ERR_IE_EDC_DIE1(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_DIE1_SHIFT)) & MEW_EDC_ERR_IE_EDC_DIE1_MASK) 325 326 #define MEW_EDC_ERR_IE_EDC_DIE2_MASK (0x20000U) 327 #define MEW_EDC_ERR_IE_EDC_DIE2_SHIFT (17U) 328 #define MEW_EDC_ERR_IE_EDC_DIE2_WIDTH (1U) 329 #define MEW_EDC_ERR_IE_EDC_DIE2(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_DIE2_SHIFT)) & MEW_EDC_ERR_IE_EDC_DIE2_MASK) 330 331 #define MEW_EDC_ERR_IE_EDC_DIE3_MASK (0x40000U) 332 #define MEW_EDC_ERR_IE_EDC_DIE3_SHIFT (18U) 333 #define MEW_EDC_ERR_IE_EDC_DIE3_WIDTH (1U) 334 #define MEW_EDC_ERR_IE_EDC_DIE3(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_DIE3_SHIFT)) & MEW_EDC_ERR_IE_EDC_DIE3_MASK) 335 336 #define MEW_EDC_ERR_IE_EDC_DIE4_MASK (0x80000U) 337 #define MEW_EDC_ERR_IE_EDC_DIE4_SHIFT (19U) 338 #define MEW_EDC_ERR_IE_EDC_DIE4_WIDTH (1U) 339 #define MEW_EDC_ERR_IE_EDC_DIE4(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IE_EDC_DIE4_SHIFT)) & MEW_EDC_ERR_IE_EDC_DIE4_MASK) 340 /*! @} */ 341 342 /*! @name EDC_ERR_IN_STCLR - AXI EDC Error Interrupt Status And Clear */ 343 /*! @{ */ 344 345 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC1_MASK (0x1U) 346 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC1_SHIFT (0U) 347 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC1_WIDTH (1U) 348 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC1(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_ENC1_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_ENC1_MASK) 349 350 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC2_MASK (0x2U) 351 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC2_SHIFT (1U) 352 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC2_WIDTH (1U) 353 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC2(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_ENC2_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_ENC2_MASK) 354 355 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC3_MASK (0x4U) 356 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC3_SHIFT (2U) 357 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC3_WIDTH (1U) 358 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC3(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_ENC3_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_ENC3_MASK) 359 360 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC4_MASK (0x8U) 361 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC4_SHIFT (3U) 362 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC4_WIDTH (1U) 363 #define MEW_EDC_ERR_IN_STCLR_EDC_ENC4(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_ENC4_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_ENC4_MASK) 364 365 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC1_MASK (0x10000U) 366 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC1_SHIFT (16U) 367 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC1_WIDTH (1U) 368 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC1(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_DEC1_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_DEC1_MASK) 369 370 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC2_MASK (0x20000U) 371 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC2_SHIFT (17U) 372 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC2_WIDTH (1U) 373 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC2(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_DEC2_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_DEC2_MASK) 374 375 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC3_MASK (0x40000U) 376 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC3_SHIFT (18U) 377 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC3_WIDTH (1U) 378 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC3(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_DEC3_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_DEC3_MASK) 379 380 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC4_MASK (0x80000U) 381 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC4_SHIFT (19U) 382 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC4_WIDTH (1U) 383 #define MEW_EDC_ERR_IN_STCLR_EDC_DEC4(x) (((uint32_t)(((uint32_t)(x)) << MEW_EDC_ERR_IN_STCLR_EDC_DEC4_SHIFT)) & MEW_EDC_ERR_IN_STCLR_EDC_DEC4_MASK) 384 /*! @} */ 385 386 /*! @name ECC_SHD_STAT_CTRL - Shadow Control, RW Path Status And Status Clear */ 387 /*! @{ */ 388 389 #define MEW_ECC_SHD_STAT_CTRL_STAT_CLR_MASK (0x1U) 390 #define MEW_ECC_SHD_STAT_CTRL_STAT_CLR_SHIFT (0U) 391 #define MEW_ECC_SHD_STAT_CTRL_STAT_CLR_WIDTH (1U) 392 #define MEW_ECC_SHD_STAT_CTRL_STAT_CLR(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_STAT_CLR_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_STAT_CLR_MASK) 393 394 #define MEW_ECC_SHD_STAT_CTRL_COUNT_CLR_MASK (0x2U) 395 #define MEW_ECC_SHD_STAT_CTRL_COUNT_CLR_SHIFT (1U) 396 #define MEW_ECC_SHD_STAT_CTRL_COUNT_CLR_WIDTH (1U) 397 #define MEW_ECC_SHD_STAT_CTRL_COUNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_COUNT_CLR_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_COUNT_CLR_MASK) 398 399 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_FULL_MASK (0x100U) 400 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_FULL_SHIFT (8U) 401 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_FULL_WIDTH (1U) 402 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_FULL(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_RD_TX_FULL_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_RD_TX_FULL_MASK) 403 404 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_FULL_MASK (0x200U) 405 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_FULL_SHIFT (9U) 406 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_FULL_WIDTH (1U) 407 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_FULL(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_WR_TX_FULL_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_WR_TX_FULL_MASK) 408 409 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_FULL_MASK (0x400U) 410 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_FULL_SHIFT (10U) 411 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_FULL_WIDTH (1U) 412 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_FULL(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_WR_RES_FULL_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_WR_RES_FULL_MASK) 413 414 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_EMP_MASK (0x10000U) 415 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_EMP_SHIFT (16U) 416 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_EMP_WIDTH (1U) 417 #define MEW_ECC_SHD_STAT_CTRL_RD_TX_EMP(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_RD_TX_EMP_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_RD_TX_EMP_MASK) 418 419 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_EMP_MASK (0x20000U) 420 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_EMP_SHIFT (17U) 421 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_EMP_WIDTH (1U) 422 #define MEW_ECC_SHD_STAT_CTRL_WR_TX_EMP(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_WR_TX_EMP_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_WR_TX_EMP_MASK) 423 424 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_EMP_MASK (0x40000U) 425 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_EMP_SHIFT (18U) 426 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_EMP_WIDTH (1U) 427 #define MEW_ECC_SHD_STAT_CTRL_WR_RES_EMP(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_WR_RES_EMP_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_WR_RES_EMP_MASK) 428 429 #define MEW_ECC_SHD_STAT_CTRL_SHD_RGN_SLT_MASK (0x1000000U) 430 #define MEW_ECC_SHD_STAT_CTRL_SHD_RGN_SLT_SHIFT (24U) 431 #define MEW_ECC_SHD_STAT_CTRL_SHD_RGN_SLT_WIDTH (1U) 432 #define MEW_ECC_SHD_STAT_CTRL_SHD_RGN_SLT(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_SHD_STAT_CTRL_SHD_RGN_SLT_SHIFT)) & MEW_ECC_SHD_STAT_CTRL_SHD_RGN_SLT_MASK) 433 /*! @} */ 434 435 /*! @name ECC_CBL_UNCBL_BIT_EC - Correctable And Uncorrectable Bit Error Counter */ 436 /*! @{ */ 437 438 #define MEW_ECC_CBL_UNCBL_BIT_EC_CLB_BIT_EC_MASK (0x7FFFU) 439 #define MEW_ECC_CBL_UNCBL_BIT_EC_CLB_BIT_EC_SHIFT (0U) 440 #define MEW_ECC_CBL_UNCBL_BIT_EC_CLB_BIT_EC_WIDTH (15U) 441 #define MEW_ECC_CBL_UNCBL_BIT_EC_CLB_BIT_EC(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UNCBL_BIT_EC_CLB_BIT_EC_SHIFT)) & MEW_ECC_CBL_UNCBL_BIT_EC_CLB_BIT_EC_MASK) 442 443 #define MEW_ECC_CBL_UNCBL_BIT_EC_CBL_BIT_OF_MASK (0x8000U) 444 #define MEW_ECC_CBL_UNCBL_BIT_EC_CBL_BIT_OF_SHIFT (15U) 445 #define MEW_ECC_CBL_UNCBL_BIT_EC_CBL_BIT_OF_WIDTH (1U) 446 #define MEW_ECC_CBL_UNCBL_BIT_EC_CBL_BIT_OF(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UNCBL_BIT_EC_CBL_BIT_OF_SHIFT)) & MEW_ECC_CBL_UNCBL_BIT_EC_CBL_BIT_OF_MASK) 447 448 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_EC_MASK (0x7FFF0000U) 449 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_EC_SHIFT (16U) 450 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_EC_WIDTH (15U) 451 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_EC(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_EC_SHIFT)) & MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_EC_MASK) 452 453 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_OF_MASK (0x80000000U) 454 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_OF_SHIFT (31U) 455 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_OF_WIDTH (1U) 456 #define MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_OF(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_OF_SHIFT)) & MEW_ECC_CBL_UNCBL_BIT_EC_UCBL_BIT_OF_MASK) 457 /*! @} */ 458 459 /*! @name ECC_CBL_UCBL_BEAT_EC - Correctable And Uncorrectable Beat Error Counter */ 460 /*! @{ */ 461 462 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_EC_MASK (0x7FFFU) 463 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_EC_SHIFT (0U) 464 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_EC_WIDTH (15U) 465 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_EC(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_EC_SHIFT)) & MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_EC_MASK) 466 467 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_OF_MASK (0x8000U) 468 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_OF_SHIFT (15U) 469 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_OF_WIDTH (1U) 470 #define MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_OF(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_OF_SHIFT)) & MEW_ECC_CBL_UCBL_BEAT_EC_CBL_BEAT_OF_MASK) 471 472 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_EC_MASK (0x7FFF0000U) 473 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_EC_SHIFT (16U) 474 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_EC_WIDTH (15U) 475 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_EC(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_EC_SHIFT)) & MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_EC_MASK) 476 477 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_OF_MASK (0x80000000U) 478 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_OF_SHIFT (31U) 479 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_OF_WIDTH (1U) 480 #define MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_OF(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_OF_SHIFT)) & MEW_ECC_CBL_UCBL_BEAT_EC_UCBL_BEAT_OF_MASK) 481 /*! @} */ 482 483 /*! @name ECC_DBG_CTRL - Debug And Debug Control */ 484 /*! @{ */ 485 486 #define MEW_ECC_DBG_CTRL_ADD_EN_ECC_DIS_MASK (0x1U) 487 #define MEW_ECC_DBG_CTRL_ADD_EN_ECC_DIS_SHIFT (0U) 488 #define MEW_ECC_DBG_CTRL_ADD_EN_ECC_DIS_WIDTH (1U) 489 #define MEW_ECC_DBG_CTRL_ADD_EN_ECC_DIS(x) (((uint32_t)(((uint32_t)(x)) << MEW_ECC_DBG_CTRL_ADD_EN_ECC_DIS_SHIFT)) & MEW_ECC_DBG_CTRL_ADD_EN_ECC_DIS_MASK) 490 /*! @} */ 491 492 /*! 493 * @} 494 */ /* end of group MEW_Register_Masks */ 495 496 /*! 497 * @} 498 */ /* end of group MEW_Peripheral_Access_Layer */ 499 500 #endif /* #if !defined(S32Z2_MEW_H_) */ 501
