1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MC_RGM.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_MC_RGM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MC_RGM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MC_RGM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MC_RGM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MC_RGM_Peripheral_Access_Layer MC_RGM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MC_RGM - Size of Registers Arrays */ 72 #define MC_RGM_PRST_0_COUNT 3u 73 #define MC_RGM_PSTAT_0_COUNT 3u 74 75 /** MC_RGM - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t DES; /**< Destructive Event Status Register, offset: 0x0 */ 78 uint8_t RESERVED_0[4]; 79 __IO uint32_t FES; /**< Functional /External Reset Status Register, offset: 0x8 */ 80 __IO uint32_t FERD; /**< Functional Event Reset Disable Register, offset: 0xC */ 81 __I uint32_t FBRE; /**< Functional Bidirectional Reset Enable Register, offset: 0x10 */ 82 __IO uint32_t FREC; /**< Functional Reset Escalation Counter Register, offset: 0x14 */ 83 __IO uint32_t FRET; /**< Functional Reset Escalation Threshold Register, offset: 0x18 */ 84 __IO uint32_t DRET; /**< Destructive Reset Escalation Threshold Register, offset: 0x1C */ 85 __IO uint32_t ERCTRL; /**< External Reset Control Register, offset: 0x20 */ 86 uint8_t RESERVED_1[4]; 87 __IO uint32_t FRENTC; /**< Functional Reset Entry Timeout Control Register, offset: 0x28 */ 88 uint8_t RESERVED_2[20]; 89 struct MC_RGM_PRST_0 { /* offset: 0x40, array step: 0x8 */ 90 __IO uint32_t PRST_0; /**< Peripheral Reset, array offset: 0x40, array step: 0x8 */ 91 uint8_t RESERVED_0[4]; 92 } PRST_0[MC_RGM_PRST_0_COUNT]; 93 uint8_t RESERVED_3[232]; 94 struct MC_RGM_PSTAT_0 { /* offset: 0x140, array step: 0x8 */ 95 __I uint32_t PSTAT_0; /**< Peripheral Reset Status Register, array offset: 0x140, array step: 0x8 */ 96 uint8_t RESERVED_0[4]; 97 } PSTAT_0[MC_RGM_PSTAT_0_COUNT]; 98 } MC_RGM_Type, *MC_RGM_MemMapPtr; 99 100 /** Number of instances of the MC_RGM module. */ 101 #define MC_RGM_INSTANCE_COUNT (1u) 102 103 /* MC_RGM - Peripheral instance base addresses */ 104 /** Peripheral MC_RGM base address */ 105 #define IP_MC_RGM_BASE (0x41850000u) 106 /** Peripheral MC_RGM base pointer */ 107 #define IP_MC_RGM ((MC_RGM_Type *)IP_MC_RGM_BASE) 108 /** Array initializer of MC_RGM peripheral base addresses */ 109 #define IP_MC_RGM_BASE_ADDRS { IP_MC_RGM_BASE } 110 /** Array initializer of MC_RGM peripheral base pointers */ 111 #define IP_MC_RGM_BASE_PTRS { IP_MC_RGM } 112 113 /* ---------------------------------------------------------------------------- 114 -- MC_RGM Register Masks 115 ---------------------------------------------------------------------------- */ 116 117 /*! 118 * @addtogroup MC_RGM_Register_Masks MC_RGM Register Masks 119 * @{ 120 */ 121 122 /*! @name DES - Destructive Event Status Register */ 123 /*! @{ */ 124 125 #define MC_RGM_DES_F_POR_MASK (0x1U) 126 #define MC_RGM_DES_F_POR_SHIFT (0U) 127 #define MC_RGM_DES_F_POR_WIDTH (1U) 128 #define MC_RGM_DES_F_POR(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_POR_SHIFT)) & MC_RGM_DES_F_POR_MASK) 129 130 #define MC_RGM_DES_F_DR_1_MASK (0x2U) 131 #define MC_RGM_DES_F_DR_1_SHIFT (1U) 132 #define MC_RGM_DES_F_DR_1_WIDTH (1U) 133 #define MC_RGM_DES_F_DR_1(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_1_SHIFT)) & MC_RGM_DES_F_DR_1_MASK) 134 135 #define MC_RGM_DES_F_DR_3_MASK (0x8U) 136 #define MC_RGM_DES_F_DR_3_SHIFT (3U) 137 #define MC_RGM_DES_F_DR_3_WIDTH (1U) 138 #define MC_RGM_DES_F_DR_3(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_3_SHIFT)) & MC_RGM_DES_F_DR_3_MASK) 139 140 #define MC_RGM_DES_F_DR_4_MASK (0x10U) 141 #define MC_RGM_DES_F_DR_4_SHIFT (4U) 142 #define MC_RGM_DES_F_DR_4_WIDTH (1U) 143 #define MC_RGM_DES_F_DR_4(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_4_SHIFT)) & MC_RGM_DES_F_DR_4_MASK) 144 145 #define MC_RGM_DES_F_DR_6_MASK (0x40U) 146 #define MC_RGM_DES_F_DR_6_SHIFT (6U) 147 #define MC_RGM_DES_F_DR_6_WIDTH (1U) 148 #define MC_RGM_DES_F_DR_6(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_6_SHIFT)) & MC_RGM_DES_F_DR_6_MASK) 149 150 #define MC_RGM_DES_F_DR_8_MASK (0x100U) 151 #define MC_RGM_DES_F_DR_8_SHIFT (8U) 152 #define MC_RGM_DES_F_DR_8_WIDTH (1U) 153 #define MC_RGM_DES_F_DR_8(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_8_SHIFT)) & MC_RGM_DES_F_DR_8_MASK) 154 155 #define MC_RGM_DES_F_DR_9_MASK (0x200U) 156 #define MC_RGM_DES_F_DR_9_SHIFT (9U) 157 #define MC_RGM_DES_F_DR_9_WIDTH (1U) 158 #define MC_RGM_DES_F_DR_9(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_9_SHIFT)) & MC_RGM_DES_F_DR_9_MASK) 159 160 #define MC_RGM_DES_F_DR_10_MASK (0x400U) 161 #define MC_RGM_DES_F_DR_10_SHIFT (10U) 162 #define MC_RGM_DES_F_DR_10_WIDTH (1U) 163 #define MC_RGM_DES_F_DR_10(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_10_SHIFT)) & MC_RGM_DES_F_DR_10_MASK) 164 165 #define MC_RGM_DES_F_DR_11_MASK (0x800U) 166 #define MC_RGM_DES_F_DR_11_SHIFT (11U) 167 #define MC_RGM_DES_F_DR_11_WIDTH (1U) 168 #define MC_RGM_DES_F_DR_11(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_11_SHIFT)) & MC_RGM_DES_F_DR_11_MASK) 169 170 #define MC_RGM_DES_F_DR_12_MASK (0x1000U) 171 #define MC_RGM_DES_F_DR_12_SHIFT (12U) 172 #define MC_RGM_DES_F_DR_12_WIDTH (1U) 173 #define MC_RGM_DES_F_DR_12(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_12_SHIFT)) & MC_RGM_DES_F_DR_12_MASK) 174 175 #define MC_RGM_DES_F_DR_13_MASK (0x2000U) 176 #define MC_RGM_DES_F_DR_13_SHIFT (13U) 177 #define MC_RGM_DES_F_DR_13_WIDTH (1U) 178 #define MC_RGM_DES_F_DR_13(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_13_SHIFT)) & MC_RGM_DES_F_DR_13_MASK) 179 180 #define MC_RGM_DES_F_DR_14_MASK (0x4000U) 181 #define MC_RGM_DES_F_DR_14_SHIFT (14U) 182 #define MC_RGM_DES_F_DR_14_WIDTH (1U) 183 #define MC_RGM_DES_F_DR_14(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_14_SHIFT)) & MC_RGM_DES_F_DR_14_MASK) 184 185 #define MC_RGM_DES_F_DR_15_MASK (0x8000U) 186 #define MC_RGM_DES_F_DR_15_SHIFT (15U) 187 #define MC_RGM_DES_F_DR_15_WIDTH (1U) 188 #define MC_RGM_DES_F_DR_15(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_15_SHIFT)) & MC_RGM_DES_F_DR_15_MASK) 189 190 #define MC_RGM_DES_F_DR_16_MASK (0x10000U) 191 #define MC_RGM_DES_F_DR_16_SHIFT (16U) 192 #define MC_RGM_DES_F_DR_16_WIDTH (1U) 193 #define MC_RGM_DES_F_DR_16(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_16_SHIFT)) & MC_RGM_DES_F_DR_16_MASK) 194 195 #define MC_RGM_DES_F_DR_17_MASK (0x20000U) 196 #define MC_RGM_DES_F_DR_17_SHIFT (17U) 197 #define MC_RGM_DES_F_DR_17_WIDTH (1U) 198 #define MC_RGM_DES_F_DR_17(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_17_SHIFT)) & MC_RGM_DES_F_DR_17_MASK) 199 200 #define MC_RGM_DES_F_DR_18_MASK (0x40000U) 201 #define MC_RGM_DES_F_DR_18_SHIFT (18U) 202 #define MC_RGM_DES_F_DR_18_WIDTH (1U) 203 #define MC_RGM_DES_F_DR_18(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_18_SHIFT)) & MC_RGM_DES_F_DR_18_MASK) 204 205 #define MC_RGM_DES_F_DR_30_MASK (0x40000000U) 206 #define MC_RGM_DES_F_DR_30_SHIFT (30U) 207 #define MC_RGM_DES_F_DR_30_WIDTH (1U) 208 #define MC_RGM_DES_F_DR_30(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_30_SHIFT)) & MC_RGM_DES_F_DR_30_MASK) 209 210 #define MC_RGM_DES_F_DR_31_MASK (0x80000000U) 211 #define MC_RGM_DES_F_DR_31_SHIFT (31U) 212 #define MC_RGM_DES_F_DR_31_WIDTH (1U) 213 #define MC_RGM_DES_F_DR_31(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DES_F_DR_31_SHIFT)) & MC_RGM_DES_F_DR_31_MASK) 214 /*! @} */ 215 216 /*! @name FES - Functional /External Reset Status Register */ 217 /*! @{ */ 218 219 #define MC_RGM_FES_F_EXR_MASK (0x1U) 220 #define MC_RGM_FES_F_EXR_SHIFT (0U) 221 #define MC_RGM_FES_F_EXR_WIDTH (1U) 222 #define MC_RGM_FES_F_EXR(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_F_EXR_SHIFT)) & MC_RGM_FES_F_EXR_MASK) 223 224 #define MC_RGM_FES_F_FR_3_MASK (0x8U) 225 #define MC_RGM_FES_F_FR_3_SHIFT (3U) 226 #define MC_RGM_FES_F_FR_3_WIDTH (1U) 227 #define MC_RGM_FES_F_FR_3(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_F_FR_3_SHIFT)) & MC_RGM_FES_F_FR_3_MASK) 228 229 #define MC_RGM_FES_F_FR_4_MASK (0x10U) 230 #define MC_RGM_FES_F_FR_4_SHIFT (4U) 231 #define MC_RGM_FES_F_FR_4_WIDTH (1U) 232 #define MC_RGM_FES_F_FR_4(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_F_FR_4_SHIFT)) & MC_RGM_FES_F_FR_4_MASK) 233 234 #define MC_RGM_FES_F_FR_20_MASK (0x100000U) 235 #define MC_RGM_FES_F_FR_20_SHIFT (20U) 236 #define MC_RGM_FES_F_FR_20_WIDTH (1U) 237 #define MC_RGM_FES_F_FR_20(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_F_FR_20_SHIFT)) & MC_RGM_FES_F_FR_20_MASK) 238 239 #define MC_RGM_FES_F_FR_30_MASK (0x40000000U) 240 #define MC_RGM_FES_F_FR_30_SHIFT (30U) 241 #define MC_RGM_FES_F_FR_30_WIDTH (1U) 242 #define MC_RGM_FES_F_FR_30(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_F_FR_30_SHIFT)) & MC_RGM_FES_F_FR_30_MASK) 243 244 #define MC_RGM_FES_F_FR_31_MASK (0x80000000U) 245 #define MC_RGM_FES_F_FR_31_SHIFT (31U) 246 #define MC_RGM_FES_F_FR_31_WIDTH (1U) 247 #define MC_RGM_FES_F_FR_31(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FES_F_FR_31_SHIFT)) & MC_RGM_FES_F_FR_31_MASK) 248 /*! @} */ 249 250 /*! @name FERD - Functional Event Reset Disable Register */ 251 /*! @{ */ 252 253 #define MC_RGM_FERD_D_EXR_MASK (0x1U) 254 #define MC_RGM_FERD_D_EXR_SHIFT (0U) 255 #define MC_RGM_FERD_D_EXR_WIDTH (1U) 256 #define MC_RGM_FERD_D_EXR(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_EXR_SHIFT)) & MC_RGM_FERD_D_EXR_MASK) 257 258 #define MC_RGM_FERD_D_F_FR_3_MASK (0x8U) 259 #define MC_RGM_FERD_D_F_FR_3_SHIFT (3U) 260 #define MC_RGM_FERD_D_F_FR_3_WIDTH (1U) 261 #define MC_RGM_FERD_D_F_FR_3(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_F_FR_3_SHIFT)) & MC_RGM_FERD_D_F_FR_3_MASK) 262 263 #define MC_RGM_FERD_D_F_FR_4_MASK (0x10U) 264 #define MC_RGM_FERD_D_F_FR_4_SHIFT (4U) 265 #define MC_RGM_FERD_D_F_FR_4_WIDTH (1U) 266 #define MC_RGM_FERD_D_F_FR_4(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_F_FR_4_SHIFT)) & MC_RGM_FERD_D_F_FR_4_MASK) 267 268 #define MC_RGM_FERD_D_F_FR_20_MASK (0x100000U) 269 #define MC_RGM_FERD_D_F_FR_20_SHIFT (20U) 270 #define MC_RGM_FERD_D_F_FR_20_WIDTH (1U) 271 #define MC_RGM_FERD_D_F_FR_20(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_F_FR_20_SHIFT)) & MC_RGM_FERD_D_F_FR_20_MASK) 272 273 #define MC_RGM_FERD_D_F_FR_31_MASK (0x80000000U) 274 #define MC_RGM_FERD_D_F_FR_31_SHIFT (31U) 275 #define MC_RGM_FERD_D_F_FR_31_WIDTH (1U) 276 #define MC_RGM_FERD_D_F_FR_31(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FERD_D_F_FR_31_SHIFT)) & MC_RGM_FERD_D_F_FR_31_MASK) 277 /*! @} */ 278 279 /*! @name FBRE - Functional Bidirectional Reset Enable Register */ 280 /*! @{ */ 281 282 #define MC_RGM_FBRE_BE_EXR_MASK (0x1U) 283 #define MC_RGM_FBRE_BE_EXR_SHIFT (0U) 284 #define MC_RGM_FBRE_BE_EXR_WIDTH (1U) 285 #define MC_RGM_FBRE_BE_EXR(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_EXR_SHIFT)) & MC_RGM_FBRE_BE_EXR_MASK) 286 287 #define MC_RGM_FBRE_BE_F_FR_3_MASK (0x8U) 288 #define MC_RGM_FBRE_BE_F_FR_3_SHIFT (3U) 289 #define MC_RGM_FBRE_BE_F_FR_3_WIDTH (1U) 290 #define MC_RGM_FBRE_BE_F_FR_3(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_F_FR_3_SHIFT)) & MC_RGM_FBRE_BE_F_FR_3_MASK) 291 292 #define MC_RGM_FBRE_BE_F_FR_4_MASK (0x10U) 293 #define MC_RGM_FBRE_BE_F_FR_4_SHIFT (4U) 294 #define MC_RGM_FBRE_BE_F_FR_4_WIDTH (1U) 295 #define MC_RGM_FBRE_BE_F_FR_4(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_F_FR_4_SHIFT)) & MC_RGM_FBRE_BE_F_FR_4_MASK) 296 297 #define MC_RGM_FBRE_BE_F_FR_20_MASK (0x100000U) 298 #define MC_RGM_FBRE_BE_F_FR_20_SHIFT (20U) 299 #define MC_RGM_FBRE_BE_F_FR_20_WIDTH (1U) 300 #define MC_RGM_FBRE_BE_F_FR_20(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_F_FR_20_SHIFT)) & MC_RGM_FBRE_BE_F_FR_20_MASK) 301 302 #define MC_RGM_FBRE_BE_F_FR_30_MASK (0x40000000U) 303 #define MC_RGM_FBRE_BE_F_FR_30_SHIFT (30U) 304 #define MC_RGM_FBRE_BE_F_FR_30_WIDTH (1U) 305 #define MC_RGM_FBRE_BE_F_FR_30(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_F_FR_30_SHIFT)) & MC_RGM_FBRE_BE_F_FR_30_MASK) 306 307 #define MC_RGM_FBRE_BE_F_FR_31_MASK (0x80000000U) 308 #define MC_RGM_FBRE_BE_F_FR_31_SHIFT (31U) 309 #define MC_RGM_FBRE_BE_F_FR_31_WIDTH (1U) 310 #define MC_RGM_FBRE_BE_F_FR_31(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FBRE_BE_F_FR_31_SHIFT)) & MC_RGM_FBRE_BE_F_FR_31_MASK) 311 /*! @} */ 312 313 /*! @name FREC - Functional Reset Escalation Counter Register */ 314 /*! @{ */ 315 316 #define MC_RGM_FREC_FREC_MASK (0xFU) 317 #define MC_RGM_FREC_FREC_SHIFT (0U) 318 #define MC_RGM_FREC_FREC_WIDTH (4U) 319 #define MC_RGM_FREC_FREC(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FREC_FREC_SHIFT)) & MC_RGM_FREC_FREC_MASK) 320 /*! @} */ 321 322 /*! @name FRET - Functional Reset Escalation Threshold Register */ 323 /*! @{ */ 324 325 #define MC_RGM_FRET_FRET_MASK (0xFU) 326 #define MC_RGM_FRET_FRET_SHIFT (0U) 327 #define MC_RGM_FRET_FRET_WIDTH (4U) 328 #define MC_RGM_FRET_FRET(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FRET_FRET_SHIFT)) & MC_RGM_FRET_FRET_MASK) 329 /*! @} */ 330 331 /*! @name DRET - Destructive Reset Escalation Threshold Register */ 332 /*! @{ */ 333 334 #define MC_RGM_DRET_DRET_MASK (0xFU) 335 #define MC_RGM_DRET_DRET_SHIFT (0U) 336 #define MC_RGM_DRET_DRET_WIDTH (4U) 337 #define MC_RGM_DRET_DRET(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_DRET_DRET_SHIFT)) & MC_RGM_DRET_DRET_MASK) 338 /*! @} */ 339 340 /*! @name ERCTRL - External Reset Control Register */ 341 /*! @{ */ 342 343 #define MC_RGM_ERCTRL_ERASSERT_MASK (0x1U) 344 #define MC_RGM_ERCTRL_ERASSERT_SHIFT (0U) 345 #define MC_RGM_ERCTRL_ERASSERT_WIDTH (1U) 346 #define MC_RGM_ERCTRL_ERASSERT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_ERCTRL_ERASSERT_SHIFT)) & MC_RGM_ERCTRL_ERASSERT_MASK) 347 /*! @} */ 348 349 /*! @name FRENTC - Functional Reset Entry Timeout Control Register */ 350 /*! @{ */ 351 352 #define MC_RGM_FRENTC_FRET_EN_MASK (0x1U) 353 #define MC_RGM_FRENTC_FRET_EN_SHIFT (0U) 354 #define MC_RGM_FRENTC_FRET_EN_WIDTH (1U) 355 #define MC_RGM_FRENTC_FRET_EN(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FRENTC_FRET_EN_SHIFT)) & MC_RGM_FRENTC_FRET_EN_MASK) 356 357 #define MC_RGM_FRENTC_FRET_TIMEOUT_MASK (0xFFFFFFFEU) 358 #define MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT (1U) 359 #define MC_RGM_FRENTC_FRET_TIMEOUT_WIDTH (31U) 360 #define MC_RGM_FRENTC_FRET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_FRENTC_FRET_TIMEOUT_SHIFT)) & MC_RGM_FRENTC_FRET_TIMEOUT_MASK) 361 /*! @} */ 362 363 /*! @name PRST_0 - Peripheral Reset */ 364 /*! @{ */ 365 366 #define MC_RGM_PRST_0_PERIPH_3_RST_MASK (0x8U) 367 #define MC_RGM_PRST_0_PERIPH_3_RST_SHIFT (3U) 368 #define MC_RGM_PRST_0_PERIPH_3_RST_WIDTH (1U) 369 #define MC_RGM_PRST_0_PERIPH_3_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_3_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_3_RST_MASK) 370 371 #define MC_RGM_PRST_0_PERIPH_4_RST_MASK (0x10U) 372 #define MC_RGM_PRST_0_PERIPH_4_RST_SHIFT (4U) 373 #define MC_RGM_PRST_0_PERIPH_4_RST_WIDTH (1U) 374 #define MC_RGM_PRST_0_PERIPH_4_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_4_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_4_RST_MASK) 375 376 #define MC_RGM_PRST_0_PERIPH_8_RST_MASK (0x100U) 377 #define MC_RGM_PRST_0_PERIPH_8_RST_SHIFT (8U) 378 #define MC_RGM_PRST_0_PERIPH_8_RST_WIDTH (1U) 379 #define MC_RGM_PRST_0_PERIPH_8_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_8_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_8_RST_MASK) 380 381 #define MC_RGM_PRST_0_PERIPH_16_RST_MASK (0x10000U) 382 #define MC_RGM_PRST_0_PERIPH_16_RST_SHIFT (16U) 383 #define MC_RGM_PRST_0_PERIPH_16_RST_WIDTH (1U) 384 #define MC_RGM_PRST_0_PERIPH_16_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_16_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_16_RST_MASK) 385 386 #define MC_RGM_PRST_0_PERIPH_17_RST_MASK (0x20000U) 387 #define MC_RGM_PRST_0_PERIPH_17_RST_SHIFT (17U) 388 #define MC_RGM_PRST_0_PERIPH_17_RST_WIDTH (1U) 389 #define MC_RGM_PRST_0_PERIPH_17_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_17_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_17_RST_MASK) 390 391 #define MC_RGM_PRST_0_PERIPH_24_RST_MASK (0x1000000U) 392 #define MC_RGM_PRST_0_PERIPH_24_RST_SHIFT (24U) 393 #define MC_RGM_PRST_0_PERIPH_24_RST_WIDTH (1U) 394 #define MC_RGM_PRST_0_PERIPH_24_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_24_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_24_RST_MASK) 395 396 #define MC_RGM_PRST_0_PERIPH_25_RST_MASK (0x2000000U) 397 #define MC_RGM_PRST_0_PERIPH_25_RST_SHIFT (25U) 398 #define MC_RGM_PRST_0_PERIPH_25_RST_WIDTH (1U) 399 #define MC_RGM_PRST_0_PERIPH_25_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_25_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_25_RST_MASK) 400 401 #define MC_RGM_PRST_0_PERIPH_64_RST_MASK (0x1U) 402 #define MC_RGM_PRST_0_PERIPH_64_RST_SHIFT (0U) 403 #define MC_RGM_PRST_0_PERIPH_64_RST_WIDTH (1U) 404 #define MC_RGM_PRST_0_PERIPH_64_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_64_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_64_RST_MASK) 405 406 #define MC_RGM_PRST_0_PERIPH_65_RST_MASK (0x2U) 407 #define MC_RGM_PRST_0_PERIPH_65_RST_SHIFT (1U) 408 #define MC_RGM_PRST_0_PERIPH_65_RST_WIDTH (1U) 409 #define MC_RGM_PRST_0_PERIPH_65_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_65_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_65_RST_MASK) 410 411 #define MC_RGM_PRST_0_PERIPH_66_RST_MASK (0x4U) 412 #define MC_RGM_PRST_0_PERIPH_66_RST_SHIFT (2U) 413 #define MC_RGM_PRST_0_PERIPH_66_RST_WIDTH (1U) 414 #define MC_RGM_PRST_0_PERIPH_66_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_66_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_66_RST_MASK) 415 416 #define MC_RGM_PRST_0_PERIPH_67_RST_MASK (0x8U) 417 #define MC_RGM_PRST_0_PERIPH_67_RST_SHIFT (3U) 418 #define MC_RGM_PRST_0_PERIPH_67_RST_WIDTH (1U) 419 #define MC_RGM_PRST_0_PERIPH_67_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_67_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_67_RST_MASK) 420 421 #define MC_RGM_PRST_0_PERIPH_68_RST_MASK (0x10U) 422 #define MC_RGM_PRST_0_PERIPH_68_RST_SHIFT (4U) 423 #define MC_RGM_PRST_0_PERIPH_68_RST_WIDTH (1U) 424 #define MC_RGM_PRST_0_PERIPH_68_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_68_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_68_RST_MASK) 425 426 #define MC_RGM_PRST_0_PERIPH_128_RST_MASK (0x1U) 427 #define MC_RGM_PRST_0_PERIPH_128_RST_SHIFT (0U) 428 #define MC_RGM_PRST_0_PERIPH_128_RST_WIDTH (1U) 429 #define MC_RGM_PRST_0_PERIPH_128_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_128_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_128_RST_MASK) 430 431 #define MC_RGM_PRST_0_PERIPH_129_RST_MASK (0x2U) 432 #define MC_RGM_PRST_0_PERIPH_129_RST_SHIFT (1U) 433 #define MC_RGM_PRST_0_PERIPH_129_RST_WIDTH (1U) 434 #define MC_RGM_PRST_0_PERIPH_129_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_129_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_129_RST_MASK) 435 436 #define MC_RGM_PRST_0_PERIPH_130_RST_MASK (0x4U) 437 #define MC_RGM_PRST_0_PERIPH_130_RST_SHIFT (2U) 438 #define MC_RGM_PRST_0_PERIPH_130_RST_WIDTH (1U) 439 #define MC_RGM_PRST_0_PERIPH_130_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_130_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_130_RST_MASK) 440 441 #define MC_RGM_PRST_0_PERIPH_131_RST_MASK (0x8U) 442 #define MC_RGM_PRST_0_PERIPH_131_RST_SHIFT (3U) 443 #define MC_RGM_PRST_0_PERIPH_131_RST_WIDTH (1U) 444 #define MC_RGM_PRST_0_PERIPH_131_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_131_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_131_RST_MASK) 445 446 #define MC_RGM_PRST_0_PERIPH_132_RST_MASK (0x10U) 447 #define MC_RGM_PRST_0_PERIPH_132_RST_SHIFT (4U) 448 #define MC_RGM_PRST_0_PERIPH_132_RST_WIDTH (1U) 449 #define MC_RGM_PRST_0_PERIPH_132_RST(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PRST_0_PERIPH_132_RST_SHIFT)) & MC_RGM_PRST_0_PERIPH_132_RST_MASK) 450 /*! @} */ 451 452 /*! @name PSTAT_0 - Peripheral Reset Status Register */ 453 /*! @{ */ 454 455 #define MC_RGM_PSTAT_0_PERIPH_3_STAT_MASK (0x8U) 456 #define MC_RGM_PSTAT_0_PERIPH_3_STAT_SHIFT (3U) 457 #define MC_RGM_PSTAT_0_PERIPH_3_STAT_WIDTH (1U) 458 #define MC_RGM_PSTAT_0_PERIPH_3_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_3_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_3_STAT_MASK) 459 460 #define MC_RGM_PSTAT_0_PERIPH_4_STAT_MASK (0x10U) 461 #define MC_RGM_PSTAT_0_PERIPH_4_STAT_SHIFT (4U) 462 #define MC_RGM_PSTAT_0_PERIPH_4_STAT_WIDTH (1U) 463 #define MC_RGM_PSTAT_0_PERIPH_4_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_4_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_4_STAT_MASK) 464 465 #define MC_RGM_PSTAT_0_PERIPH_8_STAT_MASK (0x100U) 466 #define MC_RGM_PSTAT_0_PERIPH_8_STAT_SHIFT (8U) 467 #define MC_RGM_PSTAT_0_PERIPH_8_STAT_WIDTH (1U) 468 #define MC_RGM_PSTAT_0_PERIPH_8_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_8_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_8_STAT_MASK) 469 470 #define MC_RGM_PSTAT_0_PERIPH_16_STAT_MASK (0x10000U) 471 #define MC_RGM_PSTAT_0_PERIPH_16_STAT_SHIFT (16U) 472 #define MC_RGM_PSTAT_0_PERIPH_16_STAT_WIDTH (1U) 473 #define MC_RGM_PSTAT_0_PERIPH_16_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_16_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_16_STAT_MASK) 474 475 #define MC_RGM_PSTAT_0_PERIPH_17_STAT_MASK (0x20000U) 476 #define MC_RGM_PSTAT_0_PERIPH_17_STAT_SHIFT (17U) 477 #define MC_RGM_PSTAT_0_PERIPH_17_STAT_WIDTH (1U) 478 #define MC_RGM_PSTAT_0_PERIPH_17_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_17_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_17_STAT_MASK) 479 480 #define MC_RGM_PSTAT_0_PERIPH_24_STAT_MASK (0x1000000U) 481 #define MC_RGM_PSTAT_0_PERIPH_24_STAT_SHIFT (24U) 482 #define MC_RGM_PSTAT_0_PERIPH_24_STAT_WIDTH (1U) 483 #define MC_RGM_PSTAT_0_PERIPH_24_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_24_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_24_STAT_MASK) 484 485 #define MC_RGM_PSTAT_0_PERIPH_25_STAT_MASK (0x2000000U) 486 #define MC_RGM_PSTAT_0_PERIPH_25_STAT_SHIFT (25U) 487 #define MC_RGM_PSTAT_0_PERIPH_25_STAT_WIDTH (1U) 488 #define MC_RGM_PSTAT_0_PERIPH_25_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_25_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_25_STAT_MASK) 489 490 #define MC_RGM_PSTAT_0_PERIPH_64_STAT_MASK (0x1U) 491 #define MC_RGM_PSTAT_0_PERIPH_64_STAT_SHIFT (0U) 492 #define MC_RGM_PSTAT_0_PERIPH_64_STAT_WIDTH (1U) 493 #define MC_RGM_PSTAT_0_PERIPH_64_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_64_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_64_STAT_MASK) 494 495 #define MC_RGM_PSTAT_0_PERIPH_65_STAT_MASK (0x2U) 496 #define MC_RGM_PSTAT_0_PERIPH_65_STAT_SHIFT (1U) 497 #define MC_RGM_PSTAT_0_PERIPH_65_STAT_WIDTH (1U) 498 #define MC_RGM_PSTAT_0_PERIPH_65_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_65_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_65_STAT_MASK) 499 500 #define MC_RGM_PSTAT_0_PERIPH_66_STAT_MASK (0x4U) 501 #define MC_RGM_PSTAT_0_PERIPH_66_STAT_SHIFT (2U) 502 #define MC_RGM_PSTAT_0_PERIPH_66_STAT_WIDTH (1U) 503 #define MC_RGM_PSTAT_0_PERIPH_66_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_66_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_66_STAT_MASK) 504 505 #define MC_RGM_PSTAT_0_PERIPH_67_STAT_MASK (0x8U) 506 #define MC_RGM_PSTAT_0_PERIPH_67_STAT_SHIFT (3U) 507 #define MC_RGM_PSTAT_0_PERIPH_67_STAT_WIDTH (1U) 508 #define MC_RGM_PSTAT_0_PERIPH_67_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_67_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_67_STAT_MASK) 509 510 #define MC_RGM_PSTAT_0_PERIPH_68_STAT_MASK (0x10U) 511 #define MC_RGM_PSTAT_0_PERIPH_68_STAT_SHIFT (4U) 512 #define MC_RGM_PSTAT_0_PERIPH_68_STAT_WIDTH (1U) 513 #define MC_RGM_PSTAT_0_PERIPH_68_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_68_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_68_STAT_MASK) 514 515 #define MC_RGM_PSTAT_0_PERIPH_128_STAT_MASK (0x1U) 516 #define MC_RGM_PSTAT_0_PERIPH_128_STAT_SHIFT (0U) 517 #define MC_RGM_PSTAT_0_PERIPH_128_STAT_WIDTH (1U) 518 #define MC_RGM_PSTAT_0_PERIPH_128_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_128_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_128_STAT_MASK) 519 520 #define MC_RGM_PSTAT_0_PERIPH_129_STAT_MASK (0x2U) 521 #define MC_RGM_PSTAT_0_PERIPH_129_STAT_SHIFT (1U) 522 #define MC_RGM_PSTAT_0_PERIPH_129_STAT_WIDTH (1U) 523 #define MC_RGM_PSTAT_0_PERIPH_129_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_129_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_129_STAT_MASK) 524 525 #define MC_RGM_PSTAT_0_PERIPH_130_STAT_MASK (0x4U) 526 #define MC_RGM_PSTAT_0_PERIPH_130_STAT_SHIFT (2U) 527 #define MC_RGM_PSTAT_0_PERIPH_130_STAT_WIDTH (1U) 528 #define MC_RGM_PSTAT_0_PERIPH_130_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_130_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_130_STAT_MASK) 529 530 #define MC_RGM_PSTAT_0_PERIPH_131_STAT_MASK (0x8U) 531 #define MC_RGM_PSTAT_0_PERIPH_131_STAT_SHIFT (3U) 532 #define MC_RGM_PSTAT_0_PERIPH_131_STAT_WIDTH (1U) 533 #define MC_RGM_PSTAT_0_PERIPH_131_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_131_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_131_STAT_MASK) 534 535 #define MC_RGM_PSTAT_0_PERIPH_132_STAT_MASK (0x10U) 536 #define MC_RGM_PSTAT_0_PERIPH_132_STAT_SHIFT (4U) 537 #define MC_RGM_PSTAT_0_PERIPH_132_STAT_WIDTH (1U) 538 #define MC_RGM_PSTAT_0_PERIPH_132_STAT(x) (((uint32_t)(((uint32_t)(x)) << MC_RGM_PSTAT_0_PERIPH_132_STAT_SHIFT)) & MC_RGM_PSTAT_0_PERIPH_132_STAT_MASK) 539 /*! @} */ 540 541 /*! 542 * @} 543 */ /* end of group MC_RGM_Register_Masks */ 544 545 /*! 546 * @} 547 */ /* end of group MC_RGM_Peripheral_Access_Layer */ 548 549 #endif /* #if !defined(S32Z2_MC_RGM_H_) */ 550
