1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MCM.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_MCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MCM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MCM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MCM - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[8]; 74 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 75 __I uint16_t PLAMC; /**< Crossbar Switch Master Configuration, offset: 0xA */ 76 uint8_t RESERVED_1[4]; 77 __IO uint32_t ISCR; /**< Interrupt Status and Control, offset: 0x10 */ 78 uint8_t RESERVED_2[12]; 79 __I uint32_t FADR; /**< Write Buffer Fault Address, offset: 0x20 */ 80 __I uint32_t FATR; /**< Store Buffer Fault Attributes, offset: 0x24 */ 81 __I uint32_t FDR; /**< Store Buffer Fault Data, offset: 0x28 */ 82 uint8_t RESERVED_3[8]; 83 __I uint32_t CPCR2; /**< Core Platform Control 2, offset: 0x34 */ 84 uint8_t RESERVED_4[24]; 85 __IO uint32_t GPCR0; /**< General Purpose Control 0, offset: 0x50 */ 86 uint8_t RESERVED_5[940]; 87 __IO uint32_t LMDR0; /**< Local Memory Descriptor 0, offset: 0x400 */ 88 __IO uint32_t LMDR1; /**< Local Memory Descriptor 1, offset: 0x404 */ 89 } MCM_Type, *MCM_MemMapPtr; 90 91 /** Number of instances of the MCM module. */ 92 #define MCM_INSTANCE_COUNT (2u) 93 94 /* MCM - Peripheral instance base addresses */ 95 /** Peripheral CE_MCM base address */ 96 #define IP_CE_MCM_BASE (0xE0080000u) 97 /** Peripheral CE_MCM base pointer */ 98 #define IP_CE_MCM ((MCM_Type *)IP_CE_MCM_BASE) 99 /** Peripheral SMU__MCM base address */ 100 #define IP_SMU__MCM_BASE (0xE0080000u) 101 /** Peripheral SMU__MCM base pointer */ 102 #define IP_SMU__MCM ((MCM_Type *)IP_SMU__MCM_BASE) 103 /** Array initializer of MCM peripheral base addresses */ 104 #define IP_MCM_BASE_ADDRS { IP_CE_MCM_BASE, IP_SMU__MCM_BASE } 105 /** Array initializer of MCM peripheral base pointers */ 106 #define IP_MCM_BASE_PTRS { IP_CE_MCM, IP_SMU__MCM } 107 108 /* ---------------------------------------------------------------------------- 109 -- MCM Register Masks 110 ---------------------------------------------------------------------------- */ 111 112 /*! 113 * @addtogroup MCM_Register_Masks MCM Register Masks 114 * @{ 115 */ 116 117 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 118 /*! @{ */ 119 120 #define MCM_PLASC_ASC0_MASK (0x1U) 121 #define MCM_PLASC_ASC0_SHIFT (0U) 122 #define MCM_PLASC_ASC0_WIDTH (1U) 123 #define MCM_PLASC_ASC0(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC0_SHIFT)) & MCM_PLASC_ASC0_MASK) 124 125 #define MCM_PLASC_ASC1_MASK (0x2U) 126 #define MCM_PLASC_ASC1_SHIFT (1U) 127 #define MCM_PLASC_ASC1_WIDTH (1U) 128 #define MCM_PLASC_ASC1(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC1_SHIFT)) & MCM_PLASC_ASC1_MASK) 129 130 #define MCM_PLASC_ASC2_MASK (0x4U) 131 #define MCM_PLASC_ASC2_SHIFT (2U) 132 #define MCM_PLASC_ASC2_WIDTH (1U) 133 #define MCM_PLASC_ASC2(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC2_SHIFT)) & MCM_PLASC_ASC2_MASK) 134 135 #define MCM_PLASC_ASC3_MASK (0x8U) 136 #define MCM_PLASC_ASC3_SHIFT (3U) 137 #define MCM_PLASC_ASC3_WIDTH (1U) 138 #define MCM_PLASC_ASC3(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC3_SHIFT)) & MCM_PLASC_ASC3_MASK) 139 140 #define MCM_PLASC_ASC4_MASK (0x10U) 141 #define MCM_PLASC_ASC4_SHIFT (4U) 142 #define MCM_PLASC_ASC4_WIDTH (1U) 143 #define MCM_PLASC_ASC4(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC4_SHIFT)) & MCM_PLASC_ASC4_MASK) 144 145 #define MCM_PLASC_ASC5_MASK (0x20U) 146 #define MCM_PLASC_ASC5_SHIFT (5U) 147 #define MCM_PLASC_ASC5_WIDTH (1U) 148 #define MCM_PLASC_ASC5(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC5_SHIFT)) & MCM_PLASC_ASC5_MASK) 149 150 #define MCM_PLASC_ASC6_MASK (0x40U) 151 #define MCM_PLASC_ASC6_SHIFT (6U) 152 #define MCM_PLASC_ASC6_WIDTH (1U) 153 #define MCM_PLASC_ASC6(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC6_SHIFT)) & MCM_PLASC_ASC6_MASK) 154 155 #define MCM_PLASC_ASC7_MASK (0x80U) 156 #define MCM_PLASC_ASC7_SHIFT (7U) 157 #define MCM_PLASC_ASC7_WIDTH (1U) 158 #define MCM_PLASC_ASC7(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC7_SHIFT)) & MCM_PLASC_ASC7_MASK) 159 /*! @} */ 160 161 /*! @name PLAMC - Crossbar Switch Master Configuration */ 162 /*! @{ */ 163 164 #define MCM_PLAMC_AMC0_MASK (0x1U) 165 #define MCM_PLAMC_AMC0_SHIFT (0U) 166 #define MCM_PLAMC_AMC0_WIDTH (1U) 167 #define MCM_PLAMC_AMC0(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC0_SHIFT)) & MCM_PLAMC_AMC0_MASK) 168 169 #define MCM_PLAMC_AMC1_MASK (0x2U) 170 #define MCM_PLAMC_AMC1_SHIFT (1U) 171 #define MCM_PLAMC_AMC1_WIDTH (1U) 172 #define MCM_PLAMC_AMC1(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC1_SHIFT)) & MCM_PLAMC_AMC1_MASK) 173 174 #define MCM_PLAMC_AMC2_MASK (0x4U) 175 #define MCM_PLAMC_AMC2_SHIFT (2U) 176 #define MCM_PLAMC_AMC2_WIDTH (1U) 177 #define MCM_PLAMC_AMC2(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC2_SHIFT)) & MCM_PLAMC_AMC2_MASK) 178 179 #define MCM_PLAMC_AMC3_MASK (0x8U) 180 #define MCM_PLAMC_AMC3_SHIFT (3U) 181 #define MCM_PLAMC_AMC3_WIDTH (1U) 182 #define MCM_PLAMC_AMC3(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC3_SHIFT)) & MCM_PLAMC_AMC3_MASK) 183 184 #define MCM_PLAMC_AMC4_MASK (0x10U) 185 #define MCM_PLAMC_AMC4_SHIFT (4U) 186 #define MCM_PLAMC_AMC4_WIDTH (1U) 187 #define MCM_PLAMC_AMC4(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC4_SHIFT)) & MCM_PLAMC_AMC4_MASK) 188 189 #define MCM_PLAMC_AMC5_MASK (0x20U) 190 #define MCM_PLAMC_AMC5_SHIFT (5U) 191 #define MCM_PLAMC_AMC5_WIDTH (1U) 192 #define MCM_PLAMC_AMC5(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC5_SHIFT)) & MCM_PLAMC_AMC5_MASK) 193 194 #define MCM_PLAMC_AMC6_MASK (0x40U) 195 #define MCM_PLAMC_AMC6_SHIFT (6U) 196 #define MCM_PLAMC_AMC6_WIDTH (1U) 197 #define MCM_PLAMC_AMC6(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC6_SHIFT)) & MCM_PLAMC_AMC6_MASK) 198 199 #define MCM_PLAMC_AMC7_MASK (0x80U) 200 #define MCM_PLAMC_AMC7_SHIFT (7U) 201 #define MCM_PLAMC_AMC7_WIDTH (1U) 202 #define MCM_PLAMC_AMC7(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC7_SHIFT)) & MCM_PLAMC_AMC7_MASK) 203 /*! @} */ 204 205 /*! @name ISCR - Interrupt Status and Control */ 206 /*! @{ */ 207 208 #define MCM_ISCR_CWBER_MASK (0x10U) 209 #define MCM_ISCR_CWBER_SHIFT (4U) 210 #define MCM_ISCR_CWBER_WIDTH (1U) 211 #define MCM_ISCR_CWBER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBER_SHIFT)) & MCM_ISCR_CWBER_MASK) 212 213 #define MCM_ISCR_FIOC_MASK (0x100U) 214 #define MCM_ISCR_FIOC_SHIFT (8U) 215 #define MCM_ISCR_FIOC_WIDTH (1U) 216 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) 217 218 #define MCM_ISCR_FDZC_MASK (0x200U) 219 #define MCM_ISCR_FDZC_SHIFT (9U) 220 #define MCM_ISCR_FDZC_WIDTH (1U) 221 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) 222 223 #define MCM_ISCR_FOFC_MASK (0x400U) 224 #define MCM_ISCR_FOFC_SHIFT (10U) 225 #define MCM_ISCR_FOFC_WIDTH (1U) 226 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) 227 228 #define MCM_ISCR_FUFC_MASK (0x800U) 229 #define MCM_ISCR_FUFC_SHIFT (11U) 230 #define MCM_ISCR_FUFC_WIDTH (1U) 231 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) 232 233 #define MCM_ISCR_FIXC_MASK (0x1000U) 234 #define MCM_ISCR_FIXC_SHIFT (12U) 235 #define MCM_ISCR_FIXC_WIDTH (1U) 236 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) 237 238 #define MCM_ISCR_FIDC_MASK (0x8000U) 239 #define MCM_ISCR_FIDC_SHIFT (15U) 240 #define MCM_ISCR_FIDC_WIDTH (1U) 241 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) 242 243 #define MCM_ISCR_CWBEE_MASK (0x100000U) 244 #define MCM_ISCR_CWBEE_SHIFT (20U) 245 #define MCM_ISCR_CWBEE_WIDTH (1U) 246 #define MCM_ISCR_CWBEE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_CWBEE_SHIFT)) & MCM_ISCR_CWBEE_MASK) 247 248 #define MCM_ISCR_FIOCE_MASK (0x1000000U) 249 #define MCM_ISCR_FIOCE_SHIFT (24U) 250 #define MCM_ISCR_FIOCE_WIDTH (1U) 251 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) 252 253 #define MCM_ISCR_FDZCE_MASK (0x2000000U) 254 #define MCM_ISCR_FDZCE_SHIFT (25U) 255 #define MCM_ISCR_FDZCE_WIDTH (1U) 256 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) 257 258 #define MCM_ISCR_FOFCE_MASK (0x4000000U) 259 #define MCM_ISCR_FOFCE_SHIFT (26U) 260 #define MCM_ISCR_FOFCE_WIDTH (1U) 261 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) 262 263 #define MCM_ISCR_FUFCE_MASK (0x8000000U) 264 #define MCM_ISCR_FUFCE_SHIFT (27U) 265 #define MCM_ISCR_FUFCE_WIDTH (1U) 266 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) 267 268 #define MCM_ISCR_FIXCE_MASK (0x10000000U) 269 #define MCM_ISCR_FIXCE_SHIFT (28U) 270 #define MCM_ISCR_FIXCE_WIDTH (1U) 271 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) 272 273 #define MCM_ISCR_FIDCE_MASK (0x80000000U) 274 #define MCM_ISCR_FIDCE_SHIFT (31U) 275 #define MCM_ISCR_FIDCE_WIDTH (1U) 276 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) 277 /*! @} */ 278 279 /*! @name FADR - Write Buffer Fault Address */ 280 /*! @{ */ 281 282 #define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) 283 #define MCM_FADR_ADDRESS_SHIFT (0U) 284 #define MCM_FADR_ADDRESS_WIDTH (32U) 285 #define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) 286 /*! @} */ 287 288 /*! @name FATR - Store Buffer Fault Attributes */ 289 /*! @{ */ 290 291 #define MCM_FATR_BEDA_MASK (0x1U) 292 #define MCM_FATR_BEDA_SHIFT (0U) 293 #define MCM_FATR_BEDA_WIDTH (1U) 294 #define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) 295 296 #define MCM_FATR_BEMD_MASK (0x2U) 297 #define MCM_FATR_BEMD_SHIFT (1U) 298 #define MCM_FATR_BEMD_WIDTH (1U) 299 #define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) 300 301 #define MCM_FATR_BESZ_MASK (0x30U) 302 #define MCM_FATR_BESZ_SHIFT (4U) 303 #define MCM_FATR_BESZ_WIDTH (2U) 304 #define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) 305 306 #define MCM_FATR_BEWT_MASK (0x80U) 307 #define MCM_FATR_BEWT_SHIFT (7U) 308 #define MCM_FATR_BEWT_WIDTH (1U) 309 #define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) 310 311 #define MCM_FATR_BEMN_MASK (0xF00U) 312 #define MCM_FATR_BEMN_SHIFT (8U) 313 #define MCM_FATR_BEMN_WIDTH (4U) 314 #define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) 315 316 #define MCM_FATR_BEOVR_MASK (0x80000000U) 317 #define MCM_FATR_BEOVR_SHIFT (31U) 318 #define MCM_FATR_BEOVR_WIDTH (1U) 319 #define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) 320 /*! @} */ 321 322 /*! @name FDR - Store Buffer Fault Data */ 323 /*! @{ */ 324 325 #define MCM_FDR_DATA_MASK (0xFFFFFFFFU) 326 #define MCM_FDR_DATA_SHIFT (0U) 327 #define MCM_FDR_DATA_WIDTH (32U) 328 #define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) 329 /*! @} */ 330 331 /*! @name CPCR2 - Core Platform Control 2 */ 332 /*! @{ */ 333 334 #define MCM_CPCR2_CBCS_MASK (0xF0U) 335 #define MCM_CPCR2_CBCS_SHIFT (4U) 336 #define MCM_CPCR2_CBCS_WIDTH (4U) 337 #define MCM_CPCR2_CBCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_CBCS_SHIFT)) & MCM_CPCR2_CBCS_MASK) 338 339 #define MCM_CPCR2_SBCS_MASK (0xF000U) 340 #define MCM_CPCR2_SBCS_SHIFT (12U) 341 #define MCM_CPCR2_SBCS_WIDTH (4U) 342 #define MCM_CPCR2_SBCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR2_SBCS_SHIFT)) & MCM_CPCR2_SBCS_MASK) 343 /*! @} */ 344 345 /*! @name GPCR0 - General Purpose Control 0 */ 346 /*! @{ */ 347 348 #define MCM_GPCR0_CORE_TASKID_MASK (0xFU) 349 #define MCM_GPCR0_CORE_TASKID_SHIFT (0U) 350 #define MCM_GPCR0_CORE_TASKID_WIDTH (4U) 351 #define MCM_GPCR0_CORE_TASKID(x) (((uint32_t)(((uint32_t)(x)) << MCM_GPCR0_CORE_TASKID_SHIFT)) & MCM_GPCR0_CORE_TASKID_MASK) 352 /*! @} */ 353 354 /*! @name LMDR0 - Local Memory Descriptor 0 */ 355 /*! @{ */ 356 357 #define MCM_LMDR0_EEWG_MASK (0x1U) 358 #define MCM_LMDR0_EEWG_SHIFT (0U) 359 #define MCM_LMDR0_EEWG_WIDTH (1U) 360 #define MCM_LMDR0_EEWG(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_EEWG_SHIFT)) & MCM_LMDR0_EEWG_MASK) 361 362 #define MCM_LMDR0_EERC_MASK (0x2U) 363 #define MCM_LMDR0_EERC_SHIFT (1U) 364 #define MCM_LMDR0_EERC_WIDTH (1U) 365 #define MCM_LMDR0_EERC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_EERC_SHIFT)) & MCM_LMDR0_EERC_MASK) 366 367 #define MCM_LMDR0_MT_MASK (0xE000U) 368 #define MCM_LMDR0_MT_SHIFT (13U) 369 #define MCM_LMDR0_MT_WIDTH (3U) 370 #define MCM_LMDR0_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_MT_SHIFT)) & MCM_LMDR0_MT_MASK) 371 372 #define MCM_LMDR0_RO_MASK (0x10000U) 373 #define MCM_LMDR0_RO_SHIFT (16U) 374 #define MCM_LMDR0_RO_WIDTH (1U) 375 #define MCM_LMDR0_RO(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_RO_SHIFT)) & MCM_LMDR0_RO_MASK) 376 377 #define MCM_LMDR0_DPW_MASK (0xE0000U) 378 #define MCM_LMDR0_DPW_SHIFT (17U) 379 #define MCM_LMDR0_DPW_WIDTH (3U) 380 #define MCM_LMDR0_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_DPW_SHIFT)) & MCM_LMDR0_DPW_MASK) 381 382 #define MCM_LMDR0_WY_MASK (0xF00000U) 383 #define MCM_LMDR0_WY_SHIFT (20U) 384 #define MCM_LMDR0_WY_WIDTH (4U) 385 #define MCM_LMDR0_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_WY_SHIFT)) & MCM_LMDR0_WY_MASK) 386 387 #define MCM_LMDR0_LMSZ_MASK (0xF000000U) 388 #define MCM_LMDR0_LMSZ_SHIFT (24U) 389 #define MCM_LMDR0_LMSZ_WIDTH (4U) 390 #define MCM_LMDR0_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_LMSZ_SHIFT)) & MCM_LMDR0_LMSZ_MASK) 391 392 #define MCM_LMDR0_LMSZH_MASK (0x10000000U) 393 #define MCM_LMDR0_LMSZH_SHIFT (28U) 394 #define MCM_LMDR0_LMSZH_WIDTH (1U) 395 #define MCM_LMDR0_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_LMSZH_SHIFT)) & MCM_LMDR0_LMSZH_MASK) 396 397 #define MCM_LMDR0_V_MASK (0x80000000U) 398 #define MCM_LMDR0_V_SHIFT (31U) 399 #define MCM_LMDR0_V_WIDTH (1U) 400 #define MCM_LMDR0_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR0_V_SHIFT)) & MCM_LMDR0_V_MASK) 401 /*! @} */ 402 403 /*! @name LMDR1 - Local Memory Descriptor 1 */ 404 /*! @{ */ 405 406 #define MCM_LMDR1_EEWG_MASK (0x1U) 407 #define MCM_LMDR1_EEWG_SHIFT (0U) 408 #define MCM_LMDR1_EEWG_WIDTH (1U) 409 #define MCM_LMDR1_EEWG(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_EEWG_SHIFT)) & MCM_LMDR1_EEWG_MASK) 410 411 #define MCM_LMDR1_EERC_MASK (0x2U) 412 #define MCM_LMDR1_EERC_SHIFT (1U) 413 #define MCM_LMDR1_EERC_WIDTH (1U) 414 #define MCM_LMDR1_EERC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_EERC_SHIFT)) & MCM_LMDR1_EERC_MASK) 415 416 #define MCM_LMDR1_MT_MASK (0xE000U) 417 #define MCM_LMDR1_MT_SHIFT (13U) 418 #define MCM_LMDR1_MT_WIDTH (3U) 419 #define MCM_LMDR1_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_MT_SHIFT)) & MCM_LMDR1_MT_MASK) 420 421 #define MCM_LMDR1_RO_MASK (0x10000U) 422 #define MCM_LMDR1_RO_SHIFT (16U) 423 #define MCM_LMDR1_RO_WIDTH (1U) 424 #define MCM_LMDR1_RO(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_RO_SHIFT)) & MCM_LMDR1_RO_MASK) 425 426 #define MCM_LMDR1_DPW_MASK (0xE0000U) 427 #define MCM_LMDR1_DPW_SHIFT (17U) 428 #define MCM_LMDR1_DPW_WIDTH (3U) 429 #define MCM_LMDR1_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_DPW_SHIFT)) & MCM_LMDR1_DPW_MASK) 430 431 #define MCM_LMDR1_WY_MASK (0xF00000U) 432 #define MCM_LMDR1_WY_SHIFT (20U) 433 #define MCM_LMDR1_WY_WIDTH (4U) 434 #define MCM_LMDR1_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_WY_SHIFT)) & MCM_LMDR1_WY_MASK) 435 436 #define MCM_LMDR1_LMSZ_MASK (0xF000000U) 437 #define MCM_LMDR1_LMSZ_SHIFT (24U) 438 #define MCM_LMDR1_LMSZ_WIDTH (4U) 439 #define MCM_LMDR1_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_LMSZ_SHIFT)) & MCM_LMDR1_LMSZ_MASK) 440 441 #define MCM_LMDR1_LMSZH_MASK (0x10000000U) 442 #define MCM_LMDR1_LMSZH_SHIFT (28U) 443 #define MCM_LMDR1_LMSZH_WIDTH (1U) 444 #define MCM_LMDR1_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_LMSZH_SHIFT)) & MCM_LMDR1_LMSZH_MASK) 445 446 #define MCM_LMDR1_V_MASK (0x80000000U) 447 #define MCM_LMDR1_V_SHIFT (31U) 448 #define MCM_LMDR1_V_WIDTH (1U) 449 #define MCM_LMDR1_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR1_V_SHIFT)) & MCM_LMDR1_V_MASK) 450 /*! @} */ 451 452 /*! 453 * @} 454 */ /* end of group MCM_Register_Masks */ 455 456 /*! 457 * @} 458 */ /* end of group MCM_Peripheral_Access_Layer */ 459 460 #endif /* #if !defined(S32Z2_MCM_H_) */ 461
