1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LSTCU_14_15_17_18.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_LSTCU_14_15_17_18 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LSTCU_14_15_17_18_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LSTCU_14_15_17_18_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LSTCU_14_15_17_18 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LSTCU_14_15_17_18_Peripheral_Access_Layer LSTCU_14_15_17_18 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LSTCU_14_15_17_18 - Size of Registers Arrays */ 72 #define LSTCU_14_15_17_18_MBIST_SCH_PTR_COUNT 2u 73 #define LSTCU_14_15_17_18_LBIST_SCH_PTR_COUNT 1u 74 75 /** LSTCU_14_15_17_18 - Register Layout Typedef */ 76 typedef struct { 77 uint8_t RESERVED_0[8]; 78 __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x8 */ 79 uint8_t RESERVED_1[4]; 80 __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x10 */ 81 uint8_t RESERVED_2[76]; 82 __I uint32_t MB_RSTAT0; /**< MBIST Run Status 0, offset: 0x60 */ 83 __I uint32_t MB_RSTAT1; /**< MBIST Run Status 1, offset: 0x64 */ 84 uint8_t RESERVED_3[152]; 85 __I uint32_t LB_RSTAT0; /**< LBIST Run Status 0, offset: 0x100 */ 86 uint8_t RESERVED_4[124]; 87 __IO uint32_t MBFM0; /**< MBIST Fault Mapping 0, offset: 0x180 */ 88 __IO uint32_t MBFM1; /**< MBIST Fault Mapping 1, offset: 0x184 */ 89 uint8_t RESERVED_5[152]; 90 __IO uint32_t LBFM0; /**< LBIST Fault Mapping 0, offset: 0x220 */ 91 uint8_t RESERVED_6[60]; 92 __IO uint32_t STAG; /**< Stagger, offset: 0x260 */ 93 uint8_t RESERVED_7[12]; 94 __IO uint32_t PH1_DUR; /**< Phase 1 Duration, offset: 0x270 */ 95 uint8_t RESERVED_8[140]; 96 __IO uint32_t MBPTR[LSTCU_14_15_17_18_MBIST_SCH_PTR_COUNT]; /**< MBIST Scheduler Pointer, array offset: 0x300, array step: 0x4 */ 97 uint8_t RESERVED_9[152]; 98 __IO uint32_t LBPTR[LSTCU_14_15_17_18_LBIST_SCH_PTR_COUNT]; /**< LBIST Scheduler Pointer, array offset: 0x3A0, array step: 0x4 */ 99 } LSTCU_14_15_17_18_Type, *LSTCU_14_15_17_18_MemMapPtr; 100 101 /** Number of instances of the LSTCU_14_15_17_18 module. */ 102 #define LSTCU_14_15_17_18_INSTANCE_COUNT (4u) 103 104 /* LSTCU_14_15_17_18 - Peripheral instance base addresses */ 105 /** Peripheral LSTCU_14 base address */ 106 #define IP_LSTCU_14_BASE (0x4C009000u) 107 /** Peripheral LSTCU_14 base pointer */ 108 #define IP_LSTCU_14 ((LSTCU_14_15_17_18_Type *)IP_LSTCU_14_BASE) 109 /** Peripheral LSTCU_15 base address */ 110 #define IP_LSTCU_15_BASE (0x4C00A000u) 111 /** Peripheral LSTCU_15 base pointer */ 112 #define IP_LSTCU_15 ((LSTCU_14_15_17_18_Type *)IP_LSTCU_15_BASE) 113 /** Peripheral LSTCU_17 base address */ 114 #define IP_LSTCU_17_BASE (0x4C809000u) 115 /** Peripheral LSTCU_17 base pointer */ 116 #define IP_LSTCU_17 ((LSTCU_14_15_17_18_Type *)IP_LSTCU_17_BASE) 117 /** Peripheral LSTCU_18 base address */ 118 #define IP_LSTCU_18_BASE (0x4C80A000u) 119 /** Peripheral LSTCU_18 base pointer */ 120 #define IP_LSTCU_18 ((LSTCU_14_15_17_18_Type *)IP_LSTCU_18_BASE) 121 /** Array initializer of LSTCU_14_15_17_18 peripheral base addresses */ 122 #define IP_LSTCU_14_15_17_18_BASE_ADDRS { IP_LSTCU_14_BASE, IP_LSTCU_15_BASE, IP_LSTCU_17_BASE, IP_LSTCU_18_BASE } 123 /** Array initializer of LSTCU_14_15_17_18 peripheral base pointers */ 124 #define IP_LSTCU_14_15_17_18_BASE_PTRS { IP_LSTCU_14, IP_LSTCU_15, IP_LSTCU_17, IP_LSTCU_18 } 125 126 /* ---------------------------------------------------------------------------- 127 -- LSTCU_14_15_17_18 Register Masks 128 ---------------------------------------------------------------------------- */ 129 130 /*! 131 * @addtogroup LSTCU_14_15_17_18_Register_Masks LSTCU_14_15_17_18 Register Masks 132 * @{ 133 */ 134 135 /*! @name ERR_STAT - Error Status */ 136 /*! @{ */ 137 138 #define LSTCU_14_15_17_18_ERR_STAT_INVP_MB_MASK (0x2U) 139 #define LSTCU_14_15_17_18_ERR_STAT_INVP_MB_SHIFT (1U) 140 #define LSTCU_14_15_17_18_ERR_STAT_INVP_MB_WIDTH (1U) 141 #define LSTCU_14_15_17_18_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_ERR_STAT_INVP_MB_SHIFT)) & LSTCU_14_15_17_18_ERR_STAT_INVP_MB_MASK) 142 143 #define LSTCU_14_15_17_18_ERR_STAT_INVP_LB_MASK (0x4U) 144 #define LSTCU_14_15_17_18_ERR_STAT_INVP_LB_SHIFT (2U) 145 #define LSTCU_14_15_17_18_ERR_STAT_INVP_LB_WIDTH (1U) 146 #define LSTCU_14_15_17_18_ERR_STAT_INVP_LB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_ERR_STAT_INVP_LB_SHIFT)) & LSTCU_14_15_17_18_ERR_STAT_INVP_LB_MASK) 147 148 #define LSTCU_14_15_17_18_ERR_STAT_UFSF_MASK (0x10000U) 149 #define LSTCU_14_15_17_18_ERR_STAT_UFSF_SHIFT (16U) 150 #define LSTCU_14_15_17_18_ERR_STAT_UFSF_WIDTH (1U) 151 #define LSTCU_14_15_17_18_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_ERR_STAT_UFSF_SHIFT)) & LSTCU_14_15_17_18_ERR_STAT_UFSF_MASK) 152 153 #define LSTCU_14_15_17_18_ERR_STAT_RFSF_MASK (0x20000U) 154 #define LSTCU_14_15_17_18_ERR_STAT_RFSF_SHIFT (17U) 155 #define LSTCU_14_15_17_18_ERR_STAT_RFSF_WIDTH (1U) 156 #define LSTCU_14_15_17_18_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_ERR_STAT_RFSF_SHIFT)) & LSTCU_14_15_17_18_ERR_STAT_RFSF_MASK) 157 /*! @} */ 158 159 /*! @name ERR_FM - Error Fault Mapping */ 160 /*! @{ */ 161 162 #define LSTCU_14_15_17_18_ERR_FM_INVPFMMB_MASK (0x2U) 163 #define LSTCU_14_15_17_18_ERR_FM_INVPFMMB_SHIFT (1U) 164 #define LSTCU_14_15_17_18_ERR_FM_INVPFMMB_WIDTH (1U) 165 #define LSTCU_14_15_17_18_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_ERR_FM_INVPFMMB_SHIFT)) & LSTCU_14_15_17_18_ERR_FM_INVPFMMB_MASK) 166 167 #define LSTCU_14_15_17_18_ERR_FM_INVPFMLB_MASK (0x4U) 168 #define LSTCU_14_15_17_18_ERR_FM_INVPFMLB_SHIFT (2U) 169 #define LSTCU_14_15_17_18_ERR_FM_INVPFMLB_WIDTH (1U) 170 #define LSTCU_14_15_17_18_ERR_FM_INVPFMLB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_ERR_FM_INVPFMLB_SHIFT)) & LSTCU_14_15_17_18_ERR_FM_INVPFMLB_MASK) 171 /*! @} */ 172 173 /*! @name MB_RSTAT0 - MBIST Run Status 0 */ 174 /*! @{ */ 175 176 #define LSTCU_14_15_17_18_MB_RSTAT0_MBSTAT0_MASK (0x1U) 177 #define LSTCU_14_15_17_18_MB_RSTAT0_MBSTAT0_SHIFT (0U) 178 #define LSTCU_14_15_17_18_MB_RSTAT0_MBSTAT0_WIDTH (1U) 179 #define LSTCU_14_15_17_18_MB_RSTAT0_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_MB_RSTAT0_MBSTAT0_SHIFT)) & LSTCU_14_15_17_18_MB_RSTAT0_MBSTAT0_MASK) 180 /*! @} */ 181 182 /*! @name MB_RSTAT1 - MBIST Run Status 1 */ 183 /*! @{ */ 184 185 #define LSTCU_14_15_17_18_MB_RSTAT1_MBSTAT0_MASK (0x1U) 186 #define LSTCU_14_15_17_18_MB_RSTAT1_MBSTAT0_SHIFT (0U) 187 #define LSTCU_14_15_17_18_MB_RSTAT1_MBSTAT0_WIDTH (1U) 188 #define LSTCU_14_15_17_18_MB_RSTAT1_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_MB_RSTAT1_MBSTAT0_SHIFT)) & LSTCU_14_15_17_18_MB_RSTAT1_MBSTAT0_MASK) 189 /*! @} */ 190 191 /*! @name LB_RSTAT0 - LBIST Run Status 0 */ 192 /*! @{ */ 193 194 #define LSTCU_14_15_17_18_LB_RSTAT0_LBSTAT0_MASK (0x1U) 195 #define LSTCU_14_15_17_18_LB_RSTAT0_LBSTAT0_SHIFT (0U) 196 #define LSTCU_14_15_17_18_LB_RSTAT0_LBSTAT0_WIDTH (1U) 197 #define LSTCU_14_15_17_18_LB_RSTAT0_LBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_LB_RSTAT0_LBSTAT0_SHIFT)) & LSTCU_14_15_17_18_LB_RSTAT0_LBSTAT0_MASK) 198 /*! @} */ 199 200 /*! @name MBFM0 - MBIST Fault Mapping 0 */ 201 /*! @{ */ 202 203 #define LSTCU_14_15_17_18_MBFM0_MBSTATFM0_MASK (0x1U) 204 #define LSTCU_14_15_17_18_MBFM0_MBSTATFM0_SHIFT (0U) 205 #define LSTCU_14_15_17_18_MBFM0_MBSTATFM0_WIDTH (1U) 206 #define LSTCU_14_15_17_18_MBFM0_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_MBFM0_MBSTATFM0_SHIFT)) & LSTCU_14_15_17_18_MBFM0_MBSTATFM0_MASK) 207 /*! @} */ 208 209 /*! @name MBFM1 - MBIST Fault Mapping 1 */ 210 /*! @{ */ 211 212 #define LSTCU_14_15_17_18_MBFM1_MBSTATFM0_MASK (0x1U) 213 #define LSTCU_14_15_17_18_MBFM1_MBSTATFM0_SHIFT (0U) 214 #define LSTCU_14_15_17_18_MBFM1_MBSTATFM0_WIDTH (1U) 215 #define LSTCU_14_15_17_18_MBFM1_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_MBFM1_MBSTATFM0_SHIFT)) & LSTCU_14_15_17_18_MBFM1_MBSTATFM0_MASK) 216 /*! @} */ 217 218 /*! @name LBFM0 - LBIST Fault Mapping 0 */ 219 /*! @{ */ 220 221 #define LSTCU_14_15_17_18_LBFM0_LBSTATFM0_MASK (0x1U) 222 #define LSTCU_14_15_17_18_LBFM0_LBSTATFM0_SHIFT (0U) 223 #define LSTCU_14_15_17_18_LBFM0_LBSTATFM0_WIDTH (1U) 224 #define LSTCU_14_15_17_18_LBFM0_LBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_LBFM0_LBSTATFM0_SHIFT)) & LSTCU_14_15_17_18_LBFM0_LBSTATFM0_MASK) 225 /*! @} */ 226 227 /*! @name STAG - Stagger */ 228 /*! @{ */ 229 230 #define LSTCU_14_15_17_18_STAG_MB_DELAY_MASK (0xFF00U) 231 #define LSTCU_14_15_17_18_STAG_MB_DELAY_SHIFT (8U) 232 #define LSTCU_14_15_17_18_STAG_MB_DELAY_WIDTH (8U) 233 #define LSTCU_14_15_17_18_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_STAG_MB_DELAY_SHIFT)) & LSTCU_14_15_17_18_STAG_MB_DELAY_MASK) 234 235 #define LSTCU_14_15_17_18_STAG_LB_DELAY_MASK (0xFF0000U) 236 #define LSTCU_14_15_17_18_STAG_LB_DELAY_SHIFT (16U) 237 #define LSTCU_14_15_17_18_STAG_LB_DELAY_WIDTH (8U) 238 #define LSTCU_14_15_17_18_STAG_LB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_STAG_LB_DELAY_SHIFT)) & LSTCU_14_15_17_18_STAG_LB_DELAY_MASK) 239 /*! @} */ 240 241 /*! @name PH1_DUR - Phase 1 Duration */ 242 /*! @{ */ 243 244 #define LSTCU_14_15_17_18_PH1_DUR_PH1DUR_MASK (0x3FFU) 245 #define LSTCU_14_15_17_18_PH1_DUR_PH1DUR_SHIFT (0U) 246 #define LSTCU_14_15_17_18_PH1_DUR_PH1DUR_WIDTH (10U) 247 #define LSTCU_14_15_17_18_PH1_DUR_PH1DUR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_PH1_DUR_PH1DUR_SHIFT)) & LSTCU_14_15_17_18_PH1_DUR_PH1DUR_MASK) 248 /*! @} */ 249 250 /*! @name MBPTR - MBIST Scheduler Pointer */ 251 /*! @{ */ 252 253 #define LSTCU_14_15_17_18_MBPTR_MBPTR_MASK (0xFFU) 254 #define LSTCU_14_15_17_18_MBPTR_MBPTR_SHIFT (0U) 255 #define LSTCU_14_15_17_18_MBPTR_MBPTR_WIDTH (8U) 256 #define LSTCU_14_15_17_18_MBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_MBPTR_MBPTR_SHIFT)) & LSTCU_14_15_17_18_MBPTR_MBPTR_MASK) 257 258 #define LSTCU_14_15_17_18_MBPTR_MBCSM_MASK (0x100U) 259 #define LSTCU_14_15_17_18_MBPTR_MBCSM_SHIFT (8U) 260 #define LSTCU_14_15_17_18_MBPTR_MBCSM_WIDTH (1U) 261 #define LSTCU_14_15_17_18_MBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_MBPTR_MBCSM_SHIFT)) & LSTCU_14_15_17_18_MBPTR_MBCSM_MASK) 262 263 #define LSTCU_14_15_17_18_MBPTR_MBEOL_MASK (0x80000000U) 264 #define LSTCU_14_15_17_18_MBPTR_MBEOL_SHIFT (31U) 265 #define LSTCU_14_15_17_18_MBPTR_MBEOL_WIDTH (1U) 266 #define LSTCU_14_15_17_18_MBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_MBPTR_MBEOL_SHIFT)) & LSTCU_14_15_17_18_MBPTR_MBEOL_MASK) 267 /*! @} */ 268 269 /*! @name LBPTR - LBIST Scheduler Pointer */ 270 /*! @{ */ 271 272 #define LSTCU_14_15_17_18_LBPTR_LBPTR_MASK (0xFFU) 273 #define LSTCU_14_15_17_18_LBPTR_LBPTR_SHIFT (0U) 274 #define LSTCU_14_15_17_18_LBPTR_LBPTR_WIDTH (8U) 275 #define LSTCU_14_15_17_18_LBPTR_LBPTR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_LBPTR_LBPTR_SHIFT)) & LSTCU_14_15_17_18_LBPTR_LBPTR_MASK) 276 277 #define LSTCU_14_15_17_18_LBPTR_LBCSM_MASK (0x100U) 278 #define LSTCU_14_15_17_18_LBPTR_LBCSM_SHIFT (8U) 279 #define LSTCU_14_15_17_18_LBPTR_LBCSM_WIDTH (1U) 280 #define LSTCU_14_15_17_18_LBPTR_LBCSM(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_LBPTR_LBCSM_SHIFT)) & LSTCU_14_15_17_18_LBPTR_LBCSM_MASK) 281 282 #define LSTCU_14_15_17_18_LBPTR_LBEOL_MASK (0x80000000U) 283 #define LSTCU_14_15_17_18_LBPTR_LBEOL_SHIFT (31U) 284 #define LSTCU_14_15_17_18_LBPTR_LBEOL_WIDTH (1U) 285 #define LSTCU_14_15_17_18_LBPTR_LBEOL(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_14_15_17_18_LBPTR_LBEOL_SHIFT)) & LSTCU_14_15_17_18_LBPTR_LBEOL_MASK) 286 /*! @} */ 287 288 /*! 289 * @} 290 */ /* end of group LSTCU_14_15_17_18_Register_Masks */ 291 292 /*! 293 * @} 294 */ /* end of group LSTCU_14_15_17_18_Peripheral_Access_Layer */ 295 296 #endif /* #if !defined(S32Z2_LSTCU_14_15_17_18_H_) */ 297
