1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LSTCU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_LSTCU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LSTCU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LSTCU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LSTCU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LSTCU_Peripheral_Access_Layer LSTCU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LSTCU - Size of Registers Arrays */ 72 #define LSTCU_MBIST_SCH_PTR_COUNT 1u 73 #define LSTCU_LBIST_SCH_PTR_COUNT 1u 74 75 /** LSTCU - Register Layout Typedef */ 76 typedef struct { 77 uint8_t RESERVED_0[8]; 78 __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x8 */ 79 uint8_t RESERVED_1[4]; 80 __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x10 */ 81 uint8_t RESERVED_2[76]; 82 __I uint32_t MB_RSTAT0; /**< MBIST Run Status 0, offset: 0x60 */ 83 uint8_t RESERVED_3[156]; 84 __I uint32_t LB_RSTAT0; /**< LBIST Run Status 0, offset: 0x100, not available in all instances (available on 10 out of 14) */ 85 uint8_t RESERVED_4[124]; 86 __IO uint32_t MBFM0; /**< MBIST Fault Mapping 0, offset: 0x180 */ 87 uint8_t RESERVED_5[156]; 88 __IO uint32_t LBFM0; /**< LBIST Fault Mapping 0, offset: 0x220, not available in all instances (available on 10 out of 14) */ 89 uint8_t RESERVED_6[60]; 90 __IO uint32_t STAG; /**< Stagger, offset: 0x260 */ 91 uint8_t RESERVED_7[12]; 92 __IO uint32_t PH1_DUR; /**< Phase 1 Duration, offset: 0x270 */ 93 __IO uint32_t ISODUR; /**< Isolation Duration, offset: 0x274 */ 94 __IO uint32_t SRCENDUR; /**< Synchronous Reset Clock Enable Duration, offset: 0x278 */ 95 uint8_t RESERVED_8[132]; 96 __IO uint32_t MBPTR[LSTCU_MBIST_SCH_PTR_COUNT]; /**< MBIST Scheduler Pointer, array offset: 0x300, array step: 0x4 */ 97 uint8_t RESERVED_9[156]; 98 __IO uint32_t LBPTR[LSTCU_LBIST_SCH_PTR_COUNT]; /**< LBIST Scheduler Pointer, array offset: 0x3A0, array step: 0x4, not available in all instances (available on 10 out of 14) */ 99 } LSTCU_Type, *LSTCU_MemMapPtr; 100 101 /** Number of instances of the LSTCU module. */ 102 #define LSTCU_INSTANCE_COUNT (14u) 103 104 /* LSTCU - Peripheral instance base addresses */ 105 /** Peripheral LSTCU_0 base address */ 106 #define IP_LSTCU_0_BASE (0x4D408000u) 107 /** Peripheral LSTCU_0 base pointer */ 108 #define IP_LSTCU_0 ((LSTCU_Type *)IP_LSTCU_0_BASE) 109 /** Peripheral LSTCU_1 base address */ 110 #define IP_LSTCU_1_BASE (0x4D208000u) 111 /** Peripheral LSTCU_1 base pointer */ 112 #define IP_LSTCU_1 ((LSTCU_Type *)IP_LSTCU_1_BASE) 113 /** Peripheral LSTCU_2 base address */ 114 #define IP_LSTCU_2_BASE (0x4D108000u) 115 /** Peripheral LSTCU_2 base pointer */ 116 #define IP_LSTCU_2 ((LSTCU_Type *)IP_LSTCU_2_BASE) 117 /** Peripheral LSTCU_3 base address */ 118 #define IP_LSTCU_3_BASE (0x4D288000u) 119 /** Peripheral LSTCU_3 base pointer */ 120 #define IP_LSTCU_3 ((LSTCU_Type *)IP_LSTCU_3_BASE) 121 /** Peripheral LSTCU_4 base address */ 122 #define IP_LSTCU_4_BASE (0x4D308000u) 123 /** Peripheral LSTCU_4 base pointer */ 124 #define IP_LSTCU_4 ((LSTCU_Type *)IP_LSTCU_4_BASE) 125 /** Peripheral LSTCU_5 base address */ 126 #define IP_LSTCU_5_BASE (0x4D388000u) 127 /** Peripheral LSTCU_5 base pointer */ 128 #define IP_LSTCU_5 ((LSTCU_Type *)IP_LSTCU_5_BASE) 129 /** Peripheral LSTCU_6 base address */ 130 #define IP_LSTCU_6_BASE (0x4D008000u) 131 /** Peripheral LSTCU_6 base pointer */ 132 #define IP_LSTCU_6 ((LSTCU_Type *)IP_LSTCU_6_BASE) 133 /** Peripheral LSTCU_7 base address */ 134 #define IP_LSTCU_7_BASE (0x4D209000u) 135 /** Peripheral LSTCU_7 base pointer */ 136 #define IP_LSTCU_7 ((LSTCU_Type *)IP_LSTCU_7_BASE) 137 /** Peripheral LSTCU_8 base address */ 138 #define IP_LSTCU_8_BASE (0x4D289000u) 139 /** Peripheral LSTCU_8 base pointer */ 140 #define IP_LSTCU_8 ((LSTCU_Type *)IP_LSTCU_8_BASE) 141 /** Peripheral LSTCU_9 base address */ 142 #define IP_LSTCU_9_BASE (0x4D409000u) 143 /** Peripheral LSTCU_9 base pointer */ 144 #define IP_LSTCU_9 ((LSTCU_Type *)IP_LSTCU_9_BASE) 145 /** Peripheral LSTCU_10 base address */ 146 #define IP_LSTCU_10_BASE (0x4D109000u) 147 /** Peripheral LSTCU_10 base pointer */ 148 #define IP_LSTCU_10 ((LSTCU_Type *)IP_LSTCU_10_BASE) 149 /** Peripheral LSTCU_11 base address */ 150 #define IP_LSTCU_11_BASE (0x4D10A000u) 151 /** Peripheral LSTCU_11 base pointer */ 152 #define IP_LSTCU_11 ((LSTCU_Type *)IP_LSTCU_11_BASE) 153 /** Peripheral LSTCU_12 base address */ 154 #define IP_LSTCU_12_BASE (0x4D309000u) 155 /** Peripheral LSTCU_12 base pointer */ 156 #define IP_LSTCU_12 ((LSTCU_Type *)IP_LSTCU_12_BASE) 157 /** Peripheral LSTCU_19 base address */ 158 #define IP_LSTCU_19_BASE (0x4D389000u) 159 /** Peripheral LSTCU_19 base pointer */ 160 #define IP_LSTCU_19 ((LSTCU_Type *)IP_LSTCU_19_BASE) 161 /** Array initializer of LSTCU peripheral base addresses */ 162 #define IP_LSTCU_BASE_ADDRS { IP_LSTCU_0_BASE, IP_LSTCU_1_BASE, IP_LSTCU_2_BASE, IP_LSTCU_3_BASE, IP_LSTCU_4_BASE, IP_LSTCU_5_BASE, IP_LSTCU_6_BASE, IP_LSTCU_7_BASE, IP_LSTCU_8_BASE, IP_LSTCU_9_BASE, IP_LSTCU_10_BASE, IP_LSTCU_11_BASE, IP_LSTCU_12_BASE, IP_LSTCU_19_BASE } 163 /** Array initializer of LSTCU peripheral base pointers */ 164 #define IP_LSTCU_BASE_PTRS { IP_LSTCU_0, IP_LSTCU_1, IP_LSTCU_2, IP_LSTCU_3, IP_LSTCU_4, IP_LSTCU_5, IP_LSTCU_6, IP_LSTCU_7, IP_LSTCU_8, IP_LSTCU_9, IP_LSTCU_10, IP_LSTCU_11, IP_LSTCU_12, IP_LSTCU_19 } 165 166 /* ---------------------------------------------------------------------------- 167 -- LSTCU Register Masks 168 ---------------------------------------------------------------------------- */ 169 170 /*! 171 * @addtogroup LSTCU_Register_Masks LSTCU Register Masks 172 * @{ 173 */ 174 175 /*! @name ERR_STAT - Error Status */ 176 /*! @{ */ 177 178 #define LSTCU_ERR_STAT_INVP_MB_MASK (0x2U) 179 #define LSTCU_ERR_STAT_INVP_MB_SHIFT (1U) 180 #define LSTCU_ERR_STAT_INVP_MB_WIDTH (1U) 181 #define LSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ERR_STAT_INVP_MB_SHIFT)) & LSTCU_ERR_STAT_INVP_MB_MASK) 182 183 #define LSTCU_ERR_STAT_INVP_LB_MASK (0x4U) 184 #define LSTCU_ERR_STAT_INVP_LB_SHIFT (2U) 185 #define LSTCU_ERR_STAT_INVP_LB_WIDTH (1U) 186 #define LSTCU_ERR_STAT_INVP_LB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ERR_STAT_INVP_LB_SHIFT)) & LSTCU_ERR_STAT_INVP_LB_MASK) 187 188 #define LSTCU_ERR_STAT_UFSF_MASK (0x10000U) 189 #define LSTCU_ERR_STAT_UFSF_SHIFT (16U) 190 #define LSTCU_ERR_STAT_UFSF_WIDTH (1U) 191 #define LSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ERR_STAT_UFSF_SHIFT)) & LSTCU_ERR_STAT_UFSF_MASK) 192 193 #define LSTCU_ERR_STAT_RFSF_MASK (0x20000U) 194 #define LSTCU_ERR_STAT_RFSF_SHIFT (17U) 195 #define LSTCU_ERR_STAT_RFSF_WIDTH (1U) 196 #define LSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ERR_STAT_RFSF_SHIFT)) & LSTCU_ERR_STAT_RFSF_MASK) 197 /*! @} */ 198 199 /*! @name ERR_FM - Error Fault Mapping */ 200 /*! @{ */ 201 202 #define LSTCU_ERR_FM_INVPFMMB_MASK (0x2U) 203 #define LSTCU_ERR_FM_INVPFMMB_SHIFT (1U) 204 #define LSTCU_ERR_FM_INVPFMMB_WIDTH (1U) 205 #define LSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ERR_FM_INVPFMMB_SHIFT)) & LSTCU_ERR_FM_INVPFMMB_MASK) 206 207 #define LSTCU_ERR_FM_INVPFMLB_MASK (0x4U) 208 #define LSTCU_ERR_FM_INVPFMLB_SHIFT (2U) 209 #define LSTCU_ERR_FM_INVPFMLB_WIDTH (1U) 210 #define LSTCU_ERR_FM_INVPFMLB(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ERR_FM_INVPFMLB_SHIFT)) & LSTCU_ERR_FM_INVPFMLB_MASK) 211 /*! @} */ 212 213 /*! @name MB_RSTAT0 - MBIST Run Status 0 */ 214 /*! @{ */ 215 216 #define LSTCU_MB_RSTAT0_MBSTAT0_MASK (0x1U) 217 #define LSTCU_MB_RSTAT0_MBSTAT0_SHIFT (0U) 218 #define LSTCU_MB_RSTAT0_MBSTAT0_WIDTH (1U) 219 #define LSTCU_MB_RSTAT0_MBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_MB_RSTAT0_MBSTAT0_SHIFT)) & LSTCU_MB_RSTAT0_MBSTAT0_MASK) 220 /*! @} */ 221 222 /*! @name LB_RSTAT0 - LBIST Run Status 0 */ 223 /*! @{ */ 224 225 #define LSTCU_LB_RSTAT0_LBSTAT0_MASK (0x1U) 226 #define LSTCU_LB_RSTAT0_LBSTAT0_SHIFT (0U) 227 #define LSTCU_LB_RSTAT0_LBSTAT0_WIDTH (1U) 228 #define LSTCU_LB_RSTAT0_LBSTAT0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_LB_RSTAT0_LBSTAT0_SHIFT)) & LSTCU_LB_RSTAT0_LBSTAT0_MASK) 229 /*! @} */ 230 231 /*! @name MBFM0 - MBIST Fault Mapping 0 */ 232 /*! @{ */ 233 234 #define LSTCU_MBFM0_MBSTATFM0_MASK (0x1U) 235 #define LSTCU_MBFM0_MBSTATFM0_SHIFT (0U) 236 #define LSTCU_MBFM0_MBSTATFM0_WIDTH (1U) 237 #define LSTCU_MBFM0_MBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_MBFM0_MBSTATFM0_SHIFT)) & LSTCU_MBFM0_MBSTATFM0_MASK) 238 /*! @} */ 239 240 /*! @name LBFM0 - LBIST Fault Mapping 0 */ 241 /*! @{ */ 242 243 #define LSTCU_LBFM0_LBSTATFM0_MASK (0x1U) 244 #define LSTCU_LBFM0_LBSTATFM0_SHIFT (0U) 245 #define LSTCU_LBFM0_LBSTATFM0_WIDTH (1U) 246 #define LSTCU_LBFM0_LBSTATFM0(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_LBFM0_LBSTATFM0_SHIFT)) & LSTCU_LBFM0_LBSTATFM0_MASK) 247 /*! @} */ 248 249 /*! @name STAG - Stagger */ 250 /*! @{ */ 251 252 #define LSTCU_STAG_MB_DELAY_MASK (0xFF00U) 253 #define LSTCU_STAG_MB_DELAY_SHIFT (8U) 254 #define LSTCU_STAG_MB_DELAY_WIDTH (8U) 255 #define LSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_STAG_MB_DELAY_SHIFT)) & LSTCU_STAG_MB_DELAY_MASK) 256 257 #define LSTCU_STAG_LB_DELAY_MASK (0xFF0000U) 258 #define LSTCU_STAG_LB_DELAY_SHIFT (16U) 259 #define LSTCU_STAG_LB_DELAY_WIDTH (8U) 260 #define LSTCU_STAG_LB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_STAG_LB_DELAY_SHIFT)) & LSTCU_STAG_LB_DELAY_MASK) 261 /*! @} */ 262 263 /*! @name PH1_DUR - Phase 1 Duration */ 264 /*! @{ */ 265 266 #define LSTCU_PH1_DUR_PH1DUR_MASK (0x3FFU) 267 #define LSTCU_PH1_DUR_PH1DUR_SHIFT (0U) 268 #define LSTCU_PH1_DUR_PH1DUR_WIDTH (10U) 269 #define LSTCU_PH1_DUR_PH1DUR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_PH1_DUR_PH1DUR_SHIFT)) & LSTCU_PH1_DUR_PH1DUR_MASK) 270 /*! @} */ 271 272 /*! @name ISODUR - Isolation Duration */ 273 /*! @{ */ 274 275 #define LSTCU_ISODUR_EN_DUR_MASK (0x3FFU) 276 #define LSTCU_ISODUR_EN_DUR_SHIFT (0U) 277 #define LSTCU_ISODUR_EN_DUR_WIDTH (10U) 278 #define LSTCU_ISODUR_EN_DUR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ISODUR_EN_DUR_SHIFT)) & LSTCU_ISODUR_EN_DUR_MASK) 279 280 #define LSTCU_ISODUR_DIS_DUR_MASK (0x3FF0000U) 281 #define LSTCU_ISODUR_DIS_DUR_SHIFT (16U) 282 #define LSTCU_ISODUR_DIS_DUR_WIDTH (10U) 283 #define LSTCU_ISODUR_DIS_DUR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_ISODUR_DIS_DUR_SHIFT)) & LSTCU_ISODUR_DIS_DUR_MASK) 284 /*! @} */ 285 286 /*! @name SRCENDUR - Synchronous Reset Clock Enable Duration */ 287 /*! @{ */ 288 289 #define LSTCU_SRCENDUR_CLKENDUR_MASK (0x3FFU) 290 #define LSTCU_SRCENDUR_CLKENDUR_SHIFT (0U) 291 #define LSTCU_SRCENDUR_CLKENDUR_WIDTH (10U) 292 #define LSTCU_SRCENDUR_CLKENDUR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_SRCENDUR_CLKENDUR_SHIFT)) & LSTCU_SRCENDUR_CLKENDUR_MASK) 293 /*! @} */ 294 295 /*! @name MBPTR - MBIST Scheduler Pointer */ 296 /*! @{ */ 297 298 #define LSTCU_MBPTR_MBPTR_MASK (0xFFU) 299 #define LSTCU_MBPTR_MBPTR_SHIFT (0U) 300 #define LSTCU_MBPTR_MBPTR_WIDTH (8U) 301 #define LSTCU_MBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_MBPTR_MBPTR_SHIFT)) & LSTCU_MBPTR_MBPTR_MASK) 302 303 #define LSTCU_MBPTR_MBCSM_MASK (0x100U) 304 #define LSTCU_MBPTR_MBCSM_SHIFT (8U) 305 #define LSTCU_MBPTR_MBCSM_WIDTH (1U) 306 #define LSTCU_MBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_MBPTR_MBCSM_SHIFT)) & LSTCU_MBPTR_MBCSM_MASK) 307 308 #define LSTCU_MBPTR_MBEOL_MASK (0x80000000U) 309 #define LSTCU_MBPTR_MBEOL_SHIFT (31U) 310 #define LSTCU_MBPTR_MBEOL_WIDTH (1U) 311 #define LSTCU_MBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_MBPTR_MBEOL_SHIFT)) & LSTCU_MBPTR_MBEOL_MASK) 312 /*! @} */ 313 314 /*! @name LBPTR - LBIST Scheduler Pointer */ 315 /*! @{ */ 316 317 #define LSTCU_LBPTR_LBPTR_MASK (0xFFU) 318 #define LSTCU_LBPTR_LBPTR_SHIFT (0U) 319 #define LSTCU_LBPTR_LBPTR_WIDTH (8U) 320 #define LSTCU_LBPTR_LBPTR(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_LBPTR_LBPTR_SHIFT)) & LSTCU_LBPTR_LBPTR_MASK) 321 322 #define LSTCU_LBPTR_LBCSM_MASK (0x100U) 323 #define LSTCU_LBPTR_LBCSM_SHIFT (8U) 324 #define LSTCU_LBPTR_LBCSM_WIDTH (1U) 325 #define LSTCU_LBPTR_LBCSM(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_LBPTR_LBCSM_SHIFT)) & LSTCU_LBPTR_LBCSM_MASK) 326 327 #define LSTCU_LBPTR_LBEOL_MASK (0x80000000U) 328 #define LSTCU_LBPTR_LBEOL_SHIFT (31U) 329 #define LSTCU_LBPTR_LBEOL_WIDTH (1U) 330 #define LSTCU_LBPTR_LBEOL(x) (((uint32_t)(((uint32_t)(x)) << LSTCU_LBPTR_LBEOL_SHIFT)) & LSTCU_LBPTR_LBEOL_MASK) 331 /*! @} */ 332 333 /*! 334 * @} 335 */ /* end of group LSTCU_Register_Masks */ 336 337 /*! 338 * @} 339 */ /* end of group LSTCU_Peripheral_Access_Layer */ 340 341 #endif /* #if !defined(S32Z2_LSTCU_H_) */ 342
