1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LMEM64.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_LMEM64 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LMEM64_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LMEM64_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LMEM64 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LMEM64_Peripheral_Access_Layer LMEM64 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LMEM64 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t PCCCR; /**< PC bus Cache control register, offset: 0x0 */ 74 __IO uint32_t PCCLCR; /**< PC bus Cache line control register, offset: 0x4 */ 75 __IO uint32_t PCCSAR; /**< PC bus Cache search address register, offset: 0x8 */ 76 __IO uint32_t PCCCVR; /**< PC bus Cache read/write value register, offset: 0xC */ 77 uint8_t RESERVED_0[2032]; 78 __IO uint32_t PSCCR; /**< PS bus Cache control register, offset: 0x800 */ 79 __IO uint32_t PSCLCR; /**< PS bus Cache line control register, offset: 0x804 */ 80 __IO uint32_t PSCSAR; /**< PS bus Cache search address register, offset: 0x808 */ 81 __IO uint32_t PSCCVR; /**< PS bus Cache read/write value register, offset: 0x80C */ 82 } LMEM64_Type, *LMEM64_MemMapPtr; 83 84 /** Number of instances of the LMEM64 module. */ 85 #define LMEM64_INSTANCE_COUNT (2u) 86 87 /* LMEM64 - Peripheral instance base addresses */ 88 /** Peripheral CE_LMEM64 base address */ 89 #define IP_CE_LMEM64_BASE (0xE0082000u) 90 /** Peripheral CE_LMEM64 base pointer */ 91 #define IP_CE_LMEM64 ((LMEM64_Type *)IP_CE_LMEM64_BASE) 92 /** Peripheral SMU__LMEM64 base address */ 93 #define IP_SMU__LMEM64_BASE (0xE0082000u) 94 /** Peripheral SMU__LMEM64 base pointer */ 95 #define IP_SMU__LMEM64 ((LMEM64_Type *)IP_SMU__LMEM64_BASE) 96 /** Array initializer of LMEM64 peripheral base addresses */ 97 #define IP_LMEM64_BASE_ADDRS { IP_CE_LMEM64_BASE, IP_SMU__LMEM64_BASE } 98 /** Array initializer of LMEM64 peripheral base pointers */ 99 #define IP_LMEM64_BASE_PTRS { IP_CE_LMEM64, IP_SMU__LMEM64 } 100 101 /* ---------------------------------------------------------------------------- 102 -- LMEM64 Register Masks 103 ---------------------------------------------------------------------------- */ 104 105 /*! 106 * @addtogroup LMEM64_Register_Masks LMEM64 Register Masks 107 * @{ 108 */ 109 110 /*! @name PCCCR - PC bus Cache control register */ 111 /*! @{ */ 112 113 #define LMEM64_PCCCR_ENCACHE_MASK (0x1U) 114 #define LMEM64_PCCCR_ENCACHE_SHIFT (0U) 115 #define LMEM64_PCCCR_ENCACHE_WIDTH (1U) 116 #define LMEM64_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_ENCACHE_SHIFT)) & LMEM64_PCCCR_ENCACHE_MASK) 117 118 #define LMEM64_PCCCR_ENWRBUF_MASK (0x2U) 119 #define LMEM64_PCCCR_ENWRBUF_SHIFT (1U) 120 #define LMEM64_PCCCR_ENWRBUF_WIDTH (1U) 121 #define LMEM64_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_ENWRBUF_SHIFT)) & LMEM64_PCCCR_ENWRBUF_MASK) 122 123 #define LMEM64_PCCCR_PCCR2_MASK (0x4U) 124 #define LMEM64_PCCCR_PCCR2_SHIFT (2U) 125 #define LMEM64_PCCCR_PCCR2_WIDTH (1U) 126 #define LMEM64_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_PCCR2_SHIFT)) & LMEM64_PCCCR_PCCR2_MASK) 127 128 #define LMEM64_PCCCR_PCCR3_MASK (0x8U) 129 #define LMEM64_PCCCR_PCCR3_SHIFT (3U) 130 #define LMEM64_PCCCR_PCCR3_WIDTH (1U) 131 #define LMEM64_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_PCCR3_SHIFT)) & LMEM64_PCCCR_PCCR3_MASK) 132 133 #define LMEM64_PCCCR_INVW0_MASK (0x1000000U) 134 #define LMEM64_PCCCR_INVW0_SHIFT (24U) 135 #define LMEM64_PCCCR_INVW0_WIDTH (1U) 136 #define LMEM64_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_INVW0_SHIFT)) & LMEM64_PCCCR_INVW0_MASK) 137 138 #define LMEM64_PCCCR_PUSHW0_MASK (0x2000000U) 139 #define LMEM64_PCCCR_PUSHW0_SHIFT (25U) 140 #define LMEM64_PCCCR_PUSHW0_WIDTH (1U) 141 #define LMEM64_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_PUSHW0_SHIFT)) & LMEM64_PCCCR_PUSHW0_MASK) 142 143 #define LMEM64_PCCCR_INVW1_MASK (0x4000000U) 144 #define LMEM64_PCCCR_INVW1_SHIFT (26U) 145 #define LMEM64_PCCCR_INVW1_WIDTH (1U) 146 #define LMEM64_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_INVW1_SHIFT)) & LMEM64_PCCCR_INVW1_MASK) 147 148 #define LMEM64_PCCCR_PUSHW1_MASK (0x8000000U) 149 #define LMEM64_PCCCR_PUSHW1_SHIFT (27U) 150 #define LMEM64_PCCCR_PUSHW1_WIDTH (1U) 151 #define LMEM64_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_PUSHW1_SHIFT)) & LMEM64_PCCCR_PUSHW1_MASK) 152 153 #define LMEM64_PCCCR_GO_MASK (0x80000000U) 154 #define LMEM64_PCCCR_GO_SHIFT (31U) 155 #define LMEM64_PCCCR_GO_WIDTH (1U) 156 #define LMEM64_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCR_GO_SHIFT)) & LMEM64_PCCCR_GO_MASK) 157 /*! @} */ 158 159 /*! @name PCCLCR - PC bus Cache line control register */ 160 /*! @{ */ 161 162 #define LMEM64_PCCLCR_LGO_MASK (0x1U) 163 #define LMEM64_PCCLCR_LGO_SHIFT (0U) 164 #define LMEM64_PCCLCR_LGO_WIDTH (1U) 165 #define LMEM64_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_LGO_SHIFT)) & LMEM64_PCCLCR_LGO_MASK) 166 167 #define LMEM64_PCCLCR_CACHEADDR_MASK (0x3FFCU) 168 #define LMEM64_PCCLCR_CACHEADDR_SHIFT (2U) 169 #define LMEM64_PCCLCR_CACHEADDR_WIDTH (12U) 170 #define LMEM64_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_CACHEADDR_SHIFT)) & LMEM64_PCCLCR_CACHEADDR_MASK) 171 172 #define LMEM64_PCCLCR_WSEL_MASK (0x4000U) 173 #define LMEM64_PCCLCR_WSEL_SHIFT (14U) 174 #define LMEM64_PCCLCR_WSEL_WIDTH (1U) 175 #define LMEM64_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_WSEL_SHIFT)) & LMEM64_PCCLCR_WSEL_MASK) 176 177 #define LMEM64_PCCLCR_TDSEL_MASK (0x10000U) 178 #define LMEM64_PCCLCR_TDSEL_SHIFT (16U) 179 #define LMEM64_PCCLCR_TDSEL_WIDTH (1U) 180 #define LMEM64_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_TDSEL_SHIFT)) & LMEM64_PCCLCR_TDSEL_MASK) 181 182 #define LMEM64_PCCLCR_LCIVB_MASK (0x100000U) 183 #define LMEM64_PCCLCR_LCIVB_SHIFT (20U) 184 #define LMEM64_PCCLCR_LCIVB_WIDTH (1U) 185 #define LMEM64_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_LCIVB_SHIFT)) & LMEM64_PCCLCR_LCIVB_MASK) 186 187 #define LMEM64_PCCLCR_LCIMB_MASK (0x200000U) 188 #define LMEM64_PCCLCR_LCIMB_SHIFT (21U) 189 #define LMEM64_PCCLCR_LCIMB_WIDTH (1U) 190 #define LMEM64_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_LCIMB_SHIFT)) & LMEM64_PCCLCR_LCIMB_MASK) 191 192 #define LMEM64_PCCLCR_LCWAY_MASK (0x400000U) 193 #define LMEM64_PCCLCR_LCWAY_SHIFT (22U) 194 #define LMEM64_PCCLCR_LCWAY_WIDTH (1U) 195 #define LMEM64_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_LCWAY_SHIFT)) & LMEM64_PCCLCR_LCWAY_MASK) 196 197 #define LMEM64_PCCLCR_LCMD_MASK (0x3000000U) 198 #define LMEM64_PCCLCR_LCMD_SHIFT (24U) 199 #define LMEM64_PCCLCR_LCMD_WIDTH (2U) 200 #define LMEM64_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_LCMD_SHIFT)) & LMEM64_PCCLCR_LCMD_MASK) 201 202 #define LMEM64_PCCLCR_LADSEL_MASK (0x4000000U) 203 #define LMEM64_PCCLCR_LADSEL_SHIFT (26U) 204 #define LMEM64_PCCLCR_LADSEL_WIDTH (1U) 205 #define LMEM64_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_LADSEL_SHIFT)) & LMEM64_PCCLCR_LADSEL_MASK) 206 207 #define LMEM64_PCCLCR_LACC_MASK (0x8000000U) 208 #define LMEM64_PCCLCR_LACC_SHIFT (27U) 209 #define LMEM64_PCCLCR_LACC_WIDTH (1U) 210 #define LMEM64_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCLCR_LACC_SHIFT)) & LMEM64_PCCLCR_LACC_MASK) 211 /*! @} */ 212 213 /*! @name PCCSAR - PC bus Cache search address register */ 214 /*! @{ */ 215 216 #define LMEM64_PCCSAR_LGO_MASK (0x1U) 217 #define LMEM64_PCCSAR_LGO_SHIFT (0U) 218 #define LMEM64_PCCSAR_LGO_WIDTH (1U) 219 #define LMEM64_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCSAR_LGO_SHIFT)) & LMEM64_PCCSAR_LGO_MASK) 220 221 #define LMEM64_PCCSAR_PHYADDR_MASK (0xFFFFFFFEU) 222 #define LMEM64_PCCSAR_PHYADDR_SHIFT (1U) 223 #define LMEM64_PCCSAR_PHYADDR_WIDTH (31U) 224 #define LMEM64_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCSAR_PHYADDR_SHIFT)) & LMEM64_PCCSAR_PHYADDR_MASK) 225 /*! @} */ 226 227 /*! @name PCCCVR - PC bus Cache read/write value register */ 228 /*! @{ */ 229 230 #define LMEM64_PCCCVR_DATA_MASK (0xFFFFFFFFU) 231 #define LMEM64_PCCCVR_DATA_SHIFT (0U) 232 #define LMEM64_PCCCVR_DATA_WIDTH (32U) 233 #define LMEM64_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PCCCVR_DATA_SHIFT)) & LMEM64_PCCCVR_DATA_MASK) 234 /*! @} */ 235 236 /*! @name PSCCR - PS bus Cache control register */ 237 /*! @{ */ 238 239 #define LMEM64_PSCCR_ENCACHE_MASK (0x1U) 240 #define LMEM64_PSCCR_ENCACHE_SHIFT (0U) 241 #define LMEM64_PSCCR_ENCACHE_WIDTH (1U) 242 #define LMEM64_PSCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_ENCACHE_SHIFT)) & LMEM64_PSCCR_ENCACHE_MASK) 243 244 #define LMEM64_PSCCR_ENWRBUF_MASK (0x2U) 245 #define LMEM64_PSCCR_ENWRBUF_SHIFT (1U) 246 #define LMEM64_PSCCR_ENWRBUF_WIDTH (1U) 247 #define LMEM64_PSCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_ENWRBUF_SHIFT)) & LMEM64_PSCCR_ENWRBUF_MASK) 248 249 #define LMEM64_PSCCR_PSCR2_MASK (0x4U) 250 #define LMEM64_PSCCR_PSCR2_SHIFT (2U) 251 #define LMEM64_PSCCR_PSCR2_WIDTH (1U) 252 #define LMEM64_PSCCR_PSCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_PSCR2_SHIFT)) & LMEM64_PSCCR_PSCR2_MASK) 253 254 #define LMEM64_PSCCR_PSCR3_MASK (0x8U) 255 #define LMEM64_PSCCR_PSCR3_SHIFT (3U) 256 #define LMEM64_PSCCR_PSCR3_WIDTH (1U) 257 #define LMEM64_PSCCR_PSCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_PSCR3_SHIFT)) & LMEM64_PSCCR_PSCR3_MASK) 258 259 #define LMEM64_PSCCR_INVW0_MASK (0x1000000U) 260 #define LMEM64_PSCCR_INVW0_SHIFT (24U) 261 #define LMEM64_PSCCR_INVW0_WIDTH (1U) 262 #define LMEM64_PSCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_INVW0_SHIFT)) & LMEM64_PSCCR_INVW0_MASK) 263 264 #define LMEM64_PSCCR_PUSHW0_MASK (0x2000000U) 265 #define LMEM64_PSCCR_PUSHW0_SHIFT (25U) 266 #define LMEM64_PSCCR_PUSHW0_WIDTH (1U) 267 #define LMEM64_PSCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_PUSHW0_SHIFT)) & LMEM64_PSCCR_PUSHW0_MASK) 268 269 #define LMEM64_PSCCR_INVW1_MASK (0x4000000U) 270 #define LMEM64_PSCCR_INVW1_SHIFT (26U) 271 #define LMEM64_PSCCR_INVW1_WIDTH (1U) 272 #define LMEM64_PSCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_INVW1_SHIFT)) & LMEM64_PSCCR_INVW1_MASK) 273 274 #define LMEM64_PSCCR_PUSHW1_MASK (0x8000000U) 275 #define LMEM64_PSCCR_PUSHW1_SHIFT (27U) 276 #define LMEM64_PSCCR_PUSHW1_WIDTH (1U) 277 #define LMEM64_PSCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_PUSHW1_SHIFT)) & LMEM64_PSCCR_PUSHW1_MASK) 278 279 #define LMEM64_PSCCR_GO_MASK (0x80000000U) 280 #define LMEM64_PSCCR_GO_SHIFT (31U) 281 #define LMEM64_PSCCR_GO_WIDTH (1U) 282 #define LMEM64_PSCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCR_GO_SHIFT)) & LMEM64_PSCCR_GO_MASK) 283 /*! @} */ 284 285 /*! @name PSCLCR - PS bus Cache line control register */ 286 /*! @{ */ 287 288 #define LMEM64_PSCLCR_LGO_MASK (0x1U) 289 #define LMEM64_PSCLCR_LGO_SHIFT (0U) 290 #define LMEM64_PSCLCR_LGO_WIDTH (1U) 291 #define LMEM64_PSCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_LGO_SHIFT)) & LMEM64_PSCLCR_LGO_MASK) 292 293 #define LMEM64_PSCLCR_CACHEADDR_MASK (0x3FFCU) 294 #define LMEM64_PSCLCR_CACHEADDR_SHIFT (2U) 295 #define LMEM64_PSCLCR_CACHEADDR_WIDTH (12U) 296 #define LMEM64_PSCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_CACHEADDR_SHIFT)) & LMEM64_PSCLCR_CACHEADDR_MASK) 297 298 #define LMEM64_PSCLCR_WSEL_MASK (0x4000U) 299 #define LMEM64_PSCLCR_WSEL_SHIFT (14U) 300 #define LMEM64_PSCLCR_WSEL_WIDTH (1U) 301 #define LMEM64_PSCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_WSEL_SHIFT)) & LMEM64_PSCLCR_WSEL_MASK) 302 303 #define LMEM64_PSCLCR_TDSEL_MASK (0x10000U) 304 #define LMEM64_PSCLCR_TDSEL_SHIFT (16U) 305 #define LMEM64_PSCLCR_TDSEL_WIDTH (1U) 306 #define LMEM64_PSCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_TDSEL_SHIFT)) & LMEM64_PSCLCR_TDSEL_MASK) 307 308 #define LMEM64_PSCLCR_LCIVB_MASK (0x100000U) 309 #define LMEM64_PSCLCR_LCIVB_SHIFT (20U) 310 #define LMEM64_PSCLCR_LCIVB_WIDTH (1U) 311 #define LMEM64_PSCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_LCIVB_SHIFT)) & LMEM64_PSCLCR_LCIVB_MASK) 312 313 #define LMEM64_PSCLCR_LCIMB_MASK (0x200000U) 314 #define LMEM64_PSCLCR_LCIMB_SHIFT (21U) 315 #define LMEM64_PSCLCR_LCIMB_WIDTH (1U) 316 #define LMEM64_PSCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_LCIMB_SHIFT)) & LMEM64_PSCLCR_LCIMB_MASK) 317 318 #define LMEM64_PSCLCR_LCWAY_MASK (0x400000U) 319 #define LMEM64_PSCLCR_LCWAY_SHIFT (22U) 320 #define LMEM64_PSCLCR_LCWAY_WIDTH (1U) 321 #define LMEM64_PSCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_LCWAY_SHIFT)) & LMEM64_PSCLCR_LCWAY_MASK) 322 323 #define LMEM64_PSCLCR_LCMD_MASK (0x3000000U) 324 #define LMEM64_PSCLCR_LCMD_SHIFT (24U) 325 #define LMEM64_PSCLCR_LCMD_WIDTH (2U) 326 #define LMEM64_PSCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_LCMD_SHIFT)) & LMEM64_PSCLCR_LCMD_MASK) 327 328 #define LMEM64_PSCLCR_LADSEL_MASK (0x4000000U) 329 #define LMEM64_PSCLCR_LADSEL_SHIFT (26U) 330 #define LMEM64_PSCLCR_LADSEL_WIDTH (1U) 331 #define LMEM64_PSCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_LADSEL_SHIFT)) & LMEM64_PSCLCR_LADSEL_MASK) 332 333 #define LMEM64_PSCLCR_LACC_MASK (0x8000000U) 334 #define LMEM64_PSCLCR_LACC_SHIFT (27U) 335 #define LMEM64_PSCLCR_LACC_WIDTH (1U) 336 #define LMEM64_PSCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCLCR_LACC_SHIFT)) & LMEM64_PSCLCR_LACC_MASK) 337 /*! @} */ 338 339 /*! @name PSCSAR - PS bus Cache search address register */ 340 /*! @{ */ 341 342 #define LMEM64_PSCSAR_LGO_MASK (0x1U) 343 #define LMEM64_PSCSAR_LGO_SHIFT (0U) 344 #define LMEM64_PSCSAR_LGO_WIDTH (1U) 345 #define LMEM64_PSCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCSAR_LGO_SHIFT)) & LMEM64_PSCSAR_LGO_MASK) 346 347 #define LMEM64_PSCSAR_PHYADDR_MASK (0xFFFFFFFEU) 348 #define LMEM64_PSCSAR_PHYADDR_SHIFT (1U) 349 #define LMEM64_PSCSAR_PHYADDR_WIDTH (31U) 350 #define LMEM64_PSCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCSAR_PHYADDR_SHIFT)) & LMEM64_PSCSAR_PHYADDR_MASK) 351 /*! @} */ 352 353 /*! @name PSCCVR - PS bus Cache read/write value register */ 354 /*! @{ */ 355 356 #define LMEM64_PSCCVR_DATA_MASK (0xFFFFFFFFU) 357 #define LMEM64_PSCCVR_DATA_SHIFT (0U) 358 #define LMEM64_PSCCVR_DATA_WIDTH (32U) 359 #define LMEM64_PSCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM64_PSCCVR_DATA_SHIFT)) & LMEM64_PSCCVR_DATA_MASK) 360 /*! @} */ 361 362 /*! 363 * @} 364 */ /* end of group LMEM64_Register_Masks */ 365 366 /*! 367 * @} 368 */ /* end of group LMEM64_Peripheral_Access_Layer */ 369 370 #endif /* #if !defined(S32Z2_LMEM64_H_) */ 371
