1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LLC_FSC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_LLC_FSC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LLC_FSC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LLC_FSC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LLC_FSC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LLC_FSC_Peripheral_Access_Layer LLC_FSC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LLC_FSC - Size of Registers Arrays */ 72 #define LLC_FSC_FSCLF_COUNT 3u 73 #define LLC_FSC_FSCMF_COUNT 3u 74 #define LLC_FSC_FSCCETHF_COUNT 3u 75 76 /** LLC_FSC - Register Layout Typedef */ 77 typedef struct { 78 __O uint32_t FSCBISTCR; /**< FSC BIST Control, offset: 0x0 */ 79 __I uint32_t FSCBISTAR; /**< FSC BIST Activity, offset: 0x4 */ 80 uint8_t RESERVED_0[8]; 81 __I uint32_t FSCLF0; /**< FSC Latent Fault Inputs 0, offset: 0x10 */ 82 __I uint32_t FSCLF[LLC_FSC_FSCLF_COUNT]; /**< FSC Latent Fault Inputs, array offset: 0x14, array step: 0x4 */ 83 __I uint32_t FSCMF0; /**< FSC Mission Fault 0, offset: 0x20 */ 84 __I uint32_t FSCMF[LLC_FSC_FSCMF_COUNT]; /**< FSC Mission Fault Inputs, array offset: 0x24, array step: 0x4 */ 85 __I uint32_t FSCCETHF0; /**< FSC Correctable Error Over Theshold 0, offset: 0x30 */ 86 __I uint32_t FSCCETHF[LLC_FSC_FSCCETHF_COUNT]; /**< FSC Correctable Error Over Threshold 1..FSC Correctable Error Over Threshold 3, array offset: 0x34, array step: 0x4 */ 87 } LLC_FSC_Type, *LLC_FSC_MemMapPtr; 88 89 /** Number of instances of the LLC_FSC module. */ 90 #define LLC_FSC_INSTANCE_COUNT (2u) 91 92 /* LLC_FSC - Peripheral instance base addresses */ 93 /** Peripheral RTU0__LLC_FSC base address */ 94 #define IP_RTU0__LLC_FSC_BASE (0x76040000u) 95 /** Peripheral RTU0__LLC_FSC base pointer */ 96 #define IP_RTU0__LLC_FSC ((LLC_FSC_Type *)IP_RTU0__LLC_FSC_BASE) 97 /** Peripheral RTU1__LLC_FSC base address */ 98 #define IP_RTU1__LLC_FSC_BASE (0x76840000u) 99 /** Peripheral RTU1__LLC_FSC base pointer */ 100 #define IP_RTU1__LLC_FSC ((LLC_FSC_Type *)IP_RTU1__LLC_FSC_BASE) 101 /** Array initializer of LLC_FSC peripheral base addresses */ 102 #define IP_LLC_FSC_BASE_ADDRS { IP_RTU0__LLC_FSC_BASE, IP_RTU1__LLC_FSC_BASE } 103 /** Array initializer of LLC_FSC peripheral base pointers */ 104 #define IP_LLC_FSC_BASE_PTRS { IP_RTU0__LLC_FSC, IP_RTU1__LLC_FSC } 105 106 /* ---------------------------------------------------------------------------- 107 -- LLC_FSC Register Masks 108 ---------------------------------------------------------------------------- */ 109 110 /*! 111 * @addtogroup LLC_FSC_Register_Masks LLC_FSC Register Masks 112 * @{ 113 */ 114 115 /*! @name FSCBISTCR - FSC BIST Control */ 116 /*! @{ */ 117 118 #define LLC_FSC_FSCBISTCR_bist_start_MASK (0x1U) 119 #define LLC_FSC_FSCBISTCR_bist_start_SHIFT (0U) 120 #define LLC_FSC_FSCBISTCR_bist_start_WIDTH (1U) 121 #define LLC_FSC_FSCBISTCR_bist_start(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCBISTCR_bist_start_SHIFT)) & LLC_FSC_FSCBISTCR_bist_start_MASK) 122 123 #define LLC_FSC_FSCBISTCR_bist_step_MASK (0x2U) 124 #define LLC_FSC_FSCBISTCR_bist_step_SHIFT (1U) 125 #define LLC_FSC_FSCBISTCR_bist_step_WIDTH (1U) 126 #define LLC_FSC_FSCBISTCR_bist_step(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCBISTCR_bist_step_SHIFT)) & LLC_FSC_FSCBISTCR_bist_step_MASK) 127 /*! @} */ 128 129 /*! @name FSCBISTAR - FSC BIST Activity */ 130 /*! @{ */ 131 132 #define LLC_FSC_FSCBISTAR_bist_done_MASK (0x1FU) 133 #define LLC_FSC_FSCBISTAR_bist_done_SHIFT (0U) 134 #define LLC_FSC_FSCBISTAR_bist_done_WIDTH (5U) 135 #define LLC_FSC_FSCBISTAR_bist_done(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCBISTAR_bist_done_SHIFT)) & LLC_FSC_FSCBISTAR_bist_done_MASK) 136 137 #define LLC_FSC_FSCBISTAR_bist_err_MASK (0x3E0U) 138 #define LLC_FSC_FSCBISTAR_bist_err_SHIFT (5U) 139 #define LLC_FSC_FSCBISTAR_bist_err_WIDTH (5U) 140 #define LLC_FSC_FSCBISTAR_bist_err(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCBISTAR_bist_err_SHIFT)) & LLC_FSC_FSCBISTAR_bist_err_MASK) 141 /*! @} */ 142 143 /*! @name FSCLF0 - FSC Latent Fault Inputs 0 */ 144 /*! @{ */ 145 146 #define LLC_FSC_FSCLF0_latent_fault_MASK (0xFFFFFFFFU) 147 #define LLC_FSC_FSCLF0_latent_fault_SHIFT (0U) 148 #define LLC_FSC_FSCLF0_latent_fault_WIDTH (32U) 149 #define LLC_FSC_FSCLF0_latent_fault(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCLF0_latent_fault_SHIFT)) & LLC_FSC_FSCLF0_latent_fault_MASK) 150 /*! @} */ 151 152 /*! @name FSCLF - FSC Latent Fault Inputs */ 153 /*! @{ */ 154 155 #define LLC_FSC_FSCLF_latent_fault_MASK (0xFFFFFFFFU) 156 #define LLC_FSC_FSCLF_latent_fault_SHIFT (0U) 157 #define LLC_FSC_FSCLF_latent_fault_WIDTH (32U) 158 #define LLC_FSC_FSCLF_latent_fault(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCLF_latent_fault_SHIFT)) & LLC_FSC_FSCLF_latent_fault_MASK) 159 /*! @} */ 160 161 /*! @name FSCMF0 - FSC Mission Fault 0 */ 162 /*! @{ */ 163 164 #define LLC_FSC_FSCMF0_mission_fault_MASK (0xFFFFFFFFU) 165 #define LLC_FSC_FSCMF0_mission_fault_SHIFT (0U) 166 #define LLC_FSC_FSCMF0_mission_fault_WIDTH (32U) 167 #define LLC_FSC_FSCMF0_mission_fault(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCMF0_mission_fault_SHIFT)) & LLC_FSC_FSCMF0_mission_fault_MASK) 168 /*! @} */ 169 170 /*! @name FSCMF - FSC Mission Fault Inputs */ 171 /*! @{ */ 172 173 #define LLC_FSC_FSCMF_mission_fault_MASK (0xFFFFFFFFU) 174 #define LLC_FSC_FSCMF_mission_fault_SHIFT (0U) 175 #define LLC_FSC_FSCMF_mission_fault_WIDTH (32U) 176 #define LLC_FSC_FSCMF_mission_fault(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCMF_mission_fault_SHIFT)) & LLC_FSC_FSCMF_mission_fault_MASK) 177 /*! @} */ 178 179 /*! @name FSCCETHF0 - FSC Correctable Error Over Theshold 0 */ 180 /*! @{ */ 181 182 #define LLC_FSC_FSCCETHF0_cerr_over_thresh_MASK (0xFFFFFFFFU) 183 #define LLC_FSC_FSCCETHF0_cerr_over_thresh_SHIFT (0U) 184 #define LLC_FSC_FSCCETHF0_cerr_over_thresh_WIDTH (32U) 185 #define LLC_FSC_FSCCETHF0_cerr_over_thresh(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCCETHF0_cerr_over_thresh_SHIFT)) & LLC_FSC_FSCCETHF0_cerr_over_thresh_MASK) 186 /*! @} */ 187 188 /*! @name FSCCETHF - FSC Correctable Error Over Threshold 1..FSC Correctable Error Over Threshold 3 */ 189 /*! @{ */ 190 191 #define LLC_FSC_FSCCETHF_cerr_over_thresh_MASK (0xFFFFFFFFU) 192 #define LLC_FSC_FSCCETHF_cerr_over_thresh_SHIFT (0U) 193 #define LLC_FSC_FSCCETHF_cerr_over_thresh_WIDTH (32U) 194 #define LLC_FSC_FSCCETHF_cerr_over_thresh(x) (((uint32_t)(((uint32_t)(x)) << LLC_FSC_FSCCETHF_cerr_over_thresh_SHIFT)) & LLC_FSC_FSCCETHF_cerr_over_thresh_MASK) 195 /*! @} */ 196 197 /*! 198 * @} 199 */ /* end of group LLC_FSC_Register_Masks */ 200 201 /*! 202 * @} 203 */ /* end of group LLC_FSC_Peripheral_Access_Layer */ 204 205 #endif /* #if !defined(S32Z2_LLC_FSC_H_) */ 206
