1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR2.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_GPR2 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR2_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR2_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR2 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR2_Peripheral_Access_Layer GPR2 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR2 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LVFCCUGD2; /**< VFCCU Global DID register 2, offset: 0x0 */ 74 __IO uint32_t LVFCCULD6; /**< VFCCU Local DID register 6, offset: 0x4 */ 75 __IO uint32_t LVFCCULD7; /**< VFCCU Local DID register 7, offset: 0x8 */ 76 __IO uint32_t LVFCCULD8; /**< VFCCU Local DID register 8, offset: 0xC */ 77 __IO uint32_t SPF2C; /**< CEVA_SPF2 Control, offset: 0x10 */ 78 uint8_t RESERVED_0[36]; 79 __IO uint32_t FUNCC4; /**< Miscellaneous Control, offset: 0x38 */ 80 uint8_t RESERVED_1[12]; 81 __I uint32_t INITM2; /**< NoC Initiator NIU Timeout Status, offset: 0x48 */ 82 __I uint32_t TARGTMS2; /**< NoC Target NIU Timeout Status, offset: 0x4C */ 83 __IO uint32_t TARGTMC2; /**< NoC Target NIU Timeout Control, offset: 0x50 */ 84 uint8_t RESERVED_2[4]; 85 __IO uint32_t SMURSTCNT; /**< SMU Cortex-M33 Core Reset Counter, offset: 0x58 */ 86 uint8_t RESERVED_3[4]; 87 __I uint32_t SMUS; /**< SMU Cortex-M33 Core Status, offset: 0x60 */ 88 uint8_t RESERVED_4[28]; 89 __IO uint32_t XPAR2; /**< Interface parity control and status register, offset: 0x80 */ 90 } GPR2_Type, *GPR2_MemMapPtr; 91 92 /** Number of instances of the GPR2 module. */ 93 #define GPR2_INSTANCE_COUNT (1u) 94 95 /* GPR2 - Peripheral instance base addresses */ 96 /** Peripheral GPR2 base address */ 97 #define IP_GPR2_BASE (0x41060000u) 98 /** Peripheral GPR2 base pointer */ 99 #define IP_GPR2 ((GPR2_Type *)IP_GPR2_BASE) 100 /** Array initializer of GPR2 peripheral base addresses */ 101 #define IP_GPR2_BASE_ADDRS { IP_GPR2_BASE } 102 /** Array initializer of GPR2 peripheral base pointers */ 103 #define IP_GPR2_BASE_PTRS { IP_GPR2 } 104 105 /* ---------------------------------------------------------------------------- 106 -- GPR2 Register Masks 107 ---------------------------------------------------------------------------- */ 108 109 /*! 110 * @addtogroup GPR2_Register_Masks GPR2 Register Masks 111 * @{ 112 */ 113 114 /*! @name LVFCCUGD2 - VFCCU Global DID register 2 */ 115 /*! @{ */ 116 117 #define GPR2_LVFCCUGD2_FHID_MASK (0xFU) 118 #define GPR2_LVFCCUGD2_FHID_SHIFT (0U) 119 #define GPR2_LVFCCUGD2_FHID_WIDTH (4U) 120 #define GPR2_LVFCCUGD2_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR2_LVFCCUGD2_FHID_SHIFT)) & GPR2_LVFCCUGD2_FHID_MASK) 121 /*! @} */ 122 123 /*! @name LVFCCULD6 - VFCCU Local DID register 6 */ 124 /*! @{ */ 125 126 #define GPR2_LVFCCULD6_FHID_MASK (0xFFFFFFFFU) 127 #define GPR2_LVFCCULD6_FHID_SHIFT (0U) 128 #define GPR2_LVFCCULD6_FHID_WIDTH (32U) 129 #define GPR2_LVFCCULD6_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR2_LVFCCULD6_FHID_SHIFT)) & GPR2_LVFCCULD6_FHID_MASK) 130 /*! @} */ 131 132 /*! @name LVFCCULD7 - VFCCU Local DID register 7 */ 133 /*! @{ */ 134 135 #define GPR2_LVFCCULD7_FHID_MASK (0xFFFFFFFFU) 136 #define GPR2_LVFCCULD7_FHID_SHIFT (0U) 137 #define GPR2_LVFCCULD7_FHID_WIDTH (32U) 138 #define GPR2_LVFCCULD7_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR2_LVFCCULD7_FHID_SHIFT)) & GPR2_LVFCCULD7_FHID_MASK) 139 /*! @} */ 140 141 /*! @name LVFCCULD8 - VFCCU Local DID register 8 */ 142 /*! @{ */ 143 144 #define GPR2_LVFCCULD8_FHID_MASK (0xFFFFFFFFU) 145 #define GPR2_LVFCCULD8_FHID_SHIFT (0U) 146 #define GPR2_LVFCCULD8_FHID_WIDTH (32U) 147 #define GPR2_LVFCCULD8_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR2_LVFCCULD8_FHID_SHIFT)) & GPR2_LVFCCULD8_FHID_MASK) 148 /*! @} */ 149 150 /*! @name SPF2C - CEVA_SPF2 Control */ 151 /*! @{ */ 152 153 #define GPR2_SPF2C_PGEN_MASK (0x1U) 154 #define GPR2_SPF2C_PGEN_SHIFT (0U) 155 #define GPR2_SPF2C_PGEN_WIDTH (1U) 156 #define GPR2_SPF2C_PGEN(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SPF2C_PGEN_SHIFT)) & GPR2_SPF2C_PGEN_MASK) 157 158 #define GPR2_SPF2C_RET1N_MASK (0x2U) 159 #define GPR2_SPF2C_RET1N_SHIFT (1U) 160 #define GPR2_SPF2C_RET1N_WIDTH (1U) 161 #define GPR2_SPF2C_RET1N(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SPF2C_RET1N_SHIFT)) & GPR2_SPF2C_RET1N_MASK) 162 163 #define GPR2_SPF2C_RET2N_MASK (0x4U) 164 #define GPR2_SPF2C_RET2N_SHIFT (2U) 165 #define GPR2_SPF2C_RET2N_WIDTH (1U) 166 #define GPR2_SPF2C_RET2N(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SPF2C_RET2N_SHIFT)) & GPR2_SPF2C_RET2N_MASK) 167 168 #define GPR2_SPF2C_ACULOCK_MASK (0x8U) 169 #define GPR2_SPF2C_ACULOCK_SHIFT (3U) 170 #define GPR2_SPF2C_ACULOCK_WIDTH (1U) 171 #define GPR2_SPF2C_ACULOCK(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SPF2C_ACULOCK_SHIFT)) & GPR2_SPF2C_ACULOCK_MASK) 172 173 #define GPR2_SPF2C_ICULOCK_MASK (0x10U) 174 #define GPR2_SPF2C_ICULOCK_SHIFT (4U) 175 #define GPR2_SPF2C_ICULOCK_WIDTH (1U) 176 #define GPR2_SPF2C_ICULOCK(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SPF2C_ICULOCK_SHIFT)) & GPR2_SPF2C_ICULOCK_MASK) 177 /*! @} */ 178 179 /*! @name FUNCC4 - Miscellaneous Control */ 180 /*! @{ */ 181 182 #define GPR2_FUNCC4_CTRL_MASK (0xFFFFFFFFU) 183 #define GPR2_FUNCC4_CTRL_SHIFT (0U) 184 #define GPR2_FUNCC4_CTRL_WIDTH (32U) 185 #define GPR2_FUNCC4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GPR2_FUNCC4_CTRL_SHIFT)) & GPR2_FUNCC4_CTRL_MASK) 186 /*! @} */ 187 188 /*! @name INITM2 - NoC Initiator NIU Timeout Status */ 189 /*! @{ */ 190 191 #define GPR2_INITM2_STAT_MASK (0xFFFFFFFFU) 192 #define GPR2_INITM2_STAT_SHIFT (0U) 193 #define GPR2_INITM2_STAT_WIDTH (32U) 194 #define GPR2_INITM2_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR2_INITM2_STAT_SHIFT)) & GPR2_INITM2_STAT_MASK) 195 /*! @} */ 196 197 /*! @name TARGTMS2 - NoC Target NIU Timeout Status */ 198 /*! @{ */ 199 200 #define GPR2_TARGTMS2_STAT_MASK (0xFFFFFFFFU) 201 #define GPR2_TARGTMS2_STAT_SHIFT (0U) 202 #define GPR2_TARGTMS2_STAT_WIDTH (32U) 203 #define GPR2_TARGTMS2_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR2_TARGTMS2_STAT_SHIFT)) & GPR2_TARGTMS2_STAT_MASK) 204 /*! @} */ 205 206 /*! @name TARGTMC2 - NoC Target NIU Timeout Control */ 207 /*! @{ */ 208 209 #define GPR2_TARGTMC2_EN_MASK (0xFFFFFFFFU) 210 #define GPR2_TARGTMC2_EN_SHIFT (0U) 211 #define GPR2_TARGTMC2_EN_WIDTH (32U) 212 #define GPR2_TARGTMC2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPR2_TARGTMC2_EN_SHIFT)) & GPR2_TARGTMC2_EN_MASK) 213 /*! @} */ 214 215 /*! @name SMURSTCNT - SMU Cortex-M33 Core Reset Counter */ 216 /*! @{ */ 217 218 #define GPR2_SMURSTCNT_CNTVAL_MASK (0x3FU) 219 #define GPR2_SMURSTCNT_CNTVAL_SHIFT (0U) 220 #define GPR2_SMURSTCNT_CNTVAL_WIDTH (6U) 221 #define GPR2_SMURSTCNT_CNTVAL(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMURSTCNT_CNTVAL_SHIFT)) & GPR2_SMURSTCNT_CNTVAL_MASK) 222 /*! @} */ 223 224 /*! @name SMUS - SMU Cortex-M33 Core Status */ 225 /*! @{ */ 226 227 #define GPR2_SMUS_SLEEPDEEP_MASK (0x1U) 228 #define GPR2_SMUS_SLEEPDEEP_SHIFT (0U) 229 #define GPR2_SMUS_SLEEPDEEP_WIDTH (1U) 230 #define GPR2_SMUS_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_SLEEPDEEP_SHIFT)) & GPR2_SMUS_SLEEPDEEP_MASK) 231 232 #define GPR2_SMUS_SLEEPHOLDAn_MASK (0x2U) 233 #define GPR2_SMUS_SLEEPHOLDAn_SHIFT (1U) 234 #define GPR2_SMUS_SLEEPHOLDAn_WIDTH (1U) 235 #define GPR2_SMUS_SLEEPHOLDAn(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_SLEEPHOLDAn_SHIFT)) & GPR2_SMUS_SLEEPHOLDAn_MASK) 236 237 #define GPR2_SMUS_SLEEPING_MASK (0x4U) 238 #define GPR2_SMUS_SLEEPING_SHIFT (2U) 239 #define GPR2_SMUS_SLEEPING_WIDTH (1U) 240 #define GPR2_SMUS_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_SLEEPING_SHIFT)) & GPR2_SMUS_SLEEPING_MASK) 241 242 #define GPR2_SMUS_CORECLKEN_MASK (0x8U) 243 #define GPR2_SMUS_CORECLKEN_SHIFT (3U) 244 #define GPR2_SMUS_CORECLKEN_WIDTH (1U) 245 #define GPR2_SMUS_CORECLKEN(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_CORECLKEN_SHIFT)) & GPR2_SMUS_CORECLKEN_MASK) 246 247 #define GPR2_SMUS_INTVFETCH_MASK (0x10U) 248 #define GPR2_SMUS_INTVFETCH_SHIFT (4U) 249 #define GPR2_SMUS_INTVFETCH_WIDTH (1U) 250 #define GPR2_SMUS_INTVFETCH(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_INTVFETCH_SHIFT)) & GPR2_SMUS_INTVFETCH_MASK) 251 252 #define GPR2_SMUS_CPULOCKUP_MASK (0x20U) 253 #define GPR2_SMUS_CPULOCKUP_SHIFT (5U) 254 #define GPR2_SMUS_CPULOCKUP_WIDTH (1U) 255 #define GPR2_SMUS_CPULOCKUP(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_CPULOCKUP_SHIFT)) & GPR2_SMUS_CPULOCKUP_MASK) 256 257 #define GPR2_SMUS_CURRNS_MASK (0x40U) 258 #define GPR2_SMUS_CURRNS_SHIFT (6U) 259 #define GPR2_SMUS_CURRNS_WIDTH (1U) 260 #define GPR2_SMUS_CURRNS(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_CURRNS_SHIFT)) & GPR2_SMUS_CURRNS_MASK) 261 262 #define GPR2_SMUS_SYSRSTREQ_MASK (0x80U) 263 #define GPR2_SMUS_SYSRSTREQ_SHIFT (7U) 264 #define GPR2_SMUS_SYSRSTREQ_WIDTH (1U) 265 #define GPR2_SMUS_SYSRSTREQ(x) (((uint32_t)(((uint32_t)(x)) << GPR2_SMUS_SYSRSTREQ_SHIFT)) & GPR2_SMUS_SYSRSTREQ_MASK) 266 /*! @} */ 267 268 /*! @name XPAR2 - Interface parity control and status register */ 269 /*! @{ */ 270 271 #define GPR2_XPAR2_DIS_MASK (0x1FU) 272 #define GPR2_XPAR2_DIS_SHIFT (0U) 273 #define GPR2_XPAR2_DIS_WIDTH (5U) 274 #define GPR2_XPAR2_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPR2_XPAR2_DIS_SHIFT)) & GPR2_XPAR2_DIS_MASK) 275 276 #define GPR2_XPAR2_STAT_MASK (0x1F00U) 277 #define GPR2_XPAR2_STAT_SHIFT (8U) 278 #define GPR2_XPAR2_STAT_WIDTH (5U) 279 #define GPR2_XPAR2_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR2_XPAR2_STAT_SHIFT)) & GPR2_XPAR2_STAT_MASK) 280 /*! @} */ 281 282 /*! 283 * @} 284 */ /* end of group GPR2_Register_Masks */ 285 286 /*! 287 * @} 288 */ /* end of group GPR2_Peripheral_Access_Layer */ 289 290 #endif /* #if !defined(S32Z2_GPR2_H_) */ 291
