1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_FXOSC.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_FXOSC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_FXOSC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_FXOSC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FXOSC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FXOSC_Peripheral_Access_Layer FXOSC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FXOSC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CTRL; /**< FXOSC Control Register, offset: 0x0 */ 74 __I uint32_t STAT; /**< Oscillator Status Register, offset: 0x4 */ 75 } FXOSC_Type, *FXOSC_MemMapPtr; 76 77 /** Number of instances of the FXOSC module. */ 78 #define FXOSC_INSTANCE_COUNT (1u) 79 80 /* FXOSC - Peripheral instance base addresses */ 81 /** Peripheral FXOSC base address */ 82 #define IP_FXOSC_BASE (0x40200000u) 83 /** Peripheral FXOSC base pointer */ 84 #define IP_FXOSC ((FXOSC_Type *)IP_FXOSC_BASE) 85 /** Array initializer of FXOSC peripheral base addresses */ 86 #define IP_FXOSC_BASE_ADDRS { IP_FXOSC_BASE } 87 /** Array initializer of FXOSC peripheral base pointers */ 88 #define IP_FXOSC_BASE_PTRS { IP_FXOSC } 89 90 /* ---------------------------------------------------------------------------- 91 -- FXOSC Register Masks 92 ---------------------------------------------------------------------------- */ 93 94 /*! 95 * @addtogroup FXOSC_Register_Masks FXOSC Register Masks 96 * @{ 97 */ 98 99 /*! @name CTRL - FXOSC Control Register */ 100 /*! @{ */ 101 102 #define FXOSC_CTRL_OSCON_MASK (0x1U) 103 #define FXOSC_CTRL_OSCON_SHIFT (0U) 104 #define FXOSC_CTRL_OSCON_WIDTH (1U) 105 #define FXOSC_CTRL_OSCON(x) (((uint32_t)(((uint32_t)(x)) << FXOSC_CTRL_OSCON_SHIFT)) & FXOSC_CTRL_OSCON_MASK) 106 107 #define FXOSC_CTRL_ALC_D_MASK (0x4U) 108 #define FXOSC_CTRL_ALC_D_SHIFT (2U) 109 #define FXOSC_CTRL_ALC_D_WIDTH (1U) 110 #define FXOSC_CTRL_ALC_D(x) (((uint32_t)(((uint32_t)(x)) << FXOSC_CTRL_ALC_D_SHIFT)) & FXOSC_CTRL_ALC_D_MASK) 111 112 #define FXOSC_CTRL_GM_SEL_MASK (0xF0U) 113 #define FXOSC_CTRL_GM_SEL_SHIFT (4U) 114 #define FXOSC_CTRL_GM_SEL_WIDTH (4U) 115 #define FXOSC_CTRL_GM_SEL(x) (((uint32_t)(((uint32_t)(x)) << FXOSC_CTRL_GM_SEL_SHIFT)) & FXOSC_CTRL_GM_SEL_MASK) 116 117 #define FXOSC_CTRL_EOCV_MASK (0xFF0000U) 118 #define FXOSC_CTRL_EOCV_SHIFT (16U) 119 #define FXOSC_CTRL_EOCV_WIDTH (8U) 120 #define FXOSC_CTRL_EOCV(x) (((uint32_t)(((uint32_t)(x)) << FXOSC_CTRL_EOCV_SHIFT)) & FXOSC_CTRL_EOCV_MASK) 121 122 #define FXOSC_CTRL_COMP_EN_MASK (0x1000000U) 123 #define FXOSC_CTRL_COMP_EN_SHIFT (24U) 124 #define FXOSC_CTRL_COMP_EN_WIDTH (1U) 125 #define FXOSC_CTRL_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << FXOSC_CTRL_COMP_EN_SHIFT)) & FXOSC_CTRL_COMP_EN_MASK) 126 127 #define FXOSC_CTRL_OSC_BYP_MASK (0x80000000U) 128 #define FXOSC_CTRL_OSC_BYP_SHIFT (31U) 129 #define FXOSC_CTRL_OSC_BYP_WIDTH (1U) 130 #define FXOSC_CTRL_OSC_BYP(x) (((uint32_t)(((uint32_t)(x)) << FXOSC_CTRL_OSC_BYP_SHIFT)) & FXOSC_CTRL_OSC_BYP_MASK) 131 /*! @} */ 132 133 /*! @name STAT - Oscillator Status Register */ 134 /*! @{ */ 135 136 #define FXOSC_STAT_OSC_STAT_MASK (0x80000000U) 137 #define FXOSC_STAT_OSC_STAT_SHIFT (31U) 138 #define FXOSC_STAT_OSC_STAT_WIDTH (1U) 139 #define FXOSC_STAT_OSC_STAT(x) (((uint32_t)(((uint32_t)(x)) << FXOSC_STAT_OSC_STAT_SHIFT)) & FXOSC_STAT_OSC_STAT_MASK) 140 /*! @} */ 141 142 /*! 143 * @} 144 */ /* end of group FXOSC_Register_Masks */ 145 146 /*! 147 * @} 148 */ /* end of group FXOSC_Peripheral_Access_Layer */ 149 150 #endif /* #if !defined(S32Z2_FXOSC_H_) */ 151
