1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_FEED_DMA_TCD.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_FEED_DMA_TCD 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_FEED_DMA_TCD_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_FEED_DMA_TCD_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FEED_DMA_TCD Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FEED_DMA_TCD_Peripheral_Access_Layer FEED_DMA_TCD Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FEED_DMA_TCD - Size of Registers Arrays */ 72 #define FEED_DMA_TCD_TCD_COUNT 24u 73 74 /** FEED_DMA_TCD - Register Layout Typedef */ 75 typedef struct { 76 struct FEED_DMA_TCD_TCD { /* offset: 0x0, array step: 0x1000 */ 77 __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x0, array step: 0x1000 */ 78 __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x4, array step: 0x1000 */ 79 __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8, array step: 0x1000 */ 80 __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0xC, array step: 0x1000 */ 81 __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10, array step: 0x1000 */ 82 uint8_t RESERVED_0[12]; 83 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x20, array step: 0x1000 */ 84 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x24, array step: 0x1000 */ 85 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x26, array step: 0x1000 */ 86 union { /* offset: 0x28, array step: 0x1000 */ 87 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x28, array step: 0x1000 */ 88 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x28, array step: 0x1000 */ 89 } NBYTES; 90 __IO uint32_t SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x2C, array step: 0x1000 */ 91 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x30, array step: 0x1000 */ 92 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x34, array step: 0x1000 */ 93 union { /* offset: 0x36, array step: 0x1000 */ 94 __IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x36, array step: 0x1000 */ 95 __IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x36, array step: 0x1000 */ 96 } CITER; 97 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x38, array step: 0x1000 */ 98 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x3C, array step: 0x1000 */ 99 union { /* offset: 0x3E, array step: 0x1000 */ 100 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x3E, array step: 0x1000 */ 101 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x3E, array step: 0x1000 */ 102 } BITER; 103 uint8_t RESERVED_1[4032]; 104 } TCD[FEED_DMA_TCD_TCD_COUNT]; 105 } FEED_DMA_TCD_Type, *FEED_DMA_TCD_MemMapPtr; 106 107 /** Number of instances of the FEED_DMA_TCD module. */ 108 #define FEED_DMA_TCD_INSTANCE_COUNT (1u) 109 110 /* FEED_DMA_TCD - Peripheral instance base addresses */ 111 /** Peripheral AES__FEED_DMA_TCD base address */ 112 #define IP_AES__FEED_DMA_TCD_BASE (0x47210000u) 113 /** Peripheral AES__FEED_DMA_TCD base pointer */ 114 #define IP_AES__FEED_DMA_TCD ((FEED_DMA_TCD_Type *)IP_AES__FEED_DMA_TCD_BASE) 115 /** Array initializer of FEED_DMA_TCD peripheral base addresses */ 116 #define IP_FEED_DMA_TCD_BASE_ADDRS { IP_AES__FEED_DMA_TCD_BASE } 117 /** Array initializer of FEED_DMA_TCD peripheral base pointers */ 118 #define IP_FEED_DMA_TCD_BASE_PTRS { IP_AES__FEED_DMA_TCD } 119 120 /* ---------------------------------------------------------------------------- 121 -- FEED_DMA_TCD Register Masks 122 ---------------------------------------------------------------------------- */ 123 124 /*! 125 * @addtogroup FEED_DMA_TCD_Register_Masks FEED_DMA_TCD Register Masks 126 * @{ 127 */ 128 129 /*! @name CH_CSR - Channel Control and Status */ 130 /*! @{ */ 131 132 #define FEED_DMA_TCD_CH_CSR_ERQ_MASK (0x1U) 133 #define FEED_DMA_TCD_CH_CSR_ERQ_SHIFT (0U) 134 #define FEED_DMA_TCD_CH_CSR_ERQ_WIDTH (1U) 135 #define FEED_DMA_TCD_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_CSR_ERQ_SHIFT)) & FEED_DMA_TCD_CH_CSR_ERQ_MASK) 136 137 #define FEED_DMA_TCD_CH_CSR_EARQ_MASK (0x2U) 138 #define FEED_DMA_TCD_CH_CSR_EARQ_SHIFT (1U) 139 #define FEED_DMA_TCD_CH_CSR_EARQ_WIDTH (1U) 140 #define FEED_DMA_TCD_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_CSR_EARQ_SHIFT)) & FEED_DMA_TCD_CH_CSR_EARQ_MASK) 141 142 #define FEED_DMA_TCD_CH_CSR_EEI_MASK (0x4U) 143 #define FEED_DMA_TCD_CH_CSR_EEI_SHIFT (2U) 144 #define FEED_DMA_TCD_CH_CSR_EEI_WIDTH (1U) 145 #define FEED_DMA_TCD_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_CSR_EEI_SHIFT)) & FEED_DMA_TCD_CH_CSR_EEI_MASK) 146 147 #define FEED_DMA_TCD_CH_CSR_EBW_MASK (0x8U) 148 #define FEED_DMA_TCD_CH_CSR_EBW_SHIFT (3U) 149 #define FEED_DMA_TCD_CH_CSR_EBW_WIDTH (1U) 150 #define FEED_DMA_TCD_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_CSR_EBW_SHIFT)) & FEED_DMA_TCD_CH_CSR_EBW_MASK) 151 152 #define FEED_DMA_TCD_CH_CSR_DONE_MASK (0x40000000U) 153 #define FEED_DMA_TCD_CH_CSR_DONE_SHIFT (30U) 154 #define FEED_DMA_TCD_CH_CSR_DONE_WIDTH (1U) 155 #define FEED_DMA_TCD_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_CSR_DONE_SHIFT)) & FEED_DMA_TCD_CH_CSR_DONE_MASK) 156 157 #define FEED_DMA_TCD_CH_CSR_ACTIVE_MASK (0x80000000U) 158 #define FEED_DMA_TCD_CH_CSR_ACTIVE_SHIFT (31U) 159 #define FEED_DMA_TCD_CH_CSR_ACTIVE_WIDTH (1U) 160 #define FEED_DMA_TCD_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_CSR_ACTIVE_SHIFT)) & FEED_DMA_TCD_CH_CSR_ACTIVE_MASK) 161 /*! @} */ 162 163 /*! @name CH_ES - Channel Error Status */ 164 /*! @{ */ 165 166 #define FEED_DMA_TCD_CH_ES_DBE_MASK (0x1U) 167 #define FEED_DMA_TCD_CH_ES_DBE_SHIFT (0U) 168 #define FEED_DMA_TCD_CH_ES_DBE_WIDTH (1U) 169 #define FEED_DMA_TCD_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_DBE_SHIFT)) & FEED_DMA_TCD_CH_ES_DBE_MASK) 170 171 #define FEED_DMA_TCD_CH_ES_SBE_MASK (0x2U) 172 #define FEED_DMA_TCD_CH_ES_SBE_SHIFT (1U) 173 #define FEED_DMA_TCD_CH_ES_SBE_WIDTH (1U) 174 #define FEED_DMA_TCD_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_SBE_SHIFT)) & FEED_DMA_TCD_CH_ES_SBE_MASK) 175 176 #define FEED_DMA_TCD_CH_ES_SGE_MASK (0x4U) 177 #define FEED_DMA_TCD_CH_ES_SGE_SHIFT (2U) 178 #define FEED_DMA_TCD_CH_ES_SGE_WIDTH (1U) 179 #define FEED_DMA_TCD_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_SGE_SHIFT)) & FEED_DMA_TCD_CH_ES_SGE_MASK) 180 181 #define FEED_DMA_TCD_CH_ES_NCE_MASK (0x8U) 182 #define FEED_DMA_TCD_CH_ES_NCE_SHIFT (3U) 183 #define FEED_DMA_TCD_CH_ES_NCE_WIDTH (1U) 184 #define FEED_DMA_TCD_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_NCE_SHIFT)) & FEED_DMA_TCD_CH_ES_NCE_MASK) 185 186 #define FEED_DMA_TCD_CH_ES_DOE_MASK (0x10U) 187 #define FEED_DMA_TCD_CH_ES_DOE_SHIFT (4U) 188 #define FEED_DMA_TCD_CH_ES_DOE_WIDTH (1U) 189 #define FEED_DMA_TCD_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_DOE_SHIFT)) & FEED_DMA_TCD_CH_ES_DOE_MASK) 190 191 #define FEED_DMA_TCD_CH_ES_DAE_MASK (0x20U) 192 #define FEED_DMA_TCD_CH_ES_DAE_SHIFT (5U) 193 #define FEED_DMA_TCD_CH_ES_DAE_WIDTH (1U) 194 #define FEED_DMA_TCD_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_DAE_SHIFT)) & FEED_DMA_TCD_CH_ES_DAE_MASK) 195 196 #define FEED_DMA_TCD_CH_ES_SOE_MASK (0x40U) 197 #define FEED_DMA_TCD_CH_ES_SOE_SHIFT (6U) 198 #define FEED_DMA_TCD_CH_ES_SOE_WIDTH (1U) 199 #define FEED_DMA_TCD_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_SOE_SHIFT)) & FEED_DMA_TCD_CH_ES_SOE_MASK) 200 201 #define FEED_DMA_TCD_CH_ES_SAE_MASK (0x80U) 202 #define FEED_DMA_TCD_CH_ES_SAE_SHIFT (7U) 203 #define FEED_DMA_TCD_CH_ES_SAE_WIDTH (1U) 204 #define FEED_DMA_TCD_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_SAE_SHIFT)) & FEED_DMA_TCD_CH_ES_SAE_MASK) 205 206 #define FEED_DMA_TCD_CH_ES_ERR_MASK (0x80000000U) 207 #define FEED_DMA_TCD_CH_ES_ERR_SHIFT (31U) 208 #define FEED_DMA_TCD_CH_ES_ERR_WIDTH (1U) 209 #define FEED_DMA_TCD_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_ES_ERR_SHIFT)) & FEED_DMA_TCD_CH_ES_ERR_MASK) 210 /*! @} */ 211 212 /*! @name CH_INT - Channel Interrupt Status */ 213 /*! @{ */ 214 215 #define FEED_DMA_TCD_CH_INT_INT_MASK (0x1U) 216 #define FEED_DMA_TCD_CH_INT_INT_SHIFT (0U) 217 #define FEED_DMA_TCD_CH_INT_INT_WIDTH (1U) 218 #define FEED_DMA_TCD_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_INT_INT_SHIFT)) & FEED_DMA_TCD_CH_INT_INT_MASK) 219 /*! @} */ 220 221 /*! @name CH_SBR - Channel System Bus */ 222 /*! @{ */ 223 224 #define FEED_DMA_TCD_CH_SBR_MID_MASK (0x3FU) 225 #define FEED_DMA_TCD_CH_SBR_MID_SHIFT (0U) 226 #define FEED_DMA_TCD_CH_SBR_MID_WIDTH (6U) 227 #define FEED_DMA_TCD_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_SBR_MID_SHIFT)) & FEED_DMA_TCD_CH_SBR_MID_MASK) 228 229 #define FEED_DMA_TCD_CH_SBR_PAL_MASK (0x8000U) 230 #define FEED_DMA_TCD_CH_SBR_PAL_SHIFT (15U) 231 #define FEED_DMA_TCD_CH_SBR_PAL_WIDTH (1U) 232 #define FEED_DMA_TCD_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_SBR_PAL_SHIFT)) & FEED_DMA_TCD_CH_SBR_PAL_MASK) 233 234 #define FEED_DMA_TCD_CH_SBR_EMI_MASK (0x10000U) 235 #define FEED_DMA_TCD_CH_SBR_EMI_SHIFT (16U) 236 #define FEED_DMA_TCD_CH_SBR_EMI_WIDTH (1U) 237 #define FEED_DMA_TCD_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_SBR_EMI_SHIFT)) & FEED_DMA_TCD_CH_SBR_EMI_MASK) 238 239 #define FEED_DMA_TCD_CH_SBR_ATTR_MASK (0xE0000U) 240 #define FEED_DMA_TCD_CH_SBR_ATTR_SHIFT (17U) 241 #define FEED_DMA_TCD_CH_SBR_ATTR_WIDTH (3U) 242 #define FEED_DMA_TCD_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_SBR_ATTR_SHIFT)) & FEED_DMA_TCD_CH_SBR_ATTR_MASK) 243 /*! @} */ 244 245 /*! @name CH_PRI - Channel Priority */ 246 /*! @{ */ 247 248 #define FEED_DMA_TCD_CH_PRI_APL_MASK (0x7U) 249 #define FEED_DMA_TCD_CH_PRI_APL_SHIFT (0U) 250 #define FEED_DMA_TCD_CH_PRI_APL_WIDTH (3U) 251 #define FEED_DMA_TCD_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_PRI_APL_SHIFT)) & FEED_DMA_TCD_CH_PRI_APL_MASK) 252 253 #define FEED_DMA_TCD_CH_PRI_DPA_MASK (0x40000000U) 254 #define FEED_DMA_TCD_CH_PRI_DPA_SHIFT (30U) 255 #define FEED_DMA_TCD_CH_PRI_DPA_WIDTH (1U) 256 #define FEED_DMA_TCD_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_PRI_DPA_SHIFT)) & FEED_DMA_TCD_CH_PRI_DPA_MASK) 257 258 #define FEED_DMA_TCD_CH_PRI_ECP_MASK (0x80000000U) 259 #define FEED_DMA_TCD_CH_PRI_ECP_SHIFT (31U) 260 #define FEED_DMA_TCD_CH_PRI_ECP_WIDTH (1U) 261 #define FEED_DMA_TCD_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_CH_PRI_ECP_SHIFT)) & FEED_DMA_TCD_CH_PRI_ECP_MASK) 262 /*! @} */ 263 264 /*! @name SADDR - TCD Source Address */ 265 /*! @{ */ 266 267 #define FEED_DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) 268 #define FEED_DMA_TCD_SADDR_SADDR_SHIFT (0U) 269 #define FEED_DMA_TCD_SADDR_SADDR_WIDTH (32U) 270 #define FEED_DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_SADDR_SADDR_SHIFT)) & FEED_DMA_TCD_SADDR_SADDR_MASK) 271 /*! @} */ 272 273 /*! @name SOFF - TCD Signed Source Address Offset */ 274 /*! @{ */ 275 276 #define FEED_DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) 277 #define FEED_DMA_TCD_SOFF_SOFF_SHIFT (0U) 278 #define FEED_DMA_TCD_SOFF_SOFF_WIDTH (16U) 279 #define FEED_DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_SOFF_SOFF_SHIFT)) & FEED_DMA_TCD_SOFF_SOFF_MASK) 280 /*! @} */ 281 282 /*! @name ATTR - TCD Transfer Attributes */ 283 /*! @{ */ 284 285 #define FEED_DMA_TCD_ATTR_DSIZE_MASK (0x7U) 286 #define FEED_DMA_TCD_ATTR_DSIZE_SHIFT (0U) 287 #define FEED_DMA_TCD_ATTR_DSIZE_WIDTH (3U) 288 #define FEED_DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_ATTR_DSIZE_SHIFT)) & FEED_DMA_TCD_ATTR_DSIZE_MASK) 289 290 #define FEED_DMA_TCD_ATTR_DMOD_MASK (0xF8U) 291 #define FEED_DMA_TCD_ATTR_DMOD_SHIFT (3U) 292 #define FEED_DMA_TCD_ATTR_DMOD_WIDTH (5U) 293 #define FEED_DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_ATTR_DMOD_SHIFT)) & FEED_DMA_TCD_ATTR_DMOD_MASK) 294 295 #define FEED_DMA_TCD_ATTR_SSIZE_MASK (0x700U) 296 #define FEED_DMA_TCD_ATTR_SSIZE_SHIFT (8U) 297 #define FEED_DMA_TCD_ATTR_SSIZE_WIDTH (3U) 298 #define FEED_DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_ATTR_SSIZE_SHIFT)) & FEED_DMA_TCD_ATTR_SSIZE_MASK) 299 300 #define FEED_DMA_TCD_ATTR_SMOD_MASK (0xF800U) 301 #define FEED_DMA_TCD_ATTR_SMOD_SHIFT (11U) 302 #define FEED_DMA_TCD_ATTR_SMOD_WIDTH (5U) 303 #define FEED_DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_ATTR_SMOD_SHIFT)) & FEED_DMA_TCD_ATTR_SMOD_MASK) 304 /*! @} */ 305 306 /*! @name NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 307 /*! @{ */ 308 309 #define FEED_DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 310 #define FEED_DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 311 #define FEED_DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 312 #define FEED_DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & FEED_DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) 313 314 #define FEED_DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 315 #define FEED_DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 316 #define FEED_DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 317 #define FEED_DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & FEED_DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) 318 319 #define FEED_DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 320 #define FEED_DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 321 #define FEED_DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 322 #define FEED_DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & FEED_DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) 323 /*! @} */ 324 325 /*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 326 /*! @{ */ 327 328 #define FEED_DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 329 #define FEED_DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 330 #define FEED_DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 331 #define FEED_DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & FEED_DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) 332 333 #define FEED_DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 334 #define FEED_DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 335 #define FEED_DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 336 #define FEED_DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & FEED_DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) 337 338 #define FEED_DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 339 #define FEED_DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 340 #define FEED_DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 341 #define FEED_DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & FEED_DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) 342 343 #define FEED_DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 344 #define FEED_DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 345 #define FEED_DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 346 #define FEED_DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & FEED_DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) 347 /*! @} */ 348 349 /*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 350 /*! @{ */ 351 352 #define FEED_DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 353 #define FEED_DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) 354 #define FEED_DMA_TCD_SLAST_SDA_SLAST_SDA_WIDTH (32U) 355 #define FEED_DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & FEED_DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) 356 /*! @} */ 357 358 /*! @name DADDR - TCD Destination Address */ 359 /*! @{ */ 360 361 #define FEED_DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) 362 #define FEED_DMA_TCD_DADDR_DADDR_SHIFT (0U) 363 #define FEED_DMA_TCD_DADDR_DADDR_WIDTH (32U) 364 #define FEED_DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_DADDR_DADDR_SHIFT)) & FEED_DMA_TCD_DADDR_DADDR_MASK) 365 /*! @} */ 366 367 /*! @name DOFF - TCD Signed Destination Address Offset */ 368 /*! @{ */ 369 370 #define FEED_DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) 371 #define FEED_DMA_TCD_DOFF_DOFF_SHIFT (0U) 372 #define FEED_DMA_TCD_DOFF_DOFF_WIDTH (16U) 373 #define FEED_DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_DOFF_DOFF_SHIFT)) & FEED_DMA_TCD_DOFF_DOFF_MASK) 374 /*! @} */ 375 376 /*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 377 /*! @{ */ 378 379 #define FEED_DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) 380 #define FEED_DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) 381 #define FEED_DMA_TCD_CITER_ELINKNO_CITER_WIDTH (15U) 382 #define FEED_DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & FEED_DMA_TCD_CITER_ELINKNO_CITER_MASK) 383 384 #define FEED_DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) 385 #define FEED_DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) 386 #define FEED_DMA_TCD_CITER_ELINKNO_ELINK_WIDTH (1U) 387 #define FEED_DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & FEED_DMA_TCD_CITER_ELINKNO_ELINK_MASK) 388 /*! @} */ 389 390 /*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 391 /*! @{ */ 392 393 #define FEED_DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) 394 #define FEED_DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) 395 #define FEED_DMA_TCD_CITER_ELINKYES_CITER_WIDTH (9U) 396 #define FEED_DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & FEED_DMA_TCD_CITER_ELINKYES_CITER_MASK) 397 398 #define FEED_DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) 399 #define FEED_DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) 400 #define FEED_DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH (5U) 401 #define FEED_DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & FEED_DMA_TCD_CITER_ELINKYES_LINKCH_MASK) 402 403 #define FEED_DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) 404 #define FEED_DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) 405 #define FEED_DMA_TCD_CITER_ELINKYES_ELINK_WIDTH (1U) 406 #define FEED_DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & FEED_DMA_TCD_CITER_ELINKYES_ELINK_MASK) 407 /*! @} */ 408 409 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 410 /*! @{ */ 411 412 #define FEED_DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 413 #define FEED_DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) 414 #define FEED_DMA_TCD_DLAST_SGA_DLAST_SGA_WIDTH (32U) 415 #define FEED_DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << FEED_DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & FEED_DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) 416 /*! @} */ 417 418 /*! @name CSR - TCD Control and Status */ 419 /*! @{ */ 420 421 #define FEED_DMA_TCD_CSR_START_MASK (0x1U) 422 #define FEED_DMA_TCD_CSR_START_SHIFT (0U) 423 #define FEED_DMA_TCD_CSR_START_WIDTH (1U) 424 #define FEED_DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_START_SHIFT)) & FEED_DMA_TCD_CSR_START_MASK) 425 426 #define FEED_DMA_TCD_CSR_INTMAJOR_MASK (0x2U) 427 #define FEED_DMA_TCD_CSR_INTMAJOR_SHIFT (1U) 428 #define FEED_DMA_TCD_CSR_INTMAJOR_WIDTH (1U) 429 #define FEED_DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_INTMAJOR_SHIFT)) & FEED_DMA_TCD_CSR_INTMAJOR_MASK) 430 431 #define FEED_DMA_TCD_CSR_INTHALF_MASK (0x4U) 432 #define FEED_DMA_TCD_CSR_INTHALF_SHIFT (2U) 433 #define FEED_DMA_TCD_CSR_INTHALF_WIDTH (1U) 434 #define FEED_DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_INTHALF_SHIFT)) & FEED_DMA_TCD_CSR_INTHALF_MASK) 435 436 #define FEED_DMA_TCD_CSR_DREQ_MASK (0x8U) 437 #define FEED_DMA_TCD_CSR_DREQ_SHIFT (3U) 438 #define FEED_DMA_TCD_CSR_DREQ_WIDTH (1U) 439 #define FEED_DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_DREQ_SHIFT)) & FEED_DMA_TCD_CSR_DREQ_MASK) 440 441 #define FEED_DMA_TCD_CSR_ESG_MASK (0x10U) 442 #define FEED_DMA_TCD_CSR_ESG_SHIFT (4U) 443 #define FEED_DMA_TCD_CSR_ESG_WIDTH (1U) 444 #define FEED_DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_ESG_SHIFT)) & FEED_DMA_TCD_CSR_ESG_MASK) 445 446 #define FEED_DMA_TCD_CSR_MAJORELINK_MASK (0x20U) 447 #define FEED_DMA_TCD_CSR_MAJORELINK_SHIFT (5U) 448 #define FEED_DMA_TCD_CSR_MAJORELINK_WIDTH (1U) 449 #define FEED_DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_MAJORELINK_SHIFT)) & FEED_DMA_TCD_CSR_MAJORELINK_MASK) 450 451 #define FEED_DMA_TCD_CSR_ESDA_MASK (0x80U) 452 #define FEED_DMA_TCD_CSR_ESDA_SHIFT (7U) 453 #define FEED_DMA_TCD_CSR_ESDA_WIDTH (1U) 454 #define FEED_DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_ESDA_SHIFT)) & FEED_DMA_TCD_CSR_ESDA_MASK) 455 456 #define FEED_DMA_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) 457 #define FEED_DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) 458 #define FEED_DMA_TCD_CSR_MAJORLINKCH_WIDTH (5U) 459 #define FEED_DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & FEED_DMA_TCD_CSR_MAJORLINKCH_MASK) 460 461 #define FEED_DMA_TCD_CSR_BWC_MASK (0xC000U) 462 #define FEED_DMA_TCD_CSR_BWC_SHIFT (14U) 463 #define FEED_DMA_TCD_CSR_BWC_WIDTH (2U) 464 #define FEED_DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_CSR_BWC_SHIFT)) & FEED_DMA_TCD_CSR_BWC_MASK) 465 /*! @} */ 466 467 /*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 468 /*! @{ */ 469 470 #define FEED_DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) 471 #define FEED_DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) 472 #define FEED_DMA_TCD_BITER_ELINKNO_BITER_WIDTH (15U) 473 #define FEED_DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & FEED_DMA_TCD_BITER_ELINKNO_BITER_MASK) 474 475 #define FEED_DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) 476 #define FEED_DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) 477 #define FEED_DMA_TCD_BITER_ELINKNO_ELINK_WIDTH (1U) 478 #define FEED_DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & FEED_DMA_TCD_BITER_ELINKNO_ELINK_MASK) 479 /*! @} */ 480 481 /*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 482 /*! @{ */ 483 484 #define FEED_DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) 485 #define FEED_DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) 486 #define FEED_DMA_TCD_BITER_ELINKYES_BITER_WIDTH (9U) 487 #define FEED_DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & FEED_DMA_TCD_BITER_ELINKYES_BITER_MASK) 488 489 #define FEED_DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) 490 #define FEED_DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) 491 #define FEED_DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH (5U) 492 #define FEED_DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & FEED_DMA_TCD_BITER_ELINKYES_LINKCH_MASK) 493 494 #define FEED_DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) 495 #define FEED_DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) 496 #define FEED_DMA_TCD_BITER_ELINKYES_ELINK_WIDTH (1U) 497 #define FEED_DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << FEED_DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & FEED_DMA_TCD_BITER_ELINKYES_ELINK_MASK) 498 /*! @} */ 499 500 /*! 501 * @} 502 */ /* end of group FEED_DMA_TCD_Register_Masks */ 503 504 /*! 505 * @} 506 */ /* end of group FEED_DMA_TCD_Peripheral_Access_Layer */ 507 508 #endif /* #if !defined(S32Z2_FEED_DMA_TCD_H_) */ 509
