1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_EIM_GTM.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_EIM_GTM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_EIM_GTM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_EIM_GTM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EIM_GTM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EIM_GTM_Peripheral_Access_Layer EIM_GTM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EIM_GTM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ 74 __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ 75 uint8_t RESERVED_0[248]; 76 __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ 77 __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ 78 uint8_t RESERVED_1[56]; 79 __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ 80 __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ 81 uint8_t RESERVED_2[56]; 82 __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ 83 __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ 84 uint8_t RESERVED_3[56]; 85 __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ 86 __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ 87 uint8_t RESERVED_4[56]; 88 __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ 89 __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ 90 uint8_t RESERVED_5[56]; 91 __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ 92 __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ 93 uint8_t RESERVED_6[56]; 94 __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ 95 __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ 96 uint8_t RESERVED_7[56]; 97 __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ 98 __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ 99 uint8_t RESERVED_8[56]; 100 __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ 101 __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ 102 uint8_t RESERVED_9[56]; 103 __IO uint32_t EICHD9_WORD0; /**< Error Injection Channel Descriptor 9, Word0, offset: 0x340 */ 104 __IO uint32_t EICHD9_WORD1; /**< Error Injection Channel Descriptor 9, Word1, offset: 0x344 */ 105 uint8_t RESERVED_10[56]; 106 __IO uint32_t EICHD10_WORD0; /**< Error Injection Channel Descriptor 10, Word0, offset: 0x380 */ 107 __IO uint32_t EICHD10_WORD1; /**< Error Injection Channel Descriptor 10, Word1, offset: 0x384 */ 108 uint8_t RESERVED_11[56]; 109 __IO uint32_t EICHD11_WORD0; /**< Error Injection Channel Descriptor 11, Word0, offset: 0x3C0 */ 110 __IO uint32_t EICHD11_WORD1; /**< Error Injection Channel Descriptor 11, Word1, offset: 0x3C4 */ 111 } EIM_GTM_Type, *EIM_GTM_MemMapPtr; 112 113 /** Number of instances of the EIM_GTM module. */ 114 #define EIM_GTM_INSTANCE_COUNT (1u) 115 116 /* EIM_GTM - Peripheral instance base addresses */ 117 /** Peripheral EIM_GTM base address */ 118 #define IP_EIM_GTM_BASE (0x40378000u) 119 /** Peripheral EIM_GTM base pointer */ 120 #define IP_EIM_GTM ((EIM_GTM_Type *)IP_EIM_GTM_BASE) 121 /** Array initializer of EIM_GTM peripheral base addresses */ 122 #define IP_EIM_GTM_BASE_ADDRS { IP_EIM_GTM_BASE } 123 /** Array initializer of EIM_GTM peripheral base pointers */ 124 #define IP_EIM_GTM_BASE_PTRS { IP_EIM_GTM } 125 126 /* ---------------------------------------------------------------------------- 127 -- EIM_GTM Register Masks 128 ---------------------------------------------------------------------------- */ 129 130 /*! 131 * @addtogroup EIM_GTM_Register_Masks EIM_GTM Register Masks 132 * @{ 133 */ 134 135 /*! @name EIMCR - Error Injection Module Configuration Register */ 136 /*! @{ */ 137 138 #define EIM_GTM_EIMCR_GEIEN_MASK (0x1U) 139 #define EIM_GTM_EIMCR_GEIEN_SHIFT (0U) 140 #define EIM_GTM_EIMCR_GEIEN_WIDTH (1U) 141 #define EIM_GTM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EIMCR_GEIEN_SHIFT)) & EIM_GTM_EIMCR_GEIEN_MASK) 142 /*! @} */ 143 144 /*! @name EICHEN - Error Injection Channel Enable register */ 145 /*! @{ */ 146 147 #define EIM_GTM_EICHEN_EICH11EN_MASK (0x100000U) 148 #define EIM_GTM_EICHEN_EICH11EN_SHIFT (20U) 149 #define EIM_GTM_EICHEN_EICH11EN_WIDTH (1U) 150 #define EIM_GTM_EICHEN_EICH11EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH11EN_SHIFT)) & EIM_GTM_EICHEN_EICH11EN_MASK) 151 152 #define EIM_GTM_EICHEN_EICH10EN_MASK (0x200000U) 153 #define EIM_GTM_EICHEN_EICH10EN_SHIFT (21U) 154 #define EIM_GTM_EICHEN_EICH10EN_WIDTH (1U) 155 #define EIM_GTM_EICHEN_EICH10EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH10EN_SHIFT)) & EIM_GTM_EICHEN_EICH10EN_MASK) 156 157 #define EIM_GTM_EICHEN_EICH9EN_MASK (0x400000U) 158 #define EIM_GTM_EICHEN_EICH9EN_SHIFT (22U) 159 #define EIM_GTM_EICHEN_EICH9EN_WIDTH (1U) 160 #define EIM_GTM_EICHEN_EICH9EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH9EN_SHIFT)) & EIM_GTM_EICHEN_EICH9EN_MASK) 161 162 #define EIM_GTM_EICHEN_EICH8EN_MASK (0x800000U) 163 #define EIM_GTM_EICHEN_EICH8EN_SHIFT (23U) 164 #define EIM_GTM_EICHEN_EICH8EN_WIDTH (1U) 165 #define EIM_GTM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH8EN_SHIFT)) & EIM_GTM_EICHEN_EICH8EN_MASK) 166 167 #define EIM_GTM_EICHEN_EICH7EN_MASK (0x1000000U) 168 #define EIM_GTM_EICHEN_EICH7EN_SHIFT (24U) 169 #define EIM_GTM_EICHEN_EICH7EN_WIDTH (1U) 170 #define EIM_GTM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH7EN_SHIFT)) & EIM_GTM_EICHEN_EICH7EN_MASK) 171 172 #define EIM_GTM_EICHEN_EICH6EN_MASK (0x2000000U) 173 #define EIM_GTM_EICHEN_EICH6EN_SHIFT (25U) 174 #define EIM_GTM_EICHEN_EICH6EN_WIDTH (1U) 175 #define EIM_GTM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH6EN_SHIFT)) & EIM_GTM_EICHEN_EICH6EN_MASK) 176 177 #define EIM_GTM_EICHEN_EICH5EN_MASK (0x4000000U) 178 #define EIM_GTM_EICHEN_EICH5EN_SHIFT (26U) 179 #define EIM_GTM_EICHEN_EICH5EN_WIDTH (1U) 180 #define EIM_GTM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH5EN_SHIFT)) & EIM_GTM_EICHEN_EICH5EN_MASK) 181 182 #define EIM_GTM_EICHEN_EICH4EN_MASK (0x8000000U) 183 #define EIM_GTM_EICHEN_EICH4EN_SHIFT (27U) 184 #define EIM_GTM_EICHEN_EICH4EN_WIDTH (1U) 185 #define EIM_GTM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH4EN_SHIFT)) & EIM_GTM_EICHEN_EICH4EN_MASK) 186 187 #define EIM_GTM_EICHEN_EICH3EN_MASK (0x10000000U) 188 #define EIM_GTM_EICHEN_EICH3EN_SHIFT (28U) 189 #define EIM_GTM_EICHEN_EICH3EN_WIDTH (1U) 190 #define EIM_GTM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH3EN_SHIFT)) & EIM_GTM_EICHEN_EICH3EN_MASK) 191 192 #define EIM_GTM_EICHEN_EICH2EN_MASK (0x20000000U) 193 #define EIM_GTM_EICHEN_EICH2EN_SHIFT (29U) 194 #define EIM_GTM_EICHEN_EICH2EN_WIDTH (1U) 195 #define EIM_GTM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH2EN_SHIFT)) & EIM_GTM_EICHEN_EICH2EN_MASK) 196 197 #define EIM_GTM_EICHEN_EICH1EN_MASK (0x40000000U) 198 #define EIM_GTM_EICHEN_EICH1EN_SHIFT (30U) 199 #define EIM_GTM_EICHEN_EICH1EN_WIDTH (1U) 200 #define EIM_GTM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH1EN_SHIFT)) & EIM_GTM_EICHEN_EICH1EN_MASK) 201 202 #define EIM_GTM_EICHEN_EICH0EN_MASK (0x80000000U) 203 #define EIM_GTM_EICHEN_EICH0EN_SHIFT (31U) 204 #define EIM_GTM_EICHEN_EICH0EN_WIDTH (1U) 205 #define EIM_GTM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHEN_EICH0EN_SHIFT)) & EIM_GTM_EICHEN_EICH0EN_MASK) 206 /*! @} */ 207 208 /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ 209 /*! @{ */ 210 211 #define EIM_GTM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 212 #define EIM_GTM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (24U) 213 #define EIM_GTM_EICHD0_WORD0_CHKBIT_MASK_WIDTH (8U) 214 #define EIM_GTM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD0_WORD0_CHKBIT_MASK_MASK) 215 /*! @} */ 216 217 /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ 218 /*! @{ */ 219 220 #define EIM_GTM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 221 #define EIM_GTM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) 222 #define EIM_GTM_EICHD0_WORD1_B0_3DATA_MASK_WIDTH (32U) 223 #define EIM_GTM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD0_WORD1_B0_3DATA_MASK_MASK) 224 /*! @} */ 225 226 /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ 227 /*! @{ */ 228 229 #define EIM_GTM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 230 #define EIM_GTM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (24U) 231 #define EIM_GTM_EICHD1_WORD0_CHKBIT_MASK_WIDTH (8U) 232 #define EIM_GTM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD1_WORD0_CHKBIT_MASK_MASK) 233 /*! @} */ 234 235 /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ 236 /*! @{ */ 237 238 #define EIM_GTM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 239 #define EIM_GTM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) 240 #define EIM_GTM_EICHD1_WORD1_B0_3DATA_MASK_WIDTH (32U) 241 #define EIM_GTM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD1_WORD1_B0_3DATA_MASK_MASK) 242 /*! @} */ 243 244 /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ 245 /*! @{ */ 246 247 #define EIM_GTM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 248 #define EIM_GTM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (24U) 249 #define EIM_GTM_EICHD2_WORD0_CHKBIT_MASK_WIDTH (8U) 250 #define EIM_GTM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD2_WORD0_CHKBIT_MASK_MASK) 251 /*! @} */ 252 253 /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ 254 /*! @{ */ 255 256 #define EIM_GTM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFU) 257 #define EIM_GTM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) 258 #define EIM_GTM_EICHD2_WORD1_B0_3DATA_MASK_WIDTH (24U) 259 #define EIM_GTM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD2_WORD1_B0_3DATA_MASK_MASK) 260 /*! @} */ 261 262 /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ 263 /*! @{ */ 264 265 #define EIM_GTM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 266 #define EIM_GTM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (24U) 267 #define EIM_GTM_EICHD3_WORD0_CHKBIT_MASK_WIDTH (8U) 268 #define EIM_GTM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD3_WORD0_CHKBIT_MASK_MASK) 269 /*! @} */ 270 271 /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ 272 /*! @{ */ 273 274 #define EIM_GTM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFU) 275 #define EIM_GTM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) 276 #define EIM_GTM_EICHD3_WORD1_B0_3DATA_MASK_WIDTH (24U) 277 #define EIM_GTM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD3_WORD1_B0_3DATA_MASK_MASK) 278 /*! @} */ 279 280 /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ 281 /*! @{ */ 282 283 #define EIM_GTM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 284 #define EIM_GTM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (24U) 285 #define EIM_GTM_EICHD4_WORD0_CHKBIT_MASK_WIDTH (8U) 286 #define EIM_GTM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD4_WORD0_CHKBIT_MASK_MASK) 287 /*! @} */ 288 289 /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ 290 /*! @{ */ 291 292 #define EIM_GTM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFU) 293 #define EIM_GTM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) 294 #define EIM_GTM_EICHD4_WORD1_B0_3DATA_MASK_WIDTH (24U) 295 #define EIM_GTM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD4_WORD1_B0_3DATA_MASK_MASK) 296 /*! @} */ 297 298 /*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ 299 /*! @{ */ 300 301 #define EIM_GTM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 302 #define EIM_GTM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (24U) 303 #define EIM_GTM_EICHD5_WORD0_CHKBIT_MASK_WIDTH (8U) 304 #define EIM_GTM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD5_WORD0_CHKBIT_MASK_MASK) 305 /*! @} */ 306 307 /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ 308 /*! @{ */ 309 310 #define EIM_GTM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0x1FFFFFFFU) 311 #define EIM_GTM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) 312 #define EIM_GTM_EICHD5_WORD1_B0_3DATA_MASK_WIDTH (29U) 313 #define EIM_GTM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD5_WORD1_B0_3DATA_MASK_MASK) 314 /*! @} */ 315 316 /*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ 317 /*! @{ */ 318 319 #define EIM_GTM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 320 #define EIM_GTM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (24U) 321 #define EIM_GTM_EICHD6_WORD0_CHKBIT_MASK_WIDTH (8U) 322 #define EIM_GTM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD6_WORD0_CHKBIT_MASK_MASK) 323 /*! @} */ 324 325 /*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ 326 /*! @{ */ 327 328 #define EIM_GTM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 329 #define EIM_GTM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) 330 #define EIM_GTM_EICHD6_WORD1_B0_3DATA_MASK_WIDTH (32U) 331 #define EIM_GTM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD6_WORD1_B0_3DATA_MASK_MASK) 332 /*! @} */ 333 334 /*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ 335 /*! @{ */ 336 337 #define EIM_GTM_EICHD7_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 338 #define EIM_GTM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (24U) 339 #define EIM_GTM_EICHD7_WORD0_CHKBIT_MASK_WIDTH (8U) 340 #define EIM_GTM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD7_WORD0_CHKBIT_MASK_MASK) 341 /*! @} */ 342 343 /*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ 344 /*! @{ */ 345 346 #define EIM_GTM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 347 #define EIM_GTM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) 348 #define EIM_GTM_EICHD7_WORD1_B0_3DATA_MASK_WIDTH (32U) 349 #define EIM_GTM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD7_WORD1_B0_3DATA_MASK_MASK) 350 /*! @} */ 351 352 /*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ 353 /*! @{ */ 354 355 #define EIM_GTM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 356 #define EIM_GTM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (24U) 357 #define EIM_GTM_EICHD8_WORD0_CHKBIT_MASK_WIDTH (8U) 358 #define EIM_GTM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD8_WORD0_CHKBIT_MASK_MASK) 359 /*! @} */ 360 361 /*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ 362 /*! @{ */ 363 364 #define EIM_GTM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 365 #define EIM_GTM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) 366 #define EIM_GTM_EICHD8_WORD1_B0_3DATA_MASK_WIDTH (32U) 367 #define EIM_GTM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD8_WORD1_B0_3DATA_MASK_MASK) 368 /*! @} */ 369 370 /*! @name EICHD9_WORD0 - Error Injection Channel Descriptor 9, Word0 */ 371 /*! @{ */ 372 373 #define EIM_GTM_EICHD9_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 374 #define EIM_GTM_EICHD9_WORD0_CHKBIT_MASK_SHIFT (24U) 375 #define EIM_GTM_EICHD9_WORD0_CHKBIT_MASK_WIDTH (8U) 376 #define EIM_GTM_EICHD9_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD9_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD9_WORD0_CHKBIT_MASK_MASK) 377 /*! @} */ 378 379 /*! @name EICHD9_WORD1 - Error Injection Channel Descriptor 9, Word1 */ 380 /*! @{ */ 381 382 #define EIM_GTM_EICHD9_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 383 #define EIM_GTM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT (0U) 384 #define EIM_GTM_EICHD9_WORD1_B0_3DATA_MASK_WIDTH (32U) 385 #define EIM_GTM_EICHD9_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD9_WORD1_B0_3DATA_MASK_MASK) 386 /*! @} */ 387 388 /*! @name EICHD10_WORD0 - Error Injection Channel Descriptor 10, Word0 */ 389 /*! @{ */ 390 391 #define EIM_GTM_EICHD10_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 392 #define EIM_GTM_EICHD10_WORD0_CHKBIT_MASK_SHIFT (24U) 393 #define EIM_GTM_EICHD10_WORD0_CHKBIT_MASK_WIDTH (8U) 394 #define EIM_GTM_EICHD10_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD10_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD10_WORD0_CHKBIT_MASK_MASK) 395 /*! @} */ 396 397 /*! @name EICHD10_WORD1 - Error Injection Channel Descriptor 10, Word1 */ 398 /*! @{ */ 399 400 #define EIM_GTM_EICHD10_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 401 #define EIM_GTM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT (0U) 402 #define EIM_GTM_EICHD10_WORD1_B0_3DATA_MASK_WIDTH (32U) 403 #define EIM_GTM_EICHD10_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD10_WORD1_B0_3DATA_MASK_MASK) 404 /*! @} */ 405 406 /*! @name EICHD11_WORD0 - Error Injection Channel Descriptor 11, Word0 */ 407 /*! @{ */ 408 409 #define EIM_GTM_EICHD11_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 410 #define EIM_GTM_EICHD11_WORD0_CHKBIT_MASK_SHIFT (24U) 411 #define EIM_GTM_EICHD11_WORD0_CHKBIT_MASK_WIDTH (8U) 412 #define EIM_GTM_EICHD11_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD11_WORD0_CHKBIT_MASK_SHIFT)) & EIM_GTM_EICHD11_WORD0_CHKBIT_MASK_MASK) 413 /*! @} */ 414 415 /*! @name EICHD11_WORD1 - Error Injection Channel Descriptor 11, Word1 */ 416 /*! @{ */ 417 418 #define EIM_GTM_EICHD11_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 419 #define EIM_GTM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT (0U) 420 #define EIM_GTM_EICHD11_WORD1_B0_3DATA_MASK_WIDTH (32U) 421 #define EIM_GTM_EICHD11_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_GTM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_GTM_EICHD11_WORD1_B0_3DATA_MASK_MASK) 422 /*! @} */ 423 424 /*! 425 * @} 426 */ /* end of group EIM_GTM_Register_Masks */ 427 428 /*! 429 * @} 430 */ /* end of group EIM_GTM_Peripheral_Access_Layer */ 431 432 #endif /* #if !defined(S32Z2_EIM_GTM_H_) */ 433
