1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CORESIGHT_PROGRAMMING_MODEL.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_CORESIGHT_PROGRAMMING_MODEL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CORESIGHT_PROGRAMMING_MODEL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CORESIGHT_PROGRAMMING_MODEL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CORESIGHT_PROGRAMMING_MODEL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CORESIGHT_PROGRAMMING_MODEL_Peripheral_Access_Layer CORESIGHT_PROGRAMMING_MODEL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CORESIGHT_PROGRAMMING_MODEL - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t P_ID4; /**< PMSS ID4 Register, offset: 0x0 */ 74 uint8_t RESERVED_0[12]; 75 __I uint32_t P_ID0; /**< PMSS ID0 Register, offset: 0x10 */ 76 __I uint32_t P_ID1; /**< PMSS ID1 Register, offset: 0x14 */ 77 __I uint32_t P_ID2; /**< PMSS ID2 Register, offset: 0x18 */ 78 __I uint32_t P_ID3; /**< PMSS ID3 Register, offset: 0x1C */ 79 __I uint32_t C_ID0; /**< Core ID0 Register, offset: 0x20 */ 80 __I uint32_t C_ID1; /**< Core ID1 Register, offset: 0x24 */ 81 __I uint32_t C_ID2; /**< Core ID2 Register, offset: 0x28 */ 82 __I uint32_t C_ID3; /**< Core ID3 Register, offset: 0x2C */ 83 } CORESIGHT_PROGRAMMING_MODEL_Type, *CORESIGHT_PROGRAMMING_MODEL_MemMapPtr; 84 85 /** Number of instances of the CORESIGHT_PROGRAMMING_MODEL module. */ 86 #define CORESIGHT_PROGRAMMING_MODEL_INSTANCE_COUNT (1u) 87 88 /* CORESIGHT_PROGRAMMING_MODEL - Peripheral instance base addresses */ 89 /** Peripheral CEVA_SPF2_APB__CORESIGHT_PROGRAMMING_MODEL base address */ 90 #define IP_CEVA_SPF2_APB__CORESIGHT_PROGRAMMING_MODEL_BASE (0x4D180FD0u) 91 /** Peripheral CEVA_SPF2_APB__CORESIGHT_PROGRAMMING_MODEL base pointer */ 92 #define IP_CEVA_SPF2_APB__CORESIGHT_PROGRAMMING_MODEL ((CORESIGHT_PROGRAMMING_MODEL_Type *)IP_CEVA_SPF2_APB__CORESIGHT_PROGRAMMING_MODEL_BASE) 93 /** Array initializer of CORESIGHT_PROGRAMMING_MODEL peripheral base addresses */ 94 #define IP_CORESIGHT_PROGRAMMING_MODEL_BASE_ADDRS { IP_CEVA_SPF2_APB__CORESIGHT_PROGRAMMING_MODEL_BASE } 95 /** Array initializer of CORESIGHT_PROGRAMMING_MODEL peripheral base pointers */ 96 #define IP_CORESIGHT_PROGRAMMING_MODEL_BASE_PTRS { IP_CEVA_SPF2_APB__CORESIGHT_PROGRAMMING_MODEL } 97 98 /* ---------------------------------------------------------------------------- 99 -- CORESIGHT_PROGRAMMING_MODEL Register Masks 100 ---------------------------------------------------------------------------- */ 101 102 /*! 103 * @addtogroup CORESIGHT_PROGRAMMING_MODEL_Register_Masks CORESIGHT_PROGRAMMING_MODEL Register Masks 104 * @{ 105 */ 106 107 /*! @name P_ID4 - PMSS ID4 Register */ 108 /*! @{ */ 109 110 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_JEP106_CC_MASK (0xFU) 111 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_JEP106_CC_SHIFT (0U) 112 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_JEP106_CC_WIDTH (4U) 113 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_JEP106_CC(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID4_JEP106_CC_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID4_JEP106_CC_MASK) 114 115 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_FOURKB_C_MASK (0xF0U) 116 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_FOURKB_C_SHIFT (4U) 117 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_FOURKB_C_WIDTH (4U) 118 #define CORESIGHT_PROGRAMMING_MODEL_P_ID4_FOURKB_C(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID4_FOURKB_C_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID4_FOURKB_C_MASK) 119 /*! @} */ 120 121 /*! @name P_ID0 - PMSS ID0 Register */ 122 /*! @{ */ 123 124 #define CORESIGHT_PROGRAMMING_MODEL_P_ID0_PN_L_MASK (0xFFU) 125 #define CORESIGHT_PROGRAMMING_MODEL_P_ID0_PN_L_SHIFT (0U) 126 #define CORESIGHT_PROGRAMMING_MODEL_P_ID0_PN_L_WIDTH (8U) 127 #define CORESIGHT_PROGRAMMING_MODEL_P_ID0_PN_L(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID0_PN_L_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID0_PN_L_MASK) 128 /*! @} */ 129 130 /*! @name P_ID1 - PMSS ID1 Register */ 131 /*! @{ */ 132 133 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_PN_M_MASK (0xFU) 134 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_PN_M_SHIFT (0U) 135 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_PN_M_WIDTH (4U) 136 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_PN_M(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID1_PN_M_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID1_PN_M_MASK) 137 138 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_JEP106_ICL_MASK (0xF0U) 139 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_JEP106_ICL_SHIFT (4U) 140 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_JEP106_ICL_WIDTH (4U) 141 #define CORESIGHT_PROGRAMMING_MODEL_P_ID1_JEP106_ICL(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID1_JEP106_ICL_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID1_JEP106_ICL_MASK) 142 /*! @} */ 143 144 /*! @name P_ID2 - PMSS ID2 Register */ 145 /*! @{ */ 146 147 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEP106_ICH_MASK (0x3U) 148 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEP106_ICH_SHIFT (0U) 149 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEP106_ICH_WIDTH (2U) 150 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEP106_ICH(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEP106_ICH_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEP106_ICH_MASK) 151 152 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEDEC_A_MASK (0x8U) 153 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEDEC_A_SHIFT (3U) 154 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEDEC_A_WIDTH (1U) 155 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEDEC_A(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEDEC_A_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID2_JEDEC_A_MASK) 156 157 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_REV_MASK (0xF0U) 158 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_REV_SHIFT (4U) 159 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_REV_WIDTH (4U) 160 #define CORESIGHT_PROGRAMMING_MODEL_P_ID2_REV(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID2_REV_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID2_REV_MASK) 161 /*! @} */ 162 163 /*! @name P_ID3 - PMSS ID3 Register */ 164 /*! @{ */ 165 166 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_CU_MO_MASK (0xFU) 167 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_CU_MO_SHIFT (0U) 168 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_CU_MO_WIDTH (4U) 169 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_CU_MO(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID3_CU_MO_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID3_CU_MO_MASK) 170 171 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_RE_AN_MASK (0xF0U) 172 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_RE_AN_SHIFT (4U) 173 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_RE_AN_WIDTH (4U) 174 #define CORESIGHT_PROGRAMMING_MODEL_P_ID3_RE_AN(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_P_ID3_RE_AN_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_P_ID3_RE_AN_MASK) 175 /*! @} */ 176 177 /*! @name C_ID0 - Core ID0 Register */ 178 /*! @{ */ 179 180 #define CORESIGHT_PROGRAMMING_MODEL_C_ID0_ID0_VAL_MASK (0xFFU) 181 #define CORESIGHT_PROGRAMMING_MODEL_C_ID0_ID0_VAL_SHIFT (0U) 182 #define CORESIGHT_PROGRAMMING_MODEL_C_ID0_ID0_VAL_WIDTH (8U) 183 #define CORESIGHT_PROGRAMMING_MODEL_C_ID0_ID0_VAL(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_C_ID0_ID0_VAL_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_C_ID0_ID0_VAL_MASK) 184 /*! @} */ 185 186 /*! @name C_ID1 - Core ID1 Register */ 187 /*! @{ */ 188 189 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_ID1_VAL_MASK (0xFU) 190 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_ID1_VAL_SHIFT (0U) 191 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_ID1_VAL_WIDTH (4U) 192 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_ID1_VAL(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_C_ID1_ID1_VAL_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_C_ID1_ID1_VAL_MASK) 193 194 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_CCLA_MASK (0xF0U) 195 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_CCLA_SHIFT (4U) 196 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_CCLA_WIDTH (4U) 197 #define CORESIGHT_PROGRAMMING_MODEL_C_ID1_CCLA(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_C_ID1_CCLA_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_C_ID1_CCLA_MASK) 198 /*! @} */ 199 200 /*! @name C_ID2 - Core ID2 Register */ 201 /*! @{ */ 202 203 #define CORESIGHT_PROGRAMMING_MODEL_C_ID2_ID2_VAL_MASK (0xFFU) 204 #define CORESIGHT_PROGRAMMING_MODEL_C_ID2_ID2_VAL_SHIFT (0U) 205 #define CORESIGHT_PROGRAMMING_MODEL_C_ID2_ID2_VAL_WIDTH (8U) 206 #define CORESIGHT_PROGRAMMING_MODEL_C_ID2_ID2_VAL(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_C_ID2_ID2_VAL_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_C_ID2_ID2_VAL_MASK) 207 /*! @} */ 208 209 /*! @name C_ID3 - Core ID3 Register */ 210 /*! @{ */ 211 212 #define CORESIGHT_PROGRAMMING_MODEL_C_ID3_ID3_VAL_MASK (0xFFU) 213 #define CORESIGHT_PROGRAMMING_MODEL_C_ID3_ID3_VAL_SHIFT (0U) 214 #define CORESIGHT_PROGRAMMING_MODEL_C_ID3_ID3_VAL_WIDTH (8U) 215 #define CORESIGHT_PROGRAMMING_MODEL_C_ID3_ID3_VAL(x) (((uint32_t)(((uint32_t)(x)) << CORESIGHT_PROGRAMMING_MODEL_C_ID3_ID3_VAL_SHIFT)) & CORESIGHT_PROGRAMMING_MODEL_C_ID3_ID3_VAL_MASK) 216 /*! @} */ 217 218 /*! 219 * @} 220 */ /* end of group CORESIGHT_PROGRAMMING_MODEL_Register_Masks */ 221 222 /*! 223 * @} 224 */ /* end of group CORESIGHT_PROGRAMMING_MODEL_Peripheral_Access_Layer */ 225 226 #endif /* #if !defined(S32Z2_CORESIGHT_PROGRAMMING_MODEL_H_) */ 227
