1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CLASS_0X9_CORESIGHT_COMPONENT.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_CLASS_0X9_CORESIGHT_COMPONENT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CLASS_0X9_CORESIGHT_COMPONENT_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CLASS_0X9_CORESIGHT_COMPONENT_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CLASS_0X9_CORESIGHT_COMPONENT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CLASS_0X9_CORESIGHT_COMPONENT_Peripheral_Access_Layer CLASS_0X9_CORESIGHT_COMPONENT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CLASS_0X9_CORESIGHT_COMPONENT - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t DTIR; /**< DTIR Register, offset: 0x0 */ 74 } CLASS_0X9_CORESIGHT_COMPONENT_Type, *CLASS_0X9_CORESIGHT_COMPONENT_MemMapPtr; 75 76 /** Number of instances of the CLASS_0X9_CORESIGHT_COMPONENT module. */ 77 #define CLASS_0X9_CORESIGHT_COMPONENT_INSTANCE_COUNT (1u) 78 79 /* CLASS_0X9_CORESIGHT_COMPONENT - Peripheral instance base addresses */ 80 /** Peripheral CEVA_SPF2_APB__CLASS_0X9_CORESIGHT_COMPONENT base address */ 81 #define IP_CEVA_SPF2_APB__CLASS_0X9_CORESIGHT_COMPONENT_BASE (0x4D180FCCu) 82 /** Peripheral CEVA_SPF2_APB__CLASS_0X9_CORESIGHT_COMPONENT base pointer */ 83 #define IP_CEVA_SPF2_APB__CLASS_0X9_CORESIGHT_COMPONENT ((CLASS_0X9_CORESIGHT_COMPONENT_Type *)IP_CEVA_SPF2_APB__CLASS_0X9_CORESIGHT_COMPONENT_BASE) 84 /** Array initializer of CLASS_0X9_CORESIGHT_COMPONENT peripheral base addresses 85 * */ 86 #define IP_CLASS_0X9_CORESIGHT_COMPONENT_BASE_ADDRS { IP_CEVA_SPF2_APB__CLASS_0X9_CORESIGHT_COMPONENT_BASE } 87 /** Array initializer of CLASS_0X9_CORESIGHT_COMPONENT peripheral base pointers 88 * */ 89 #define IP_CLASS_0X9_CORESIGHT_COMPONENT_BASE_PTRS { IP_CEVA_SPF2_APB__CLASS_0X9_CORESIGHT_COMPONENT } 90 91 /* ---------------------------------------------------------------------------- 92 -- CLASS_0X9_CORESIGHT_COMPONENT Register Masks 93 ---------------------------------------------------------------------------- */ 94 95 /*! 96 * @addtogroup CLASS_0X9_CORESIGHT_COMPONENT_Register_Masks CLASS_0X9_CORESIGHT_COMPONENT Register Masks 97 * @{ 98 */ 99 100 /*! @name DTIR - DTIR Register */ 101 /*! @{ */ 102 103 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_MAJ_T_MASK (0xFU) 104 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_MAJ_T_SHIFT (0U) 105 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_MAJ_T_WIDTH (4U) 106 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_MAJ_T(x) (((uint32_t)(((uint32_t)(x)) << CLASS_0X9_CORESIGHT_COMPONENT_DTIR_MAJ_T_SHIFT)) & CLASS_0X9_CORESIGHT_COMPONENT_DTIR_MAJ_T_MASK) 107 108 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_SUB_T_MASK (0xF0U) 109 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_SUB_T_SHIFT (4U) 110 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_SUB_T_WIDTH (4U) 111 #define CLASS_0X9_CORESIGHT_COMPONENT_DTIR_SUB_T(x) (((uint32_t)(((uint32_t)(x)) << CLASS_0X9_CORESIGHT_COMPONENT_DTIR_SUB_T_SHIFT)) & CLASS_0X9_CORESIGHT_COMPONENT_DTIR_SUB_T_MASK) 112 /*! @} */ 113 114 /*! 115 * @} 116 */ /* end of group CLASS_0X9_CORESIGHT_COMPONENT_Register_Masks */ 117 118 /*! 119 * @} 120 */ /* end of group CLASS_0X9_CORESIGHT_COMPONENT_Peripheral_Access_Layer */ 121 122 #endif /* #if !defined(S32Z2_CLASS_0X9_CORESIGHT_COMPONENT_H_) */ 123
