1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_STCU.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_STCU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_STCU_H_) /* Check if memory map has not been already included */ 58 #define S32K344_STCU_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- STCU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup STCU_Peripheral_Access_Layer STCU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** STCU - Size of Registers Arrays */ 72 #define STCU_LB_COUNT 1u 73 #define STCU_MB_CTRL_COUNT 12u 74 75 /** STCU - Register Layout Typedef */ 76 typedef struct { 77 uint8_t RESERVED_0[4]; 78 __IO uint32_t RUNSW; /**< STCU2 Run Software, offset: 0x4 */ 79 __O uint32_t SKC; /**< STCU2 SK Code, offset: 0x8 */ 80 __IO uint32_t CFG; /**< STCU2 Configuration, offset: 0xC */ 81 uint8_t RESERVED_1[4]; 82 __IO uint32_t WDG; /**< STCU2 Watchdog Granularity, offset: 0x14 */ 83 uint8_t RESERVED_2[12]; 84 __IO uint32_t ERR_STAT; /**< STCU2 Error, offset: 0x24 */ 85 __IO uint32_t ERR_FM; /**< STCU2 Error FM, offset: 0x28 */ 86 uint8_t RESERVED_3[32]; 87 __I uint32_t LBSSW0; /**< STCU2 Online LBIST Status, offset: 0x4C */ 88 uint8_t RESERVED_4[12]; 89 __I uint32_t LBESW0; /**< STCU2 Online LBIST End Flag, offset: 0x5C */ 90 uint8_t RESERVED_5[28]; 91 __IO uint32_t LBUFM0; /**< STCU2 Online LBIST Unrecoverable FM, offset: 0x7C */ 92 uint8_t RESERVED_6[140]; 93 __I uint32_t MBSSW0; /**< STCU2 Online MBIST Status, offset: 0x10C */ 94 uint8_t RESERVED_7[60]; 95 __I uint32_t MBESW0; /**< STCU2 Online MBIST End Flag, offset: 0x14C */ 96 uint8_t RESERVED_8[60]; 97 __IO uint32_t MBUFM0; /**< STCU2 MBIST Unrecoverable FM, offset: 0x18C */ 98 uint8_t RESERVED_9[112]; 99 struct { /* offset: 0x200, array step: 0x30 */ 100 __IO uint32_t CTRL; /**< STCU2 LBIST Control, array offset: 0x200, array step: 0x30 */ 101 __IO uint32_t PCS; /**< STCU2 LBIST PC Stop, array offset: 0x204, array step: 0x30 */ 102 uint8_t RESERVED_0[24]; 103 __IO uint32_t MISRELSW; /**< STCU2 Online LBIST MISR Expected Low, array offset: 0x220, array step: 0x30 */ 104 __IO uint32_t MISREHSW; /**< STCU2 Online LBIST MISR Expected High, array offset: 0x224, array step: 0x30 */ 105 __I uint32_t MISRRLSW; /**< STCU2 Online LBIST MISR Read Low, array offset: 0x228, array step: 0x30 */ 106 __I uint32_t MISRRHSW; /**< STCU2 Online LBIST MISR Read High, array offset: 0x22C, array step: 0x30 */ 107 } LB[STCU_LB_COUNT]; 108 uint8_t RESERVED_10[8144]; 109 __IO uint32_t ALGOSEL; /**< STCU2 Algorithm Select, offset: 0x2200 */ 110 uint8_t RESERVED_11[8]; 111 __IO uint32_t STGGR; /**< STCU2 MBIST Stagger, offset: 0x220C */ 112 __IO uint32_t BSTART; /**< STCU2 BIST Start, offset: 0x2210 */ 113 __IO uint32_t MB_CTRL[STCU_MB_CTRL_COUNT]; /**< STCU2 MBIST Control, array offset: 0x2214, array step: 0x4 */ 114 } STCU_Type, *STCU_MemMapPtr; 115 116 /** Number of instances of the STCU module. */ 117 #define STCU_INSTANCE_COUNT (1u) 118 119 /* STCU - Peripheral instance base addresses */ 120 /** Peripheral STCU base address */ 121 #define IP_STCU_BASE (0x403A0000u) 122 /** Peripheral STCU base pointer */ 123 #define IP_STCU ((STCU_Type *)IP_STCU_BASE) 124 /** Array initializer of STCU peripheral base addresses */ 125 #define IP_STCU_BASE_ADDRS { IP_STCU_BASE } 126 /** Array initializer of STCU peripheral base pointers */ 127 #define IP_STCU_BASE_PTRS { IP_STCU } 128 129 /* ---------------------------------------------------------------------------- 130 -- STCU Register Masks 131 ---------------------------------------------------------------------------- */ 132 133 /*! 134 * @addtogroup STCU_Register_Masks STCU Register Masks 135 * @{ 136 */ 137 138 /*! @name RUNSW - STCU2 Run Software */ 139 /*! @{ */ 140 141 #define STCU_RUNSW_RUNSW_MASK (0x1U) 142 #define STCU_RUNSW_RUNSW_SHIFT (0U) 143 #define STCU_RUNSW_RUNSW_WIDTH (1U) 144 #define STCU_RUNSW_RUNSW(x) (((uint32_t)(((uint32_t)(x)) << STCU_RUNSW_RUNSW_SHIFT)) & STCU_RUNSW_RUNSW_MASK) 145 146 #define STCU_RUNSW_LBSWPLLEN_MASK (0x100U) 147 #define STCU_RUNSW_LBSWPLLEN_SHIFT (8U) 148 #define STCU_RUNSW_LBSWPLLEN_WIDTH (1U) 149 #define STCU_RUNSW_LBSWPLLEN(x) (((uint32_t)(((uint32_t)(x)) << STCU_RUNSW_LBSWPLLEN_SHIFT)) & STCU_RUNSW_LBSWPLLEN_MASK) 150 151 #define STCU_RUNSW_MBSWPLLEN_MASK (0x200U) 152 #define STCU_RUNSW_MBSWPLLEN_SHIFT (9U) 153 #define STCU_RUNSW_MBSWPLLEN_WIDTH (1U) 154 #define STCU_RUNSW_MBSWPLLEN(x) (((uint32_t)(((uint32_t)(x)) << STCU_RUNSW_MBSWPLLEN_SHIFT)) & STCU_RUNSW_MBSWPLLEN_MASK) 155 /*! @} */ 156 157 /*! @name SKC - STCU2 SK Code */ 158 /*! @{ */ 159 160 #define STCU_SKC_SKC_MASK (0xFFFFFFFFU) 161 #define STCU_SKC_SKC_SHIFT (0U) 162 #define STCU_SKC_SKC_WIDTH (32U) 163 #define STCU_SKC_SKC(x) (((uint32_t)(((uint32_t)(x)) << STCU_SKC_SKC_SHIFT)) & STCU_SKC_SKC_MASK) 164 /*! @} */ 165 166 /*! @name CFG - STCU2 Configuration */ 167 /*! @{ */ 168 169 #define STCU_CFG_CLK_CFG_MASK (0x7U) 170 #define STCU_CFG_CLK_CFG_SHIFT (0U) 171 #define STCU_CFG_CLK_CFG_WIDTH (3U) 172 #define STCU_CFG_CLK_CFG(x) (((uint32_t)(((uint32_t)(x)) << STCU_CFG_CLK_CFG_SHIFT)) & STCU_CFG_CLK_CFG_MASK) 173 174 #define STCU_CFG_WRP_MASK (0x100U) 175 #define STCU_CFG_WRP_SHIFT (8U) 176 #define STCU_CFG_WRP_WIDTH (1U) 177 #define STCU_CFG_WRP(x) (((uint32_t)(((uint32_t)(x)) << STCU_CFG_WRP_SHIFT)) & STCU_CFG_WRP_MASK) 178 179 #define STCU_CFG_LB_DELAY_MASK (0x1FE000U) 180 #define STCU_CFG_LB_DELAY_SHIFT (13U) 181 #define STCU_CFG_LB_DELAY_WIDTH (8U) 182 #define STCU_CFG_LB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << STCU_CFG_LB_DELAY_SHIFT)) & STCU_CFG_LB_DELAY_MASK) 183 184 #define STCU_CFG_PTR_MASK (0x7FE00000U) 185 #define STCU_CFG_PTR_SHIFT (21U) 186 #define STCU_CFG_PTR_WIDTH (10U) 187 #define STCU_CFG_PTR(x) (((uint32_t)(((uint32_t)(x)) << STCU_CFG_PTR_SHIFT)) & STCU_CFG_PTR_MASK) 188 /*! @} */ 189 190 /*! @name WDG - STCU2 Watchdog Granularity */ 191 /*! @{ */ 192 193 #define STCU_WDG_WDGEOC_MASK (0xFFFFFFFFU) 194 #define STCU_WDG_WDGEOC_SHIFT (0U) 195 #define STCU_WDG_WDGEOC_WIDTH (32U) 196 #define STCU_WDG_WDGEOC(x) (((uint32_t)(((uint32_t)(x)) << STCU_WDG_WDGEOC_SHIFT)) & STCU_WDG_WDGEOC_MASK) 197 /*! @} */ 198 199 /*! @name ERR_STAT - STCU2 Error */ 200 /*! @{ */ 201 202 #define STCU_ERR_STAT_RFSF_MASK (0x100U) 203 #define STCU_ERR_STAT_RFSF_SHIFT (8U) 204 #define STCU_ERR_STAT_RFSF_WIDTH (1U) 205 #define STCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_STAT_RFSF_SHIFT)) & STCU_ERR_STAT_RFSF_MASK) 206 207 #define STCU_ERR_STAT_UFSF_MASK (0x200U) 208 #define STCU_ERR_STAT_UFSF_SHIFT (9U) 209 #define STCU_ERR_STAT_UFSF_WIDTH (1U) 210 #define STCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_STAT_UFSF_SHIFT)) & STCU_ERR_STAT_UFSF_MASK) 211 212 #define STCU_ERR_STAT_INVPSW_MASK (0x10000U) 213 #define STCU_ERR_STAT_INVPSW_SHIFT (16U) 214 #define STCU_ERR_STAT_INVPSW_WIDTH (1U) 215 #define STCU_ERR_STAT_INVPSW(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_STAT_INVPSW_SHIFT)) & STCU_ERR_STAT_INVPSW_MASK) 216 217 #define STCU_ERR_STAT_ENGESW_MASK (0x20000U) 218 #define STCU_ERR_STAT_ENGESW_SHIFT (17U) 219 #define STCU_ERR_STAT_ENGESW_WIDTH (1U) 220 #define STCU_ERR_STAT_ENGESW(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_STAT_ENGESW_SHIFT)) & STCU_ERR_STAT_ENGESW_MASK) 221 222 #define STCU_ERR_STAT_WDTOSW_MASK (0x80000U) 223 #define STCU_ERR_STAT_WDTOSW_SHIFT (19U) 224 #define STCU_ERR_STAT_WDTOSW_WIDTH (1U) 225 #define STCU_ERR_STAT_WDTOSW(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_STAT_WDTOSW_SHIFT)) & STCU_ERR_STAT_WDTOSW_MASK) 226 227 #define STCU_ERR_STAT_LOCKESW_MASK (0x100000U) 228 #define STCU_ERR_STAT_LOCKESW_SHIFT (20U) 229 #define STCU_ERR_STAT_LOCKESW_WIDTH (1U) 230 #define STCU_ERR_STAT_LOCKESW(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_STAT_LOCKESW_SHIFT)) & STCU_ERR_STAT_LOCKESW_MASK) 231 /*! @} */ 232 233 /*! @name ERR_FM - STCU2 Error FM */ 234 /*! @{ */ 235 236 #define STCU_ERR_FM_INVPUFM_MASK (0x1U) 237 #define STCU_ERR_FM_INVPUFM_SHIFT (0U) 238 #define STCU_ERR_FM_INVPUFM_WIDTH (1U) 239 #define STCU_ERR_FM_INVPUFM(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_FM_INVPUFM_SHIFT)) & STCU_ERR_FM_INVPUFM_MASK) 240 241 #define STCU_ERR_FM_ENGEUFM_MASK (0x2U) 242 #define STCU_ERR_FM_ENGEUFM_SHIFT (1U) 243 #define STCU_ERR_FM_ENGEUFM_WIDTH (1U) 244 #define STCU_ERR_FM_ENGEUFM(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_FM_ENGEUFM_SHIFT)) & STCU_ERR_FM_ENGEUFM_MASK) 245 246 #define STCU_ERR_FM_WDTOUFM_MASK (0x8U) 247 #define STCU_ERR_FM_WDTOUFM_SHIFT (3U) 248 #define STCU_ERR_FM_WDTOUFM_WIDTH (1U) 249 #define STCU_ERR_FM_WDTOUFM(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_FM_WDTOUFM_SHIFT)) & STCU_ERR_FM_WDTOUFM_MASK) 250 251 #define STCU_ERR_FM_LOCKEUFM_MASK (0x10U) 252 #define STCU_ERR_FM_LOCKEUFM_SHIFT (4U) 253 #define STCU_ERR_FM_LOCKEUFM_WIDTH (1U) 254 #define STCU_ERR_FM_LOCKEUFM(x) (((uint32_t)(((uint32_t)(x)) << STCU_ERR_FM_LOCKEUFM_SHIFT)) & STCU_ERR_FM_LOCKEUFM_MASK) 255 /*! @} */ 256 257 /*! @name LBSSW0 - STCU2 Online LBIST Status */ 258 /*! @{ */ 259 260 #define STCU_LBSSW0_LBSSW0_MASK (0x1U) 261 #define STCU_LBSSW0_LBSSW0_SHIFT (0U) 262 #define STCU_LBSSW0_LBSSW0_WIDTH (1U) 263 #define STCU_LBSSW0_LBSSW0(x) (((uint32_t)(((uint32_t)(x)) << STCU_LBSSW0_LBSSW0_SHIFT)) & STCU_LBSSW0_LBSSW0_MASK) 264 /*! @} */ 265 266 /*! @name LBESW0 - STCU2 Online LBIST End Flag */ 267 /*! @{ */ 268 269 #define STCU_LBESW0_LBESW0_MASK (0x1U) 270 #define STCU_LBESW0_LBESW0_SHIFT (0U) 271 #define STCU_LBESW0_LBESW0_WIDTH (1U) 272 #define STCU_LBESW0_LBESW0(x) (((uint32_t)(((uint32_t)(x)) << STCU_LBESW0_LBESW0_SHIFT)) & STCU_LBESW0_LBESW0_MASK) 273 /*! @} */ 274 275 /*! @name LBUFM0 - STCU2 Online LBIST Unrecoverable FM */ 276 /*! @{ */ 277 278 #define STCU_LBUFM0_LBUFM0_MASK (0x1U) 279 #define STCU_LBUFM0_LBUFM0_SHIFT (0U) 280 #define STCU_LBUFM0_LBUFM0_WIDTH (1U) 281 #define STCU_LBUFM0_LBUFM0(x) (((uint32_t)(((uint32_t)(x)) << STCU_LBUFM0_LBUFM0_SHIFT)) & STCU_LBUFM0_LBUFM0_MASK) 282 /*! @} */ 283 284 /*! @name MBSSW0 - STCU2 Online MBIST Status */ 285 /*! @{ */ 286 287 #define STCU_MBSSW0_MBSSW0_MASK (0x1U) 288 #define STCU_MBSSW0_MBSSW0_SHIFT (0U) 289 #define STCU_MBSSW0_MBSSW0_WIDTH (1U) 290 #define STCU_MBSSW0_MBSSW0(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW0_SHIFT)) & STCU_MBSSW0_MBSSW0_MASK) 291 292 #define STCU_MBSSW0_MBSSW1_MASK (0x2U) 293 #define STCU_MBSSW0_MBSSW1_SHIFT (1U) 294 #define STCU_MBSSW0_MBSSW1_WIDTH (1U) 295 #define STCU_MBSSW0_MBSSW1(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW1_SHIFT)) & STCU_MBSSW0_MBSSW1_MASK) 296 297 #define STCU_MBSSW0_MBSSW2_MASK (0x4U) 298 #define STCU_MBSSW0_MBSSW2_SHIFT (2U) 299 #define STCU_MBSSW0_MBSSW2_WIDTH (1U) 300 #define STCU_MBSSW0_MBSSW2(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW2_SHIFT)) & STCU_MBSSW0_MBSSW2_MASK) 301 302 #define STCU_MBSSW0_MBSSW3_MASK (0x8U) 303 #define STCU_MBSSW0_MBSSW3_SHIFT (3U) 304 #define STCU_MBSSW0_MBSSW3_WIDTH (1U) 305 #define STCU_MBSSW0_MBSSW3(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW3_SHIFT)) & STCU_MBSSW0_MBSSW3_MASK) 306 307 #define STCU_MBSSW0_MBSSW4_MASK (0x10U) 308 #define STCU_MBSSW0_MBSSW4_SHIFT (4U) 309 #define STCU_MBSSW0_MBSSW4_WIDTH (1U) 310 #define STCU_MBSSW0_MBSSW4(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW4_SHIFT)) & STCU_MBSSW0_MBSSW4_MASK) 311 312 #define STCU_MBSSW0_MBSSW5_MASK (0x20U) 313 #define STCU_MBSSW0_MBSSW5_SHIFT (5U) 314 #define STCU_MBSSW0_MBSSW5_WIDTH (1U) 315 #define STCU_MBSSW0_MBSSW5(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW5_SHIFT)) & STCU_MBSSW0_MBSSW5_MASK) 316 317 #define STCU_MBSSW0_MBSSW6_MASK (0x40U) 318 #define STCU_MBSSW0_MBSSW6_SHIFT (6U) 319 #define STCU_MBSSW0_MBSSW6_WIDTH (1U) 320 #define STCU_MBSSW0_MBSSW6(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW6_SHIFT)) & STCU_MBSSW0_MBSSW6_MASK) 321 322 #define STCU_MBSSW0_MBSSW7_MASK (0x80U) 323 #define STCU_MBSSW0_MBSSW7_SHIFT (7U) 324 #define STCU_MBSSW0_MBSSW7_WIDTH (1U) 325 #define STCU_MBSSW0_MBSSW7(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW7_SHIFT)) & STCU_MBSSW0_MBSSW7_MASK) 326 327 #define STCU_MBSSW0_MBSSW8_MASK (0x100U) 328 #define STCU_MBSSW0_MBSSW8_SHIFT (8U) 329 #define STCU_MBSSW0_MBSSW8_WIDTH (1U) 330 #define STCU_MBSSW0_MBSSW8(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW8_SHIFT)) & STCU_MBSSW0_MBSSW8_MASK) 331 332 #define STCU_MBSSW0_MBSSW9_MASK (0x200U) 333 #define STCU_MBSSW0_MBSSW9_SHIFT (9U) 334 #define STCU_MBSSW0_MBSSW9_WIDTH (1U) 335 #define STCU_MBSSW0_MBSSW9(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW9_SHIFT)) & STCU_MBSSW0_MBSSW9_MASK) 336 337 #define STCU_MBSSW0_MBSSW10_MASK (0x400U) 338 #define STCU_MBSSW0_MBSSW10_SHIFT (10U) 339 #define STCU_MBSSW0_MBSSW10_WIDTH (1U) 340 #define STCU_MBSSW0_MBSSW10(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW10_SHIFT)) & STCU_MBSSW0_MBSSW10_MASK) 341 342 #define STCU_MBSSW0_MBSSW11_MASK (0x800U) 343 #define STCU_MBSSW0_MBSSW11_SHIFT (11U) 344 #define STCU_MBSSW0_MBSSW11_WIDTH (1U) 345 #define STCU_MBSSW0_MBSSW11(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBSSW0_MBSSW11_SHIFT)) & STCU_MBSSW0_MBSSW11_MASK) 346 /*! @} */ 347 348 /*! @name MBESW0 - STCU2 Online MBIST End Flag */ 349 /*! @{ */ 350 351 #define STCU_MBESW0_MBESW0_MASK (0x1U) 352 #define STCU_MBESW0_MBESW0_SHIFT (0U) 353 #define STCU_MBESW0_MBESW0_WIDTH (1U) 354 #define STCU_MBESW0_MBESW0(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW0_SHIFT)) & STCU_MBESW0_MBESW0_MASK) 355 356 #define STCU_MBESW0_MBESW1_MASK (0x2U) 357 #define STCU_MBESW0_MBESW1_SHIFT (1U) 358 #define STCU_MBESW0_MBESW1_WIDTH (1U) 359 #define STCU_MBESW0_MBESW1(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW1_SHIFT)) & STCU_MBESW0_MBESW1_MASK) 360 361 #define STCU_MBESW0_MBESW2_MASK (0x4U) 362 #define STCU_MBESW0_MBESW2_SHIFT (2U) 363 #define STCU_MBESW0_MBESW2_WIDTH (1U) 364 #define STCU_MBESW0_MBESW2(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW2_SHIFT)) & STCU_MBESW0_MBESW2_MASK) 365 366 #define STCU_MBESW0_MBESW3_MASK (0x8U) 367 #define STCU_MBESW0_MBESW3_SHIFT (3U) 368 #define STCU_MBESW0_MBESW3_WIDTH (1U) 369 #define STCU_MBESW0_MBESW3(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW3_SHIFT)) & STCU_MBESW0_MBESW3_MASK) 370 371 #define STCU_MBESW0_MBESW4_MASK (0x10U) 372 #define STCU_MBESW0_MBESW4_SHIFT (4U) 373 #define STCU_MBESW0_MBESW4_WIDTH (1U) 374 #define STCU_MBESW0_MBESW4(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW4_SHIFT)) & STCU_MBESW0_MBESW4_MASK) 375 376 #define STCU_MBESW0_MBESW5_MASK (0x20U) 377 #define STCU_MBESW0_MBESW5_SHIFT (5U) 378 #define STCU_MBESW0_MBESW5_WIDTH (1U) 379 #define STCU_MBESW0_MBESW5(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW5_SHIFT)) & STCU_MBESW0_MBESW5_MASK) 380 381 #define STCU_MBESW0_MBESW6_MASK (0x40U) 382 #define STCU_MBESW0_MBESW6_SHIFT (6U) 383 #define STCU_MBESW0_MBESW6_WIDTH (1U) 384 #define STCU_MBESW0_MBESW6(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW6_SHIFT)) & STCU_MBESW0_MBESW6_MASK) 385 386 #define STCU_MBESW0_MBESW7_MASK (0x80U) 387 #define STCU_MBESW0_MBESW7_SHIFT (7U) 388 #define STCU_MBESW0_MBESW7_WIDTH (1U) 389 #define STCU_MBESW0_MBESW7(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW7_SHIFT)) & STCU_MBESW0_MBESW7_MASK) 390 391 #define STCU_MBESW0_MBESW8_MASK (0x100U) 392 #define STCU_MBESW0_MBESW8_SHIFT (8U) 393 #define STCU_MBESW0_MBESW8_WIDTH (1U) 394 #define STCU_MBESW0_MBESW8(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW8_SHIFT)) & STCU_MBESW0_MBESW8_MASK) 395 396 #define STCU_MBESW0_MBESW9_MASK (0x200U) 397 #define STCU_MBESW0_MBESW9_SHIFT (9U) 398 #define STCU_MBESW0_MBESW9_WIDTH (1U) 399 #define STCU_MBESW0_MBESW9(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW9_SHIFT)) & STCU_MBESW0_MBESW9_MASK) 400 401 #define STCU_MBESW0_MBESW10_MASK (0x400U) 402 #define STCU_MBESW0_MBESW10_SHIFT (10U) 403 #define STCU_MBESW0_MBESW10_WIDTH (1U) 404 #define STCU_MBESW0_MBESW10(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW10_SHIFT)) & STCU_MBESW0_MBESW10_MASK) 405 406 #define STCU_MBESW0_MBESW11_MASK (0x800U) 407 #define STCU_MBESW0_MBESW11_SHIFT (11U) 408 #define STCU_MBESW0_MBESW11_WIDTH (1U) 409 #define STCU_MBESW0_MBESW11(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBESW0_MBESW11_SHIFT)) & STCU_MBESW0_MBESW11_MASK) 410 /*! @} */ 411 412 /*! @name MBUFM0 - STCU2 MBIST Unrecoverable FM */ 413 /*! @{ */ 414 415 #define STCU_MBUFM0_MBUFM0_MASK (0x1U) 416 #define STCU_MBUFM0_MBUFM0_SHIFT (0U) 417 #define STCU_MBUFM0_MBUFM0_WIDTH (1U) 418 #define STCU_MBUFM0_MBUFM0(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM0_SHIFT)) & STCU_MBUFM0_MBUFM0_MASK) 419 420 #define STCU_MBUFM0_MBUFM1_MASK (0x2U) 421 #define STCU_MBUFM0_MBUFM1_SHIFT (1U) 422 #define STCU_MBUFM0_MBUFM1_WIDTH (1U) 423 #define STCU_MBUFM0_MBUFM1(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM1_SHIFT)) & STCU_MBUFM0_MBUFM1_MASK) 424 425 #define STCU_MBUFM0_MBUFM2_MASK (0x4U) 426 #define STCU_MBUFM0_MBUFM2_SHIFT (2U) 427 #define STCU_MBUFM0_MBUFM2_WIDTH (1U) 428 #define STCU_MBUFM0_MBUFM2(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM2_SHIFT)) & STCU_MBUFM0_MBUFM2_MASK) 429 430 #define STCU_MBUFM0_MBUFM3_MASK (0x8U) 431 #define STCU_MBUFM0_MBUFM3_SHIFT (3U) 432 #define STCU_MBUFM0_MBUFM3_WIDTH (1U) 433 #define STCU_MBUFM0_MBUFM3(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM3_SHIFT)) & STCU_MBUFM0_MBUFM3_MASK) 434 435 #define STCU_MBUFM0_MBUFM4_MASK (0x10U) 436 #define STCU_MBUFM0_MBUFM4_SHIFT (4U) 437 #define STCU_MBUFM0_MBUFM4_WIDTH (1U) 438 #define STCU_MBUFM0_MBUFM4(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM4_SHIFT)) & STCU_MBUFM0_MBUFM4_MASK) 439 440 #define STCU_MBUFM0_MBUFM5_MASK (0x20U) 441 #define STCU_MBUFM0_MBUFM5_SHIFT (5U) 442 #define STCU_MBUFM0_MBUFM5_WIDTH (1U) 443 #define STCU_MBUFM0_MBUFM5(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM5_SHIFT)) & STCU_MBUFM0_MBUFM5_MASK) 444 445 #define STCU_MBUFM0_MBUFM6_MASK (0x40U) 446 #define STCU_MBUFM0_MBUFM6_SHIFT (6U) 447 #define STCU_MBUFM0_MBUFM6_WIDTH (1U) 448 #define STCU_MBUFM0_MBUFM6(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM6_SHIFT)) & STCU_MBUFM0_MBUFM6_MASK) 449 450 #define STCU_MBUFM0_MBUFM7_MASK (0x80U) 451 #define STCU_MBUFM0_MBUFM7_SHIFT (7U) 452 #define STCU_MBUFM0_MBUFM7_WIDTH (1U) 453 #define STCU_MBUFM0_MBUFM7(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM7_SHIFT)) & STCU_MBUFM0_MBUFM7_MASK) 454 455 #define STCU_MBUFM0_MBUFM8_MASK (0x100U) 456 #define STCU_MBUFM0_MBUFM8_SHIFT (8U) 457 #define STCU_MBUFM0_MBUFM8_WIDTH (1U) 458 #define STCU_MBUFM0_MBUFM8(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM8_SHIFT)) & STCU_MBUFM0_MBUFM8_MASK) 459 460 #define STCU_MBUFM0_MBUFM9_MASK (0x200U) 461 #define STCU_MBUFM0_MBUFM9_SHIFT (9U) 462 #define STCU_MBUFM0_MBUFM9_WIDTH (1U) 463 #define STCU_MBUFM0_MBUFM9(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM9_SHIFT)) & STCU_MBUFM0_MBUFM9_MASK) 464 465 #define STCU_MBUFM0_MBUFM10_MASK (0x400U) 466 #define STCU_MBUFM0_MBUFM10_SHIFT (10U) 467 #define STCU_MBUFM0_MBUFM10_WIDTH (1U) 468 #define STCU_MBUFM0_MBUFM10(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM10_SHIFT)) & STCU_MBUFM0_MBUFM10_MASK) 469 470 #define STCU_MBUFM0_MBUFM11_MASK (0x800U) 471 #define STCU_MBUFM0_MBUFM11_SHIFT (11U) 472 #define STCU_MBUFM0_MBUFM11_WIDTH (1U) 473 #define STCU_MBUFM0_MBUFM11(x) (((uint32_t)(((uint32_t)(x)) << STCU_MBUFM0_MBUFM11_SHIFT)) & STCU_MBUFM0_MBUFM11_MASK) 474 /*! @} */ 475 476 /*! @name CTRL - STCU2 LBIST Control */ 477 /*! @{ */ 478 479 #define STCU_CTRL_CWS_MASK (0x3FU) 480 #define STCU_CTRL_CWS_SHIFT (0U) 481 #define STCU_CTRL_CWS_WIDTH (6U) 482 #define STCU_CTRL_CWS(x) (((uint32_t)(((uint32_t)(x)) << STCU_CTRL_CWS_SHIFT)) & STCU_CTRL_CWS_MASK) 483 484 #define STCU_CTRL_SCEN_ON_MASK (0xF00U) 485 #define STCU_CTRL_SCEN_ON_SHIFT (8U) 486 #define STCU_CTRL_SCEN_ON_WIDTH (4U) 487 #define STCU_CTRL_SCEN_ON(x) (((uint32_t)(((uint32_t)(x)) << STCU_CTRL_SCEN_ON_SHIFT)) & STCU_CTRL_SCEN_ON_MASK) 488 489 #define STCU_CTRL_SCEN_OFF_MASK (0xF000U) 490 #define STCU_CTRL_SCEN_OFF_SHIFT (12U) 491 #define STCU_CTRL_SCEN_OFF_WIDTH (4U) 492 #define STCU_CTRL_SCEN_OFF(x) (((uint32_t)(((uint32_t)(x)) << STCU_CTRL_SCEN_OFF_SHIFT)) & STCU_CTRL_SCEN_OFF_MASK) 493 494 #define STCU_CTRL_SHS_MASK (0x70000U) 495 #define STCU_CTRL_SHS_SHIFT (16U) 496 #define STCU_CTRL_SHS_WIDTH (3U) 497 #define STCU_CTRL_SHS(x) (((uint32_t)(((uint32_t)(x)) << STCU_CTRL_SHS_SHIFT)) & STCU_CTRL_SHS_MASK) 498 499 #define STCU_CTRL_PTR_MASK (0x7FE00000U) 500 #define STCU_CTRL_PTR_SHIFT (21U) 501 #define STCU_CTRL_PTR_WIDTH (10U) 502 #define STCU_CTRL_PTR(x) (((uint32_t)(((uint32_t)(x)) << STCU_CTRL_PTR_SHIFT)) & STCU_CTRL_PTR_MASK) 503 504 #define STCU_CTRL_CSM_MASK (0x80000000U) 505 #define STCU_CTRL_CSM_SHIFT (31U) 506 #define STCU_CTRL_CSM_WIDTH (1U) 507 #define STCU_CTRL_CSM(x) (((uint32_t)(((uint32_t)(x)) << STCU_CTRL_CSM_SHIFT)) & STCU_CTRL_CSM_MASK) 508 /*! @} */ 509 510 /*! @name PCS - STCU2 LBIST PC Stop */ 511 /*! @{ */ 512 513 #define STCU_PCS_PCS_MASK (0x3FFFFFFU) 514 #define STCU_PCS_PCS_SHIFT (0U) 515 #define STCU_PCS_PCS_WIDTH (26U) 516 #define STCU_PCS_PCS(x) (((uint32_t)(((uint32_t)(x)) << STCU_PCS_PCS_SHIFT)) & STCU_PCS_PCS_MASK) 517 /*! @} */ 518 519 /*! @name MISRELSW - STCU2 Online LBIST MISR Expected Low */ 520 /*! @{ */ 521 522 #define STCU_MISRELSW_MISRESWx_MASK (0xFFFFFFFFU) 523 #define STCU_MISRELSW_MISRESWx_SHIFT (0U) 524 #define STCU_MISRELSW_MISRESWx_WIDTH (32U) 525 #define STCU_MISRELSW_MISRESWx(x) (((uint32_t)(((uint32_t)(x)) << STCU_MISRELSW_MISRESWx_SHIFT)) & STCU_MISRELSW_MISRESWx_MASK) 526 /*! @} */ 527 528 /*! @name MISREHSW - STCU2 Online LBIST MISR Expected High */ 529 /*! @{ */ 530 531 #define STCU_MISREHSW_MISRESWx_MASK (0xFFFFFFFFU) 532 #define STCU_MISREHSW_MISRESWx_SHIFT (0U) 533 #define STCU_MISREHSW_MISRESWx_WIDTH (32U) 534 #define STCU_MISREHSW_MISRESWx(x) (((uint32_t)(((uint32_t)(x)) << STCU_MISREHSW_MISRESWx_SHIFT)) & STCU_MISREHSW_MISRESWx_MASK) 535 /*! @} */ 536 537 /*! @name MISRRLSW - STCU2 Online LBIST MISR Read Low */ 538 /*! @{ */ 539 540 #define STCU_MISRRLSW_MISRRSWx_MASK (0xFFFFFFFFU) 541 #define STCU_MISRRLSW_MISRRSWx_SHIFT (0U) 542 #define STCU_MISRRLSW_MISRRSWx_WIDTH (32U) 543 #define STCU_MISRRLSW_MISRRSWx(x) (((uint32_t)(((uint32_t)(x)) << STCU_MISRRLSW_MISRRSWx_SHIFT)) & STCU_MISRRLSW_MISRRSWx_MASK) 544 /*! @} */ 545 546 /*! @name MISRRHSW - STCU2 Online LBIST MISR Read High */ 547 /*! @{ */ 548 549 #define STCU_MISRRHSW_MISRRSWx_MASK (0xFFFFFFFFU) 550 #define STCU_MISRRHSW_MISRRSWx_SHIFT (0U) 551 #define STCU_MISRRHSW_MISRRSWx_WIDTH (32U) 552 #define STCU_MISRRHSW_MISRRSWx(x) (((uint32_t)(((uint32_t)(x)) << STCU_MISRRHSW_MISRRSWx_SHIFT)) & STCU_MISRRHSW_MISRRSWx_MASK) 553 /*! @} */ 554 555 /*! @name ALGOSEL - STCU2 Algorithm Select */ 556 /*! @{ */ 557 558 #define STCU_ALGOSEL_ALGOSEL0_MASK (0x1U) 559 #define STCU_ALGOSEL_ALGOSEL0_SHIFT (0U) 560 #define STCU_ALGOSEL_ALGOSEL0_WIDTH (1U) 561 #define STCU_ALGOSEL_ALGOSEL0(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL0_SHIFT)) & STCU_ALGOSEL_ALGOSEL0_MASK) 562 563 #define STCU_ALGOSEL_ALGOSEL1_MASK (0x2U) 564 #define STCU_ALGOSEL_ALGOSEL1_SHIFT (1U) 565 #define STCU_ALGOSEL_ALGOSEL1_WIDTH (1U) 566 #define STCU_ALGOSEL_ALGOSEL1(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL1_SHIFT)) & STCU_ALGOSEL_ALGOSEL1_MASK) 567 568 #define STCU_ALGOSEL_ALGOSEL2_MASK (0x4U) 569 #define STCU_ALGOSEL_ALGOSEL2_SHIFT (2U) 570 #define STCU_ALGOSEL_ALGOSEL2_WIDTH (1U) 571 #define STCU_ALGOSEL_ALGOSEL2(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL2_SHIFT)) & STCU_ALGOSEL_ALGOSEL2_MASK) 572 573 #define STCU_ALGOSEL_ALGOSEL3_MASK (0x8U) 574 #define STCU_ALGOSEL_ALGOSEL3_SHIFT (3U) 575 #define STCU_ALGOSEL_ALGOSEL3_WIDTH (1U) 576 #define STCU_ALGOSEL_ALGOSEL3(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL3_SHIFT)) & STCU_ALGOSEL_ALGOSEL3_MASK) 577 578 #define STCU_ALGOSEL_ALGOSEL4_MASK (0x10U) 579 #define STCU_ALGOSEL_ALGOSEL4_SHIFT (4U) 580 #define STCU_ALGOSEL_ALGOSEL4_WIDTH (1U) 581 #define STCU_ALGOSEL_ALGOSEL4(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL4_SHIFT)) & STCU_ALGOSEL_ALGOSEL4_MASK) 582 583 #define STCU_ALGOSEL_ALGOSEL5_MASK (0x20U) 584 #define STCU_ALGOSEL_ALGOSEL5_SHIFT (5U) 585 #define STCU_ALGOSEL_ALGOSEL5_WIDTH (1U) 586 #define STCU_ALGOSEL_ALGOSEL5(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL5_SHIFT)) & STCU_ALGOSEL_ALGOSEL5_MASK) 587 588 #define STCU_ALGOSEL_ALGOSEL6_MASK (0x40U) 589 #define STCU_ALGOSEL_ALGOSEL6_SHIFT (6U) 590 #define STCU_ALGOSEL_ALGOSEL6_WIDTH (1U) 591 #define STCU_ALGOSEL_ALGOSEL6(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL6_SHIFT)) & STCU_ALGOSEL_ALGOSEL6_MASK) 592 593 #define STCU_ALGOSEL_ALGOSEL7_MASK (0x80U) 594 #define STCU_ALGOSEL_ALGOSEL7_SHIFT (7U) 595 #define STCU_ALGOSEL_ALGOSEL7_WIDTH (1U) 596 #define STCU_ALGOSEL_ALGOSEL7(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL7_SHIFT)) & STCU_ALGOSEL_ALGOSEL7_MASK) 597 598 #define STCU_ALGOSEL_ALGOSEL8_MASK (0x100U) 599 #define STCU_ALGOSEL_ALGOSEL8_SHIFT (8U) 600 #define STCU_ALGOSEL_ALGOSEL8_WIDTH (1U) 601 #define STCU_ALGOSEL_ALGOSEL8(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL8_SHIFT)) & STCU_ALGOSEL_ALGOSEL8_MASK) 602 603 #define STCU_ALGOSEL_ALGOSEL9_MASK (0x200U) 604 #define STCU_ALGOSEL_ALGOSEL9_SHIFT (9U) 605 #define STCU_ALGOSEL_ALGOSEL9_WIDTH (1U) 606 #define STCU_ALGOSEL_ALGOSEL9(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL9_SHIFT)) & STCU_ALGOSEL_ALGOSEL9_MASK) 607 608 #define STCU_ALGOSEL_ALGOSEL10_MASK (0x400U) 609 #define STCU_ALGOSEL_ALGOSEL10_SHIFT (10U) 610 #define STCU_ALGOSEL_ALGOSEL10_WIDTH (1U) 611 #define STCU_ALGOSEL_ALGOSEL10(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL10_SHIFT)) & STCU_ALGOSEL_ALGOSEL10_MASK) 612 613 #define STCU_ALGOSEL_ALGOSEL11_MASK (0x800U) 614 #define STCU_ALGOSEL_ALGOSEL11_SHIFT (11U) 615 #define STCU_ALGOSEL_ALGOSEL11_WIDTH (1U) 616 #define STCU_ALGOSEL_ALGOSEL11(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL11_SHIFT)) & STCU_ALGOSEL_ALGOSEL11_MASK) 617 618 #define STCU_ALGOSEL_ALGOSEL12_MASK (0x1000U) 619 #define STCU_ALGOSEL_ALGOSEL12_SHIFT (12U) 620 #define STCU_ALGOSEL_ALGOSEL12_WIDTH (1U) 621 #define STCU_ALGOSEL_ALGOSEL12(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL12_SHIFT)) & STCU_ALGOSEL_ALGOSEL12_MASK) 622 623 #define STCU_ALGOSEL_ALGOSEL13_MASK (0x2000U) 624 #define STCU_ALGOSEL_ALGOSEL13_SHIFT (13U) 625 #define STCU_ALGOSEL_ALGOSEL13_WIDTH (1U) 626 #define STCU_ALGOSEL_ALGOSEL13(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL13_SHIFT)) & STCU_ALGOSEL_ALGOSEL13_MASK) 627 628 #define STCU_ALGOSEL_ALGOSEL14_MASK (0x4000U) 629 #define STCU_ALGOSEL_ALGOSEL14_SHIFT (14U) 630 #define STCU_ALGOSEL_ALGOSEL14_WIDTH (1U) 631 #define STCU_ALGOSEL_ALGOSEL14(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL14_SHIFT)) & STCU_ALGOSEL_ALGOSEL14_MASK) 632 633 #define STCU_ALGOSEL_ALGOSEL15_MASK (0x8000U) 634 #define STCU_ALGOSEL_ALGOSEL15_SHIFT (15U) 635 #define STCU_ALGOSEL_ALGOSEL15_WIDTH (1U) 636 #define STCU_ALGOSEL_ALGOSEL15(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL15_SHIFT)) & STCU_ALGOSEL_ALGOSEL15_MASK) 637 638 #define STCU_ALGOSEL_ALGOSEL16_MASK (0x10000U) 639 #define STCU_ALGOSEL_ALGOSEL16_SHIFT (16U) 640 #define STCU_ALGOSEL_ALGOSEL16_WIDTH (1U) 641 #define STCU_ALGOSEL_ALGOSEL16(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL16_SHIFT)) & STCU_ALGOSEL_ALGOSEL16_MASK) 642 643 #define STCU_ALGOSEL_ALGOSEL17_MASK (0x20000U) 644 #define STCU_ALGOSEL_ALGOSEL17_SHIFT (17U) 645 #define STCU_ALGOSEL_ALGOSEL17_WIDTH (1U) 646 #define STCU_ALGOSEL_ALGOSEL17(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL17_SHIFT)) & STCU_ALGOSEL_ALGOSEL17_MASK) 647 648 #define STCU_ALGOSEL_ALGOSEL18_MASK (0x40000U) 649 #define STCU_ALGOSEL_ALGOSEL18_SHIFT (18U) 650 #define STCU_ALGOSEL_ALGOSEL18_WIDTH (1U) 651 #define STCU_ALGOSEL_ALGOSEL18(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL18_SHIFT)) & STCU_ALGOSEL_ALGOSEL18_MASK) 652 653 #define STCU_ALGOSEL_ALGOSEL19_MASK (0x80000U) 654 #define STCU_ALGOSEL_ALGOSEL19_SHIFT (19U) 655 #define STCU_ALGOSEL_ALGOSEL19_WIDTH (1U) 656 #define STCU_ALGOSEL_ALGOSEL19(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL19_SHIFT)) & STCU_ALGOSEL_ALGOSEL19_MASK) 657 658 #define STCU_ALGOSEL_ALGOSEL20_MASK (0x100000U) 659 #define STCU_ALGOSEL_ALGOSEL20_SHIFT (20U) 660 #define STCU_ALGOSEL_ALGOSEL20_WIDTH (1U) 661 #define STCU_ALGOSEL_ALGOSEL20(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL20_SHIFT)) & STCU_ALGOSEL_ALGOSEL20_MASK) 662 663 #define STCU_ALGOSEL_ALGOSEL21_MASK (0x200000U) 664 #define STCU_ALGOSEL_ALGOSEL21_SHIFT (21U) 665 #define STCU_ALGOSEL_ALGOSEL21_WIDTH (1U) 666 #define STCU_ALGOSEL_ALGOSEL21(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL21_SHIFT)) & STCU_ALGOSEL_ALGOSEL21_MASK) 667 668 #define STCU_ALGOSEL_ALGOSEL22_MASK (0x400000U) 669 #define STCU_ALGOSEL_ALGOSEL22_SHIFT (22U) 670 #define STCU_ALGOSEL_ALGOSEL22_WIDTH (1U) 671 #define STCU_ALGOSEL_ALGOSEL22(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL22_SHIFT)) & STCU_ALGOSEL_ALGOSEL22_MASK) 672 673 #define STCU_ALGOSEL_ALGOSEL23_MASK (0x800000U) 674 #define STCU_ALGOSEL_ALGOSEL23_SHIFT (23U) 675 #define STCU_ALGOSEL_ALGOSEL23_WIDTH (1U) 676 #define STCU_ALGOSEL_ALGOSEL23(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL23_SHIFT)) & STCU_ALGOSEL_ALGOSEL23_MASK) 677 678 #define STCU_ALGOSEL_ALGOSEL24_MASK (0x1000000U) 679 #define STCU_ALGOSEL_ALGOSEL24_SHIFT (24U) 680 #define STCU_ALGOSEL_ALGOSEL24_WIDTH (1U) 681 #define STCU_ALGOSEL_ALGOSEL24(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL24_SHIFT)) & STCU_ALGOSEL_ALGOSEL24_MASK) 682 683 #define STCU_ALGOSEL_ALGOSEL25_MASK (0x2000000U) 684 #define STCU_ALGOSEL_ALGOSEL25_SHIFT (25U) 685 #define STCU_ALGOSEL_ALGOSEL25_WIDTH (1U) 686 #define STCU_ALGOSEL_ALGOSEL25(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL25_SHIFT)) & STCU_ALGOSEL_ALGOSEL25_MASK) 687 688 #define STCU_ALGOSEL_ALGOSEL26_MASK (0x4000000U) 689 #define STCU_ALGOSEL_ALGOSEL26_SHIFT (26U) 690 #define STCU_ALGOSEL_ALGOSEL26_WIDTH (1U) 691 #define STCU_ALGOSEL_ALGOSEL26(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL26_SHIFT)) & STCU_ALGOSEL_ALGOSEL26_MASK) 692 693 #define STCU_ALGOSEL_ALGOSEL27_MASK (0x8000000U) 694 #define STCU_ALGOSEL_ALGOSEL27_SHIFT (27U) 695 #define STCU_ALGOSEL_ALGOSEL27_WIDTH (1U) 696 #define STCU_ALGOSEL_ALGOSEL27(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL27_SHIFT)) & STCU_ALGOSEL_ALGOSEL27_MASK) 697 698 #define STCU_ALGOSEL_ALGOSEL28_MASK (0x10000000U) 699 #define STCU_ALGOSEL_ALGOSEL28_SHIFT (28U) 700 #define STCU_ALGOSEL_ALGOSEL28_WIDTH (1U) 701 #define STCU_ALGOSEL_ALGOSEL28(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL28_SHIFT)) & STCU_ALGOSEL_ALGOSEL28_MASK) 702 703 #define STCU_ALGOSEL_ALGOSEL29_MASK (0x20000000U) 704 #define STCU_ALGOSEL_ALGOSEL29_SHIFT (29U) 705 #define STCU_ALGOSEL_ALGOSEL29_WIDTH (1U) 706 #define STCU_ALGOSEL_ALGOSEL29(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL29_SHIFT)) & STCU_ALGOSEL_ALGOSEL29_MASK) 707 708 #define STCU_ALGOSEL_ALGOSEL30_MASK (0x40000000U) 709 #define STCU_ALGOSEL_ALGOSEL30_SHIFT (30U) 710 #define STCU_ALGOSEL_ALGOSEL30_WIDTH (1U) 711 #define STCU_ALGOSEL_ALGOSEL30(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL30_SHIFT)) & STCU_ALGOSEL_ALGOSEL30_MASK) 712 713 #define STCU_ALGOSEL_ALGOSEL31_MASK (0x80000000U) 714 #define STCU_ALGOSEL_ALGOSEL31_SHIFT (31U) 715 #define STCU_ALGOSEL_ALGOSEL31_WIDTH (1U) 716 #define STCU_ALGOSEL_ALGOSEL31(x) (((uint32_t)(((uint32_t)(x)) << STCU_ALGOSEL_ALGOSEL31_SHIFT)) & STCU_ALGOSEL_ALGOSEL31_MASK) 717 /*! @} */ 718 719 /*! @name STGGR - STCU2 MBIST Stagger */ 720 /*! @{ */ 721 722 #define STCU_STGGR_STAG_MASK (0xFFFFFFFFU) 723 #define STCU_STGGR_STAG_SHIFT (0U) 724 #define STCU_STGGR_STAG_WIDTH (32U) 725 #define STCU_STGGR_STAG(x) (((uint32_t)(((uint32_t)(x)) << STCU_STGGR_STAG_SHIFT)) & STCU_STGGR_STAG_MASK) 726 /*! @} */ 727 728 /*! @name BSTART - STCU2 BIST Start */ 729 /*! @{ */ 730 731 #define STCU_BSTART_BSTART0_MASK (0x1U) 732 #define STCU_BSTART_BSTART0_SHIFT (0U) 733 #define STCU_BSTART_BSTART0_WIDTH (1U) 734 #define STCU_BSTART_BSTART0(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART0_SHIFT)) & STCU_BSTART_BSTART0_MASK) 735 736 #define STCU_BSTART_BSTART1_MASK (0x2U) 737 #define STCU_BSTART_BSTART1_SHIFT (1U) 738 #define STCU_BSTART_BSTART1_WIDTH (1U) 739 #define STCU_BSTART_BSTART1(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART1_SHIFT)) & STCU_BSTART_BSTART1_MASK) 740 741 #define STCU_BSTART_BSTART2_MASK (0x4U) 742 #define STCU_BSTART_BSTART2_SHIFT (2U) 743 #define STCU_BSTART_BSTART2_WIDTH (1U) 744 #define STCU_BSTART_BSTART2(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART2_SHIFT)) & STCU_BSTART_BSTART2_MASK) 745 746 #define STCU_BSTART_BSTART3_MASK (0x8U) 747 #define STCU_BSTART_BSTART3_SHIFT (3U) 748 #define STCU_BSTART_BSTART3_WIDTH (1U) 749 #define STCU_BSTART_BSTART3(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART3_SHIFT)) & STCU_BSTART_BSTART3_MASK) 750 751 #define STCU_BSTART_BSTART4_MASK (0x10U) 752 #define STCU_BSTART_BSTART4_SHIFT (4U) 753 #define STCU_BSTART_BSTART4_WIDTH (1U) 754 #define STCU_BSTART_BSTART4(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART4_SHIFT)) & STCU_BSTART_BSTART4_MASK) 755 756 #define STCU_BSTART_BSTART5_MASK (0x20U) 757 #define STCU_BSTART_BSTART5_SHIFT (5U) 758 #define STCU_BSTART_BSTART5_WIDTH (1U) 759 #define STCU_BSTART_BSTART5(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART5_SHIFT)) & STCU_BSTART_BSTART5_MASK) 760 761 #define STCU_BSTART_BSTART6_MASK (0x40U) 762 #define STCU_BSTART_BSTART6_SHIFT (6U) 763 #define STCU_BSTART_BSTART6_WIDTH (1U) 764 #define STCU_BSTART_BSTART6(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART6_SHIFT)) & STCU_BSTART_BSTART6_MASK) 765 766 #define STCU_BSTART_BSTART7_MASK (0x80U) 767 #define STCU_BSTART_BSTART7_SHIFT (7U) 768 #define STCU_BSTART_BSTART7_WIDTH (1U) 769 #define STCU_BSTART_BSTART7(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART7_SHIFT)) & STCU_BSTART_BSTART7_MASK) 770 771 #define STCU_BSTART_BSTART8_MASK (0x100U) 772 #define STCU_BSTART_BSTART8_SHIFT (8U) 773 #define STCU_BSTART_BSTART8_WIDTH (1U) 774 #define STCU_BSTART_BSTART8(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART8_SHIFT)) & STCU_BSTART_BSTART8_MASK) 775 776 #define STCU_BSTART_BSTART9_MASK (0x200U) 777 #define STCU_BSTART_BSTART9_SHIFT (9U) 778 #define STCU_BSTART_BSTART9_WIDTH (1U) 779 #define STCU_BSTART_BSTART9(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART9_SHIFT)) & STCU_BSTART_BSTART9_MASK) 780 781 #define STCU_BSTART_BSTART10_MASK (0x400U) 782 #define STCU_BSTART_BSTART10_SHIFT (10U) 783 #define STCU_BSTART_BSTART10_WIDTH (1U) 784 #define STCU_BSTART_BSTART10(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART10_SHIFT)) & STCU_BSTART_BSTART10_MASK) 785 786 #define STCU_BSTART_BSTART11_MASK (0x800U) 787 #define STCU_BSTART_BSTART11_SHIFT (11U) 788 #define STCU_BSTART_BSTART11_WIDTH (1U) 789 #define STCU_BSTART_BSTART11(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART11_SHIFT)) & STCU_BSTART_BSTART11_MASK) 790 791 #define STCU_BSTART_BSTART12_MASK (0x1000U) 792 #define STCU_BSTART_BSTART12_SHIFT (12U) 793 #define STCU_BSTART_BSTART12_WIDTH (1U) 794 #define STCU_BSTART_BSTART12(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART12_SHIFT)) & STCU_BSTART_BSTART12_MASK) 795 796 #define STCU_BSTART_BSTART13_MASK (0x2000U) 797 #define STCU_BSTART_BSTART13_SHIFT (13U) 798 #define STCU_BSTART_BSTART13_WIDTH (1U) 799 #define STCU_BSTART_BSTART13(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART13_SHIFT)) & STCU_BSTART_BSTART13_MASK) 800 801 #define STCU_BSTART_BSTART14_MASK (0x4000U) 802 #define STCU_BSTART_BSTART14_SHIFT (14U) 803 #define STCU_BSTART_BSTART14_WIDTH (1U) 804 #define STCU_BSTART_BSTART14(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART14_SHIFT)) & STCU_BSTART_BSTART14_MASK) 805 806 #define STCU_BSTART_BSTART15_MASK (0x8000U) 807 #define STCU_BSTART_BSTART15_SHIFT (15U) 808 #define STCU_BSTART_BSTART15_WIDTH (1U) 809 #define STCU_BSTART_BSTART15(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART15_SHIFT)) & STCU_BSTART_BSTART15_MASK) 810 811 #define STCU_BSTART_BSTART16_MASK (0x10000U) 812 #define STCU_BSTART_BSTART16_SHIFT (16U) 813 #define STCU_BSTART_BSTART16_WIDTH (1U) 814 #define STCU_BSTART_BSTART16(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART16_SHIFT)) & STCU_BSTART_BSTART16_MASK) 815 816 #define STCU_BSTART_BSTART17_MASK (0x20000U) 817 #define STCU_BSTART_BSTART17_SHIFT (17U) 818 #define STCU_BSTART_BSTART17_WIDTH (1U) 819 #define STCU_BSTART_BSTART17(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART17_SHIFT)) & STCU_BSTART_BSTART17_MASK) 820 821 #define STCU_BSTART_BSTART18_MASK (0x40000U) 822 #define STCU_BSTART_BSTART18_SHIFT (18U) 823 #define STCU_BSTART_BSTART18_WIDTH (1U) 824 #define STCU_BSTART_BSTART18(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART18_SHIFT)) & STCU_BSTART_BSTART18_MASK) 825 826 #define STCU_BSTART_BSTART19_MASK (0x80000U) 827 #define STCU_BSTART_BSTART19_SHIFT (19U) 828 #define STCU_BSTART_BSTART19_WIDTH (1U) 829 #define STCU_BSTART_BSTART19(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART19_SHIFT)) & STCU_BSTART_BSTART19_MASK) 830 831 #define STCU_BSTART_BSTART20_MASK (0x100000U) 832 #define STCU_BSTART_BSTART20_SHIFT (20U) 833 #define STCU_BSTART_BSTART20_WIDTH (1U) 834 #define STCU_BSTART_BSTART20(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART20_SHIFT)) & STCU_BSTART_BSTART20_MASK) 835 836 #define STCU_BSTART_BSTART21_MASK (0x200000U) 837 #define STCU_BSTART_BSTART21_SHIFT (21U) 838 #define STCU_BSTART_BSTART21_WIDTH (1U) 839 #define STCU_BSTART_BSTART21(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART21_SHIFT)) & STCU_BSTART_BSTART21_MASK) 840 841 #define STCU_BSTART_BSTART22_MASK (0x400000U) 842 #define STCU_BSTART_BSTART22_SHIFT (22U) 843 #define STCU_BSTART_BSTART22_WIDTH (1U) 844 #define STCU_BSTART_BSTART22(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART22_SHIFT)) & STCU_BSTART_BSTART22_MASK) 845 846 #define STCU_BSTART_BSTART23_MASK (0x800000U) 847 #define STCU_BSTART_BSTART23_SHIFT (23U) 848 #define STCU_BSTART_BSTART23_WIDTH (1U) 849 #define STCU_BSTART_BSTART23(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART23_SHIFT)) & STCU_BSTART_BSTART23_MASK) 850 851 #define STCU_BSTART_BSTART24_MASK (0x1000000U) 852 #define STCU_BSTART_BSTART24_SHIFT (24U) 853 #define STCU_BSTART_BSTART24_WIDTH (1U) 854 #define STCU_BSTART_BSTART24(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART24_SHIFT)) & STCU_BSTART_BSTART24_MASK) 855 856 #define STCU_BSTART_BSTART25_MASK (0x2000000U) 857 #define STCU_BSTART_BSTART25_SHIFT (25U) 858 #define STCU_BSTART_BSTART25_WIDTH (1U) 859 #define STCU_BSTART_BSTART25(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART25_SHIFT)) & STCU_BSTART_BSTART25_MASK) 860 861 #define STCU_BSTART_BSTART26_MASK (0x4000000U) 862 #define STCU_BSTART_BSTART26_SHIFT (26U) 863 #define STCU_BSTART_BSTART26_WIDTH (1U) 864 #define STCU_BSTART_BSTART26(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART26_SHIFT)) & STCU_BSTART_BSTART26_MASK) 865 866 #define STCU_BSTART_BSTART27_MASK (0x8000000U) 867 #define STCU_BSTART_BSTART27_SHIFT (27U) 868 #define STCU_BSTART_BSTART27_WIDTH (1U) 869 #define STCU_BSTART_BSTART27(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART27_SHIFT)) & STCU_BSTART_BSTART27_MASK) 870 871 #define STCU_BSTART_BSTART28_MASK (0x10000000U) 872 #define STCU_BSTART_BSTART28_SHIFT (28U) 873 #define STCU_BSTART_BSTART28_WIDTH (1U) 874 #define STCU_BSTART_BSTART28(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART28_SHIFT)) & STCU_BSTART_BSTART28_MASK) 875 876 #define STCU_BSTART_BSTART29_MASK (0x20000000U) 877 #define STCU_BSTART_BSTART29_SHIFT (29U) 878 #define STCU_BSTART_BSTART29_WIDTH (1U) 879 #define STCU_BSTART_BSTART29(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART29_SHIFT)) & STCU_BSTART_BSTART29_MASK) 880 881 #define STCU_BSTART_BSTART30_MASK (0x40000000U) 882 #define STCU_BSTART_BSTART30_SHIFT (30U) 883 #define STCU_BSTART_BSTART30_WIDTH (1U) 884 #define STCU_BSTART_BSTART30(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART30_SHIFT)) & STCU_BSTART_BSTART30_MASK) 885 886 #define STCU_BSTART_BSTART31_MASK (0x80000000U) 887 #define STCU_BSTART_BSTART31_SHIFT (31U) 888 #define STCU_BSTART_BSTART31_WIDTH (1U) 889 #define STCU_BSTART_BSTART31(x) (((uint32_t)(((uint32_t)(x)) << STCU_BSTART_BSTART31_SHIFT)) & STCU_BSTART_BSTART31_MASK) 890 /*! @} */ 891 892 /*! @name MB_CTRL - STCU2 MBIST Control */ 893 /*! @{ */ 894 895 #define STCU_MB_CTRL_BSEL_MASK (0x100000U) 896 #define STCU_MB_CTRL_BSEL_SHIFT (20U) 897 #define STCU_MB_CTRL_BSEL_WIDTH (1U) 898 #define STCU_MB_CTRL_BSEL(x) (((uint32_t)(((uint32_t)(x)) << STCU_MB_CTRL_BSEL_SHIFT)) & STCU_MB_CTRL_BSEL_MASK) 899 900 #define STCU_MB_CTRL_PTR_MASK (0x7FE00000U) 901 #define STCU_MB_CTRL_PTR_SHIFT (21U) 902 #define STCU_MB_CTRL_PTR_WIDTH (10U) 903 #define STCU_MB_CTRL_PTR(x) (((uint32_t)(((uint32_t)(x)) << STCU_MB_CTRL_PTR_SHIFT)) & STCU_MB_CTRL_PTR_MASK) 904 905 #define STCU_MB_CTRL_CSM_MASK (0x80000000U) 906 #define STCU_MB_CTRL_CSM_SHIFT (31U) 907 #define STCU_MB_CTRL_CSM_WIDTH (1U) 908 #define STCU_MB_CTRL_CSM(x) (((uint32_t)(((uint32_t)(x)) << STCU_MB_CTRL_CSM_SHIFT)) & STCU_MB_CTRL_CSM_MASK) 909 /*! @} */ 910 911 /*! 912 * @} 913 */ /* end of group STCU_Register_Masks */ 914 915 /*! 916 * @} 917 */ /* end of group STCU_Peripheral_Access_Layer */ 918 919 #endif /* #if !defined(S32K344_STCU_H_) */ 920
