1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_SELFTEST_GPR.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_SELFTEST_GPR 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_SELFTEST_GPR_H_) /* Check if memory map has not been already included */ 58 #define S32K344_SELFTEST_GPR_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SELFTEST_GPR Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SELFTEST_GPR_Peripheral_Access_Layer SELFTEST_GPR Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SELFTEST_GPR - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CONFIG_REG; /**< Configuration register, offset: 0x0 */ 74 uint8_t RESERVED_0[16]; 75 __IO uint32_t LBIST_PROG_REG; /**< LBIST Program, offset: 0x14 */ 76 } SELFTEST_GPR_Type, *SELFTEST_GPR_MemMapPtr; 77 78 /** Number of instances of the SELFTEST_GPR module. */ 79 #define SELFTEST_GPR_INSTANCE_COUNT (1u) 80 81 /* SELFTEST_GPR - Peripheral instance base addresses */ 82 /** Peripheral SELFTEST_GPR base address */ 83 #define IP_SELFTEST_GPR_BASE (0x403B0000u) 84 /** Peripheral SELFTEST_GPR base pointer */ 85 #define IP_SELFTEST_GPR ((SELFTEST_GPR_Type *)IP_SELFTEST_GPR_BASE) 86 /** Array initializer of SELFTEST_GPR peripheral base addresses */ 87 #define IP_SELFTEST_GPR_BASE_ADDRS { IP_SELFTEST_GPR_BASE } 88 /** Array initializer of SELFTEST_GPR peripheral base pointers */ 89 #define IP_SELFTEST_GPR_BASE_PTRS { IP_SELFTEST_GPR } 90 91 /* ---------------------------------------------------------------------------- 92 -- SELFTEST_GPR Register Masks 93 ---------------------------------------------------------------------------- */ 94 95 /*! 96 * @addtogroup SELFTEST_GPR_Register_Masks SELFTEST_GPR Register Masks 97 * @{ 98 */ 99 100 /*! @name CONFIG_REG - Configuration register */ 101 /*! @{ */ 102 103 #define SELFTEST_GPR_CONFIG_REG_PCS_STEP_SIZE_MASK (0x70U) 104 #define SELFTEST_GPR_CONFIG_REG_PCS_STEP_SIZE_SHIFT (4U) 105 #define SELFTEST_GPR_CONFIG_REG_PCS_STEP_SIZE_WIDTH (3U) 106 #define SELFTEST_GPR_CONFIG_REG_PCS_STEP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SELFTEST_GPR_CONFIG_REG_PCS_STEP_SIZE_SHIFT)) & SELFTEST_GPR_CONFIG_REG_PCS_STEP_SIZE_MASK) 107 108 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_START_MASK (0x80U) 109 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_START_SHIFT (7U) 110 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_START_WIDTH (1U) 111 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_START(x) (((uint32_t)(((uint32_t)(x)) << SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_START_SHIFT)) & SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_START_MASK) 112 113 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_END_MASK (0x100U) 114 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_END_SHIFT (8U) 115 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_END_WIDTH (1U) 116 #define SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_END(x) (((uint32_t)(((uint32_t)(x)) << SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_END_SHIFT)) & SELFTEST_GPR_CONFIG_REG_PCS_ENABLE_END_MASK) 117 /*! @} */ 118 119 /*! @name LBIST_PROG_REG - LBIST Program */ 120 /*! @{ */ 121 122 #define SELFTEST_GPR_LBIST_PROG_REG_LBIST_SHIFT_COUNT_MASK (0xFFU) 123 #define SELFTEST_GPR_LBIST_PROG_REG_LBIST_SHIFT_COUNT_SHIFT (0U) 124 #define SELFTEST_GPR_LBIST_PROG_REG_LBIST_SHIFT_COUNT_WIDTH (8U) 125 #define SELFTEST_GPR_LBIST_PROG_REG_LBIST_SHIFT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SELFTEST_GPR_LBIST_PROG_REG_LBIST_SHIFT_COUNT_SHIFT)) & SELFTEST_GPR_LBIST_PROG_REG_LBIST_SHIFT_COUNT_MASK) 126 /*! @} */ 127 128 /*! 129 * @} 130 */ /* end of group SELFTEST_GPR_Register_Masks */ 131 132 /*! 133 * @} 134 */ /* end of group SELFTEST_GPR_Peripheral_Access_Layer */ 135 136 #endif /* #if !defined(S32K344_SELFTEST_GPR_H_) */ 137
