1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_QuadSPI.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_QuadSPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_QuadSPI_H_) /* Check if memory map has not been already included */ 58 #define S32K344_QuadSPI_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- QuadSPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** QuadSPI - Size of Registers Arrays */ 72 #define QuadSPI_RBDR_COUNT 64u 73 #define QuadSPI_LUT_COUNT 20u 74 75 /** QuadSPI - Register Layout Typedef */ 76 typedef struct { 77 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 78 uint8_t RESERVED_0[4]; 79 __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ 80 __IO uint32_t FLSHCR; /**< Flash Memory Configuration Register, offset: 0xC */ 81 __IO uint32_t BUF0CR; /**< Buffer 0 Configuration Register, offset: 0x10 */ 82 __IO uint32_t BUF1CR; /**< Buffer 1 Configuration Register, offset: 0x14 */ 83 __IO uint32_t BUF2CR; /**< Buffer 2 Configuration Register, offset: 0x18 */ 84 __IO uint32_t BUF3CR; /**< Buffer 3 Configuration Register, offset: 0x1C */ 85 __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ 86 __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ 87 uint8_t RESERVED_1[8]; 88 __IO uint32_t BUF0IND; /**< Buffer 0 Top Index Register, offset: 0x30 */ 89 __IO uint32_t BUF1IND; /**< Buffer 1 Top Index Register, offset: 0x34 */ 90 __IO uint32_t BUF2IND; /**< Buffer 2 Top Index Register, offset: 0x38 */ 91 uint8_t RESERVED_2[36]; 92 __IO uint32_t DLLCRA; /**< DLL Flash Memory A Configuration Register, offset: 0x60 */ 93 uint8_t RESERVED_3[156]; 94 __IO uint32_t SFAR; /**< Serial Flash Memory Address Register, offset: 0x100 */ 95 uint8_t RESERVED_4[4]; 96 __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ 97 __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ 98 __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ 99 uint8_t RESERVED_5[24]; 100 __I uint32_t DLLSR; /**< DLL Status Register, offset: 0x12C */ 101 uint8_t RESERVED_6[4]; 102 __I uint32_t DLSR_FA; /**< Data Learning Status Flash Memory A Register, offset: 0x134 */ 103 uint8_t RESERVED_7[24]; 104 __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ 105 __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ 106 __IO uint32_t TBCT; /**< TX Buffer Control Register, offset: 0x158 */ 107 __I uint32_t SR; /**< Status Register, offset: 0x15C */ 108 __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ 109 __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ 110 uint8_t RESERVED_8[4]; 111 __O uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ 112 uint8_t RESERVED_9[16]; 113 __IO uint32_t SFA1AD; /**< Serial Flash Memory A1 Top Address Register, offset: 0x180 */ 114 __IO uint32_t SFA2AD; /**< Serial Flash Memory A2 Top Address Register, offset: 0x184 */ 115 __IO uint32_t SFB1AD; /**< Serial Flash Memory B1 Top Address Register, offset: 0x188 */ 116 __IO uint32_t SFB2AD; /**< Serial Flash Memory B2 Top Address Register, offset: 0x18C */ 117 uint8_t RESERVED_10[112]; 118 __I uint32_t RBDR[QuadSPI_RBDR_COUNT]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ 119 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ 120 __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ 121 uint8_t RESERVED_11[8]; 122 __IO uint32_t LUT[QuadSPI_LUT_COUNT]; /**< LUT Register, array offset: 0x310, array step: 0x4 */ 123 } QuadSPI_Type, *QuadSPI_MemMapPtr; 124 125 /** Number of instances of the QuadSPI module. */ 126 #define QuadSPI_INSTANCE_COUNT (1) 127 128 /* QuadSPI - Peripheral instance base addresses */ 129 /** Peripheral QUADSPI base address */ 130 #define IP_QUADSPI_BASE (0x404CC000u) 131 /** Peripheral QUADSPI base pointer */ 132 #define IP_QUADSPI ((QuadSPI_Type *)IP_QUADSPI_BASE) 133 /** Array initializer of QuadSPI peripheral base addresses */ 134 #define IP_QuadSPI_BASE_ADDRS { IP_QUADSPI_BASE } 135 /** Array initializer of QuadSPI peripheral base pointers */ 136 #define IP_QuadSPI_BASE_PTRS { IP_QUADSPI } 137 138 /* ---------------------------------------------------------------------------- 139 -- QuadSPI Register Masks 140 ---------------------------------------------------------------------------- */ 141 142 /*! 143 * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks 144 * @{ 145 */ 146 147 /*! @name MCR - Module Configuration Register */ 148 /*! @{ */ 149 150 #define QuadSPI_MCR_SWRSTSD_MASK (0x1U) 151 #define QuadSPI_MCR_SWRSTSD_SHIFT (0U) 152 #define QuadSPI_MCR_SWRSTSD_WIDTH (1U) 153 #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) 154 155 #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) 156 #define QuadSPI_MCR_SWRSTHD_SHIFT (1U) 157 #define QuadSPI_MCR_SWRSTHD_WIDTH (1U) 158 #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) 159 160 #define QuadSPI_MCR_CLR_RXF_MASK (0x400U) 161 #define QuadSPI_MCR_CLR_RXF_SHIFT (10U) 162 #define QuadSPI_MCR_CLR_RXF_WIDTH (1U) 163 #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) 164 165 #define QuadSPI_MCR_CLR_TXF_MASK (0x800U) 166 #define QuadSPI_MCR_CLR_TXF_SHIFT (11U) 167 #define QuadSPI_MCR_CLR_TXF_WIDTH (1U) 168 #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) 169 170 #define QuadSPI_MCR_MDIS_MASK (0x4000U) 171 #define QuadSPI_MCR_MDIS_SHIFT (14U) 172 #define QuadSPI_MCR_MDIS_WIDTH (1U) 173 #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) 174 175 #define QuadSPI_MCR_DQS_FA_SEL_MASK (0x3000000U) 176 #define QuadSPI_MCR_DQS_FA_SEL_SHIFT (24U) 177 #define QuadSPI_MCR_DQS_FA_SEL_WIDTH (2U) 178 #define QuadSPI_MCR_DQS_FA_SEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_FA_SEL_SHIFT)) & QuadSPI_MCR_DQS_FA_SEL_MASK) 179 /*! @} */ 180 181 /*! @name IPCR - IP Configuration Register */ 182 /*! @{ */ 183 184 #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) 185 #define QuadSPI_IPCR_IDATSZ_SHIFT (0U) 186 #define QuadSPI_IPCR_IDATSZ_WIDTH (16U) 187 #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) 188 189 #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) 190 #define QuadSPI_IPCR_SEQID_SHIFT (24U) 191 #define QuadSPI_IPCR_SEQID_WIDTH (4U) 192 #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) 193 /*! @} */ 194 195 /*! @name FLSHCR - Flash Memory Configuration Register */ 196 /*! @{ */ 197 198 #define QuadSPI_FLSHCR_TCSS_MASK (0xFU) 199 #define QuadSPI_FLSHCR_TCSS_SHIFT (0U) 200 #define QuadSPI_FLSHCR_TCSS_WIDTH (4U) 201 #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) 202 203 #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) 204 #define QuadSPI_FLSHCR_TCSH_SHIFT (8U) 205 #define QuadSPI_FLSHCR_TCSH_WIDTH (4U) 206 #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) 207 /*! @} */ 208 209 /*! @name BUF0CR - Buffer 0 Configuration Register */ 210 /*! @{ */ 211 212 #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) 213 #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) 214 #define QuadSPI_BUF0CR_MSTRID_WIDTH (4U) 215 #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) 216 217 #define QuadSPI_BUF0CR_ADATSZ_MASK (0x3F00U) 218 #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) 219 #define QuadSPI_BUF0CR_ADATSZ_WIDTH (6U) 220 #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) 221 /*! @} */ 222 223 /*! @name BUF1CR - Buffer 1 Configuration Register */ 224 /*! @{ */ 225 226 #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) 227 #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) 228 #define QuadSPI_BUF1CR_MSTRID_WIDTH (4U) 229 #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) 230 231 #define QuadSPI_BUF1CR_ADATSZ_MASK (0x3F00U) 232 #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) 233 #define QuadSPI_BUF1CR_ADATSZ_WIDTH (6U) 234 #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) 235 /*! @} */ 236 237 /*! @name BUF2CR - Buffer 2 Configuration Register */ 238 /*! @{ */ 239 240 #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) 241 #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) 242 #define QuadSPI_BUF2CR_MSTRID_WIDTH (4U) 243 #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) 244 245 #define QuadSPI_BUF2CR_ADATSZ_MASK (0x3F00U) 246 #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) 247 #define QuadSPI_BUF2CR_ADATSZ_WIDTH (6U) 248 #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) 249 /*! @} */ 250 251 /*! @name BUF3CR - Buffer 3 Configuration Register */ 252 /*! @{ */ 253 254 #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) 255 #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) 256 #define QuadSPI_BUF3CR_MSTRID_WIDTH (4U) 257 #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) 258 259 #define QuadSPI_BUF3CR_ADATSZ_MASK (0x3F00U) 260 #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) 261 #define QuadSPI_BUF3CR_ADATSZ_WIDTH (6U) 262 #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) 263 264 #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) 265 #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) 266 #define QuadSPI_BUF3CR_ALLMST_WIDTH (1U) 267 #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) 268 /*! @} */ 269 270 /*! @name BFGENCR - Buffer Generic Configuration Register */ 271 /*! @{ */ 272 273 #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) 274 #define QuadSPI_BFGENCR_SEQID_SHIFT (12U) 275 #define QuadSPI_BFGENCR_SEQID_WIDTH (4U) 276 #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) 277 /*! @} */ 278 279 /*! @name SOCCR - SOC Configuration Register */ 280 /*! @{ */ 281 282 #define QuadSPI_SOCCR_SOCCFG_MASK (0xFFFFFFFFU) 283 #define QuadSPI_SOCCR_SOCCFG_SHIFT (0U) 284 #define QuadSPI_SOCCR_SOCCFG_WIDTH (32U) 285 #define QuadSPI_SOCCR_SOCCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_SOCCFG_SHIFT)) & QuadSPI_SOCCR_SOCCFG_MASK) 286 /*! @} */ 287 288 /*! @name BUF0IND - Buffer 0 Top Index Register */ 289 /*! @{ */ 290 291 #define QuadSPI_BUF0IND_TPINDX0_MASK (0x1F8U) 292 #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) 293 #define QuadSPI_BUF0IND_TPINDX0_WIDTH (6U) 294 #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) 295 /*! @} */ 296 297 /*! @name BUF1IND - Buffer 1 Top Index Register */ 298 /*! @{ */ 299 300 #define QuadSPI_BUF1IND_TPINDX1_MASK (0x1F8U) 301 #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) 302 #define QuadSPI_BUF1IND_TPINDX1_WIDTH (6U) 303 #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) 304 /*! @} */ 305 306 /*! @name BUF2IND - Buffer 2 Top Index Register */ 307 /*! @{ */ 308 309 #define QuadSPI_BUF2IND_TPINDX2_MASK (0x1F8U) 310 #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) 311 #define QuadSPI_BUF2IND_TPINDX2_WIDTH (6U) 312 #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) 313 /*! @} */ 314 315 /*! @name DLLCRA - DLL Flash Memory A Configuration Register */ 316 /*! @{ */ 317 318 #define QuadSPI_DLLCRA_SLV_UPD_MASK (0x1U) 319 #define QuadSPI_DLLCRA_SLV_UPD_SHIFT (0U) 320 #define QuadSPI_DLLCRA_SLV_UPD_WIDTH (1U) 321 #define QuadSPI_DLLCRA_SLV_UPD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_UPD_SHIFT)) & QuadSPI_DLLCRA_SLV_UPD_MASK) 322 323 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS_MASK (0x2U) 324 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS_SHIFT (1U) 325 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS_WIDTH (1U) 326 #define QuadSPI_DLLCRA_SLV_DLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_DLL_BYPASS_SHIFT)) & QuadSPI_DLLCRA_SLV_DLL_BYPASS_MASK) 327 328 #define QuadSPI_DLLCRA_SLV_EN_MASK (0x4U) 329 #define QuadSPI_DLLCRA_SLV_EN_SHIFT (2U) 330 #define QuadSPI_DLLCRA_SLV_EN_WIDTH (1U) 331 #define QuadSPI_DLLCRA_SLV_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_EN_SHIFT)) & QuadSPI_DLLCRA_SLV_EN_MASK) 332 333 #define QuadSPI_DLLCRA_SLV_DLY_COARSE_MASK (0xF00U) 334 #define QuadSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8U) 335 #define QuadSPI_DLLCRA_SLV_DLY_COARSE_WIDTH (4U) 336 #define QuadSPI_DLLCRA_SLV_DLY_COARSE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)) & QuadSPI_DLLCRA_SLV_DLY_COARSE_MASK) 337 338 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x7000U) 339 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12U) 340 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET_WIDTH (3U) 341 #define QuadSPI_DLLCRA_SLV_DLY_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)) & QuadSPI_DLLCRA_SLV_DLY_OFFSET_MASK) 342 343 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0xF0000U) 344 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16U) 345 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET_WIDTH (4U) 346 #define QuadSPI_DLLCRA_SLV_FINE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)) & QuadSPI_DLLCRA_SLV_FINE_OFFSET_MASK) 347 348 #define QuadSPI_DLLCRA_FREQEN_MASK (0x40000000U) 349 #define QuadSPI_DLLCRA_FREQEN_SHIFT (30U) 350 #define QuadSPI_DLLCRA_FREQEN_WIDTH (1U) 351 #define QuadSPI_DLLCRA_FREQEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLCRA_FREQEN_SHIFT)) & QuadSPI_DLLCRA_FREQEN_MASK) 352 /*! @} */ 353 354 /*! @name SFAR - Serial Flash Memory Address Register */ 355 /*! @{ */ 356 357 #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) 358 #define QuadSPI_SFAR_SFADR_SHIFT (0U) 359 #define QuadSPI_SFAR_SFADR_WIDTH (32U) 360 #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) 361 /*! @} */ 362 363 /*! @name SMPR - Sampling Register */ 364 /*! @{ */ 365 366 #define QuadSPI_SMPR_FSPHS_MASK (0x20U) 367 #define QuadSPI_SMPR_FSPHS_SHIFT (5U) 368 #define QuadSPI_SMPR_FSPHS_WIDTH (1U) 369 #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK) 370 371 #define QuadSPI_SMPR_FSDLY_MASK (0x40U) 372 #define QuadSPI_SMPR_FSDLY_SHIFT (6U) 373 #define QuadSPI_SMPR_FSDLY_WIDTH (1U) 374 #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK) 375 376 #define QuadSPI_SMPR_DLLFSMPFA_MASK (0x7000000U) 377 #define QuadSPI_SMPR_DLLFSMPFA_SHIFT (24U) 378 #define QuadSPI_SMPR_DLLFSMPFA_WIDTH (3U) 379 #define QuadSPI_SMPR_DLLFSMPFA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DLLFSMPFA_SHIFT)) & QuadSPI_SMPR_DLLFSMPFA_MASK) 380 /*! @} */ 381 382 /*! @name RBSR - RX Buffer Status Register */ 383 /*! @{ */ 384 385 #define QuadSPI_RBSR_RDBFL_MASK (0xFFU) 386 #define QuadSPI_RBSR_RDBFL_SHIFT (0U) 387 #define QuadSPI_RBSR_RDBFL_WIDTH (8U) 388 #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) 389 390 #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) 391 #define QuadSPI_RBSR_RDCTR_SHIFT (16U) 392 #define QuadSPI_RBSR_RDCTR_WIDTH (16U) 393 #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) 394 /*! @} */ 395 396 /*! @name RBCT - RX Buffer Control Register */ 397 /*! @{ */ 398 399 #define QuadSPI_RBCT_WMRK_MASK (0x7FU) 400 #define QuadSPI_RBCT_WMRK_SHIFT (0U) 401 #define QuadSPI_RBCT_WMRK_WIDTH (7U) 402 #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) 403 404 #define QuadSPI_RBCT_RXBRD_MASK (0x100U) 405 #define QuadSPI_RBCT_RXBRD_SHIFT (8U) 406 #define QuadSPI_RBCT_RXBRD_WIDTH (1U) 407 #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) 408 /*! @} */ 409 410 /*! @name DLLSR - DLL Status Register */ 411 /*! @{ */ 412 413 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK (0xFU) 414 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT (0U) 415 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_WIDTH (4U) 416 #define QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_SHIFT)) & QuadSPI_DLLSR_DLLA_SLV_COARSE_VAL_MASK) 417 418 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK (0xF0U) 419 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT (4U) 420 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_WIDTH (4U) 421 #define QuadSPI_DLLSR_DLLA_SLV_FINE_VAL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_SHIFT)) & QuadSPI_DLLSR_DLLA_SLV_FINE_VAL_MASK) 422 423 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK (0x1000U) 424 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT (12U) 425 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_WIDTH (1U) 426 #define QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_SHIFT)) & QuadSPI_DLLSR_DLLA_FINE_UNDERFLOW_MASK) 427 428 #define QuadSPI_DLLSR_DLLA_RANGE_ERR_MASK (0x2000U) 429 #define QuadSPI_DLLSR_DLLA_RANGE_ERR_SHIFT (13U) 430 #define QuadSPI_DLLSR_DLLA_RANGE_ERR_WIDTH (1U) 431 #define QuadSPI_DLLSR_DLLA_RANGE_ERR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_RANGE_ERR_SHIFT)) & QuadSPI_DLLSR_DLLA_RANGE_ERR_MASK) 432 433 #define QuadSPI_DLLSR_SLVA_LOCK_MASK (0x4000U) 434 #define QuadSPI_DLLSR_SLVA_LOCK_SHIFT (14U) 435 #define QuadSPI_DLLSR_SLVA_LOCK_WIDTH (1U) 436 #define QuadSPI_DLLSR_SLVA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_SLVA_LOCK_SHIFT)) & QuadSPI_DLLSR_SLVA_LOCK_MASK) 437 438 #define QuadSPI_DLLSR_DLLA_LOCK_MASK (0x8000U) 439 #define QuadSPI_DLLSR_DLLA_LOCK_SHIFT (15U) 440 #define QuadSPI_DLLSR_DLLA_LOCK_WIDTH (1U) 441 #define QuadSPI_DLLSR_DLLA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLLSR_DLLA_LOCK_SHIFT)) & QuadSPI_DLLSR_DLLA_LOCK_MASK) 442 /*! @} */ 443 444 /*! @name DLSR_FA - Data Learning Status Flash Memory A Register */ 445 /*! @{ */ 446 447 #define QuadSPI_DLSR_FA_NEG_EDGE_MASK (0xFFU) 448 #define QuadSPI_DLSR_FA_NEG_EDGE_SHIFT (0U) 449 #define QuadSPI_DLSR_FA_NEG_EDGE_WIDTH (8U) 450 #define QuadSPI_DLSR_FA_NEG_EDGE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FA_NEG_EDGE_SHIFT)) & QuadSPI_DLSR_FA_NEG_EDGE_MASK) 451 452 #define QuadSPI_DLSR_FA_POS_EDGE_MASK (0xFF00U) 453 #define QuadSPI_DLSR_FA_POS_EDGE_SHIFT (8U) 454 #define QuadSPI_DLSR_FA_POS_EDGE_WIDTH (8U) 455 #define QuadSPI_DLSR_FA_POS_EDGE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FA_POS_EDGE_SHIFT)) & QuadSPI_DLSR_FA_POS_EDGE_MASK) 456 457 #define QuadSPI_DLSR_FA_DLPFFA_MASK (0x80000000U) 458 #define QuadSPI_DLSR_FA_DLPFFA_SHIFT (31U) 459 #define QuadSPI_DLSR_FA_DLPFFA_WIDTH (1U) 460 #define QuadSPI_DLSR_FA_DLPFFA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLSR_FA_DLPFFA_SHIFT)) & QuadSPI_DLSR_FA_DLPFFA_MASK) 461 /*! @} */ 462 463 /*! @name TBSR - TX Buffer Status Register */ 464 /*! @{ */ 465 466 #define QuadSPI_TBSR_TRBFL_MASK (0x3FU) 467 #define QuadSPI_TBSR_TRBFL_SHIFT (0U) 468 #define QuadSPI_TBSR_TRBFL_WIDTH (6U) 469 #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) 470 471 #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) 472 #define QuadSPI_TBSR_TRCTR_SHIFT (16U) 473 #define QuadSPI_TBSR_TRCTR_WIDTH (16U) 474 #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) 475 /*! @} */ 476 477 /*! @name TBDR - TX Buffer Data Register */ 478 /*! @{ */ 479 480 #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) 481 #define QuadSPI_TBDR_TXDATA_SHIFT (0U) 482 #define QuadSPI_TBDR_TXDATA_WIDTH (32U) 483 #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) 484 /*! @} */ 485 486 /*! @name TBCT - TX Buffer Control Register */ 487 /*! @{ */ 488 489 #define QuadSPI_TBCT_WMRK_MASK (0x1FU) 490 #define QuadSPI_TBCT_WMRK_SHIFT (0U) 491 #define QuadSPI_TBCT_WMRK_WIDTH (5U) 492 #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK) 493 /*! @} */ 494 495 /*! @name SR - Status Register */ 496 /*! @{ */ 497 498 #define QuadSPI_SR_BUSY_MASK (0x1U) 499 #define QuadSPI_SR_BUSY_SHIFT (0U) 500 #define QuadSPI_SR_BUSY_WIDTH (1U) 501 #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) 502 503 #define QuadSPI_SR_IP_ACC_MASK (0x2U) 504 #define QuadSPI_SR_IP_ACC_SHIFT (1U) 505 #define QuadSPI_SR_IP_ACC_WIDTH (1U) 506 #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) 507 508 #define QuadSPI_SR_AHB_ACC_MASK (0x4U) 509 #define QuadSPI_SR_AHB_ACC_SHIFT (2U) 510 #define QuadSPI_SR_AHB_ACC_WIDTH (1U) 511 #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) 512 513 #define QuadSPI_SR_AHBTRN_MASK (0x40U) 514 #define QuadSPI_SR_AHBTRN_SHIFT (6U) 515 #define QuadSPI_SR_AHBTRN_WIDTH (1U) 516 #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) 517 518 #define QuadSPI_SR_AHB0NE_MASK (0x80U) 519 #define QuadSPI_SR_AHB0NE_SHIFT (7U) 520 #define QuadSPI_SR_AHB0NE_WIDTH (1U) 521 #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) 522 523 #define QuadSPI_SR_AHB1NE_MASK (0x100U) 524 #define QuadSPI_SR_AHB1NE_SHIFT (8U) 525 #define QuadSPI_SR_AHB1NE_WIDTH (1U) 526 #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) 527 528 #define QuadSPI_SR_AHB2NE_MASK (0x200U) 529 #define QuadSPI_SR_AHB2NE_SHIFT (9U) 530 #define QuadSPI_SR_AHB2NE_WIDTH (1U) 531 #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) 532 533 #define QuadSPI_SR_AHB3NE_MASK (0x400U) 534 #define QuadSPI_SR_AHB3NE_SHIFT (10U) 535 #define QuadSPI_SR_AHB3NE_WIDTH (1U) 536 #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) 537 538 #define QuadSPI_SR_AHB0FUL_MASK (0x800U) 539 #define QuadSPI_SR_AHB0FUL_SHIFT (11U) 540 #define QuadSPI_SR_AHB0FUL_WIDTH (1U) 541 #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) 542 543 #define QuadSPI_SR_AHB1FUL_MASK (0x1000U) 544 #define QuadSPI_SR_AHB1FUL_SHIFT (12U) 545 #define QuadSPI_SR_AHB1FUL_WIDTH (1U) 546 #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) 547 548 #define QuadSPI_SR_AHB2FUL_MASK (0x2000U) 549 #define QuadSPI_SR_AHB2FUL_SHIFT (13U) 550 #define QuadSPI_SR_AHB2FUL_WIDTH (1U) 551 #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) 552 553 #define QuadSPI_SR_AHB3FUL_MASK (0x4000U) 554 #define QuadSPI_SR_AHB3FUL_SHIFT (14U) 555 #define QuadSPI_SR_AHB3FUL_WIDTH (1U) 556 #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) 557 558 #define QuadSPI_SR_RXWE_MASK (0x10000U) 559 #define QuadSPI_SR_RXWE_SHIFT (16U) 560 #define QuadSPI_SR_RXWE_WIDTH (1U) 561 #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) 562 563 #define QuadSPI_SR_RXFULL_MASK (0x80000U) 564 #define QuadSPI_SR_RXFULL_SHIFT (19U) 565 #define QuadSPI_SR_RXFULL_WIDTH (1U) 566 #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) 567 568 #define QuadSPI_SR_RXDMA_MASK (0x800000U) 569 #define QuadSPI_SR_RXDMA_SHIFT (23U) 570 #define QuadSPI_SR_RXDMA_WIDTH (1U) 571 #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) 572 573 #define QuadSPI_SR_TXNE_MASK (0x1000000U) 574 #define QuadSPI_SR_TXNE_SHIFT (24U) 575 #define QuadSPI_SR_TXNE_WIDTH (1U) 576 #define QuadSPI_SR_TXNE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXNE_SHIFT)) & QuadSPI_SR_TXNE_MASK) 577 578 #define QuadSPI_SR_TXWA_MASK (0x2000000U) 579 #define QuadSPI_SR_TXWA_SHIFT (25U) 580 #define QuadSPI_SR_TXWA_WIDTH (1U) 581 #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK) 582 583 #define QuadSPI_SR_TXDMA_MASK (0x4000000U) 584 #define QuadSPI_SR_TXDMA_SHIFT (26U) 585 #define QuadSPI_SR_TXDMA_WIDTH (1U) 586 #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK) 587 588 #define QuadSPI_SR_TXFULL_MASK (0x8000000U) 589 #define QuadSPI_SR_TXFULL_SHIFT (27U) 590 #define QuadSPI_SR_TXFULL_WIDTH (1U) 591 #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) 592 /*! @} */ 593 594 /*! @name FR - Flag Register */ 595 /*! @{ */ 596 597 #define QuadSPI_FR_TFF_MASK (0x1U) 598 #define QuadSPI_FR_TFF_SHIFT (0U) 599 #define QuadSPI_FR_TFF_WIDTH (1U) 600 #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) 601 602 #define QuadSPI_FR_IPIEF_MASK (0x40U) 603 #define QuadSPI_FR_IPIEF_SHIFT (6U) 604 #define QuadSPI_FR_IPIEF_WIDTH (1U) 605 #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) 606 607 #define QuadSPI_FR_IPAEF_MASK (0x80U) 608 #define QuadSPI_FR_IPAEF_SHIFT (7U) 609 #define QuadSPI_FR_IPAEF_WIDTH (1U) 610 #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) 611 612 #define QuadSPI_FR_ABOF_MASK (0x1000U) 613 #define QuadSPI_FR_ABOF_SHIFT (12U) 614 #define QuadSPI_FR_ABOF_WIDTH (1U) 615 #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) 616 617 #define QuadSPI_FR_AIBSEF_MASK (0x2000U) 618 #define QuadSPI_FR_AIBSEF_SHIFT (13U) 619 #define QuadSPI_FR_AIBSEF_WIDTH (1U) 620 #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK) 621 622 #define QuadSPI_FR_AITEF_MASK (0x4000U) 623 #define QuadSPI_FR_AITEF_SHIFT (14U) 624 #define QuadSPI_FR_AITEF_WIDTH (1U) 625 #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK) 626 627 #define QuadSPI_FR_RBDF_MASK (0x10000U) 628 #define QuadSPI_FR_RBDF_SHIFT (16U) 629 #define QuadSPI_FR_RBDF_WIDTH (1U) 630 #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) 631 632 #define QuadSPI_FR_RBOF_MASK (0x20000U) 633 #define QuadSPI_FR_RBOF_SHIFT (17U) 634 #define QuadSPI_FR_RBOF_WIDTH (1U) 635 #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) 636 637 #define QuadSPI_FR_ILLINE_MASK (0x800000U) 638 #define QuadSPI_FR_ILLINE_SHIFT (23U) 639 #define QuadSPI_FR_ILLINE_WIDTH (1U) 640 #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) 641 642 #define QuadSPI_FR_TBUF_MASK (0x4000000U) 643 #define QuadSPI_FR_TBUF_SHIFT (26U) 644 #define QuadSPI_FR_TBUF_WIDTH (1U) 645 #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) 646 647 #define QuadSPI_FR_TBFF_MASK (0x8000000U) 648 #define QuadSPI_FR_TBFF_SHIFT (27U) 649 #define QuadSPI_FR_TBFF_WIDTH (1U) 650 #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) 651 /*! @} */ 652 653 /*! @name RSER - Interrupt and DMA Request Select and Enable Register */ 654 /*! @{ */ 655 656 #define QuadSPI_RSER_TFIE_MASK (0x1U) 657 #define QuadSPI_RSER_TFIE_SHIFT (0U) 658 #define QuadSPI_RSER_TFIE_WIDTH (1U) 659 #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) 660 661 #define QuadSPI_RSER_IPIEIE_MASK (0x40U) 662 #define QuadSPI_RSER_IPIEIE_SHIFT (6U) 663 #define QuadSPI_RSER_IPIEIE_WIDTH (1U) 664 #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) 665 666 #define QuadSPI_RSER_IPAEIE_MASK (0x80U) 667 #define QuadSPI_RSER_IPAEIE_SHIFT (7U) 668 #define QuadSPI_RSER_IPAEIE_WIDTH (1U) 669 #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) 670 671 #define QuadSPI_RSER_ABOIE_MASK (0x1000U) 672 #define QuadSPI_RSER_ABOIE_SHIFT (12U) 673 #define QuadSPI_RSER_ABOIE_WIDTH (1U) 674 #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) 675 676 #define QuadSPI_RSER_AIBSIE_MASK (0x2000U) 677 #define QuadSPI_RSER_AIBSIE_SHIFT (13U) 678 #define QuadSPI_RSER_AIBSIE_WIDTH (1U) 679 #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK) 680 681 #define QuadSPI_RSER_AITIE_MASK (0x4000U) 682 #define QuadSPI_RSER_AITIE_SHIFT (14U) 683 #define QuadSPI_RSER_AITIE_WIDTH (1U) 684 #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK) 685 686 #define QuadSPI_RSER_RBDIE_MASK (0x10000U) 687 #define QuadSPI_RSER_RBDIE_SHIFT (16U) 688 #define QuadSPI_RSER_RBDIE_WIDTH (1U) 689 #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) 690 691 #define QuadSPI_RSER_RBOIE_MASK (0x20000U) 692 #define QuadSPI_RSER_RBOIE_SHIFT (17U) 693 #define QuadSPI_RSER_RBOIE_WIDTH (1U) 694 #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) 695 696 #define QuadSPI_RSER_RBDDE_MASK (0x200000U) 697 #define QuadSPI_RSER_RBDDE_SHIFT (21U) 698 #define QuadSPI_RSER_RBDDE_WIDTH (1U) 699 #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) 700 701 #define QuadSPI_RSER_ILLINIE_MASK (0x800000U) 702 #define QuadSPI_RSER_ILLINIE_SHIFT (23U) 703 #define QuadSPI_RSER_ILLINIE_WIDTH (1U) 704 #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) 705 706 #define QuadSPI_RSER_TBFDE_MASK (0x2000000U) 707 #define QuadSPI_RSER_TBFDE_SHIFT (25U) 708 #define QuadSPI_RSER_TBFDE_WIDTH (1U) 709 #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK) 710 711 #define QuadSPI_RSER_TBUIE_MASK (0x4000000U) 712 #define QuadSPI_RSER_TBUIE_SHIFT (26U) 713 #define QuadSPI_RSER_TBUIE_WIDTH (1U) 714 #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) 715 716 #define QuadSPI_RSER_TBFIE_MASK (0x8000000U) 717 #define QuadSPI_RSER_TBFIE_SHIFT (27U) 718 #define QuadSPI_RSER_TBFIE_WIDTH (1U) 719 #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) 720 /*! @} */ 721 722 /*! @name SPTRCLR - Sequence Pointer Clear Register */ 723 /*! @{ */ 724 725 #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) 726 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) 727 #define QuadSPI_SPTRCLR_BFPTRC_WIDTH (1U) 728 #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) 729 730 #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) 731 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) 732 #define QuadSPI_SPTRCLR_IPPTRC_WIDTH (1U) 733 #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) 734 /*! @} */ 735 736 /*! @name SFA1AD - Serial Flash Memory A1 Top Address Register */ 737 /*! @{ */ 738 739 #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) 740 #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) 741 #define QuadSPI_SFA1AD_TPADA1_WIDTH (22U) 742 #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) 743 /*! @} */ 744 745 /*! @name SFA2AD - Serial Flash Memory A2 Top Address Register */ 746 /*! @{ */ 747 748 #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) 749 #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) 750 #define QuadSPI_SFA2AD_TPADA2_WIDTH (22U) 751 #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) 752 /*! @} */ 753 754 /*! @name SFB1AD - Serial Flash Memory B1 Top Address Register */ 755 /*! @{ */ 756 757 #define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) 758 #define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) 759 #define QuadSPI_SFB1AD_TPADB1_WIDTH (22U) 760 #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) 761 /*! @} */ 762 763 /*! @name SFB2AD - Serial Flash Memory B2 Top Address Register */ 764 /*! @{ */ 765 766 #define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) 767 #define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) 768 #define QuadSPI_SFB2AD_TPADB2_WIDTH (22U) 769 #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) 770 /*! @} */ 771 772 /*! @name RBDR - RX Buffer Data Register */ 773 /*! @{ */ 774 775 #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) 776 #define QuadSPI_RBDR_RXDATA_SHIFT (0U) 777 #define QuadSPI_RBDR_RXDATA_WIDTH (32U) 778 #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) 779 /*! @} */ 780 781 /*! @name LUTKEY - LUT Key Register */ 782 /*! @{ */ 783 784 #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) 785 #define QuadSPI_LUTKEY_KEY_SHIFT (0U) 786 #define QuadSPI_LUTKEY_KEY_WIDTH (32U) 787 #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) 788 /*! @} */ 789 790 /*! @name LCKCR - LUT Lock Configuration Register */ 791 /*! @{ */ 792 793 #define QuadSPI_LCKCR_LOCK_MASK (0x1U) 794 #define QuadSPI_LCKCR_LOCK_SHIFT (0U) 795 #define QuadSPI_LCKCR_LOCK_WIDTH (1U) 796 #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) 797 798 #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) 799 #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) 800 #define QuadSPI_LCKCR_UNLOCK_WIDTH (1U) 801 #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) 802 /*! @} */ 803 804 /*! @name LUT - LUT Register */ 805 /*! @{ */ 806 807 #define QuadSPI_LUT_OPRND0_MASK (0xFFU) 808 #define QuadSPI_LUT_OPRND0_SHIFT (0U) 809 #define QuadSPI_LUT_OPRND0_WIDTH (8U) 810 #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) 811 812 #define QuadSPI_LUT_PAD0_MASK (0x300U) 813 #define QuadSPI_LUT_PAD0_SHIFT (8U) 814 #define QuadSPI_LUT_PAD0_WIDTH (2U) 815 #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) 816 817 #define QuadSPI_LUT_INSTR0_MASK (0xFC00U) 818 #define QuadSPI_LUT_INSTR0_SHIFT (10U) 819 #define QuadSPI_LUT_INSTR0_WIDTH (6U) 820 #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) 821 822 #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) 823 #define QuadSPI_LUT_OPRND1_SHIFT (16U) 824 #define QuadSPI_LUT_OPRND1_WIDTH (8U) 825 #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) 826 827 #define QuadSPI_LUT_PAD1_MASK (0x3000000U) 828 #define QuadSPI_LUT_PAD1_SHIFT (24U) 829 #define QuadSPI_LUT_PAD1_WIDTH (2U) 830 #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) 831 832 #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) 833 #define QuadSPI_LUT_INSTR1_SHIFT (26U) 834 #define QuadSPI_LUT_INSTR1_WIDTH (6U) 835 #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) 836 /*! @} */ 837 838 /*! 839 * @} 840 */ /* end of group QuadSPI_Register_Masks */ 841 842 /*! 843 * @} 844 */ /* end of group QuadSPI_Peripheral_Access_Layer */ 845 846 #endif /* #if !defined(S32K344_QuadSPI_H_) */ 847
